rtd FPGA35S6045HR User manual

RTD Embedded Technologies, Inc.
AS9100 and ISO 9001 Certified
FPGA35S6045HR
FPGA35S6100HR
FPGA Module
User’s Manual
BDM-610010045 Rev. C

RTD Embedded Technologies, Inc.
103 Innovation Boulevard
State College, PA 16803 USA
Telephone: [phone]
Fax: [phone]
www.rtd.com
[email protected]
[email protected]

RTD Embedded Technologies, Inc. | www.rtd.com iii FPGA35S6 User’s Manual
Revision History
Rev A Initial Release
Rev B Corrected pin names in Table 5 on page 13.Corrected FPGA Bank designations in CN4 & CN9: Digital I/O Connector on page 14.
Added IDAN connector section.
Rev C Change IDAN JTAG signals from P2 to P3 in Table 11 on page 18.
Advanced Analog I/O, Advanced Digital I/O, aAIO, aDIO, a2DIO, Autonomous SmartCal, “Catch the Express”, cpuModule, dspFramework, dspModule, expressMate, ExpressPlatform, HiDANplus, “MIL Value for
COTS prices”, multiPort, PlatformBus, and PC/104EZ are trademarks, and “Accessing the Analog World”, dataModule, IDAN, HiDAN, RTD, and the RTD logo are registered trademarks of RTD Embedded
Technologies, Inc (formerly Real Time Devices, Inc.). PS/2 is a trademark of International Business Machines Inc. PCI, PCI Express, and PCIe are trademarks of PCI-SIG. PC/104, PC/104-Plus, PCI-104, PCIe/104,
PCI/104-Express and 104 are trademarks of the PC/104 Embedded Consortium. All other trademarks appearing in this document are the property of their respective owners.
Failure to follow the instructions found in this manual may result in damage to the product described in this manual, or other components of the system. The procedure set forth in this manual shall only be performed
by persons qualified to service electronic equipment. Contents and specifications within this manual are given without warranty, and are subject to change without notice. RTD Embedded Technologies, Inc. shall not
be liable for errors or omissions in this manual, or for any loss, damage, or injury in connection with the use of this manual.
Copyright © 2014 by RTD Embedded Technologies, Inc. All rights reserved.

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Table of Contents
1Introduction 7
1.1 Product Overview........................................................................................................................................................................ 7
1.2 Board Features ........................................................................................................................................................................... 7
1.3 Ordering Information................................................................................................................................................................... 8
1.4 Contact Information .................................................................................................................................................................... 8
1.4.1 Sales Support 8
1.4.2 Technical Support 8
2Specifications 9
2.1 Operating Conditions .................................................................................................................................................................. 9
2.2 Electrical Characteristics ............................................................................................................................................................ 9
3Board Connection 10
3.1 Board Handling Precautions ..................................................................................................................................................... 10
3.2 Physical Characteristics............................................................................................................................................................ 10
3.3 Connectors and Jumpers.......................................................................................................................................................... 11
3.3.1 External I/O Connectors 12
CN3: Xilinx JTAG Programming Header 12
CN8: High Speed Digital I/O Connector 13
CN4 & CN9: Digital I/O Connector 14
3.3.2 Bus Connectors 14
CN1 (Top) & CN2 (Bottom): PCIe Connector 14
3.3.3 Jumpers 14
JP1, JP2, JP3, JP4, JP5, & JP6: Pull up/Pull down Jumper 14
JP7: Reserved 15
3.3.1 Solder Jumper 15
B1: Pull up Voltage 15
B2: Pull up Voltage 15
3.4 Steps for Installing .................................................................................................................................................................... 16
4IDAN Connections 17
4.1 Module Handling Precautions................................................................................................................................................... 17
4.2 Physical Characteristics............................................................................................................................................................ 17
4.3 Connectors and Jumpers.......................................................................................................................................................... 18
P2 & P3: Digital I/O Connector 18
P4: High Speed Digital I/O Connector 19
4.3.1 Bus Connectors 21
CN1 (Top) & CN2 (Bottom): PCIe Connector 21
4.3.2 Jumpers 21
JP1, JP2, JP3, JP4, JP5, & JP6: Pull up/Pull down Jumper 21
JP7: Reserved 21
4.3.3 Solder Jumper 21
B1: Pull up Voltage 21
B2: Pull up Voltage 21
4.4 Steps for Installing .................................................................................................................................................................... 22
5Functional Description 23
5.2 Oscillator................................................................................................................................................................................... 23
5.3 EEPROM .................................................................................................................................................................................. 23
5.4 DDR2 SRAM............................................................................................................................................................................. 23
5.5 Digital I/O .................................................................................................................................................................................. 24
6Register Address Space 25

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6.1 BAR0 –FPGA Example Register Map ..................................................................................................................................... 25
6.1.1 R_ID (Read) 25
6.1.2 R_STATUS (Read) 25
6.1.3 R_EEPROM (Read/Write) 25
6.1.4 R_PORT0_IN (Read) 26
6.1.5 R_PORT0_OUT (Write) 26
6.1.6 R_PORT0_DIR (Write) 26
6.1.7 R_PORT1_IN (Read) 26
6.1.8 R_PORT1_OUT (Write) 26
6.1.9 R_PORT1_DIR (Read/Write) 26
6.1.10 R_PORT2L_IN (Read) 26
6.1.11 R_PORT2L_OUT (Write) 26
6.1.12 R_PORT2L_DIR (Read/Write) 26
6.1.13 R_PORT2H_IN (Read) 26
6.1.14 R_PORT2H_OUT (Write) 26
6.1.15 R_PORT2H_DIR (Read/Write) 26
6.1.16 R_DDR_RD_DATA (Read) 26
6.1.17 R_DDR_WR_DATA (Read/Write) 26
6.1.18 R_DDR_ADDR (Read/Write) 26
6.1.19 R_DDR_STATUS (Read) 27
7Troubleshooting 28
8Additional Information 29
8.1 PC/104 Specifications............................................................................................................................................................... 29
8.2 PCI and PCI Express Specification .......................................................................................................................................... 29
9Limited Warranty 30

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Table of Figures
Figure 1: Board Dimensions ................................................................................................................................................................................... 10
Figure 2: Board Connections .................................................................................................................................................................................. 11
Figure 3: Bottom Solder Jumper Locations ............................................................................................................................................................ 12
Figure 4: Example 104™Stack............................................................................................................................................................................... 16
Figure 5: IDAN Dimensions .................................................................................................................................................................................... 17
Figure 6: Example IDAN System ............................................................................................................................................................................ 22
Figure 7: FPGA35S6 Block Diagram...................................................................................................................................................................... 23
Figure 8: CN4/CN9 Digital I/O Circuitry .................................................................................................................................................................. 24
Table of Tables
Table 1: Ordering Options ........................................................................................................................................................................................ 8
Table 2: Operating Conditions .................................................................................................................................................................................. 9
Table 3: Electrical Characteristics ............................................................................................................................................................................ 9
Table 4: CN3 Programming Header ....................................................................................................................................................................... 12
Table 5: CN8 I/O Pin Assignments ......................................................................................................................................................................... 13
Table 6: CN4 I/O Pin Assignments ......................................................................................................................................................................... 14
Table 7: CN9 I/O Pin Assignments ......................................................................................................................................................................... 14
Table 8: Pull up/Pull down Jumper options ............................................................................................................................................................ 14
Table 9: B1 Pull up Voltage .................................................................................................................................................................................... 15
Table 10: B2 Pull up Voltage .................................................................................................................................................................................. 15
Table 11: P2 and P3 Pin Assignments ................................................................................................................................................................... 18
Table 12: P4 Pin Assignments................................................................................................................................................................................ 19
Table 13: Pull up/Pull down Jumper options .......................................................................................................................................................... 21
Table 14: B1 Pull up Voltage .................................................................................................................................................................................. 21
Table 15: B2 Pull up Voltage .................................................................................................................................................................................. 21
Table 16: FPGA Example Register Map................................................................................................................................................................. 25

RTD Embedded Technologies, Inc. | www.rtd.com 7FPGA35S6 User’s Manual
1Introduction
1.1 Product Overview
The FPGA35S6 series of FPGA boards are designed to provide platform to create any digital I/O that is required for
your application. It interfaces with the PCIe bus and features a Xilinx Spartan 6 FPGA with a 27 MHz oscillator and
1Gb of DDR2 SDRAM. There 48 5V tolerant I/O and 40 3.3V tolerant high speed I/O.
1.2 Board Features
Xilinx Spartan 6 System level features
oXC6SLX45T
43,661 Logic Cells
2,489 kb of internal RAM
116 18Kb (2088 Kb Max) Block RAM
401 kB Distributed RAM
oXC6SLX100T
101,261 Logic Cells
5,800 kb of internal RAM
268 18Kb (4,824 Kb Max) Block RAM
976 kB Distributed RAM
oRAM hierarchical memory:
Each block RAM has two independent ports
Programmable Data Width
oIntegrated Endpoint block for PCI Express
oIntegrated Memory Controller
1 Gb of DDR2 SDRAM
Supports access rates of up to 800Mb/s
oDedicated carry logic for high-speed arithmetic
oAbundant logic resources with increased logic capacity
Optional shift register or distributed RAM support
Efficient 6-input LUTs
LUT with dual flip-flops
oFour dedicated DLLs for advanced clock control
Phase shift input clock by 0, 90, 180, 270
Multiply input clock by 2 to 32
Divide input clock by 1 to 32
Fully supported by Xilinx development system
oISE WebPACK (free download from http://www.xilinx.com)
oISE Design Suite
Digital I/O Connectors
o48 5 volt tolerant I/O with ESD protection
o40 3.3 volt tolerant high speed I/O with ESD protection
PCI Express Bus:
oPCIe/104 Universal Board
Interfaces with Type 1 or Type 2 bus
No re-population
oProvides 2.5 Gbps in each direction
oIn-band interrupts and messages
oMessage Signaled Interrupt (MSI) support

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1.3 Ordering Information
The FPGA35S6 series of FPGA boards is available in the following options:
Table 1: Ordering Options
Part Number
Description
FPGA35S6045HR
PCIe/104 Spartan-6 XC6SLX45T User Programmable FPGA Module
FPGA35S6100HR
PCIe/104 Spartan-6 XC6SLX100T User Programmable FPGA Module
IDAN-FPGA35S6045HR
PCIe/104 Spartan-6 XC6SLX45T User Programmable FPGA Module in IDAN enclosure
IDAN-FPGA35S6100HR
PCIe/104 Spartan-6 XC6SLX100T User Programmable FPGA Module in IDAN enclosure
A Starter Kit is available for any of the options, which includes the appropriate programming cable. Contact RTD Sales for more information.
The FPGA35S6 is a general use FPGA module, allowing you to design your own FPGA. It has support for custom oscillator and larger Xilinx
Spartan 6 FPGAs. Please contact RTD Embedded Technologies for more information on custom FPGA35S6 products and custom FPGA
designs.
The Intelligent Data Acquisition Node (IDAN™) building block can be used in just about any combination with other IDAN building blocks to
create a simple but rugged 104™ stack. This module can also be incorporated in a custom-built RTD HiDAN™ or HiDANplus High Reliability
Intelligent Data Acquisition Node. Contact RTD sales for more information on our high reliability systems.
1.4 Contact Information
1.4.1 SALES SUPPORT
For sales inquiries, you can contact RTD Embedded Technologies sales via the following methods:
Phone: [phone] Monday through Friday, 8:00am to 5:00pm (EST).
E-Mail: [email protected]
1.4.2 TECHNICAL SUPPORT
If you are having problems with you system, please try the steps in the Troubleshooting section of this manual.
For help with this product, or any other product made by RTD, you can contact RTD Embedded Technologies technical support via the
following methods:
Phone: [phone] Monday through Friday, 8:00am to 5:00pm (EST).
E-Mail: [email protected]

RTD Embedded Technologies, Inc. | www.rtd.com 9FPGA35S6 User’s Manual
2Specifications
2.1 Operating Conditions
Table 2: Operating Conditions
Symbol
Parameter
Test Condition
Min
Max
Unit
Vcc5
5V Supply Voltage
4.75
5.25
V
Vcc3
3.3V Supply Voltage
n/a
n/a
V
Vcc12
12V Supply Voltage
n/a
n/a
V
Ta
Operating Temperature
-40
+85
C
Ts
Storage Temperature
-40
+85
C
RH
Relative Humidity
Non-Condensing
0
90%
%
MTBF
Mean Time Before Failure
Telcordia Issue 2
30°C, Ground benign, controlled
TBD
Hours
2.2 Electrical Characteristics
Table 3: Electrical Characteristics
Symbol
Parameter
Test Condition
Min
Typ
Max
Unit
P
Power Consumption(1)
Vcc5 = 5.0V
2.5
W
Icc
5V Input Supply Current(1)
Active
500
mA
PCIe/104 Bus
Differential Output Voltage
0.8
1.2
V
DC Differential TX Impedance
80
120
Ω
Differential Input Voltage
0.175
1.2
V
DC Differential RX Impedance
80
120
Ω
Electrical Idle Detect Threshold
65
175
mV
Digital I/O
VIH
Input High Voltage
CN4,CN9
2.0
5.5
V
VIH
Input High Voltage
CN8
2.0
3.6
V
VIL
Input Low Voltage
CN4,CN8,CN9
-0.5
0.8
V
VOH
Output High Voltage
IO= -12mA CN4 CN8,CN9
2.6
3.3
V
VOL
Output Low Voltage
IO= 12mA CN4 CN8,CN9
0
0.4
V
5V Output
CN4,CN8,CN9
200
mA
DDR2 Interface
Access Rate(2)
250
800
Mb/s
Note: (1): Typical power consumption based on RTD’s FPGA example.
(2): Proving by design, not production tested.
For additionally electrical characteristic of the Spartan 6 I/O refer to http://www.xilinx.com

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3Board Connection
3.1 Board Handling Precautions
To prevent damage due to Electrostatic Discharge (ESD), keep your board in its antistatic bag until you are ready to install it into your system.
When removing it from the bag, hold the board at the edges, and do not touch the components or connectors. Handle the board in an antistatic
environment, and use a grounded workbench for testing and handling of your hardware.
3.2 Physical Characteristics
Weight: Approximately 63.5 g (0.14 lbs.)
Dimensions: 90.17 mm L x 95.89 mm W (3.550 in L x 3.775 in W)
Figure 1: Board Dimensions

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3.3 Connectors and Jumpers
Figure 2: Board Connections
JP4, JP5 & JP6:
Pull up/Pull down
Jumper
JP1, JP2 & JP3:
Pull up/Pull down
Jumper
CN3:
Programming
Header
CN1 & CN2: PCIe Connector
CN8: High Speed Digital I/O
CN4: Digital I/O
CN9: Digital I/O

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Figure 3: Bottom Solder Jumper Locations
3.3.1 EXTERNAL I/O CONNECTORS
CN3: Xilinx JTAG Programming Header
Connector CN3 provides a connection to the Xilinx JTAG programming header. The pin assignment for CN3 is shown below. This connector
header mates with the Xilinx OEM programming cable.
Table 4: CN3 Programming Header
3.3V VRef
2
1
GND
TMS
4
3
GND
TCK
6
5
GND
TDO
8
7
GND
TDI
10
9
GND
N/C
12
11
GND
N/C
14
13
GND
B1
B2
1
1

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CN8: High Speed Digital I/O Connector
Connector CN8 provides 40 digital I/O lines, along with a +5V pin and ground pins. These signals are 3.3V tolerant. The signal names reflect
the signal names I n the Xilinx UCF file with the device pin out.
CN8 is attached to Bank 1, and supports any of the Spartan 6 I/O Standards that use a 3.3V VCCO and no reference voltage. This includes
LVTTL, LVCMOS33 input and output, and LVDS_33 input. LVDS output is not supported in Bank 1.
Table 5: CN8 I/O Pin Assignments
Port2_n[0]
2
1
Port2_p[0]
Port2_n[1]
4
3
Port2_p[1]
Port2_n[2]
6
5
Port2_p[2]
Port2_n[3]
8
7
Port2_p[3]
GND
10
9
GND
Port2_n[4]
12
11
Port2_p[4]
Port2_n[5]
14
13
Port2_p[5]
Port2_n[6]
16
15
Port2_p[6]
Port2_n[7]
18
17
Port2_p[7]
GND
20
19
GND
Port2_n[8]
22
21
Port2_p[8]
Port2_n[9]
24
23
Port2_p[9]
Port2_n[10]
26
25
Port2_p[10]
Port2_n[11]
28
27
Port2_p[11]
GND
30
29
GND
Port2_n[12]
32
31
Port2_p[12]
Port2_n[13]
34
33
Port2_p[13]
Port2_n[14]
36
35
Port2_p[14]
Port2_n[15]
38
37
Port2_p[15]
GND
40
39
GND
Port2_n[16]
42
41
Port2_p[16]
Port2_n[17]
44
43
Port2_p[17]
Port2_n[18]
46
45
Port2_p[18]
Port2_n[19]
48
47
Port2_p[19]
GND
50
49
+5V

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CN4 & CN9: Digital I/O Connector
Connectors CN4 and CN9 each provide 24 digital I/O lines, along with a +5V pin and ground pins. All I/O have pull up/pull down resistors that
are controlled by jumper options, also shown in the table. These signals are 5V tolerant. The signal names reflect the signal names I n the
Xilinx UCF file with the device pin out.
CN4 and CN9 are attached to Bank 2 and 0 respectively, and support any of the Spartan 6 I/O Standards that use a 3.3V VCCO and no
reference voltage. This includes LVTTL, LVCMOS33, and LVDS_33 input and output.
Table 6: CN4 I/O Pin Assignments
GND
2
1
port0_p[0]
JP1
GND
4
3
port0_n[0]
GND
6
5
port0_p[1]
GND
8
7
port0_n[1]
GND
10
9
port0_p[2]
GND
12
11
port0_n[2]
GND
14
13
port0_p[3]
GND
16
15
port0_n[3]
GND
18
17
port0_p[4]
JP2
GND
20
19
port0_n[4]
GND
22
21
port0_p[5]
GND
24
23
port0_n[5]
GND
26
25
port0_p[6]
GND
28
27
port0_n[6]
GND
30
29
port0_p[7]
GND
32
31
port0_n[7]
GND
34
33
port0_p[8]
JP3
GND
36
35
port0_n[8]
GND
38
37
port0_p[9]
GND
40
39
port0_n[9]
GND
42
41
port0_p[10]
GND
44
43
port0_n[10]
GND
46
45
port0_p[11]
GND
48
47
port0_n[11]
GND
50
49
+5V
Table 7: CN9 I/O Pin Assignments
GND
2
1
port1_p[0]
JP4
GND
4
3
port1_n[0]
GND
6
5
port1_p[1]
GND
8
7
port1_n[1]
GND
10
9
port1_p[2]
GND
12
11
port1_n[2]
GND
14
13
port1_p[3]
GND
16
15
port1_n[3]
GND
18
17
port1_p[4]
JP5
GND
20
19
port1_n[4]
GND
22
21
port1_p[5]
GND
24
23
port1_n[5]
GND
26
25
port1_p[6]
GND
28
27
port1_n[6]
GND
30
29
port1_p[7]
GND
32
31
port1_n[7]
JP6
GND
34
33
port1_p[8]
GND
36
35
port1_n[8]
GND
38
37
port1_p[9]
GND
40
39
port1_n[9]
GND
42
41
port1_p[10]
GND
44
43
port1_n[10]
GND
46
45
port1_p[11]
GND
48
47
port1_n[11]
GND
50
49
+5V
3.3.2 BUS CONNECTORS
CN1 (Top) & CN2 (Bottom): PCIe Connector
The PCIe connector is the connection to the system CPU. The position and pin assignments are compliant with the PCI/104-Express
Specification. (See PC/104 Specifications on page 29)
The FPGA35S6 is a “Universal” board, and can connect to either a Type 1 or Type 2 PCIe/104 connector.
3.3.3 JUMPERS
JP1, JP2, JP3, JP4, JP5, & JP6: Pull up/Pull down Jumper
JP1, JP2, JP3, JP4, JP5, and JP6 are 3-pin two position jumpers that are used to set pull up or pull downs options on the I/O signal lines of
CN4 and C5. Refer to Table 6 and Table 7 to determine which I/O pins are effected by each jumper.
Table 8: Pull up/Pull down Jumper options
Setting
Description
1-2
I/O is pulled up to 3.3V or 5V (Set by B1 and B2)
2-3
I/O is pulled down to GND
No Jumper
I/O has no pull up/pull down

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JP7: Reserved
JP7 is reserved, and must be left open.
3.3.1 SOLDER JUMPER
B1: Pull up Voltage
Solder jumper B1 are used to set the pull up voltage for JP1, JP2 and JP3.
Table 9: B1 Pull up Voltage
Setting
Description
1-2
Sets Pull up voltage to 3.3V
2-3
Sets Pull up voltage to 5V
B2: Pull up Voltage
Solder jumper B1 are used to set the pull up voltage for JP4, JP5 and JP6.
Table 10: B2 Pull up Voltage
Setting
Description
1-2
Sets Pull up voltage to 3.3V
2-3
Sets Pull up voltage to 5V

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3.4 Steps for Installing
1. Always work at an ESD protected workstation, and wear a grounded wrist-strap.
2. Turn off power to the PC/104 system or stack.
3. Select and install stand-offs to properly position the module on the stack.
4. Remove the module from its anti-static bag.
5. Check that pins of the bus connector are properly positioned.
6. Check the stacking order; make sure all of the busses used by the peripheral cards are connected to the cpuModule.
7. Hold the module by its edges and orient it so the bus connector pins line up with the matching connector on the stack.
8. Gently and evenly press the module onto the PC/104 stack.
9. If any boards are to be stacked above this module, install them.
10. Attach any necessary cables to the PC/104 stack.
11. Re-connect the power cord and apply power to the stack.
12. Boot the system and verify that all of the hardware is working properly.
Figure 4: Example 104™Stack

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4IDAN Connections
4.1 Module Handling Precautions
To prevent damage due to Electrostatic Discharge (ESD), keep your module in its antistatic bag until you are ready to install it into your system.
When removing it from the bag, hold the module by the aluminum enclosure, and do not touch the components or connectors. Handle the
module in an antistatic environment, and use a grounded workbench for testing and handling of your hardware.
4.2 Physical Characteristics
Weight: Approximately 0.42 Kg (0.92 lbs.)
Dimensions: 152mm L x 130mm W x 34mm H (5.983" L x 5.117" W x 1.339" H)
Figure 5: IDAN Dimensions
1.339”
[34mm]
5.983”
[152mm]
5.117”
[130mm]
Front
Back

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4.3 Connectors and Jumpers
P2 & P3: Digital I/O Connector
Connector Part #: VALCONN HDB-62S Mating Connector: VALCONN HDB-62P
Connectors P2 and P3 each provide 24 digital I/O lines, along with a +5V pin and ground pins. All I/O have pull up/pull down resistors that are
controlled by jumper options, also shown in the table. These signals are 5V tolerant. The signal names reflect the signal names I n the Xilinx
UCF file with the device pin out.
P2 and P3 are attached to Bank 2 and 0 respectively, and support any of the Spartan 6 I/O Standards that use a 3.3V VCCO and no reference
voltage. This includes LVTTL, LVCMOS33, and LVDS_33 input and output.
Connector P2 also provides a connection to the Xilinx JTAG programming header. This connector header mates with the Xilinx OEM
programming cable through an adapter cable. The adapter cable is provided when purchasing the Starter Kit.
Table 11: P2 and P3 Pin Assignments
IDAN P2 Pin
Signal
Pull
Jmpr
CN4
Pin
IDAN P3 Pin
Signal
Pull
Jmpr
C9 Pin
Row 1
Row 2
Row 3
Row 1
Row 2
Row 3
1
port0_p[0]
JP1
1
1
port1_p[0]
JP4
1
22
GND
2
22
GND
2
43
port0_n[0]
3
43
port1_n[0]
3
2
GND
4
2
GND
4
23
port0_p[1]
5
23
port1_p[1]
5
44
GND
6
44
GND
6
3
port0_n[1]
7
3
port1_n[1]
7
24
GND
8
24
GND
8
45
port0_p[2]
9
45
port1_p[2]
9
4
GND
10
4
GND
10
25
port0_n[2]
11
25
port1_n[2]
11
46
GND
12
46
GND
12
5
port0_p[3]
13
5
port1_p[3]
13
26
GND
14
26
GND
14
47
port0_n[3]
15
47
port1_n[3]
15
6
GND
16
6
GND
16
27
port0_p[4]
JP2
17
27
port1_p[4]
JP5
17
48
GND
18
48
GND
18
7
port0_n[4]
19
7
port1_n[4]
19
28
GND
20
28
GND
20
49
port0_p[5]
21
49
port1_p[5]
21
8
GND
22
8
GND
22
29
port0_n[5]
23
29
port1_n[5]
23
50
GND
24
50
GND
24
9
port0_p[6]
25
9
port1_p[6]
25
30
GND
26
30
GND
26
51
port0_n[6]
27
51
port1_n[6]
27
10
GND
28
10
GND
28
31
port0_p[7]
29
31
port1_p[7]
29
52
GND
30
52
GND
30
11
port0_n[7]
31
11
port1_n[7]
31
32
GND
32
32
GND
32
53
port0_p[8]
JP3
33
53
port1_p[8]
JP6
33
12
GND
34
12
GND
34
33
port0_n[8]
35
33
port1_n[8]
35
54
GND
36
54
GND
36
13
port0_p[9]
37
13
port1_p[9]
37
34
GND
38
34
GND
38
55
port0_n[9]
39
55
port1_n[9]
39
14
GND
40
14
GND
40
35
port0_p[10]
41
35
port1_p[10]
41
56
GND
42
56
GND
42
15
port0_n[10]
43
15
port1_n[10]
43

RTD Embedded Technologies, Inc. | www.rtd.com 19 FPGA35S6 User’s Manual
Table 11: P2 and P3 Pin Assignments
IDAN P2 Pin
Signal
Pull
Jmpr
CN4
Pin
IDAN P3 Pin
Signal
Pull
Jmpr
C9 Pin
Row 1
Row 2
Row 3
Row 1
Row 2
Row 3
36
GND
44
36
GND
44
57
port0_p[11]
45
57
port1_p[11]
45
16
GND
46
16
GND
46
37
port0_n[11]
47
37
port1_n[11]
47
58
GND
48
58
GND
48
17
+5V
49
17
+5V
49
38
GND
50
38
GND
50
59
Reserved
59
Reserved
18
Reserved
18
jtag_vref
CN3.2
39
Reserved
39
GND
CN3.3
60
Reserved
60
jtag_tms
CN3.4
19
Reserved
19
GND_TCK
CN3.5
40
Reserved
40
jtag_tck
CN3.6
61
Reserved
61
GND
CN3.7
20
Reserved
20
jtag_tdo
CN3.8
41
Reserved
41
GND
CN3.9
62
Reserved
62
jtag_tdi
CN3.10
21
Reserved
21
Reserved
42
Reserved
42
Reserved
P4: High Speed Digital I/O Connector
Connector Part #: VALCONN HDB-62S Mating Connector: VALCONN HDB-62P
Connector P4 provides 40 digital I/O lines, along with a +5V pin and ground pins. These signals are 3.3V tolerant. The signal names reflect the
signal names I n the Xilinx UCF file with the device pin out.
P4 is attached to Bank 1, and supports any of the Spartan 6 I/O Standards that use a 3.3V VCCO and no reference voltage. This includes
LVTTL, LVCMOS33 input and output, and LVDS_33 input. LVDS output is not supported in Bank 1.
Table 12: P4 Pin Assignments
IDAN P4 Pin
Signal
C8 Pin
Row 1
Row 2
Row 3
1
Port2_p[0]
1
22
Port2_n[0]
2
43
Port2_p[1]
3
2
Port2_n[1]
4
23
Port2_p[2]
5
44
Port2_n[2]
6
3
Port2_p[3]
7
24
Port2_n[3]
8
45
GND
9
4
GND
10
25
Port2_p[4]
11
46
Port2_n[4]
12
5
Port2_p[5]
13
26
Port2_n[5]
14
47
Port2_p[6]
15
6
Port2_n[6]
16
27
Port2_p[7]
17
48
Port2_n[7]
18
7
GND
19
28
GND
20
49
Port2_p[8]
21
8
Port2_n[8]
22
29
Port2_p[9]
23
50
Port2_n[9]
24

RTD Embedded Technologies, Inc. | www.rtd.com 20 FPGA35S6 User’s Manual
Table 12: P4 Pin Assignments
IDAN P4 Pin
Signal
C8 Pin
Row 1
Row 2
Row 3
9
Port2_p[10]
25
30
Port2_n[10]
26
51
Port2_p[11]
27
10
Port2_n[11]
28
31
GND
29
52
GND
30
11
Port2_p[12]
31
32
Port2_n[12]
32
53
Port2_p[13]
33
12
Port2_n[13]
34
33
Port2_p[14]
35
54
Port2_n[14]
36
13
Port2_p[15]
37
34
Port2_n[15]
38
55
GND
39
14
GND
40
35
Port2_p[16]
41
56
Port2_n[16]
42
15
Port2_p[17]
43
36
Port2_n[17]
44
57
Port2_p[18]
45
16
Port2_n[18]
46
37
Port2_p[19]
47
58
Port2_n[19]
48
17
+5V
49
38
GND
50
59
Reserved
18
Reserved
39
Reserved
60
Reserved
19
Reserved
40
Reserved
61
Reserved
20
Reserved
41
Reserved
62
Reserved
21
Reserved
42
Reserved