ST HTSSOP38 User manual

This is information on a product in full production.
October 2012 Doc ID 023768 Rev 1 1/73
73
L6482
Fully integrated microstepping motor driver
with motion engine and SPI
Datasheet −production data
Features
■Operating voltage: 7.5 V - 85 V
■Dual full bridge gate driver for N-channel
MOSFETs
■Fully programmable gate driving
■Embedded Miller clamp function
■Programmable speed profile
■Up to 1/16 microstepping
■Advanced current control with auto-adaptive
decay mode
■Integrated voltage regulators
■SPI interface
■Low quiescent standby currents
■Programmable non-dissipative overcurrent
protection
■Overtemperature protection
Applications
■Bipolar stepper motor
Description
The L6482, realized in analog mixed signal
technology, is an advanced fully integrated
solution suitable for driving two-phase bipolar
stepper motors with microstepping.
It integrates a dual full bridge gate driver for N-
channel MOSFET power stages with embedded
non-dissipative overcurrent protection. Thanks to
a new current control, a 1/16 microstepping is
achieved through an adaptive decay mode which
outperforms traditional implementations. The
digital control core can generate user defined
motion profiles with acceleration, deceleration,
speed or target position easily programmed
through a dedicated register set. All application
commands and data registers, including those
used to set analog values (i.e. current protection
trip point, deadtime, PWM frequency, etc.) are
sent through a standard 5-Mbit/s SPI. A very rich
set of protections (thermal, low bus voltage,
overcurrent and motor stall) make the L6482
“bullet proof”, as required by the most demanding
motor control applications.
HTSSOP38
Table 1. Device summary
Order code Package Packaging
L6482H HTSSOP38 Tube
L6482HTR HTSSOP38 Tape and reel
www.st.com

Contents L6482
2/73 Doc ID 023768 Rev 1
Contents
1 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2 Electrical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.1 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.2 Recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.3 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
4 Pin connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
4.1 Pin list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
5 Typical applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
6 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
6.1 Device power-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
6.2 Logic I/O . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
6.3 Charge pump . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
6.4 Microstepping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
6.4.1 Automatic Full-step and Boost modes . . . . . . . . . . . . . . . . . . . . . . . . . . 21
6.5 Absolute position counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
6.6 Programmable speed profiles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
6.6.1 Infinite acceleration/deceleration mode . . . . . . . . . . . . . . . . . . . . . . . . . 22
6.7 Motor control commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
6.7.1 Constant speed commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
6.7.2 Positioning commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
6.7.3 Motion commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
6.7.4 Stop commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
6.7.5 Step-clock mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
6.7.6 GoUntil and ReleaseSW commands . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
6.8 Internal oscillator and oscillator driver . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
6.8.1 Internal oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
6.8.2 External clock source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

L6482 Contents
Doc ID 023768 Rev 1 3/73
6.9 Overcurrent detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
6.10 Undervoltage lockout (UVLO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
6.11 VS undervoltage lockout (UVLO_ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . 29
6.12 Thermal warning and thermal shutdown . . . . . . . . . . . . . . . . . . . . . . . . . 29
6.13 Reset and standby . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
6.14 External switch (SW pin) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
6.15 Programmable gate drivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
6.16 Deadtime and blanking time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
6.17 Integrated analog-to-digital converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
6.18 Supply management and internal voltage regulators . . . . . . . . . . . . . . . . 33
6.19 BUSY/SYNC pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
6.20 FLAG pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
7 Phase current control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
7.1 Predictive current control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
7.2 Auto-adjusted decay mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
7.3 Auto-adjusted fast decay during the falling steps . . . . . . . . . . . . . . . . . . . 38
7.4 Torque regulation (output current amplitude regulation) . . . . . . . . . . . . . . 39
8 Serial interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
9 Programming manual . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
9.1 Register and flag description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
9.1.1 ABS_POS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
9.1.2 EL_POS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
9.1.3 MARK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
9.1.4 SPEED . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
9.1.5 ACC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
9.1.6 DEC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
9.1.7 MAX_SPEED . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
9.1.8 MIN_SPEED . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
9.1.9 FS_SPD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
9.1.10 TVAL_HOLD, TVAL_RUN, TVAL_ACC and TVAL_DEC . . . . . . . . . . . . 47
9.1.11 T_FAST . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
9.1.12 TON_MIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

Contents L6482
4/73 Doc ID 023768 Rev 1
9.1.13 TOFF_MIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
9.1.14 ADC_OUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
9.1.15 OCD_TH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
9.1.16 STEP_MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
9.1.17 ALARM_EN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
9.1.18 GATECFG1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
9.1.19 GATECFG2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
9.1.20 CONFIG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
9.1.21 STATUS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
9.2 Application commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
9.2.1 Command management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
9.2.2 Nop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
9.2.3 SetParam (PARAM, VALUE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
9.2.4 GetParam (PARAM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
9.2.5 Run (DIR, SPD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
9.2.6 StepClock (DIR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
9.2.7 Move (DIR, N_STEP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
9.2.8 GoTo (ABS_POS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
9.2.9 GoTo_DIR (DIR, ABS_POS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
9.2.10 GoUntil (ACT, DIR, SPD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
9.2.11 ReleaseSW (ACT, DIR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
9.2.12 GoHome . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
9.2.13 GoMark . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
9.2.14 ResetPos . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
9.2.15 ResetDevice . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
9.2.16 SoftStop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
9.2.17 HardStop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
9.2.18 SoftHiZ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
9.2.19 HardHiZ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
9.2.20 GetStatus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
10 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
11 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

L6482 List of tables
Doc ID 023768 Rev 1 5/73
List of tables
Table 1. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Table 2. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Table 3. Recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Table 4. Thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Table 5. Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Table 6. Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Table 7. Typical application values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Table 8. CL values according to external oscillator frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Table 9. UVLO thresholds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Table 10. Thermal protection summarizing table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Table 11. Register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Table 12. EL_POS register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Table 13. MIN_SPEED register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Table 14. FS_SPD register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Table 15. Torque regulation by TVAL_HOLD, TVAL_ACC, TVAL_DEC and TVAL_RUN registers . 48
Table 16. FS_SPD register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Table 17. Maximum fast decay times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Table 18. Minimum on-time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Table 19. Minimum off-time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Table 20. ADC_OUT value and torque regulation feature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Table 21. Overcurrent detection threshold . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Table 22. STEP_MODE register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Table 23. Step mode selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Table 24. SYNC output frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Table 25. SYNC signal source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Table 26. ALARM_EN register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Table 27. GATECFG1 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Table 28. IGATE parameter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Table 29. TCC parameter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Table 30. TBOOST parameter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Table 31. GATECFG2 register (voltage mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Table 32. TDT parameter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Table 33. TBLANK parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Table 34. CONFIG register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Table 35. Oscillator management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Table 36. External switch HardStop interrupt mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Table 37. Overcurrent event . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Table 38. Programmable VCC regulator output voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Table 39. Programmable UVLO thresholds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Table 40. External torque regulation enable. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Table 41. Switching period . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Table 42. Motor supply voltage compensation enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Table 43. STATUS register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Table 44. STATUS register TH_STATUS bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Table 45. STATUS register DIR bit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Table 46. STATUS register MOT_STATE bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Table 47. Application commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Table 48. Nop command structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

List of tables L6482
6/73 Doc ID 023768 Rev 1
Table 49. SetParam command structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Table 50. GetParam command structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Table 51. Run command structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Table 52. StepClock command structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Table 53. Move command structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Table 54. GoTo command structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Table 55. GoTo_DIR command structure. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Table 56. GoUntil command structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Table 57. ReleaseSW command structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Table 58. GoHome command structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Table 59. GoMark command structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Table 60. ResetPos command structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Table 61. ResetDevice command structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Table 62. SoftStop command structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Table 63. HardStop command structure. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Table 64. SoftHiZ command structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Table 65. HardHiZ command structure. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Table 66. GetStatus command structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Table 67. HTSSOP38 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Table 68. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

L6482 List of figures
Doc ID 023768 Rev 1 7/73
List of figures
Figure 1. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Figure 2. Pin connection (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 3. Typical application schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 4. Charge pump circuitry. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 5. Normal mode and microstepping (16 microsteps) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 6. Automatic Full-step switching in Normal mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 7. Automatic Full-step switching in Boost mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 8. Speed profile in infinite acceleration/deceleration mode . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 9. Constant speed command examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 10. Positioning command examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 11. Motion command examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 12. OSCIN and OSCOUT pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Figure 13. Overcurrent detection-principle scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Figure 14. External switch connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Figure 15. Gate driving currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Figure 16. Device supply pin management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Figure 17. Predictive current control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Figure 18. Non-predictive current control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Figure 19. Adaptive decay - fast decay tuning. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Figure 20. Adaptive decay - switch from normal to slow+fast decay mode and vice versa . . . . . . . . . 38
Figure 21. Fast decay tuning during the falling steps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Figure 22. Current sensing and reference voltage generation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Figure 23. SPI timings diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Figure 24. Daisy chain configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Figure 25. Command with 3-byte argument . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Figure 26. Command with 3-byte response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Figure 27. Command response aborted . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Figure 28. HTSSOP38 package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Figure 29. HTSSOP38 footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

Block diagram L6482
8/73 Doc ID 023768 Rev 1
1 Block diagram
Figure 1. Block diagram
ADC
Charge
pump
Vdd
SPI
Current
sensing
STBY/RESET
FLAG
CS
CK
SDO
SDI
BUSY/SYNC
SW
STCK
DGND
VDD
ADCIN
VCC CP VBOOT
PGND
VS
CORE
LOGIC
VCC
HVGA1
LVGA1
HVGA2
LVGA2
HVB1
LVGB1
OUTA1
OUTA2
OUTB1
HVGB2
LVGB2
OUTB2
Vboot
Vboot
Vboot
Vboot
VSENSEA
VSENSEB
AGND
VCC
VCC
VCC
Voltage reg. VCC
VSREG VCC REG
Ext. Osc. driver
&
Clock gen.
OSCIN OSCOUT
16 MHz
Oscillator
Temperature
sensing
VREG
Voltage reg. VREG
AM15031v1

L6482 Electrical data
Doc ID 023768 Rev 1 9/73
2 Electrical data
2.1 Absolute maximum ratings
Table 2. Absolute maximum ratings
Symbol Parameter Test condition Value Unit
VDD Logic interface supply voltage 5.5 V
VREG Logic supply voltage 3.6
VSMotor supply voltage 95 V
VCC
Low-side gate driver supply
voltage 18 V
VBOOT Boot voltage 100 V
ΔVBOOT
High-side gate driver supply
voltage 0 to 20 V
VSREG
Internal VCC regulator supply
voltage 95 V
VCCREG
Internal VREG regulator
supply voltage 18 V
VOUT1A
VOUT2A
VOUT1B
VOUT2B
Full bridge output voltage
DC -5 to
VBOOT
V
AC -15 to
VBOOT
SRout
Full bridge output slew rate
(10% - 90%) 10 V/ns
VHVG1A
VHVG2A
VHVG1B
VHVG2B
High-side output driver
voltage
VOUT to
VBOOT
V
ΔVHVG1A
ΔVHVG2A
ΔVHVG1B
ΔVHVG2B
High-side output driver to
respective bridge output
voltage(VHVG - VOUT)
15 V
VLVG 1 A
VLVG 2 A
VLVG 1 B
VLVG 2 B
Low-side output driver voltage VCC + 0.3 V
IGATE-
CLAMP
High-side gate voltage clamp
current capability 100 mA
VADCIN
Integrated ADC input voltage
range (ADCIN pin) -0.3 to 3.6 V
Vout_diff
Differential voltage between
VBOOT, VS, OUT1A, OUT2A,
PGND and VBOOT, VS,
OUT1B, OUT2B, PGND pins
100 V

Electrical data L6482
10/73 Doc ID 023768 Rev 1
2.2 Recommended operating conditions
2.3 Thermal data
Vin Logic inputs voltage range -0.3 to 5.5 V
Ts TOP
Storage and operating
junction temperature -40 to 150 °C
Ptot
Total power dissipation (Tamb
= 25 ºC) Board characteristics: TBD TBD W
Table 2. Absolute maximum ratings (continued)
Symbol Parameter Test condition Value Unit
Table 3. Recommended operating conditions
Symbol Parameter Test condition Min. Typ. Max. Unit
VDD Logic interface supply voltage 3.3 V logic outputs 3.3 V
5 V logic outputs 5
VREG Logic supply voltage 3.3 V
VSMotor supply voltage VSREG 85 V
VSREG Internal VCC voltage regulator VCC voltage internally
generated VCC +3 VsV
VCC Gate driver supply voltage
VCC voltage imposed by
external source (VSREG
= VCC)
7.5 15 V
VCCREG
Internal VREG voltage regulator
supply voltage
VREG voltage internally
generated 6.3 VCC V
VADC
Integrated ADC input voltage
(ADCIN pin) 0V
REG V
TjOperating junction temperature - 25 125 °C
Table 4. Thermal data
Symbol Parameter Package Typ. Unit
Rthj-a Thermal resistance junction-to-ambient HTSSOP38 TBD °C/W

L6482 Electrical characteristics
Doc ID 023768 Rev 1 11/73
3 Electrical characteristics
VS= 48 V;VCC = 7.5 V; Tj= 25 °C, unless otherwise specified.
Table 5. Electrical characteristics
Symbol Parameter Test condition Min. Typ. Max. Unit
General
VCCthOn VCC UVLO turn-on threshold UVLO_VAL set high(1) 9.9 10.4 10.9 V
UVLO_VAL set low(1) 6.5 6.9 7.3 V
VCCthOff VCC UVLO turn-off threshold UVLO_VAL set high(1) 9.5 10 10.5 V
UVLO_VAL set low(1) 5.9 6.3 6.7 V
ΔVBOOTthOn VBOOT - VSUVLO turn-on threshold UVLO_VAL set high(1) 8.6 9.2 9.8 V
UVLO_VAL set low(1) 5.7 6 6.3 V
ΔVBOOTthOff VBOOT - VSUVLO turn-off threshold UVLO_VAL set high(1) 8.2 8.8 9.5 V
UVLO_VAL set low(1) 5.3 5.5 5.8 V
VREGthOn VREG turn-on threshold (1) 2.8 3 3.18 V
VREGthOff VREG turn-off threshold (1) 2.2 2.4 2.5 V
IVSREGqu
Undervoltage VSREG quiescent supply
current VCCREG= VREG< 2.2 V 40 μA
IVSREGq Quiescent VSREG supply current
VCCREG= VREG< 3.3 V,
internal oscillator
selected(1)
3.8 mA
IVSREGq Quiescent VSREG supply current VCCREG = VREG = 15V 6.5 mA
Thermal protection
Tj(WRN)Set Thermal warning temperature 135 °C
Tj(WRN)Rec Thermal warning recovery temperature 125 °C
Tj(OFF)Set Thermal bridge shutdown temperature 155 °C
Tj(OFF)Rec
Thermal bridge shutdown recovery
temperature 145 °C
Tj(SD)Set Thermal device shutdown temperature 170 °C
Tj(SD)Rec
Thermal device shutdown recovery
temperature 130 °C
Charge pump
Vpump Voltage swing for charge pump oscillator VCC V
fpump,min Minimum charge pump oscillator frequency(2) 660 kHz
fpump,max
Maximum charge pump oscillator
frequency(2) 800 kHz
RpumpHS Charge pump high-side RDS(ON) resistance 10 Ω

Electrical characteristics L6482
12/73 Doc ID 023768 Rev 1
RpumpLS Charge pump low-side RDS(ON) resistance 10 Ω
Iboot Average boot current 2.6 mA
Gate driver outputs
IGATE,Sink
Programmable high-side and low-side gate
sink current
VS= 38 V
VHVGX - VOUTX > 3 V
VLVG X > 3 V
2.4 4 5.6
mA
5.4 8 10.6
11.3 16 20.7
17.3 24 30.7
23.2 32 40.8
50.2 64 77.8
81 96 113
IGATE,Source
Programmable high-side and low-side gate
source current
VS= 38 V
VBOOTX - VHVGX > 3.5
V
VCC-VLVG X > 3.5 V
2.8 4 5.2
mA
5.8 8 10.2
12 16 20
18 24 30
24 32 40
51 64 77
82 96 112
IOB
High-side and low-side turn-off overboost
gate current 85 103 117 mA
RCLAMP(LS) Low-side gate driver Miller clamp resistance 6.5 10 Ω
RCLAMP(HS) High-side gate driver Miller clamp resistance 3 10 Ω
VGATE-CLAMP High-side gate voltage clamp IGATE-CLAMP=100 mA 16.7 v
tcc Programmable constant gate current time(2) TCC=’00000’ 125 ns
TCC= 11111 3750
tOB
Programmable. Turn-off overboost; gate
current time(2)
TBOOST=’001’,
internal oscillator 62.5 ns
TBOOST=’111’ 1000
IDSS Leakage current OUT = VS100 μA
OUT = GND -100 μA
trRise time
IGATE = 96 mA
VCC = 15 V
CGATE = 15 nF
2.5 μs
tfFall time
IGATE = 96 mA
VCC = 15 V
CGATE = 15 nF
2.5 μs
Table 5. Electrical characteristics (continued)
Symbol Parameter Test condition Min. Typ. Max. Unit

L6482 Electrical characteristics
Doc ID 023768 Rev 1 13/73
SRgate Gate driver output slew rate
IGATE= 96 mA
VCC = 15 V
CGATE = 15 nF
6V/μs
Deadtime and blanking
tDT Programmable deadtime(2) TDT= '00000' 125 ns
TDT=’11111’ 4000
tblank Programmable blanking time(2) TBLANK= '000' 125 ns
TBLANK=’111’ 1000
Logic
VIL Low level logic input voltage 0.8 V
VIH High level logic input voltage 2 V
IIH High level logic input current VIN = 5 V, VDDIO = 5 V 1 µA
IIL Low level logic input current VIN = 0 V, VDDIO = 5 V -1 µA
VOL Low level logic output voltage(3)
VDD = 3.3 V, IOL = 4
mA 0.3 V
VDD = 5 V, IOL = 4 mA 0.3
VOH High level logic output voltage
VDD = 3.3 V, IOH = 4
mA 2.4 V
VDD = 5 V, IOH = 4 mA 4.7
RPUCS CS pull-up resistor 430
kΩRPDRST STBY/RESET pull-down resistor 450
RPUSW SW pull-up resistor 80
thigh,STCK Step-clock input high time 300 ns
tlow,STCK Step-clock input low time 300 ns
Internal oscillator and external oscillator driver
fosc,int Internal oscillator frequency Tj = 25 °C, -5% 16 +5% MHz
fosc,ext Programmable external oscillator frequency 8 32 MHz
VOSCOUTH OSCOUT clock source high level voltage Internal oscillator 2.4 V
VOSCOUTL OSCOUT clock source low level voltage Internal oscillator 0.3 V
trOSCOUT
tfOSCOUT
OSCOUT clock source rise and fall time Internal oscillator 10 ns
thigh OSCOUT clock source high time Internal oscillator 62.5 ns
textosc Internal to external oscillator switching delay 3 ms
tintosc External to internal oscillator switching delay 100 µs
Table 5. Electrical characteristics (continued)
Symbol Parameter Test condition Min. Typ. Max. Unit

Electrical characteristics L6482
14/73 Doc ID 023768 Rev 1
SPI
fCK,MAX Maximum SPI clock frequency(4) 5MHz
trCK
tfCK
SPI clock rise and fall time(4) 1µs
thCK
tlCK
SPI clock high and low time(4) 90 ns
tsetCS Chip select setup time(4) 30 ns
tholCS Chip select hold time (4) 30 ns
tdisCS Deselect time(4) 625 ns
tsetSDI Data input setup time(4) 20 ns
tholSDI Data input hold time(4) 30 ns
tenSDO Data output enable time(4) 95 ns
tdisSDO Data output disable time(4) 95 ns
tvSDO Data output valid time(4) 35 ns
tholSDO Data output hold time(4) 0ns
Current control
VREF, max Maximum reference voltage 1000 mV
VREF, min Minimum reference voltage 7.8 mV
Overcurrent protection
VOCD
Programmable overcurrent detection voltage
VDS threshold
OCD_TH = ‘11111’ 800 1000 1100 mV
OCD_TH = ‘00000’ 27 31 35 mV
OCD_TH = ‘01001’ 270 312.5 344 mV
OCD_TH = ‘10011’ 500 625 688 mV
tOCD,Comp OCD comparator delay 100 200 ns
tOCD,Flag OCD to flag signal delay time 230 530 ns
tOCD,SD OCD to shutdown delay time
OCD_TH = '11111'
OCD event to 90% of
gate voltage
400 630 ns
Standby
ISTBY Standby mode supply current (VSREG pin)
VCC = VCCREG = 7.5 V
VSREG = 48 V 42
µA
VCC = VCCREG = 7.5
V VSREG = 18 V 37.5
ISTBY,vreg Standby mode supply current (VREG pin) 6 µA
tSTBY,min Minimum standby time 0.5 ms
tlogicwu Logic power-on and wake-up time 500 µs
Table 5. Electrical characteristics (continued)
Symbol Parameter Test condition Min. Typ. Max. Unit

L6482 Electrical characteristics
Doc ID 023768 Rev 1 15/73
tcpwu Charge pump power-on and wake-up time
Power bridges
disabled,
Cp= 10 nF, Cboot = 220
nF, VCC=15 V
1ms
Internal voltage regulators
VCCOUT Internal VCC voltage regulator output voltage
Low (default), ICC = 10
mA 7.3 7.5 V
High, ICC = 10 mA 4 15
VCCREG, drop VSREG to VCC dropout voltage ICC = 50 mA 3 V
PCC
Internal VCC voltage regulator power
dissipation 2.5 W
VREGOUT
Internal VREG voltage regulator output
voltage IREG = 10 mA 3.13
53.3 V
VSREG, drop VCCREG to VREG dropout voltage IREG = 50 mA 3 V
IREGOUT
Internal VREG voltage regulator output
current
VREG pin shorted to
ground 125 mA
IREGOUT,STB
Y
Internal VREG voltage regulator output
standby current
VREG pin shorted to
ground 55 mA
PREG
Internal VREG voltage regulator power
dissipation 0.5 W
Integrated analog-to-digital converter
NADC Analog-to-digital converter resolution 5 bit
VADC,ref Analog-to-digital converter reference voltage 3.3 V
fS
Analog-to-digital converter sampling
frequency
(2) fOSC/512 kHz
VADC,UVLO ADCIN UVLO threshold 1.05 1.16 1.35 V
1. Guaranteed in the temperature range -25 to 125 °C.
2. The value accuracy is dependent on oscillator frequency accuracy (Section 6.8).
3. FLAG and BUSY open drain outputs included.
4. See Figure 23.
Table 5. Electrical characteristics (continued)
Symbol Parameter Test condition Min. Typ. Max. Unit

Pin connection L6482
16/73 Doc ID 023768 Rev 1
4 Pin connection
4.1 Pin list
Figure 2. Pin connection (top view)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
VCCREG
VCC
CP
VBOOT
PGND
ADCIN
NC
HVGA1
LVGA1
OUTA1
HVGB1
OUTB1
LVGB1
VS
VSREG
VREG
OSCIN
OSCOUT
AGND
VDDIO
SW
STCK
DGND
SDO
SDI
CK
EPAD HVGA2
SENSEA
SENSEB
LVGA2
OUTA2
HVGB2
OUTB2
LVGB2
CS
FLAG
STBY/RESET
BUSY/SYNC
AM15032v1
Table 6. Pin description
No. Name Type Function
11 VCCREG Power supply Internal VREG voltage regulator supply voltage
13 VREG Power supply Logic supply voltage
27 VDD Power supply Logic interface supply voltage
12 VSREG Power supply Internal VCC voltage regulator supply voltage
10 VCC Power supply Gate driver supply voltage
14 OSCIN Analog input Oscillator pin1. To connect an external oscillator or
clock source
15 OSCOUT Analog output
Oscillator pin2. To connect an external oscillator.
When the internal oscillator is used, this pin can
supply a 2/4/8/16 MHz clock
9 CP Output Charge pump oscillator output
7 VBOOT Power supply Bootstrap voltage needed for driving the high-side
power DMOS of both bridges (A and B)
5 ADCIN Analog input Internal analog-to-digital converter input
6 VS Power supply Motor voltage
3 HVGA1 Power output High-side half bridge A1 gate driver output

L6482 Pin connection
Doc ID 023768 Rev 1 17/73
36 HVGA2 Power output High-side half bridge A2 gate driver output
17 HVGB1 Power output High-side half bridge B1 gate driver output
22 HVGB2 Power output High-side half bridge B2 gate driver output
1 LVGA1 Power output Low-side half bridge A1 gate driver output
38 LVGA2 Power output Low-side half bridge A2 gate driver output
19 LVGB1 Power output Low-side half bridge B1 gate driver output
20 LVGB2 Power output Low-side half bridge B2 gate driver output
8PGNDGround Power ground pins. They must be connected to other
ground pins
35 SENSEA Analog input Phase A current sensing input
23 SENSEB Analog input Phase B current sensing input
2 OUTA1 Power input Full bridge A output 1
37 OUTA2 Power input Full bridge A output 2
18 OUTB1 Power input Full bridge B output 1
21 OUTB2 Power input Full bridge B output 2
16 AGND Ground Analog ground. It must be connected to other ground
pins
33 SW Logical input External switch input pin
29 DGND Ground Digital ground. It must be connected to other ground
pins
28 SDO Logical output Data output pin for serial interface
26 SDI Logical input Data input pin for serial interface
25 CK Logical input Serial interface clock
24 CS Logical input Chip select input pin for serial interface
30 BUSY/SYNC Open drain output
By default, the BUSY / SYNC pin is forced low when
the device is performing a command.
The pin can be programmed in order to generate a
synchronization signal
31 FLAG Open drain output
Status flag pin. An internal open drain transistor can
pull the pin to GND when a programmed alarm
condition occurs (step loss, OCD, thermal pre-warning
or shutdown, UVLO, wrong command, non-
performable command)
34 STBY
RESET Logical input
Standby and reset pin. LOW logic level puts the device
in Standby mode and reset logic.
If not used, it should be connected to VREG
32 STCK Logical input Step-clock input
EPAD Exposed pad Ground Exposed pad. It must be connected to other ground
pins
Table 6. Pin description (continued)
No. Name Type Function

Typical applications L6482
18/73 Doc ID 023768 Rev 1
5 Typical applications
Figure 3. Typical application schematic
Table 7. Typical application values
Name Value
CVSPOL 220 µF
CVS 220 nF
CBOOT 470 nF
CFLY 47 nF
CVSREG 100 nF
CVCC 470 nF
CVCCREG 100 nF
CVREG 100 nF
CVREGPOL 22 µF
CVDD 100 nF
D1 Charge pump diodes
Q1,Q2,Q3,Q4,Q5,Q6,Q7
,Q8 STD25NF10
RPU 39 kΩ
RSENSE 0.2 Ω(maximum phase current 5 A)
CK
SDO
SDI
SW
STCK
DGND
VDD
ADCIN
Analog signal
VCC CP VBOOT
PGND
VS
STBY/RESET
FLAG
CS
BUSY/SYNC
HVGA1
L VGA1
LVGA2
HVGA2
HV GB1
LVGB1
OUTA1
OUTA2
OUTB1
LVGB2
HVGB2
SENSEB
OUTB2
SENSEA
AGND
VSREG
VCCREG
OSCIN
OSCOUT
VREG
L6482
CFLY
CVS
CVCC
C
VCCREG
CVDD CVSREG
CBOO T C
VSPOL
VS
CVREG
CVREGPOL
(10.5V - 85V )
D1
Q1 Q2
Q4Q3
R
SENSE
RSENSE
Q5 Q6
Q8Q7
Motor
RPU
RPU
HOST
AM15033v1

L6482 Functional description
Doc ID 023768 Rev 1 19/73
6 Functional description
6.1 Device power-up
During power-up, the device is under reset (all logic IOs disabled and power bridges in high
impedance state) until the following conditions are satisfied:
●VCC is greater than VCCthOn
●VBOOT - VSis greater than ΔVBOOTthOn
●VREG is greater than VREGthOn
●Internal oscillator is operative
●STBY/RESET input is forced high.
After power-up, the device state is the following:
●Parameters are set to default
●Internal logic is driven by internal oscillator and a 2-MHz clock is provided by the
OSCOUT pin
●Bridges are disabled (high impedance).
After power-up, a period of tlogicwu must pass before applying a command to allow proper
oscillator and logic startup.
Any movement command makes the device exit from High Z state (HardStop and SoftStop
included).
6.2 Logic I/O
Pins CS, CK, SDI, STCK, SW and STBY/RESET are TTL/CMOS 3.3 V-5 V compatible logic
inputs.
Pin SDO is a TTL/CMOS compatible logic output. VDD pin voltage imposes a logical output
voltage range.
Pins FLAG and BUSY/SYNC are open drain outputs.
SW and CS inputs are internally pulled up to VDD and STBY/RESET input is internally
pulled down to ground.
6.3 Charge pump
To ensure the correct driving of the high-side integrated MOSFETs, a voltage higher than
the motor power supply voltage needs to be applied to the VBOOT pin. The high-side gate
driver supply voltage VBOOT is obtained through an oscillator and a few external
components realizing a charge pump (see Figure 4).

Functional description L6482
20/73 Doc ID 023768 Rev 1
Figure 4. Charge pump circuitry
6.4 Microstepping
The driver is able to divide the single step into up to 16 microsteps. Stepping mode can be
programmed by the STEP_SEL parameter in the STEP_MODE register (Tab le 22 ).
Step mode can only be changed when bridges are disabled. Every time the step mode is
changed, the electrical position (i.e. the point of microstepping sinewave that is generated)
is reset to the first microstep and the absolute position counter value (Section 6.5) becomes
meaningless.
Figure 5. Normal mode and microstepping (16 microsteps)
VS
VS + V
CP D1 D2
VCP
fPUMP
to high-side
gate drivers
VS
+ V
CP V
D1
C
BOOT
C
FLY
D1D2
VBOOT CP
VDD
VV
Charge pump oscillator
AM15034v1
step 1 step 1step 2 step 3step 4 step 1
Reset
position
step 1step 2 step 3step 4
Normal driving Microstepping
PHASE A current
PHASE B current
PHASE A current
PHASE B current
microsteps
1616
microsteps
16 16
Reset
position
microstepsmicrostepsmicrosteps
AM15035v1