Siemens C500 User manual

C500
Microcontroller Family
Architecture and Instruction Set
UserÕs Manual 04.98

Edition 04.98
Published by
Siemens AG,
Bereich Halbleiter, Marketing-
Kommunikation, Balanstra§e 73,
81541 MŸnchen
© Siemens AG 1998.
All Rights Reserved.
Attention please!
As far as patents or other rights of third parties are concerned, liability is only assumed for components, not for applications, processes
and circuits implemented within components or assemblies.
The information describes the type of component and shall not be considered as assured characteristics.
Terms of delivery and rights to change design reserved.
For questions on technology, delivery and prices please contact the Semiconductor Group Offices in Germany or the Siemens Companies
and Representatives worldwide (see address list).
Due to technical requirements components may contain dangerous substances. For information on the types in question please contact
your nearest Siemens Office, Semiconductor Group.
Siemens AG is an approved CECC manufacturer.
Packing
Please use the recycling operators known to you. We can also help you Ð get in touch with your nearest sales office. By agreement we will
take packing material back, if it is sorted. You must bear the costs of transport.
For packing material that is returned to us unsorted or which we are not obliged to accept, we shall have to invoice you for any costs in-
curred.
Components used in life-support devices or systems must be expressly authorized for such purpose!
Critical components
1
of the Semiconductor Group of Siemens AG, may only be used in life-support devices or systems
2
with the express
written approval of the Semiconductor Group of Siemens AG.
1 A critical component is a component used in a life-support device or system whose failure can reasonably be expected to cause the
failure of that life-support device or system, or to affect its safety or effectiveness of that device or system.
2 Life support devices or systems are intended (a) to be implanted in the human body, or (b) to support and/or maintain and sustain hu-
man life. If they fail, it is reasonable to assume that the health of the user may be endangered.
C500 Architecture and Instruction UserÕs Manual
Revision History : 04.98 Original Version
Previous Releases: 07.96, 01.97, 09.97
Page Subjects (changes since last revision)
4-15, 4-59,
4-79
Correction: first paragraph of ÒDescriptionÓ; P is affected if <dest-byte> = A
4-16 Encoding for ANL direct,A corrected
Page Subjects (changes from 01.97 to 09.97)
4-88 Table 4-4: Mnemonics for Opcode 83
H
, 86
H
and 87
H
corrected
Page Subjects (changes from 07.96 to 01.97)
Table of
content
4-89
Reference to pages of each instruction added
Table header corrected

General Information
Table of Contents Page
Semiconductor Group I-1 1998-04-01
1 Fundamental Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1
1.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1
1.2 Memory Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2
1.2.1 Program Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2
1.2.2 Data Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3
1.2.2.1 Internal Data Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3
1.2.2.2 Internal Data Memory XRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5
1.2.2.3 External Data Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-6
1.2.3 Special Function Register Area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-6
2 CPU Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1
2.1 Accumulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2
2.2 B Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2
2.3 Program Status Word . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2
2.4 Stack Pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3
2.5 Data Pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4
2.5.1 The Importance of Additional Datapointers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5
2.5.2 How the eight Datapointers of the C500 are realized . . . . . . . . . . . . . . . . . . . . . . . . . 2-5
2.5.3 Advantages of Multiple Datapointers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6
2.5.4 Application Example and Performance Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6
2.6 Enhanced Hooks Emulation Concept . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-9
2.7 Basic Interrupt Handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-10
2.8 Interrupt Response Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-12
3 CPU Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1
3.1 Basic Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1
3.2 Accessing External Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3
3.2.1 Accessing External Program Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3
3.2.2 Accessing External Data Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4
4 Instruction Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1
4.1 Addressing Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1
4.2 Introduction to the Instruction Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-3
4.2.1 Data Transfer Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-3
4.2.2 Arithmetic Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-4
4.2.3 Logic Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-5
4.2.4 Control Transfer Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-5
4.3 Instruction Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-7
4.4 Instruction Set Summary Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-82
4.4.1 Functional Groups of Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-82
4.4.2 Hexadecimal Ordered Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-87
5 Package Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1
5.1 P-DIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1
5.2 PLCC Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2
5.3 MQFP Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-5

Fundamental Structure
C500 Family
Semiconductor Group 1-1 1998-04-01
1 Fundamental Structure
1.1 Introduction
The members of the C500 Siemens microcontroller family are basically fully compatible in
architecture and software to the standard 8051 microcontroller family. Especially, they are
functionally upward compatible to the SAB 80C52/80C32 microcontroller. While maintaining all
architectural and operational characteristics of the SAB 80C52/80C32, the C500 microcontrollers
differ in number and complexity of their peripheral units which have been adapted to the specific
application areas.
The goal of this ÒArchitecture and Instruction Set ManualÒ is to summarize the basic architecture
and functional characteristics of all members of the C500 microcontroller family. This includes the
description of the architecture and the description of the complete instruction set. Detailed
information about the different versions of the C500 microcontrollers are given in the specific User
Manuals.

Semiconductor Group 1-2 1998-04-01
Fundamental Structure
C500 Family
1.2 Memory Organization
The memory resources of the C500 family microcontrollers are organized in different types of
memories (data and program memory), which further can be located internally on the
microcontroller chip or outside of the microcontroller. The memory partitioning of the C500
microcontrollers is typical for a Harvard architecture where data and program areas are held in
separate memory areas. The on-chip peripheral units are accessed using an internal special
function register memory area.
The available memory areas have different sizes and are located in the following five address
spaces:
1.2.1 Program Memory
The program memory of the C500 family microcontrollers can be composed of either completely
external program memory, of only internal program memory (on-chip ROM / EEPROM), or of a
mixture of internal and external program memory. lf the EA pin (EA= E xternal A ccess) is held at low
level, the C500 microcontrollers execute the program code always out of the external program
memory. Romless C500 derivatives can use this type of program memory only. C500 derivatives
with on-chip program memory typically use their internal program memory only. If the internal
program memory is used the EA pin must be put to high level. With EA high, the microcontroller
executes instructions internally unless the address exceeds the upper limit of the internal program
memory. If the program counter is set to an address (e.g. by a jump instruction) which is higher than
the internal program memory, instructions are executed out of an external program memory. When
the instruction address again is below the internal program memory size limit, internal program
memory is accessed again.
Figure 1-1 shows the typical C500 family microcontroller program memory configuration for the two
cases EA=0 and EA=1. The ROM boundary shown in figure 1-1 , applies to the C501 which has 8K
byte of internal ROM. Other C500 family microcontrollers with different ROM size have different
ROM boundaries.
Table 1-1
C500 Address Spaces
Type of Memory Location Size
Program Memory External max. 64 KByte
Internal (ROM, EEPROM) Depending on C500 version
2K up to 64KByte
Data Memory External max. 64 KByte
Internal XRAM Depending on C500 version
256 Byte up to 3 KByte
Internal 128 or 256 Byte
Special Function Register Internal 128/256 Bytes

Fundamental Structure
C500 Family
Semiconductor Group 1-3 1998-04-01
Figure 1-1
Program Memory Configuration (Example of the C501)
1.2.2 Data Memory
The data memory area of the C500 family microcontrollers consists of internal and external data
memory portions. The internal data memory area is addressed using 8-bit addresses. The external
data memory and the internal XRAM data memory are addressed by 8-bit or16-bit addresses.
The content of the internal data memory (also XRAM) is not affected by a reset operation. After
power-up the content is undefined, while it remains unchanged during and after a reset as long as
the power supply is not turned off. The XRAM content is also maintained when the C500
microcontrollers are in power saving modes.
1.2.2.1 Internal Data Memory
The internal data memory address space is divided into three basic, physically separate and distinct
blocks: the lower 128 byte of internal data RAM, the upper 128 byte of internal data RAM, and the
128 byte special function register (SFR) area. The lower internal data RAM and the SFR area
further include 128 bit locations each. These bits can be handled by specific bit manipulation
instructions.
1FFF H
0000 H
Memory
Program
FFFF H
External
Internal
Program
Memory
H
2000 ROM
Boundary
EA = 1 EA = 0
External
H
FFFF
Program
Memory
H
0000
MCD02766
The location of the ROM boundary depends on the specific C500 devices.

Semiconductor Group 1-4 1998-04-01
Fundamental Structure
C500 Family
Figure 1-2 shows the configuration of the three basic internal RAM areas. The lower data RAM is
located in the address range 00H- 7FHand can be addressed directly (e.g. MOV A,direct) or
indirectly (e.g. MOV A,@R0 with address in R0). A bit-addressable area of 128 free programmable,
direct addressable bits is located at byte addresses 20H- 2FHof the lower data RAM. Bit 0 of the
internal data byte at 20Hhas the bit address 00Hwhile bit 7 of the internal data byte at 2FHhas the
bit address 7FH. The lower 32 locations of the internal lower data RAM are assigned to four banks
with eight general purpose registers (GPRs) each. Only one of these banks can be enabled at a
time to be used as general purpose registers.
Figure 1-2
Internal Data Memory Organization
MCD02767
FF FE FD FC FB FA F9 F8
FF H
F8 H
H
F0 F0
F1F2
F3
F4
F5F6
F7
H
E8 E8E9
EA
EB
EC
EDEEEF
H
E0 E0
E1E2
E3
E4
E5E6
E7
H
D8 D8D9
DA
DB
DC
DDDEDF
H
D0 D0
D1D2
D3
D4
D5D6
D7
H
C8 C8C9CACBCCCDCECF
H
C0 C0C1C2C3C4C5C6C7
H
B8 B8B9
BA
BB
BC
BDBEBF
H
B0 B0
B1B2
B3
B4
B5B6
B7
H
A8 A9A8
AA
AC
ABADAEAF
H
A0 A0
A1A2
A3
A4
A5A6
A7
H
98 9998
9A
9C
9B9D9E9F
H
90 9091929394959697
H
88 8988
8A
8C
8B8D8E8F
H
80 8081828384858687
Internal SFR Area
(direct addressable)
Byte128
7F H
7F 7E 7D 7C 3B 7A 79 78
H
30
2F H
70
7172
73
74
75
76
77
2E H
6869
6A
6B
6C
6D6E6F
2D H
6061626364656667
2C H
5859
5A
5B
5C
5D5E5F
2B H
5051525354
55
56
57
2A H
4849
4A
4B
4C
4D4E4F
29 H
40
4142
43
44
4546
47
28 H
3839
3A
3B
3C
3D3E3F
27 H
3031323334353637
26 H
2829
2A
2B
2C
2D2E2F
25 H
20
2122
23
24
2526
27
24 H
1819
1A
1B
1C
1D1E1F
23 H
10
1112
13
14
1516
17
22 H
0809
0A
0B
0C
0D0E0F
21 H
0001020304050607
H
20
R0
H
00
R1
H
01
R2
H
02
R3
H
03
R4
H
04
R5
H
05
R6
H
06
R7
H
07
08 H
1F H
18
17
H
H
10
0F
H
H
RAM Area
~
~
~
~
Registerbank 0
Registerbank 2
Registerbank 3
Registerbank 1
H
FF
H
7F
H
80
00 H
128 Byte
(indirect & direct
Lower
addressable)
Internal Data
RAM
RAM
Internal Data
addressable)
Upper
(indirect
128 Byte
1)
1) This internal RAM area is optional. Some low-end C500 family microcontrollers don't
provide this internal RAM area.
16 Bytes with 128 bitaddressable Bits

Fundamental Structure
C500 Family
Semiconductor Group 1-5 1998-04-01
While the SFR area and the upper internal RAM area share the same address locations (80H-
FFH), they must be accessed through different addressing modes. The upper internal RAM can
only be accessed through indirect addressing while the special function registers (SFRs) are
accessible only by direct addressing instructions. The SFRs which are located at addresses with
address bit 0-2 equal 0 (addresses 80H, 88H, 90H, ....F0H, FFH) are bitaddressable SFRs.
1.2.2.2 Internal Data Memory XRAM
Some members of the C500 family microcontrollers provide an additional internal data memory
area, called the XRAM. This data memory area is logically located at the upper end of the external
data memory space (except C502), but it is integrated on the chip. Because the XRAM is used in
the same way as external data memory the same instruction types must be used for accessing the
XRAM.
Figure 1-3 shows a typical 256 byte XRAM address mapping of the C500 microcontrollers.
Figure 1-3
XRAM Memory Mapping (256 Byte)
Depending on the C500 derivative, the size of the XRAM area differs from 128 upto 3K byte.
Further, the XRAM can be enabled or disabled. If an internal XRAM area is disabled, external data
memory can be accessed in the address range of the internal XRAM.
0000 H
Memory
Data
FFFF H
External
Internal
H
FFFF
XRAM
MCD02768
XRAM is located at the upper end of the external data memory area.
H
FEFF FF00 H

Semiconductor Group 1-6 1998-04-01
Fundamental Structure
C500 Family
1.2.2.3 External Data Memory
The 64 Kbyte external data memory can be addressed by instructions that use 8-bit or 16-bit indirect
addressing. A 16-bit external memory addressing mode is supported by the MOVX instructions
using the 16-bit datapointer DPTR for addressing. For 8-bit addressing MOVX instructions with the
general purpose registers R0/R1 are used.
1.2.3 Special Function Register Area
The registers of a C500 microcontroller, except the program counter and the four general purpose
register banks, reside in the special function register (SFR) area. The special function register area
typically provides 128 bytes of direct addressable SFRs. The SFRs which are located at addresses
with address bit 0-2 equal 0 (addresses 80H, 88H, 90H, ....F0H, FFH) are bitaddressable SFRs (see
also figure 1-1). For example, the SFR with byte address 80Hprovides the bit locations with bit
addresses 80Hto 87H. The bit addresses of the SFR bits reach from 80Hto FFH.
Due to the limited number of 128 standard SFRs, some derivatives of the C500 microcontroller
family provide an additional 128 byte SFR area, called the mapped SFR area. The mapped SFR
area provides the same addressing capabilities (direct addresses, bit addressing) as the standard
SFR area.
Special Function Register SYSCON (Address B1H)
As long as bit RMAP is set, mapped special function registers can be accessed. This bit is not
cleared by hardware automatically. Thus, when non-mapped/mapped registers are to be accessed,
the bit RMAP must be cleared/set by software, respectively each. Some registers (e.g. ACC) are
accessed independently of bit RMAP.
Two bits in the program status word, RS0 (PSW.3) and RS1 (PSW.4), select the active register
bank. This allows fast context switching, which is useful when entering subroutines or interrupt
service routines. The 8 general purpose registers of the selected register bank may be accessed
by register addressing. For indirect addressing modes, the registers R0 and R1 are used as pointer
or index register to address internal or external memory (e.g. MOV @R0).
Bit Function
RMAP Special function register map bit
RMAP = 0 : The access to the non-mapped (standard) special function
register area is enabled (default after reset).
RMAP = 1 : The access to the mapped special function register area is
enabled.
76543210
Ð RMAP Ð
B1HSYSCON
Bit No. MSB LSB
ÐÐ
ÐÐ Ð
The functions of the shaded bits are not described in this section.

CPU Functions
C500 Family
Semiconductor Group 2-1 1998-04-01
2 CPU Architecture
The typical architecture of a C500 family microcontroller is shown in figure 2-1 . This block diagram
includes all main functional blocks of the C500 microcontrollers. The shaded blocks are basic
functional units which are mandatory for each C500 microcontroller. The other functional blocks
such as XRAM, peripheral units, and ROM/RAM sizes are specific to each C500 microcontroller
derivative.
Figure 2-1
C500 Microcontroller Architecture Block Diagram
The core block represents the CPU (Central Processing Unit) of the C500 family microcontrollers.
The CPU consists of the instruction decoder, the arithmetic section, the CPU registers, and the
program control section. The housekeeper unit generates internal signals for controlling the
functions of the individual internal units within the microcontroller. Port 0 and port 2 are required for
accessing external code and data memory and for emulation purposes. The external control signals
and the clock generation are handled in the external control block. The access control unit is
responsible for the selection of the on-chip memory resources. The IRAM provides the internal RAM
which includes the general purpose registers. The interrupt requests from the peripheral units are
handled by an interrupt controller unit.
C500 device specific is the configuration of the on-chip peripheral units. Serial interfaces, timers,
capture/compare units, A/D converters, watchdog units, or a multiply/divide unit are typical
examples for on-chip peripheral units. The external signals of these peripheral units are available
at multifunctional parallel I/O ports or at dedicated pins.
MCB02769
RST
EA
PSEN
ALE
XTAL
Ext.
Control
Access
Control
ROM
XRAM
Housekeeper
C500 Core
(1 or 8 Datapointer)
IRAM
Interrupt
Controller
Serial
Port
Timers
WDU
MDU
Control
Parallel
Port
Peripheral
Bus
Basic functional blocks
Address Bus
Data Bus
Port0/Port2
A
D
Port
Parallel

Semiconductor Group 2-2 1998-04-01
CPU Functions
C500 Family
The arithmetic section of the core performs extensive data manipulation and is comprised of the
arithmetic/logic unit (ALU), an A register, B register and PSW register. Further, it has extensive
facilities for binary and BCD arithmetic and excels in its bit-handling capabilities. Efficient use of
program memory results from an instruction set consisting of 44% one-byte, 41% two-byte, and
15% three-byte instructions. The ALU accepts 8-bit data words from one or two sources and
generates an 8-bit result under the control of the instruction decoder. The ALU performs the
arithmetic operations add, substract, multiply, divide, increment, decrement, BDC-decimal-add-
adjust and compare, and the logic operations AND, OR, Exclusive OR, complement and rotate
(right, left or swap nibble (left four)). Also included is a Boolean processor performing the bit
operations as set, clear, complement, jump-if-not-set, jump-if-set-and-clear and move to/from carry.
Between any addressable bit (or its complement) and the carry flag, it can perform the bit operations
of logical AND or logical OR with the result returned to the carry flag.
The program control section of the core controls the sequence in which the instructions stored in
program memory are executed. The 16-bit program counter (PC) holds the address of the next
instruction to be executed. The conditional branch logic enables internal and external events to the
processor to cause a change in the program execution sequence.
2.1 Accumulator
ACC is the symbol for the accumulator register. The mnemonics for accumulator-specific
instructions, however, refer to the accumulator simply as A.
2.2 B Register
The B register is used during multiply and divide and serves as both source and destination. For
other instructions it can be treated as another scratch pad register.
2.3 Program Status Word
The Program Status Word (PSW) contains several status bits that reflect the current state of the
CPU. The bits of the PSW are used for different functions which are: two register bank selection bits,
two carry flags and an overflow flag for arithmetic instructions, a parity bit for the content of the ACC,
and two general purpose flags.
The bit definitions of the PSW are shown on the next page.

CPU Functions
C500 Family
Semiconductor Group 2-3 1998-04-01
Special Function Register PSW (Address D0H) Reset Value : 00H
2.4 Stack Pointer
The stack pointer (SP) register is 8 bits wide. It is incremented before data is stored during PUSH
and CALL executions and decremented after data is popped during a POP and RET (RETI)
execution, i.e. it always points to the last valid stack byte. While the stack may reside anywhere in
the on-chip RAM, the stack pointer is initialized to 07Hafter a reset. This causes the stack to begin
a location = 08Habove register bank zero. The SP can be read or written under software control.
Bit Function
CY Carry Flag
Used by arithmetic and conditional branch instruction.
AC Auxiliary Carry Flag
Used by instructions which execute BCD operations.
F0 General Purpose Flag
RS1
RS0
Register Bank select control bits
These bits are used to select one of the four register banks.
OV Overflow Flag
Used by arithmetic instruction.
F1 General Purpose Flag
P Parity Flag
Always set/cleared by hardware to indicate an odd/even number of "one"
bits in the accumulator, i.e. even parity.
PF1OVRS0RS1F0ACCY
01234567
LSBMSB
Bit No.
D0HPSW
RS1 RS0 Function
0 0 Registerbank 0 at data address 00H-07Hselected
0 1 Registerbank 1 at data address 08H-0FHselected
1 0 Registerbank 2 at data address 10H-17Hselected
1 1 Registerbank 3 at data address 18H-1FHselected

Semiconductor Group 2-4 1998-04-01
CPU Functions
C500 Family
2.5 Data Pointer
8-bit accesses to the internal XRAM data memory or the external data memory are executed using
the data pointer DPTR as an 16-bit address register. Normally, the C500 family microcontrollers
have one data pointer. But some members of the C500 family provide eight data pointers. The
availability of eight data pointers especially supports the programming in high level languages which
have a demand to store data in large external data memory portions.
Special Function Register DPL (Address 82H) Reset Value : 00H
Special Function Register DPH (Address 83H) Reset Value : 00H
Special Function Register DPSEL (Address D0H) Reset Value : 00H
Bit Function
Ð Reserved bits for future use
DPSEL.2 - 0 Data pointer select bits
DPSEL.2-0 defines the number of the actual active data pointer.DPTR0-7.
LSB.1.2.3.4.5.6.7
01234567
LSBMSB
Bit No.
82HDPL
.0.1.2.3.4.5.6MSB83HDPH
.0.1.2ÐÐÐÐÐ92HDPSEL
DPSEL2 DPSEL1 DPSEL0 Function
0 0 0 Data pointer 0 selected
0 0 1 Data pointer 1 selected
0 1 0 Data pointer 2 selected
0 1 1 Data pointer 3 selected
1 0 0 Data pointer 4 selected
1 0 1 Data pointer 5 selected
1 1 0 Data pointer 6 selected
1 1 1 Data pointer 7 selected

CPU Functions
C500 Family
Semiconductor Group 2-5 1998-04-01
2.5.1 The Importance of Additional Datapointers
The standard 8051 architecture provides just one 16-bit pointer for indirect addressing of external
devices (memories, peripherals, latches, etc.). Except for a 16-bit "move immediate" to this
datapointer and an increment instruction, any other pointer handling is to be done byte by byte. For
complex applications with peripherals located in the external data memory space (e.g. CAN
controller) or extended data storage capacity this turned out to be a "bottle neck" for the 8051Õs
communication to the external world. Especially programming in high-level languages (PLM51,
C51, PASCAL51) requires extended RAM capacity and at the same time a fast access to this
additional RAM because of the reduced code efficiency of these languages.
2.5.2 How the eight Datapointers of the C500 are realized
Simply adding more datapointers is not suitable because of the need to keep up 100% compatibility
to the 8051 instruction set. This instruction set, however, allows the handling of only one single 16-
bit datapointer (DPTR, consisting of the two 8-bit SFRs DPH and DPL).
To meet both of the above requirements (speed up external accesses, 100% compatibility to 8051
architecture) the C500 contains a set of eight 16-bit registers from which the actual datapointer can
be selected.
This means that the userÕs program may keep up to eight 16-bit addresses resident in these
registers, but only one register at a time is selected to be the datapointer. Thus the datapointer in
turn is accessed (or selected) via indirect addressing. This indirect addressing is done through a
special function register called DPSEL (data pointer select register). All instructions of the C500
which handle the datapointer therefore affect only one of the eight pointers which is addressed by
DPSEL at that very moment.
Figure 5-1 illustrates the addressing mechanism: a 3-bit field in register DPSEL points to the
currently used DPTRx. Any standard 8051 instruction (e.g. MOVX @DPTR, A - transfer a byte from
accumulator to an external location addressed by DPTR) now uses this activated DPTRx.

Semiconductor Group 2-6 1998-04-01
CPU Functions
C500 Family
Figure 2-2
Accessing of External Data Memory via Multiple Datapointers
2.5.3 Advantages of Multiple Datapointers
Using the above addressing mechanism for external data memory results in less code and faster
execution of external accesses. Whenever the contents of the datapointer must be altered between
two or more 16-bit addresses, one single instruction, which selects a new datapointer, does this job.
lf the program uses just one datapointer, then it has to save the old value (with two 8-bit instructions)
and load the new address, byte by byte. This not only takes more time, it also requires additional
space in the internal RAM.
2.5.4 Application Example and Performance Analysis
The following example shall demonstrate the involvement of multiple data pointers in a table
transfer from the code memory to external data memory.
Start address of ROM source table: 1FFFH
Start address of table in external RAM: 2FA0H
DPH(83 ) DPL(82 )
DPTR0
DPTR7
.0.1.2 -----
DPSEL(92 )
DPSEL Selected
Data-
pointer
.2 .1 .0
DPTR 0000
0 0 1 DPTR 1
0 1 0 DPTR 2
0 1 1 DPTR 3
1 0 0 DPTR 4
1 0 1 DPTR 5
1 1 0 DPTR 6
1 1 1 DPTR 7
MCD00779
External Data Memory
H
HH

CPU Functions
C500 Family
Semiconductor Group 2-7 1998-04-01
Example 1 : Using only One Datapointer (Code for a C501)
Initialization Routine
MOV LOW(SRC_PTR), #0FFH ;Initialize shadow_variables with source_pointer
MOV HIGH(SRC_PTR), #1FH
MOV LOW(DES_PTR), #0A0H ;Initialize shadow_variables with destination_pointer
MOV HIGH(DES_PTR), #2FH
Table Look-up Routine under Real Time Conditions
; Number of cycles
PUSH DPL ;Save old datapointer 2
PUSH DPH ; 2
MOV DPL, LOW(SRC_PTR) ;Load Source Pointer 2
MOV DPH, HIGH(SRC_PTR) ; 2
;INC DPTR Increment and check for end of table (execution time
;CJNE É not relevant for this consideration) Ð
MOVC A,@DPTR ;Fetch source data byte from ROM table 2
MOV LOW(SRC_PTR), DPL ;Save source_pointer and 2
MOV HIGH(SRC_PTR), DPH ;load destination_pointer 2
MOV DPL, LOW(DES_PTR) ; 2
MOV DPH, HIGH(DES_PTR) ; 2
INC DPTR ;Increment destination_pointer
;(ex. time not relevant) Ð
MOVX @DPTR, A ;Transfer byte to destination address 2
MOV LOW(DES_PTR), DPL ;Save destination_pointer 2
MOV HIGH(DES_PTR),DPH ; 2
POP DPH ;Restore old datapointer 2
POP DPL ; 2
; Total execution time (machine cycles) : 28

Semiconductor Group 2-8 1998-04-01
CPU Functions
C500 Family
Example 2 : Using Two Datapointers (Code for a C509)
Initialization Routine
MOV DPSEL, #06H ;Initialize DPTR6 with source pointer
MOV DPTR, #1FFFH
MOV DPSEL, #07H ;Initialize DPTR7 with destination pointer
MOV DPTR, #2FA0H
Table Look-up Routine under Real Time Conditions
; Number of cycles
PUSH DPSEL ;Save old source pointer 2
MOV DPSEL, #06H ;Load source pointer 2
;INC DPTR Increment and check for end of table (execution time
;CJNE É not relevant for this consideration) Ð
MOVC A,@DPTR ;Fetch source data byte from ROM table 2
MOV DPSEL, #07H ;Save source_pointer and
;load destination_pointer 2
MOVX @DPTR, A ;Transfer byte to destination address 2
POP DPSEL ;Save destination pointer and
;restore old datapointer 2
; Total execution time (machine cycles) : 12
The above example shows that utilization of the C500Õs multiple datapointers can make external
bus accesses two times as fast as with a standard 8051 or 8051 derivative. Here, four data variables
in the internal RAM and two additional stack bytes were spared, too. This means for some
applications where all eight datapointers are employed that an C500 program has up to 24 byte (16
variables and 8 stack bytes) of the internal RAM free for other use.

CPU Functions
C500 Family
Semiconductor Group 2-9 1998-04-01
2.6 Enhanced Hooks Emulation Concept
The Enhanced Hooks Emulation Concept of the C500 microcontroller family is a new, innovative
way to control the execution of C500 MCUs and to gain extensive information on the internal
operation of the controllers. Emulation of on-chip ROM based programs is possible, too.
Each production chip has built-in logic for the support of the Enhanced Hooks Emulation Concept.
Therefore, no costly bond-out chips are necessary for emulation. This also ensure that emulation
and production chips are identical.
The Enhanced Hooks Technology
TM
, which requires embedded logic in the C500, allows the C500
together with an EH-IC to function similar to a bond-out chip. This simplifies the design and reduces
costs of an ICE-system. ICE-systems using an EH-IC and a compatible C500 are able to emulate
all operating modes of the different versions of the C500. This includes emulation of ROM, ROM
with code rollover and ROMless modes of operation. It is also able to operate in single step mode
and to read the SFRs after a break.
Figure 2-3
Basic C500 MCU Enhanced Hooks Concept Configuration
Port 0, port 2 and some of the control lines of the C500 based MCU are used by Enhanced Hooks
Emulation Concept to control the operation of the device during emulation and to transfer
informations about the program execution and data transfer between the external emulation
hardware (ICE-system) and the C500 MCU.
MCS02647
SYSCON
PCON
TCON
RESET
EA
PSEN
ALE
Port 0
Port 2
I/O Ports
Optional
Port 3 Port 1
C500
MCU Interface Circuit
Enhanced Hooks
RPort 0RPort 2
RTCON
RPCON
RSYSCON
TEA TALE TPSEN
EH-IC
Target System Interface
ICE-System Interface
to Emulation Hardware

Semiconductor Group 2-10 1998-04-01
CPU Functions
C500 Family
2.7 Basic Interrupt Handling
Each member of the C500 microcontroller family provides several interrupt sources. These
interrupts are generated typically by external events or by the internal peripheral units. If an interrupt
is accepted by the CPU, the microcontroller interrupts a running program and proceeds the program
execution at an interrupt source specific vector address where the interrupt service routine is
located. After the execution of a RETI (return from interrupt) instruction the program is continued at
the point where it has been interrupted. Figure 2-4 shows an example for the interrupt vector
addresses of a C500 microcontroller (C501). Generally, interrupt vector addresses are located in
the code memory area starting at address 0003H. The minimum distance between two consecutive
vector addresses is always 8 bytes. Therefore, interrupt vectors can be assigned to the following
addresses: 0003H, 000BH, 0013H, 001BH, 0023H, 002BH, 0033H...... 00FBH.
Figure 2-4
Interrupt Vector Addresses (Example of the C501)
An interrupt source indicates to the interrupt controller an interrupt condition by setting an interrupt
request flag. The interrupt request flags are sampled in each machine cycle. The sampled flags are
polled during the following machine cycle. If one of the flags was in a set condition in the preceeding
cycle, the polling cycle will find it and the interrupt controller will cause the CPU to branch to the
vector address of the appropriate service routine by generating an internal LCALL. This hardware-
generated LCALL is blocked by any of the following conditions:
1. An interrupt of equal or higher priority is already in progress.
2. The current (polling) cycle is not in the final cycle of the instruction in progress.
3. The instruction in progress is RETI or any write access to interrupt enable or priority registers.
MCD02770
~
~~
~
8 Bytes
H
002B
0023 H
001B H
0013 H
000B H
0003 H
0000 H
Memory
Program
Timer 2
Interrupt
Interrupt
Serial Port
Interrupt
Timer 1
External
Interrupt 1
Interrupt
Timer 0
Interrupt 0
External
Reset
FFFF H

CPU Functions
C500 Family
Semiconductor Group 2-11 1998-04-01
Any of these three conditions will block the generation of the LCALL to the interrupt service routine.
Condition 2 ensures that the instruction in progress is completed before vectoring to any service
routine. Condition 3 ensures that if the instruction in progress is RETI or any write access to interrupt
enable or interrupt priority registers, then at least one more instruction will be executed before any
interrupt is vectored too; this delay guarantees that changes of the interrupt status can be observed
by the interrupt controller.
The polling cycle is repeated with each machine cycle, and the values polled are the values that
were present at the previous machine cycle. Note that if any interrupt flag is active but not being
responded to for one of the conditions already mentioned, or if the flag is no longer active when the
blocking condition is removed, the denied interrupt will not be serviced. In other words, the fact that
the interrupt flag was once active but not serviced is not remembered. Every polling cycle
interrogates only the pending interrupt requests.
The polling cycle/LCALL sequence is illustrated in figure 2-1 .
Figure 2-5
Interrupt Detection/Entry Diagram
Note that if an interrupt of a higher priority level goes active prior to S5P2 in the machine cycle
labeled C3 in figure 2-5 then, in accordance with the above rules, it will be vectored to during C5
and C6 without any instruction for the lower priority routine to be executed.
Thus, the processor acknowledges an interrupt request by executing a hardware-generated LCALL
to the appropriate servicing routine. In some cases it also clears the flag that generated the
interrupt, while in other cases it does not; then this has to be done by the user's software.
The program execution proceeds from that location until the RETI instruction is encountered. The
RETI instruction informs the processor that the interrupt routine is no longer in progress, then pops
the two top bytes from the stack and reloads the program counter. Execution of the interrupted
program continues from the point where it was stopped. Note that the RETI instruction is very
important because it informs the processor that the program left the current interrupt priority level.
A simple RET instruction would also have returned execution to the interrupted program, but it
would have left the interrupt control system thinking an interrupt was still in progress. In this case no
interrupt of the same or lower priority level would be acknowledged.
MCT01859
S5P2
Interrupt
is latched
Interrupts
are polled Vector Address
Long Call to Interrupt
Routine
Interrupt
C2C1 C3 C4 C5