SightLine EAN-4000-OEM User manual

© SightLine Applications, Inc
EAN-4000-OEM MIPI Cameras
2020-11-02
Exports: Export Summary Sheet
EULA: End User License Agreement
Web: sightlineapplications.com
Sales: sale[email protected]
Support: [email protected]
Phone: [phone]
1Overview ................................................................1
1.1 Additional Support Documentation.......................1
1.2 SightLine Software Requirements..........................1
2Optional Interface Boards and Adapters ...............1
3Hardware Connections...........................................1
3.1 4000-OEM MIPI Camera Bench Setup ...................1
4Configuration Settings............................................2
4.1 Acquisition Settings................................................3
5Vision Components VC-MIPI-IMX412 Camera .......3
5.1 Hardware Connection ............................................3
5.2 Exposure, Gain and White Balance ........................4
5.2.1 Manual Control ......................................................4
5.2.2 Automatic Exposure and Gain................................5
5.3 2x Binning Support.................................................6
5.3.1 Hardware Crop - 2x Vertical / Horizontal Binning..7
5.4 Hardware Crop - 4056 x 3040 Image .....................8
5.5 I2C Communication................................................9
6Troubleshooting...................................................10
6.1 Determining Settle-cnt.........................................10
7Questions and Additional Support.......................10
Appendix A - MIPI Camera Requirements for Connecting
Commercial Cameras......................................................10
A1 Vendor Provided Driver / Interface .....................10
A2 Raw Capture Only ................................................11
A3 Connector Requirements.....................................12
Appendix B - MIPI Camera Capture Requirements -
Custom MIPI Inputs ........................................................12
B1 MIPI Packet Format..............................................13
B2 MIPI Packet Timing ..............................................14
B3 Acquisition Settings for MIPI Configuration - Tx
Lanes and MIPI Clock Rate...................................14
B4 FPGA I2C Control of Camera Acquisition
(Optional).............................................................15
CAUTION: Alerts to a potential hazard that may result in personal injury, or an unsafe practice that causes damage to the equipment
if not avoided
IMPORTANT: Identifies crucial information that is important to setup and configuration procedures.
Used to emphasize points or reminds the user of something. Supplementary information that aids in the use or understanding of the
equipment or subject that is not critical to system use.

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1Overview
This document describes how to configure the SightLine 4000-OEM video processing board to receive
video from MIPI camera modules.
1.1 Additional Support Documentation
Additional Engineering Application Notes (EANs) can be found on the Documentation page of the
SightLine Applications website.
The Panel Plus User Guide provides a complete overview of settings and dialog windows located in the
Help menu of the Panel Plus application.
The Interface Command and Control (IDD) describes the native communications protocol used by the
SightLine Applications product line. The IDD is also available as a PDF download on the Documentation
page under Software Support Documentation.
1.2 SightLine Software Requirements
4000-OEM: Version 3.00.xx and higher.
IMPORTANT: The Panel Plus software version should match the firmware version running on the
board. Firmware and Panel Plus software versions are available on the Software Download page.
2Optional Interface Boards and Adapters
Additional system interface boards provide options for network interfacing, serial ports, and GPIO.
Camera interface and adapter boards provide an interface from the camera to OEM. See the ICD-3000-
4000 Adapter Boards for complete specifications and pinouts.
IMPORTANT: All boards should be connected and secured with the included cables and hardware
fasteners first before applying power.
3Hardware Connections
3.1 4000-OEM MIPI Camera Bench Setup
Connecters and cables for supported cameras are provided in the 4000-MIPI camera kit - PN: SLA-KIT-
4000-MIPI-CAM.
Cable connections:
•SLA-CAB-MIPI-02: MIPI camera and 4000-OEM interface. Connects to J9 on 4000-OEM board and to
the MIPI camera cable and adapter board. Provides serial communication and digital video to the
camera.
SLA-CAB-MIPI-02 is an FFC cable and must be oriented and connected correctly for the camera to
operate. See FFC cable instructions and precautions before connecting the cable.
•SLA-CAB-0403: Connects to J4 on the 4000-OEM board. Provides an RJ45 Ethernet connection.
•SLA-CAB-1504 / SLA-PWR-B12V-36W: Connects to J50 on the 4000-OEM board and AC power
source.

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Power and network connectivity LEDs:
A green light (D1) on the 4000-OEM board indicates that all boards are powered on. An amber light
(D5) verifies network connection.
Figure 1: 4000-OEM MIPI Camera Bench Setup
4Configuration Settings
This section covers the basic camera configuration settings in Panel Plus for the SightLine 4000-OEM
video processing board.
Before connecting with the Panel Plus software, the OEM board should be powered up and connected
through:
-a network switch or directly to the host PC (preferred) or,
-Direct serial connection (for troubleshooting or if a network connection cannot be established).
See the EAN-Startup Guide 4000-OEM for connection and video streaming instructions.
IMPORTANT: This procedure assumes that the customer has read the OEM startup guide(s) and
has a basic understanding of the following fundamentals:
•Completed a functional connection between the SightLine video processing board and Panel
Plus application
•Familiar with Panel Plus controls
•Successfully streamed video in Panel Plus
If you do not have a strong basic system setup and familiarity, we recommend reviewing the OEM
startup guide and work with our support team to establish basic connection and streaming
fundamentals.
Network Switch or PC Direct
SLA-CAB-1504 (J50)
Serial (SLA-CAB-504)
SLA-CAB-0403 (J4)
4000-OEM
RJ45 Ethernet
SLA-PWR-B12V-36W
Optional Serial SLA-CAB-0305
USB to PC
SLA-CAB-0804
SLA-CAB-MIPI-02 (J9)
MIPI
Camera
The camera is immediately
powered on when power is
connected to the OEM board.
(J6)
Optional Camera
Adapter Boards
MIPI Camera
Cable
4000-P122 Board

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4.1 Acquisition Settings
From the main menu in Panel Plus go to Configure » Acquisition Settings. If available, use the Auto Fill
drop down menu in the Acquisition Settings dialog to automatically populate the relevant fields with
the correct settings. The settings can also be manually entered as shown in Table 1.For information
about Acquisition fields in Panel Plus see EAN-Digital Video Configuration.
IMPORTANT: Save parameters and reset the board when changing parameters. Cycle system
power when changing resolution.
If video does not display, try saving and activating the settings again. Check the encoding settings
on the Compression tab and review the network addresses for the destination video.
Table 1: 4000-OEM Panel Plus Basic Acquisition Settings
Digital Cameras
Camera Index = Cam 0
Camera Type = Generic Digital
Acquisition Settings
Auto Fill
Height
Width
VFP
HFP
Bits
Input
Invert VSync
Invert HSync
Sync/Crop
Init Code
Flags
Vision Components
VC-MIPI OV9281
Mono
Vision Components
OV9281 Mono
800
1280
0
0
10
Gray
None
None
None
None
0x0
Configuration notes: Requires software version 3.01.xx and above. Enter flag <mipi=ov9281> in the Options field.
VC-MIPI IMX296
Mono
Vision Components
IMX296 Mono
1080
1440
0
0
10
Gray
None
None
None
None
0x0
Configuration notes: Requires software version 3.01.xx and above. Enter flag <mipi=imx296> in the Options field.
VC-MIPI IMX412
Color
Vision Components
IMX412 Color
2160
3840
0
0
10
Bayer
None
None
None
None
0x3
Configuration notes: Requires software version 3.01.xx and above. Enter flag <mipi=imx412> in the Options field.
5Vision Components VC-MIPI-IMX412 Camera
The IMX412 camera is a 4056 wide by 3040 high 10-bit Bayer imager that can use two or four MIPI data
lanes (Figure 2). The Auto Fill option is only for two MIPI data lanes.
Supported display resolutions are full 4K (3840x2160), 1080p, and 720p. Big snapshot supported
resolutions are 4056x3040, 4k, 1080p, and 720p.
Software 3.01, and higher, have a higher frame rate than software version 3.00, per improvements.
5.1 Hardware Connection
The VC-MIPI-IMX412 connects to the 4000-OEM J9 connector by using the components in the SLA-KIT-
4000-MIPI-CAM:
•SLA-CAB-MIPI-02 FFC Cable
•SLA-4000-PI22 ribbon interface board. Converts 30 pin OEM interface to 22 pin camera interface.
•The camera to SLA-4000-PI22 ribbon cable must be purchased with the camera from Vision
Components.

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Figure 2: Acquisitions Settings - Four MIPI Data Lanes
5.2 Exposure, Gain and White Balance
5.2.1 Manual Control
The 4000-OEM uses values from user input for exposure (integration time), gain and white balance
(red, green, and blue gains). These values can be adjusted from Panel Plus » Video tab » Image Control
(Figure 3).
In the IDD Exposure (integration time), Luma (analog gain), Red/Green/Blue (digital color gains) can be
adjusted using the Set ADC Parameter (0x18) command.
Exposure
Sets the integration time of the sensor. A higher setting is better for noise, lower is better for fast
motion. For IMX412, 0 maps to 8 lines of exposure, 255 maps to 2048 lines of exposure.
If this setting is too high, it may result in motion blur with a moving camera.
Luma
This is a gain applied on the sensor before the ADC. Increase it to get a brighter image. 0 to 255 maps
to the minimum to maximum gain available on the sensor.

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Red/Green/Blue
These are digital gains applied in the sensor after the ADC. Make small adjustments of individual gains
to achieve white balanced color. Increase them all together to get a brighter image. For lowest noise,
keep Red/Green/Blue as small as possible and increase Exposure and Luma instead to get brighter
image. 0 to 255 maps to the minimum to maximum gain available on the sensor.
Figure 3: Image Control - Panel Plus Video Tab
5.2.2 Automatic Exposure and Gain
New in 3.2.x software. The 4000-OEM supports automatic exposure and gain control for the Vision
Component IMX412 camera by automatically controlling the exposure and gains.
The system calculates the mean value over a specified ROI and then adjusts exposure and gains to
move the mean towards the target value. This is specified in the Brightness control in the Image
Control section on the Video tab in Panel Plus.
Brightness controls are on the Video tab under Image Control. Brightness sets the target value for
how bright the scene should be.
Automatic exposure and gain controls are on the Thermal tab in Panel Plus.
Figure 4: Auto Gain Controls - Panel Plus Thermal Tab

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Camera Auto Exposure Gain: This is enabled by selecting it in the dropdown menu. Choose other
settings for manual exposure and gain control.
AutoGain ROI: Sets the region that auto gain is calculated.
AutoGain Min Range: The system will stop changing if the mean is within this value of target. A small
non-zero value can reduce the auto gain solution from bouncing around. This value should be 10 or
less.
AutoGain Rate:This is the auto gain step size. Larger values force larger auto gain steps. 32 is the
default.
Minimum/Maximum Exposure:Limits the exposure range.
Auto gain algorithm notes:
•For best image quality, the system attempts to do the following in order: maximize exposure,
analog gain, digital gain.
•To make a scene brighter first increase the exposure. If the exposure is at maximum increase the
analog gain (luma). If the analog gain is set at maximum, increase the digital red, green and blue
gains. Auto gain moves the RGB gains together, increasing or decreasing them by equal amounts.
•To make a scene darker reduce digital gain, reduce analog gain, and then reduce exposure.
Coming soon - Automatic white balance.
5.3 2x Binning Support
This example shows a 4k image that is 2x binned vertically and horizontally to 1080p.
Figure 4: Acquisition Settings - 2x Binning Support

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The image represented by the red box shown in Figure 5 is taken out of the full image. It is 1920*2
(width) and 1080*2 (height) and binned (downsampled) by 2 to produce a 1920x1080 output image.
Figure 5: Downsampled 1920 x 1080 Image
5.3.1 Hardware Crop - 2x Vertical / Horizontal Binning
Images can also be cropped from the active image area using the Hardware Crop function. In
Acquisitions Settings dialog set the Horizontal Front Porch and Vertical Front Porch values, and then
select Hardware Crop in the Sync/Crop dropdown menu.
Horizontal Front Porch (HFP) and Vertical Front Porch (VFP) are applied to the full image as a starting
point to the start of the image to be binned.
Figure 6: Acquisition Settings - Hardware Crop - 2x Vertical / Horizontal Binning

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The image represented by the red box shown in Figure 7 is the image that will be binned
(downsampled) by 2 in the vertical and horizontal to get a 1920x1080 image.
The maximum HFP in the above image is 4056 - (1920*2) = 216.
The maximum VFP in the above image is 3040 - (1080*2) = 880.
Figure 7: Downsampled 1920 x 1080 Image
5.4 Hardware Crop - 4056 x 3040 Image
The example in Figure 9 shows a 1080p image cropped from the center of the 4056x3040 image using
the following Panel Plus Acquisition Settings shown in Figure 8.
Horizontal Front Porch: (4056-1920) /2 = 1068
Vertical Front Porch: (3040-1080)/2 = 980
Syn/Crop: Hardware Crop
Figure 8: Acquisition Settings - Hardware Crop - 4056 x 3040 Image

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Figure 9: 1080p Image Cropped from 4056 x 3040 Image
5.5 I2C Communication
MIPI cameras use the I2C Command (0x94) to communicate with the attached sensor. Use the Send Raw
Message dialog window to set a register in the sensor. Panel Plus main menu » File » Send Command.
For example, to set a register 0x0204 to a value of 0x01, send this command as shown in Figure 10.
The address of the IMX412 is 0x1a. Contact Sony to get a list of register descriptions and settings.
Figure 10: I2C Sensor Communication - Gain
It is possible to use Linux commands to read a register on the sensor from the command line, but
this is not a reliable process.

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6Troubleshooting
6.1 Determining Settle-cnt
In the 4000-OEM FPGA, a Ths-Prepare and THS-Zero are set. Each MIPI camera has a Ths-Settle. The
Ths-Settle (settle-cnt) is calculated in the 4000-OEM using the camera driver setting for
V4L2_CID_PIXEL_RATE.
If captured video looks incorrect or not capturing at all, adjust the V4L2_CID_PIXEL_RATE in the camera
driver so that a different settle-cnt is calculated.
7Questions and Additional Support
For questions and additional support, please contact Support. Additional support documentation and
Engineering Application Notes (EANs) can be found on the Documentation page of the SightLine
Applications website.
Appendix A - MIPI Camera Requirements for Connecting Commercial Cameras
Every commercial MIPI camera requires a Linux driver to work with any acquisition system. Camera
registers are vendor and model specific and must be configured over the MIPI I2C bus. Each camera
has different operating characteristics and requirements for proper operation. Currently a standard
interface for MIPI camera register setup and operations does not exist. For new MIPI cameras working
through configuration issues takes time. Reusing driver code from other cameras in most cases does
not work.
It is essential to address the Linux driver availability for new MIPI camera early in the process.
A1 Vendor Provided Driver / Interface
The vendor provided driver/interface does not use Snapdragon 820 ISP. A Linux driver must be
provided.
•Linux driver with I2C register settings. Helpful when setting up the camera and turning on
streaming.
•Linux driver settings must be for raw capture. The 4000-OEM only supports raw capture.
•Linux driver to include V4L2_CID_LINK_FREQ and V4L2_CID_PIXEL_RATE settings.
•SightLine recommends the device tree source file (overlay) for the DragonBoard 820c. This shows
data lanes, clock lanes, clock settings, and the I2C address of the sensor.
•Four data lanes are available at the J9 connector on the 4000-OEM.
•If available, a datasheet and register explanation for the camera.
•Maximum of 750MHz pixel clock frequency (1.5Gbps / lane).
•SightLine recommends the sensor have an ISP (Sony IMX sensors do not).
A raw capture using a sensor that does not have ISP will appear substandard. This would require
additional color 10-bit to 8-bit conversion using auto gain, brightness, and white balance.
•Format of the image - width, height, media bus format.

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Linux and board compatibility notes:
•DragonBoard 820c: 96Boards compliant board based on the Snapdragon 820 processor.
•Smart Wireless Computing SOM: Used on the 4000-OEM (IFC6601 SOM).
•96Boards: Linaro kernel / images (DB410C / DB820C Debian, OE)
A2 Raw Capture Only
Raw capture does not use Snapdragon 820 ISP.
The following are supported media bus formats for the Snapdragon:
YUYV/UYVY/YVYU/VYUY (packed YUV 4:2:2):
•V4L2_PIX_FMT_YUYV
•V4L2_PIX_FMT_UYVY (supported)
•V4L2_PIX_FMT_YVYU
•V4L2_PIX_FMT_VYUY
MIPI RAW8 - 8-bit Bayer (raw):
•V4L2_PIX_FMT_SRGGB8
•V4L2_PIX_FMT_SGRBG8
•V4L2_PIX_FMT_SGBRG8
•V4L2_PIX_FMT_SBGGR8
MIPI RAW10 - 10-bit packed Bayer (raw):
•V4L2_PIX_FMT_SBGGR10P
•V4L2_PIX_FMT_SGBRG10P
•V4L2_PIX_FMT_SGRBG10P
•V4L2_PIX_FMT_SRGGB10P (supported)
MIPI RAW12 - 12-bit packed Bayer (raw):
•V4L2_PIX_FMT_SRGGB12P
•V4L2_PIX_FMT_SGBRG12P
•V4L2_PIX_FMT_SGRBG12P
•V4L2_PIX_FMT_SRGGB12P
The 4000-SOM currently has support for V4L2_PIX_FMT_UYVY and V4L2_PIX_FMT_SRGGB10P
media bus formats.

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A3 Connector Requirements
•Four data lanes.
•One clock lane.
•Reset and standby for camera
control in Linux driver.
•I2C lines for setting register in the
camera, used by the Linux driver.
Figure A1: MIPI Connector Pinout
Appendix B - MIPI Camera Capture Requirements - Custom MIPI Inputs
This section covers requirements for customers that externally convert camera data into MIPI signals
input to the 4000-OEM. The system consists of a camera, an acquisition system, and an FPGA that can
generate MIPI signals.
The ICD-4000-OEM contains details on implementing a design with external FPGAs to interface with
the 4000-OEM. See the Customer Designed 4000-OEM Boards and Camera Interface Options section in
the ICD.
The MIPI camera interface consists of a clock signal and 1, 2 or 4 data lanes. The number of data lanes
depends on the camera frame rate and resolution. The MIPI standard also provides for an I2C bus for
camera configuration that may not be used in customer FPGA implementations.
IMPORTANT: When designing a custom MIPI (FPGA) camera board, it is important to include a way
to externally reset the FPGA and camera state machine. The commercial MIPI cameras that
SightLine supports utilize the I2C bus (over MIPI) and a Linux driver that allows for a camera reset
at appropriate times. An example would be to design an external connection to a 4000-OEM GPIO
pin or to design in an I2C to GPIO/serial bridge chip similar to the design on the 4000-MIPI adapter
board.
MIPI was designed to support cell phone cameras, which are color cameras in 8, 10, and 12 bits. There
is no support in the packet types for 14-bit IR grayscale cameras or 16-bit YCbCr cameras.

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The 4000-OEM uses the MIPI as a transport layer. The data packets are received by the processor and
treated as bytes. These bytes are then assumed to be in the format set in the acquisition parameters
persisted on the OEM. The next describe the MIPI packet format used to transport video data from
different supported cameras.
All MIPI data elements are 8-bits. Since multiple pixel values are grouped together to create data
that is divisible by 8, 10-bit color video will have a group containing the upper 8-bits of 4 pixels,
followed by a single 8-bit value that contains the lower 2-bits of the 4 pixel group. This results in
5x8-bit values to represent 4x10 bit pixels. SightLine camera support uses a full 16-bits (into 2x8) for
camera pixel values that are 14-bits. This makes the encoding simpler and there is enough
bandwidth in the MIPI bus.
B1 MIPI Packet Format
Table B1: MIPI Packet Formats
Camera Format
MIPI Type
ID,Lanes,Gear
Pkt Width
Capture Setting
Note
14/16-bit Grayscale
YUV422_8
0x1E, 2, 8
x2
Gray, bits=16
IR Camera
8-bit Grayscale
YUV422_8
0x1E, 2, 8
x1
Gray, bits=8
IR Camera
16-bit YCbCr (HD)
YUV422_8
0x1E, 2, 8
x2
YUV, bits=16
BT.1120
8-bit YCbCr (SD)
YUV422_8
0x1E, 2, 8
x2
YUV, bits=8
BT.656, NTSC/PAL
8-bit Bayer
YUV422_8
0x1E, 2, 8
x1
Bayer, bits=8
AGS720P Color
Data conversion for current (non MIPI) cameras:
•YUV422_8 packet. The packet width is optionally doubled to support 2x8-bit (16-bit data).
•16-bit data order is low byte, then high byte (little endian). We recommend providing for byte-
swap in custom FPGAs.
•Number of MIPI Tx Lanes = 2 (4-lanes for high resolution cameras coming soon).
•The data packets are received by the OEM processor and treated as bytes. They are then assumed
to be in the format set in the acquisition parameters persisted on the OEM (G16, YCbCr16,G8).
•The pixel width entered in the acquisition parameters setting is not doubled but is inferred by the
other capture parameters (bits=16/8).
•The number of rows is set by the number of packets sent between FS (Frame Start) and FE (Frame
End). Each packet is a row of data.
•Normally there is no blanking in the MIPI data, only active pixels are included. OEM system
processing provides ROI (Region of Interest) within a larger frame if you want to include blanking in
your packets. However, this adds capture overhead and reduces processing rates on the system.
•For a diagram of CSI-2 packets see page 17 in the Camera Serial Interface CSI-2 and CSI-3 document
from Mipi Alliance.

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B2 MIPI Packet Timing
The following parameters will depend on the pixel clock rate of the camera:
IMPORTANT: The high speed (HS) clock mode may require a new release of 4000-OEM firmware.
Contact Support for details.
•Low power states are used between short and long packets. See the CSI-2 packets in the previous
section. This means that timing during the transition from low power to high speed mode needs to
be specified. This is dependent on the pixel clock of the camera and therefore the MIPI Tx clock.
•This timing is covered by T-HS-PREPARE and T-HS-ZERO:
▪The timing diagram can be referenced in page 3 in the Tektronix App note on Mipi timing.
▪The timing parameters should be specified by the documentation in the MIPI IP package used
to generate the MIPI packets. This will be dependent on the camera pixel clock.
▪Figure 11 shows how a scope trace can be used to measure and compare values as the FPGA
code is being developed. The trace in this example was taken off the N phase of Tx Lane 0 (the P
phase looks different).
Figure B1: MIPI Packet Low Power to High Speed Transition
B3 Acquisition Settings for MIPI Configuration - Tx Lanes and MIPI Clock Rate
The 4000-OEM needs MIPI transmit information to be able to detect and capture the MIPI packets.
The following new settings shown in Table B2 are available in the 3.2.x software release. Settings are
set as comma separated values (CSV) in the Options field in the Acquisition Settings dialog.
Figure B2: Options Field - Mipi Acquisition Settings

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Table B2: MIPI Acquisition Settings
MIPI Settings
Setting Notes
mipi_txl=1
•The number of Tx lanes.
•Valid values are 1, 2, and 4.
•Requires a parameter save and board reset.
•Changing the number of Tx Lanes will update the TSettle count automatically.
mipi_clk=74
•MIPI clock rate in MHz. This will vary based on camera input pixel clock.
•This affects both the MIPI CSI frequency and the TSettle count.
•The CSI frequency is comparable to a sampling rate, and the TSettle count the number of
samples where it looks for the packet. The CSI frequency changes in discrete intervals.
•The CSI frequency will be either 100 MHz, 200 MHz, 266 MHz.
•Used when the 4000-MIPI cannot acquire packets from a camera source due to packet
timing incompatibility with default driver settings.
•Requires a parameter save and board reset.
The above parameter values shown in Table B2 and their effects can be seen in the debug port (Serial
0) output of the 4000-OEM. Accessing the debug serial port requires the use of the 4000-DEBUG board.
See the ICD-4000-OEM for details.
The debug serial port output defaults to 115,200 baud.
The CSI Frequency is shown in the debug output line:
Setting csi frequency=100000000 pixel_clock=74000000
The pixel_clock value will be the clock value set in mipi_clk.
The TSettle Count and number of Tx Lanes are shown in the debug output line:
pixel_clock=74000000 settle_cnt = 4 lane=0x83
1 Lane = 0x81, 2 Lane = 0x83, 4 Lane = 0x8F
Table B3: Common values for MIPI CSI Frequency and TSettle
Pixel Clock
Tx Lanes
CSI Frequency
TSettle Count
148.5
2
200
12
74.25
2
100
4
27
2
100
8
20
2
100
10
B4 FPGA I2C Control of Camera Acquisition (Optional)
The section describes how to control camera acquisition through I2C registers for custom designed
FPGAs. Although not required, implementing an I2C register interface may make it a more flexible
design.
The 4000-OEM FPGA supports programmable camera timing parameters. This allows using the same
FPGA code to support multiple camera types and resolutions. The camera timing parameters are
updated from the 4000-OEM acquisition settings into the FPGA I2C registers. This data is automatically
updated through the MIPI I2C bus to the FPGA.

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Additionally, this requires implementing I2C interface code on your FPGA and connecting the
appropriate pin for I2C to the MIPI connector. Generally, this is a data pin sda that supports open drain
(and may be identified as an I2C port) and an I2C clock scl.
The I2C data line sda must be defined as a bidirectional port and pulled up in the FPGA pin
configuration. The open drain operation can be implemented in Verilog as
assign sda = (sdaOut == 1'b0) ? 1'b0 : 1'bz;
The scl I2C clock line can also be defined as bidirectional open-drain, but this is not necessary since the
SightLine FPGA device does not do clock stretching.
Successful results have been achieved using Open Cores I2C implementation (see the OpenCores
website). This implementation requires a clock internal to the FPGA (the SightLine FPGA provides an
internal 48 Mhz reference clock) for sampling (and debouncing) the I2C clock and data lines.
The 4000-OEM can also reset the FPGA state machines (synchronized to frame sync). It does this
through an I2C register. This may not be necessary in your design.
There are two available MIPI ports on the 4000-OEM. Each port has a different I2C address. The I2C bus
speed is limited to 400 kb due to incompatibility with the SLA-3000-HDSDI-IN input board.
The FPGA interface is assumed to reside at I2C address 0x40 (7-bit I2C address). This means that the
upper 7-bits are 0x40 and the lower bit is 0 or 1 depending on the Read/Write attribute. Since the slave
address is 0x40, the 8-bit write address is 0x80 and the 8-bit read address is 0x81.
CSI2 supports I2C Bus 1 (Cam 0). CSI0 supports I2C Bus 3 (Cam 1) On the SOM Port J9.
All register values are 16-bit, little endian (low byte first).
Table B4: I2C Register Map
I2C Address
Description
Example
0x00
Version0 - read only.
Intended for firmware version or version of register map as more registers are added or
change order.
Lower 3 nibbles are version. Upper nibble is register layout (0x0 = current).
0x001 = version
0x0 = register layout0 (used if
this map of register values or
size is changed)
0x01
0x02
Version1 - read only.
SVN revision. Used to track
revisions.
0x03
0x04
FPGA Control and status.
B0 - Frame sync reset. Set B0 to high to assert reset on FPGA logic (state machines), and
then set B0 low to deassert reset. This will be deasserted on the next falling edge of
VSync (before the start of the next frame) frame sync reset of FPGA logic.
Read / Modify / Write
0x05
0x06
Dig Cam Params
16-bit exact copy of digCamParams flags, e.g., Embedded sync, Invert HSync, Invert
VSync, Byte Swap.
Hex Value
0x07
0x08
Vertical Front Porch - blanking lines at start of frame
0x0015 = 21 lines
0x09
0x0
Active Vertical Lines (height)
0x02D0 = 720
0x0B
0x0C
Horizontal Front Porch - blanking pixels at start of line
0x00E9 = 233
0x0D
0x0E
Active Horizontal Length - width in active pixels
0x00500 = 1280
0x0F
0x011
0x010
MIPI clock estimate Mhz (B9->B2) and TxLanes (B1->B0) 00=def,01=1,10=2,11=4
0x0029 = 1 TxLane, 10 MHz

EAN-4000-OEM-MIPI-Cameras
© SightLine Applications, Inc. 17
Example of register value display (for I2C bus 1):
echo Version 0
i2cget -f -y 1 0x40 1
i2cget -f -y 1 0x40 0
echo Version 1
i2cget -f -y 1 0x40 3
i2cget -f -y 1 0x40 2
echo VFP
i2cget -f -y 1 0x40 0x9
i2cget -f -y 1 0x40 0x8
echo height
i2cget -f -y 1 0x40 0xB
i2cget -f -y 1 0x40 0xA
echo HFP
i2cget -f -y 1 0x40 0xD
i2cget -f -y 1 0x40 0xC
echo width
i2cget -f -y 1 0x40 0xF
i2cget -f -y 1 0x40 0xE