Sony XT-100DAB User manual

– 1 –
SERVICE MANUAL
AEP Model
UK Model
XT-100DAB
DIGITAL AUDIO
BROADCASTING TUNER
Frequency 174.928 - 239.200 MHz
(Band III)
1452.960 - 1490.624 MHz
(L band)
Mode Mode I (Band III)
Mode II (L band)
Power requirements 12 V DC car battery
(negative earth)
Outputs BUS control output
Audio optical output
Audio output
Inputs Aerial input
BUS control input
Audio optical input
Audio input
Dimensions 240 ×35 ×163 mm
(w/h/d)
Mass Approx. 1.2 kg
Supplied accessories Parts for installation and
connection (1 set)
DAB aerial (1)
BUS cable (1)
RCA pin cord (1)
Optical cable (1)
Design and specifications are subject to change without
notice.
SPECIFICATIONS
MICROFILM

– 2 –
TABLE OF CONTENTS
1. SERVICE NOTE ................................................................ 2
2. GENERAL
Connections ............................................................................. 3
3. ELECTRICAL ADJUSTMENTS ...............................5
4. DIAGRAMS
4-1. Block Diagram –RF Section– ............................................. 7
4-2. Block Diagram –Audio Section– ........................................ 9
4-3. IC Pin Descriptions ........................................................... 11
4-4. Printed Wiring Board ........................................................ 21
4-5. Schematic Diagram –Main Board (1/4)– .......................... 25
4-6. Schematic Diagram –Main Board (2/4)– .......................... 27
4-7. Schematic Diagram –Main Board (3/4)– .......................... 29
4-8. Schematic Diagram –Main Board (4/4)– .......................... 31
5. EXPLODED VIEW .................................................... 37
6. ELECTRICAL PARTS LIST ....................................38
Notes on Chip Component Replacement
•Never reuse a disconnected chip component.
•Notice that the minus side of a tantalum capacitor may be dam-
aged by heat.
SECTION 1
SERVICE NOTE
The XT-100DAB cannot be operated alone.
When performing voltage check and electrical adjustments, the set
should be connected to a master unit such as CDX-C90R or XES-
Z50 as shown below.
regulated
DC power
supply (14.4V
)
BATT, ACC
BUS CONTROL
IN
master unit
B
+
SONY BUS
CONTROL OUT
XT-100DAB

– 3 –
SECTION 2
GENERAL This section is extracted
from instruction manual.

– 4 –
(3 A)
(3 A)
(3 A)
(3 A)

– 5 –
The set should be connected to a master unit for electrical
adjustments (See page 2).
Local OSC Adjustment
Setting:
SECTION 3
ELECTRICAL ADJUSTMENTS
Procedure:
1. Adjust T102 so as to maximize the peak of waveform at 35.84
MHz.
Adjustment Location: See page 6.
IF2 Output Gain Adjustment
Setting:
oscilloscope
main board
TP LO
digital
voltmete
r
main board
TP LEL
Procedure:
1. Adjust RV101 so that the reading on digital voltmeter is 2.25V.
Adjustment Location: See page 6.
AGC Adjustment
Setting:
ANT +B switch : OFF
Procedure:
1. Set the carrier frequency of RF SSG to 225.648 MHz.
2. Receive the channel 12B (225.648 MHz).
3. Adjust RV102 so that the reading on digital voltmeter is 3.1 ±
0.5 V.
4. Set the carrier frequency of RF SSG to 1471.792 MHz.
5. Receive the channel L12 (1471.792 MHz).
6. Adjust RV103 so that the reading on digital voltmeter is 3.2 ±
0.5 V.
Adjustment Location: See page 6.
digital
voltmete
r
main board
TP AGC
ANTENNA jack
0.01
µ F
RF SSG
set
output level : 90 dBm (32 mV)
Non-modulation
Frame Sync Adjustment
Setting:
ANT +B switch : ON
Procedure:
1. Receive the DAB signal.
2. Adjust RV104 sothat therising edgeof waveformof TPFSYNC
is positioned A.
(1) In case of Band ΙΙΙ (from channel 5A to 13F)
(2) In case of L Band (from channel L1 to L23)
CH-1 CH-2
oscilloscope
main board
TP IF2
main board
TP FSYNC
ANTENNA jack
ANTENNA
set
TP
IF2
TP
FSYNC
A
–1.68000 ms –680.00 us
200 us / div 320.00 us realtime
1 500 mV/ 2 2.00 V /
–1.12500 V 5.00000 V
Adjustment Location: See page 6.
TP
IF2
TP
FSYNC
A
–370.00 us –120.00 us
50.0 us / div 130.00 us realtime
1 500 mV/ 2 2.00 V /
125.000 mV 3.00000 V

– 6 –
Adjustment Location: main board (side A)
IF2 OUTPUT
GAIN ADJ
RV101
LOCAL
OSC
ADJ
T102
FRAME
SYNC
ADJ
RV104 TP
AGC
TP
LO
TP
LEL
TP
IF2
TP
FSYNC
RV102
AGC ADJ
(CH 12B)
RV103
AGC ADJ
(CH L12)

XT-100DAB
4-1. BLOCK DIAGRAM — RF SECTION —
– 7 – – 8 –
SECTION 4
DIAGRAMS
1
RF IN
ANT+B
3
+9V
4
+5V
10
+28V
5
SCL
6
SDA
7
LOCK
2
AGC
9
11
X-IN
ACC9V
TU5V
POWER
CONTROL
Q601
POWER
CONTROL
Q602,603
AGC
Q102,105
Q109-111
SAW
FILTER
SWF101
DC/DC
CONV.
IC602
ANTENNA
SW601
(ANT+B)
D602
8
4 1
IF OUT
TUNER UNIT
TU101
ACC9V
Q101
X2
Q103
6
5
7
AGC
THRESHOLD
SWITCH
IC102
Q104
AGC
RV102 RV103
12
9
2
16
THR
THRRPRE
AGCPRE
LO IN
IF
IN
IF
OUT
24 8
IF SIGNAL
PROCESSING
IC101
RV101
IF2 OUTPUT
GAIN
OSC
XO101
BPF
T101
17.92MHz
119
SYSTEM CONTROL
IC401 (1/2)
DAB BAND
118
DAB SEK OUT
112
AGC WATCH
1DAB LOCK IN
121
I2CSO
122
I2CCKO
120
102
107
105
116
117
115
ANTREM
SO
SI
CKI
BUSON
SYS RST
LNK OFF
EXT SI 98
ERR
XFLASH
96
EXT SO
CTL
CKO
SO
SI
XVFICID
MPEGHREQ
MPEGREQ
MREQ
HR FLG
BU IN
SLAVE ON
POWER AON
POWER DON
97
63
59
61
37
32
33
34
1
1
7
7
2 3 5
3 5
6
2 6
BATT
BATT
CN601
POWER
1
4
3
5
ANT REM
RX/DATA
TX/CK
BATT BATT
CN602
SONY BUS CONTROL
IN
CN603
SONY BUS CONTROL
OUT
HRST
SYS RST
SIRCS
CLK
DATA
BUSON
7
8
5 2
1
4
3
6
7
8
5 2
1
4
3
6
60
62
64
6
4
7
8
2 13 38
81
94
9
10
11
BUS INTERFACE
IC606
12
1
RESET
SW
SW
SW
DELAY
IC609,610
RESET
IC605
LINK OFF
Q611
BU5V
BUS ON
SIRCS
HRSTCLK
DATA SYS
RST
04
UNI
MBUS
IC612
Q613
D611
42
42
BATT
DET
Q608
BATT
BATT
BATT
1
1 2
4
2
4
5
SWITCHING
REG
IC603
5V REG
IC611
OPT5V POWER
CONTROL
Q606,607
TU5V
1 2
4
9V REG
IC601
ACC9V
1 2
3.3V REG
IC604 VDD3.3V
3 1
5V REG
IC500 DA5V
ACC 9V
5V REG
Q609,610 BU5V
VDD5V
BATT
9
15
85
72
190
207
205
204
203
186
181
187
184
127
125
134
122
136
3 2
3V TO 5V
CONV.
IC204
3
1
4
COMP.
IC103
7
1
5
3
92
LPF
IC202
OSC
XO201
24.576MHz
IC207
24
RV104
ENV.
DET.
Q106,107
21
12
155
1-8
A/D CONVERTER
IC206
VIN D0-7
CLK
144,145
147-149 151-153
Q108(1/2) Q108(2/2)
2
4
5
6
25
51
DACO
LRCKO
BCKO
DATO
MCK
LRCK
BCK
DATA
DAB RST
XRST
TRSTADCK
ADIN
0-7
FR SYNC
XTLI
ETTCXO
VCXI
PWMP0
PWMP1
ADAT
ACTL
AVLD
ACLK
SCTL
SCLK
SDIN
SDOT
VFICID
TD88
TD89
MRREQ
HFRT
AUDIO
SECTION
1
8
DAB BASEBAND
DECODER
IC201
IC205
42
IC204
8
BUS INTERFACE
IC607
BUS INTERFACE
IC608
AGC
FLAME SYNC
IC303
• Signal path
: FM

4-2. BLOCK DIAGRAM — AUDIO SECTION —
– 9 – – 10 –
XT-100DAB
RF
SECTION
1
6
5
4
3
2
1
30 31
39
40
41
42
43
44
SAMPLING RATE
CONVERTER
IC301
ICLK
LRCKI
BCKI
BCKI
DI
DI
OCSL
LRCO
BCKO
MCK
LRCK
BCK
DATA
DAB RST
BCKO
D OUT
D OUT
RSTN
DIGITAL OUT
MODULATOR
IC701 7 6 4
24 22 23
14
93 94 95 11 89
18
14
16
19
13
20
9
2
1
17
11 16
DATA LRCK
BCK
XI
CTG3 CTG2 CTG1
FSI
XTI
LRCKB
BICK
SDATA
A
OUT
L
A
OUT
R
DOI
8
6 10
17
7
918
5
PD SMUTE
106
127
77 78
72
73
69
79
SYSTEM CONTROL
IC401 (2/2)
DACMUT XAMUT
XROM CS
A1-18
D0-15
RD
95
XUNI
SEL CTL
S IN
S OUT
SCKO
DRC BUSY
XDRC MUT
71 SEL G
86
91
HWR 92
LWR
XRAM
93
EXTAL
85 XTAL
70 XMPEG RST
126
PGO
CE
108 128
A OUT
CTRL
SEL
0-2
10 7
1-3
74-76
6
13
12
14
Y5
LD
CLR
AMPIN
MUTE
BUSY
SCK
DIN
DOUT
Y7
A
B
C
G1
Y2
Y3
Y1
RESET SELECT
IC405
5
6
SDA
SCL
EEPROM
IC406
XO401
18.432KHz
SW401
(DIGITAL/ANALOG)
XO301
22.5792MHz
S1DI
BCK
LRCK
MCKOUT
SOUT1
DYNAMIC RANGE
CONTROL
IC302
MEM
BUS
CTL
IC404
1-5,18-21
24-27,42-44
7-10,13-16
29-32,35-38 41 39 40 17
28
26
11
6A0-15 I/O 0-15
CE
SRAM
IC403
7-9,11-18
20-26
40-43,45-52
54-57
1-8,17-25
48
29-36
38-45
A0-17 DQ 0-15
FLASH ROM
IC402
OEOE
LB
UB
WE WE
3 7
LPF
IC503 1
AMP
IC505
R-CH
13
D/A CONVERTER
IC501
MUTE
CONTROL
Q503,505
Q501
R-CH
R-CH
-1
L
-2
R
-1
L
-2
R
CN502
ANALOG
AUDIO
OUT
CN501
ANALOG
AUDIO
IN
6 7
5
1
1
DIGITAL
IN
IC703
DIGITAL
AUDIO
IN
4
DIGITAL
OUT
IC704
DIGITAL
AUDIO
OUT
IC702
RY501
04
• Signal path
: FM

– 11 –
4-3. IC PIN DESCRIPTIONS
• IC201 CXD1990Q (DAB BASE BAND DECODER)
Pin No. Pin Name I/O Pin Description
1 VSS — Ground
2 DACO O Clock (256fs/512fs) signal output for audio D/A converter.
3 TD75 I Test pin (Built-in pull up resistor.) (Open)
4 LRCKO O L/R clock signal output to audio D/A converter.
5 BCKO O Bit clock signal output to audio D/A converter.
6 DATO O Serial data signal output to audio D/A converter.
7 TD76 I Test pin (Built-in pull up resistor.) (Open)
8 DOUT O Digital out signal output of audio signal. (Open)
9 HFRT O Half rate display signal output (“H” : Stream playback of half rate)
10 RDIMOUT O Biphase modulation signal output of RDI signal. (Open)
11 VDD — Power supply pin (+3.3 V)
12 RDISOUT O Serial data signal output of RDI signal. (Open)
13 VSS — Ground
14 LRCKR O Clock signal output of RDI signal. (Open)
15 MRREQ O Request to read signal output to µ-con.
16 TD77 I Test pin (Built-in pull up resistor.) (Open)
17 – 19 CADR0 – 2 I Chip select address signal input (Connect to ground.)
20 TD78 I Test pin (Built-in pull up resistor.) (Open)
21 – 23 CADR3 – 5 I Chip select address signal input (Connect to ground.)
24 VDD — Power supply pin (+3.3 V)
25 XRST I Reset signal input (When “L” signal input, internal LSI is initialized.)
26 VDD — Power supply pin (+3.3 V)
27 VSS — Ground
28 SCL I Test pin (Normally open. Built-in pull up resistor.) (Connect to ground.)
29 VSS — Ground
30 – 32 TD25, 19, 20 I Test pin (Built-in pull up resistor.) (Open)
33 – 35 TD79, 18, 21 I Test pin (Built-in pull up resistor.) (Open)
36 – 38 TD17, 80, 22 I Test pin (Built-in pull up resistor.) (Open)
39 AVS — Ground
40, 41 TD16, 23 I Test pin (Built-in pull up resistor.) (Open)
42, 43 TD81, 24 I Test pin (Built-in pull up resistor.) (Open)
44 AVD — Power supply pin (+3.3 V)
45 TCK I Test pin (Connect to ground.)
46 TD82 I Test pin (Built-in pull up resistor.) (Open)
47 TMS — Test pin (Normally open.)
48 TDI — Test pin (Normally open.)
49 TDO — Test pin (Open)
50 TD83 I Test pin (Built-in pull up resistor.) (Open)
51 TRST I Reset signal input of LSI test circuit. (Connect to XRST (pin 25).)
52, 53 TD46, 47 I Test pin (Built-in pull up resistor.) (Connect to ground.)
54 – 56 TD34, 84, 35 I Test pin (Built-in pull up resistor.) (Open)
57 – 59 TD33, 7, 85 I Test pin (Built-in pull up resistor.) (Open)
60 – 62 TD8, 6, 9 I Test pin (Built-in pull up resistor.) (Open)
63, 64 TD86, 5 I Test pin (Built-in pull up resistor.) (Open)
65 TDOSEL I Test pin (Normally open. Built-in pull up resistor.) (Connect to ground.)
66 – 68 TD10, 4, 87 I Test pin (Built-in pull up resistor.) (Open)
69 – 71 TD11, 3, 12 I Test pin (Built-in pull up resistor.) (Open)
72 TD88 O Request to header read of audio stream. (Built-in pull up resistor.)
73, 74 TD2, 13 I Test pin (Built-in pull up resistor.) (Open)
75 AXXOUT I Test pin (H : Channel decoder monitor output. Built-in pull up resistor.)
76 VDD — Power supply pin (+3.3 V)

– 12 –
Pin No. Pin Name I/O Pin Description
77 DBI I Test pin (Normally open. Built-in pull up resistor.) (Connect to ground.)
78 VDD — Power supply pin (+3.3 V)
79 VSS — Ground
80 TD1 I Test pin (Built-in pull up resistor.) (Open)
81 VSS — Ground
82 – 84 TD14, 0, 15 I Test pin (Built-in pull up resistor.) (Open)
85 TD89 O Request to PAD read of audio stream. (Built-in pull up resistor.)
86, 87 TD26, 27 I Test terminal (Built-in pull up resistor.) (Open)
88 XROMW0 I Set up wait cycle of synchronous processor. (Connect to ground.)
89 TD48 I Test pin (Built-in pull up resistor.) (Connect to VDD.)
90 XROMW1 I Set up wait cycle of synchronous processor. (Connect to ground.)
91 VSS — Ground
92 EITCXO I Clock input pin for test of synchronous processor.
93 ESXICS I Test pin of synchronous processer. (Connect to VDD.)
94 VDD — Power supply pin (+3.3 V)
95 NMI I External interruption input of synchronous processor. (Connect to ground.)
96 PMI I External interruption input of synchronous processor. (Connect to ground.)
97 DREADY I Data ready input of synchronous processor. (Connect toVDD.)
98 TD49 I Test pin (Built-in pull up resistor.) (Open)
99 RXDC I Test input pin of synchronous processor. (Fixed at “H”.)
100 TXDC O Test output pin of synchronous processor. (Open)
101 HOLD I Request to hold input of synchronous processor. (Connect to ground.)
102 TD50 I Test pin (Built-in pull up resistor.) (Open)
103 HOLDA O Hold response output of synchronous processor. (Open)
104 VDD — Power supply terminal (+3.3 V)
105 VSS — Ground
106 STSTXCK I Test pin (Normally open. Built-in pull up resistor.) (Connect to ground.)
107 TD53 I Test pin (Built-in pull up resistor.) (Open)
108 STESTF I Test pin (Normally open. Built-in pull up resistor.) (Connect to ground.)
109 STESTS I Test pin (Normally open. Built-in pull up resistor.) (Connect to ground.)
110 TD28 I Test pin (Built-in pull up resistor.) (Open)
111 TD54 I Test pin (Built-in pull up resistor.) (Connect to VDD.)
112 – 114 TD29 – 31 I Test pin (Built-in pull up resistor.) (Open)
115, 116 TD55, 32 I Test pin (Built-in pull up resistor.) (Open)
117 VSS — Ground
118 – 121 TD36, 37, 56, 38 I Test pin (Built-in pull up resistor.) (Open)
122 XTLI I 24.576 MHz clock input for VCXO control or oscillator input connection pin.
123 XTLO O 24.576 MHz oscillator output pin (Open)
124 TD57 I Test pin (Built-in pull up resistor.) (Open)
125 PWMP0 O Pulse output (forward phase output) of time axis synchronous VCXO control.
126 PWMN0 O Pulse output (reversed phase output of PWMP0) of time axis synchronous VCXO
control. (Open)
127 PWMP1 O Pulse output (forward phase output) of frequency axis synchronous VCXO control.
128 TD51 I Test pin (Built-in pull up resistor.) (Connect to VDD.)
129 PWMN1 O Pulse output (reversed phase output of PWMP1) of frequency axis synchronous VCXO
control. (Open)
130 VDD — Power supply pin (+3.3 V)
131 NSHS I Mode select of VCXO control circuit (Connect to ground.)
132 VCXMO O Monitor output pin of master clock. (Open)
133 TD58 I Test pin (Built-in pull up resistor.) (Open)
134 VCXI I Master clock (24.576 MHz) input of LSI.
135 VCXSEL I Set up operation clock of LSI. (Connect to ground.)
136 FRSYNC I Frame sync signal input