Sony XT-100DAB User manual

– 1 –
SERVICE MANUAL
AEP Model
UK Model
XT-100DAB
DIGITAL AUDIO
BROADCASTING TUNER
Frequency 174.928 - 239.200 MHz
(Band III)
1452.960 - 1490.624 MHz
(L band)
Mode Mode I (Band III)
Mode II (L band)
Power requirements 12 V DC car battery
(negative earth)
Outputs BUS control output
Audio optical output
Audio output
Inputs Aerial input
BUS control input
Audio optical input
Audio input
Dimensions 240 ×35 ×163 mm
(w/h/d)
Mass Approx. 1.2 kg
Supplied accessories Parts for installation and
connection (1 set)
DAB aerial (1)
BUS cable (1)
RCA pin cord (1)
Optical cable (1)
Design and specifications are subject to change without
notice.
SPECIFICATIONS
MICROFILM

– 2 –
TABLE OF CONTENTS
1. SERVICE NOTE ................................................................ 2
2. GENERAL
Connections ............................................................................. 3
3. ELECTRICAL ADJUSTMENTS ...............................5
4. DIAGRAMS
4-1. Block Diagram –RF Section– ............................................. 7
4-2. Block Diagram –Audio Section– ........................................ 9
4-3. IC Pin Descriptions ........................................................... 11
4-4. Printed Wiring Board ........................................................ 21
4-5. Schematic Diagram –Main Board (1/4)– .......................... 25
4-6. Schematic Diagram –Main Board (2/4)– .......................... 27
4-7. Schematic Diagram –Main Board (3/4)– .......................... 29
4-8. Schematic Diagram –Main Board (4/4)– .......................... 31
5. EXPLODED VIEW .................................................... 37
6. ELECTRICAL PARTS LIST ....................................38
Notes on Chip Component Replacement
•Never reuse a disconnected chip component.
•Notice that the minus side of a tantalum capacitor may be dam-
aged by heat.
SECTION 1
SERVICE NOTE
The XT-100DAB cannot be operated alone.
When performing voltage check and electrical adjustments, the set
should be connected to a master unit such as CDX-C90R or XES-
Z50 as shown below.
regulated
DC power
supply (14.4V
)
BATT, ACC
BUS CONTROL
IN
master unit
B
+
SONY BUS
CONTROL OUT
XT-100DAB

– 3 –
SECTION 2
GENERAL This section is extracted
from instruction manual.

– 4 –
(3 A)
(3 A)
(3 A)
(3 A)

– 5 –
The set should be connected to a master unit for electrical
adjustments (See page 2).
Local OSC Adjustment
Setting:
SECTION 3
ELECTRICAL ADJUSTMENTS
Procedure:
1. Adjust T102 so as to maximize the peak of waveform at 35.84
MHz.
Adjustment Location: See page 6.
IF2 Output Gain Adjustment
Setting:
oscilloscope
main board
TP LO
digital
voltmete
r
main board
TP LEL
Procedure:
1. Adjust RV101 so that the reading on digital voltmeter is 2.25V.
Adjustment Location: See page 6.
AGC Adjustment
Setting:
ANT +B switch : OFF
Procedure:
1. Set the carrier frequency of RF SSG to 225.648 MHz.
2. Receive the channel 12B (225.648 MHz).
3. Adjust RV102 so that the reading on digital voltmeter is 3.1 ±
0.5 V.
4. Set the carrier frequency of RF SSG to 1471.792 MHz.
5. Receive the channel L12 (1471.792 MHz).
6. Adjust RV103 so that the reading on digital voltmeter is 3.2 ±
0.5 V.
Adjustment Location: See page 6.
digital
voltmete
r
main board
TP AGC
ANTENNA jack
0.01
µ F
RF SSG
set
output level : 90 dBm (32 mV)
Non-modulation
Frame Sync Adjustment
Setting:
ANT +B switch : ON
Procedure:
1. Receive the DAB signal.
2. Adjust RV104 sothat therising edgeof waveformof TPFSYNC
is positioned A.
(1) In case of Band ΙΙΙ (from channel 5A to 13F)
(2) In case of L Band (from channel L1 to L23)
CH-1 CH-2
oscilloscope
main board
TP IF2
main board
TP FSYNC
ANTENNA jack
ANTENNA
set
TP
IF2
TP
FSYNC
A
–1.68000 ms –680.00 us
200 us / div 320.00 us realtime
1 500 mV/ 2 2.00 V /
–1.12500 V 5.00000 V
Adjustment Location: See page 6.
TP
IF2
TP
FSYNC
A
–370.00 us –120.00 us
50.0 us / div 130.00 us realtime
1 500 mV/ 2 2.00 V /
125.000 mV 3.00000 V

– 6 –
Adjustment Location: main board (side A)
IF2 OUTPUT
GAIN ADJ
RV101
LOCAL
OSC
ADJ
T102
FRAME
SYNC
ADJ
RV104 TP
AGC
TP
LO
TP
LEL
TP
IF2
TP
FSYNC
RV102
AGC ADJ
(CH 12B)
RV103
AGC ADJ
(CH L12)

XT-100DAB
4-1. BLOCK DIAGRAM — RF SECTION —
– 7 – – 8 –
SECTION 4
DIAGRAMS
1
RF IN
ANT+B
3
+9V
4
+5V
10
+28V
5
SCL
6
SDA
7
LOCK
2
AGC
9
11
X-IN
ACC9V
TU5V
POWER
CONTROL
Q601
POWER
CONTROL
Q602,603
AGC
Q102,105
Q109-111
SAW
FILTER
SWF101
DC/DC
CONV.
IC602
ANTENNA
SW601
(ANT+B)
D602
8
4 1
IF OUT
TUNER UNIT
TU101
ACC9V
Q101
X2
Q103
6
5
7
AGC
THRESHOLD
SWITCH
IC102
Q104
AGC
RV102 RV103
12
9
2
16
THR
THRRPRE
AGCPRE
LO IN
IF
IN
IF
OUT
24 8
IF SIGNAL
PROCESSING
IC101
RV101
IF2 OUTPUT
GAIN
OSC
XO101
BPF
T101
17.92MHz
119
SYSTEM CONTROL
IC401 (1/2)
DAB BAND
118
DAB SEK OUT
112
AGC WATCH
1DAB LOCK IN
121
I2CSO
122
I2CCKO
120
102
107
105
116
117
115
ANTREM
SO
SI
CKI
BUSON
SYS RST
LNK OFF
EXT SI 98
ERR
XFLASH
96
EXT SO
CTL
CKO
SO
SI
XVFICID
MPEGHREQ
MPEGREQ
MREQ
HR FLG
BU IN
SLAVE ON
POWER AON
POWER DON
97
63
59
61
37
32
33
34
1
1
7
7
2 3 5
3 5
6
2 6
BATT
BATT
CN601
POWER
1
4
3
5
ANT REM
RX/DATA
TX/CK
BATT BATT
CN602
SONY BUS CONTROL
IN
CN603
SONY BUS CONTROL
OUT
HRST
SYS RST
SIRCS
CLK
DATA
BUSON
7
8
5 2
1
4
3
6
7
8
5 2
1
4
3
6
60
62
64
6
4
7
8
2 13 38
81
94
9
10
11
BUS INTERFACE
IC606
12
1
RESET
SW
SW
SW
DELAY
IC609,610
RESET
IC605
LINK OFF
Q611
BU5V
BUS ON
SIRCS
HRSTCLK
DATA SYS
RST
04
UNI
MBUS
IC612
Q613
D611
42
42
BATT
DET
Q608
BATT
BATT
BATT
1
1 2
4
2
4
5
SWITCHING
REG
IC603
5V REG
IC611
OPT5V POWER
CONTROL
Q606,607
TU5V
1 2
4
9V REG
IC601
ACC9V
1 2
3.3V REG
IC604 VDD3.3V
3 1
5V REG
IC500 DA5V
ACC 9V
5V REG
Q609,610 BU5V
VDD5V
BATT
9
15
85
72
190
207
205
204
203
186
181
187
184
127
125
134
122
136
3 2
3V TO 5V
CONV.
IC204
3
1
4
COMP.
IC103
7
1
5
3
92
LPF
IC202
OSC
XO201
24.576MHz
IC207
24
RV104
ENV.
DET.
Q106,107
21
12
155
1-8
A/D CONVERTER
IC206
VIN D0-7
CLK
144,145
147-149 151-153
Q108(1/2) Q108(2/2)
2
4
5
6
25
51
DACO
LRCKO
BCKO
DATO
MCK
LRCK
BCK
DATA
DAB RST
XRST
TRSTADCK
ADIN
0-7
FR SYNC
XTLI
ETTCXO
VCXI
PWMP0
PWMP1
ADAT
ACTL
AVLD
ACLK
SCTL
SCLK
SDIN
SDOT
VFICID
TD88
TD89
MRREQ
HFRT
AUDIO
SECTION
1
8
DAB BASEBAND
DECODER
IC201
IC205
42
IC204
8
BUS INTERFACE
IC607
BUS INTERFACE
IC608
AGC
FLAME SYNC
IC303
• Signal path
: FM

4-2. BLOCK DIAGRAM — AUDIO SECTION —
– 9 – – 10 –
XT-100DAB
RF
SECTION
1
6
5
4
3
2
1
30 31
39
40
41
42
43
44
SAMPLING RATE
CONVERTER
IC301
ICLK
LRCKI
BCKI
BCKI
DI
DI
OCSL
LRCO
BCKO
MCK
LRCK
BCK
DATA
DAB RST
BCKO
D OUT
D OUT
RSTN
DIGITAL OUT
MODULATOR
IC701 7 6 4
24 22 23
14
93 94 95 11 89
18
14
16
19
13
20
9
2
1
17
11 16
DATA LRCK
BCK
XI
CTG3 CTG2 CTG1
FSI
XTI
LRCKB
BICK
SDATA
A
OUT
L
A
OUT
R
DOI
8
6 10
17
7
918
5
PD SMUTE
106
127
77 78
72
73
69
79
SYSTEM CONTROL
IC401 (2/2)
DACMUT XAMUT
XROM CS
A1-18
D0-15
RD
95
XUNI
SEL CTL
S IN
S OUT
SCKO
DRC BUSY
XDRC MUT
71 SEL G
86
91
HWR 92
LWR
XRAM
93
EXTAL
85 XTAL
70 XMPEG RST
126
PGO
CE
108 128
A OUT
CTRL
SEL
0-2
10 7
1-3
74-76
6
13
12
14
Y5
LD
CLR
AMPIN
MUTE
BUSY
SCK
DIN
DOUT
Y7
A
B
C
G1
Y2
Y3
Y1
RESET SELECT
IC405
5
6
SDA
SCL
EEPROM
IC406
XO401
18.432KHz
SW401
(DIGITAL/ANALOG)
XO301
22.5792MHz
S1DI
BCK
LRCK
MCKOUT
SOUT1
DYNAMIC RANGE
CONTROL
IC302
MEM
BUS
CTL
IC404
1-5,18-21
24-27,42-44
7-10,13-16
29-32,35-38 41 39 40 17
28
26
11
6A0-15 I/O 0-15
CE
SRAM
IC403
7-9,11-18
20-26
40-43,45-52
54-57
1-8,17-25
48
29-36
38-45
A0-17 DQ 0-15
FLASH ROM
IC402
OEOE
LB
UB
WE WE
3 7
LPF
IC503 1
AMP
IC505
R-CH
13
D/A CONVERTER
IC501
MUTE
CONTROL
Q503,505
Q501
R-CH
R-CH
-1
L
-2
R
-1
L
-2
R
CN502
ANALOG
AUDIO
OUT
CN501
ANALOG
AUDIO
IN
6 7
5
1
1
DIGITAL
IN
IC703
DIGITAL
AUDIO
IN
4
DIGITAL
OUT
IC704
DIGITAL
AUDIO
OUT
IC702
RY501
04
• Signal path
: FM

– 11 –
4-3. IC PIN DESCRIPTIONS
• IC201 CXD1990Q (DAB BASE BAND DECODER)
Pin No. Pin Name I/O Pin Description
1 VSS — Ground
2 DACO O Clock (256fs/512fs) signal output for audio D/A converter.
3 TD75 I Test pin (Built-in pull up resistor.) (Open)
4 LRCKO O L/R clock signal output to audio D/A converter.
5 BCKO O Bit clock signal output to audio D/A converter.
6 DATO O Serial data signal output to audio D/A converter.
7 TD76 I Test pin (Built-in pull up resistor.) (Open)
8 DOUT O Digital out signal output of audio signal. (Open)
9 HFRT O Half rate display signal output (“H” : Stream playback of half rate)
10 RDIMOUT O Biphase modulation signal output of RDI signal. (Open)
11 VDD — Power supply pin (+3.3 V)
12 RDISOUT O Serial data signal output of RDI signal. (Open)
13 VSS — Ground
14 LRCKR O Clock signal output of RDI signal. (Open)
15 MRREQ O Request to read signal output to µ-con.
16 TD77 I Test pin (Built-in pull up resistor.) (Open)
17 – 19 CADR0 – 2 I Chip select address signal input (Connect to ground.)
20 TD78 I Test pin (Built-in pull up resistor.) (Open)
21 – 23 CADR3 – 5 I Chip select address signal input (Connect to ground.)
24 VDD — Power supply pin (+3.3 V)
25 XRST I Reset signal input (When “L” signal input, internal LSI is initialized.)
26 VDD — Power supply pin (+3.3 V)
27 VSS — Ground
28 SCL I Test pin (Normally open. Built-in pull up resistor.) (Connect to ground.)
29 VSS — Ground
30 – 32 TD25, 19, 20 I Test pin (Built-in pull up resistor.) (Open)
33 – 35 TD79, 18, 21 I Test pin (Built-in pull up resistor.) (Open)
36 – 38 TD17, 80, 22 I Test pin (Built-in pull up resistor.) (Open)
39 AVS — Ground
40, 41 TD16, 23 I Test pin (Built-in pull up resistor.) (Open)
42, 43 TD81, 24 I Test pin (Built-in pull up resistor.) (Open)
44 AVD — Power supply pin (+3.3 V)
45 TCK I Test pin (Connect to ground.)
46 TD82 I Test pin (Built-in pull up resistor.) (Open)
47 TMS — Test pin (Normally open.)
48 TDI — Test pin (Normally open.)
49 TDO — Test pin (Open)
50 TD83 I Test pin (Built-in pull up resistor.) (Open)
51 TRST I Reset signal input of LSI test circuit. (Connect to XRST (pin 25).)
52, 53 TD46, 47 I Test pin (Built-in pull up resistor.) (Connect to ground.)
54 – 56 TD34, 84, 35 I Test pin (Built-in pull up resistor.) (Open)
57 – 59 TD33, 7, 85 I Test pin (Built-in pull up resistor.) (Open)
60 – 62 TD8, 6, 9 I Test pin (Built-in pull up resistor.) (Open)
63, 64 TD86, 5 I Test pin (Built-in pull up resistor.) (Open)
65 TDOSEL I Test pin (Normally open. Built-in pull up resistor.) (Connect to ground.)
66 – 68 TD10, 4, 87 I Test pin (Built-in pull up resistor.) (Open)
69 – 71 TD11, 3, 12 I Test pin (Built-in pull up resistor.) (Open)
72 TD88 O Request to header read of audio stream. (Built-in pull up resistor.)
73, 74 TD2, 13 I Test pin (Built-in pull up resistor.) (Open)
75 AXXOUT I Test pin (H : Channel decoder monitor output. Built-in pull up resistor.)
76 VDD — Power supply pin (+3.3 V)

– 12 –
Pin No. Pin Name I/O Pin Description
77 DBI I Test pin (Normally open. Built-in pull up resistor.) (Connect to ground.)
78 VDD — Power supply pin (+3.3 V)
79 VSS — Ground
80 TD1 I Test pin (Built-in pull up resistor.) (Open)
81 VSS — Ground
82 – 84 TD14, 0, 15 I Test pin (Built-in pull up resistor.) (Open)
85 TD89 O Request to PAD read of audio stream. (Built-in pull up resistor.)
86, 87 TD26, 27 I Test terminal (Built-in pull up resistor.) (Open)
88 XROMW0 I Set up wait cycle of synchronous processor. (Connect to ground.)
89 TD48 I Test pin (Built-in pull up resistor.) (Connect to VDD.)
90 XROMW1 I Set up wait cycle of synchronous processor. (Connect to ground.)
91 VSS — Ground
92 EITCXO I Clock input pin for test of synchronous processor.
93 ESXICS I Test pin of synchronous processer. (Connect to VDD.)
94 VDD — Power supply pin (+3.3 V)
95 NMI I External interruption input of synchronous processor. (Connect to ground.)
96 PMI I External interruption input of synchronous processor. (Connect to ground.)
97 DREADY I Data ready input of synchronous processor. (Connect toVDD.)
98 TD49 I Test pin (Built-in pull up resistor.) (Open)
99 RXDC I Test input pin of synchronous processor. (Fixed at “H”.)
100 TXDC O Test output pin of synchronous processor. (Open)
101 HOLD I Request to hold input of synchronous processor. (Connect to ground.)
102 TD50 I Test pin (Built-in pull up resistor.) (Open)
103 HOLDA O Hold response output of synchronous processor. (Open)
104 VDD — Power supply terminal (+3.3 V)
105 VSS — Ground
106 STSTXCK I Test pin (Normally open. Built-in pull up resistor.) (Connect to ground.)
107 TD53 I Test pin (Built-in pull up resistor.) (Open)
108 STESTF I Test pin (Normally open. Built-in pull up resistor.) (Connect to ground.)
109 STESTS I Test pin (Normally open. Built-in pull up resistor.) (Connect to ground.)
110 TD28 I Test pin (Built-in pull up resistor.) (Open)
111 TD54 I Test pin (Built-in pull up resistor.) (Connect to VDD.)
112 – 114 TD29 – 31 I Test pin (Built-in pull up resistor.) (Open)
115, 116 TD55, 32 I Test pin (Built-in pull up resistor.) (Open)
117 VSS — Ground
118 – 121 TD36, 37, 56, 38 I Test pin (Built-in pull up resistor.) (Open)
122 XTLI I 24.576 MHz clock input for VCXO control or oscillator input connection pin.
123 XTLO O 24.576 MHz oscillator output pin (Open)
124 TD57 I Test pin (Built-in pull up resistor.) (Open)
125 PWMP0 O Pulse output (forward phase output) of time axis synchronous VCXO control.
126 PWMN0 O Pulse output (reversed phase output of PWMP0) of time axis synchronous VCXO
control. (Open)
127 PWMP1 O Pulse output (forward phase output) of frequency axis synchronous VCXO control.
128 TD51 I Test pin (Built-in pull up resistor.) (Connect to VDD.)
129 PWMN1 O Pulse output (reversed phase output of PWMP1) of frequency axis synchronous VCXO
control. (Open)
130 VDD — Power supply pin (+3.3 V)
131 NSHS I Mode select of VCXO control circuit (Connect to ground.)
132 VCXMO O Monitor output pin of master clock. (Open)
133 TD58 I Test pin (Built-in pull up resistor.) (Open)
134 VCXI I Master clock (24.576 MHz) input of LSI.
135 VCXSEL I Set up operation clock of LSI. (Connect to ground.)
136 FRSYNC I Frame sync signal input

– 13 –
Pin No. Pin Name I/O Pin Description
137 TD59 I Test pin (Built-in pull up resistor.) (Open)
138 WAGC O AGC window signal output (Open)
139 DIQS I Test pin (Connect to ground.)
140 SHIFT I Test pin (Connect to VDD.)
141 TD60 I Test pin (Built-in pull up resistor.) (Open)
142 MSBINV I MSB inversion of I/F digital signal (“H” : Processing to invert at internal LSI withADIN7.)
143 VSS — Ground
144 ADIN0 I Input pin of I/F digital signal (A/D converter output)
145 ADIN1 I Input pin of I/F digital signal (A/D converter output)
146 TD61 I Test pin (Built-in pull up resistor.) (Open)
147 – 149 ADIN2 – 4 I Input pin of I/F digital signal (A/D converter output)
150 TD62 I Test pin (Built-in pull up resistor.) (Open)
151 – 153 ADIN5 – 7 I Input pin of I/F digital signal (A/D converter output)
154 TD63 I Test pin (Built-in pull up resistor.) (Open)
155 ADCK O 4.096 MHz clock output for A/D converter.
156 VDD — Power supply pin (+3.3 V)
157 VSS — Ground
158 TEST0 I Test pin (Connect to VDD.)
159 TD52 I Test pin (Built-in pull up resistor.) (Connect to VDD.)
160 – 162 TEST1 – 3 I Test pin (Connect to VDD.)
163 TD64 I Test pin (Built-in pull up resistor.) (Open)
164 EXTI I Test pin (Normally open. Built-in pull down resistor.) (Connect to ground.)
165 TBDIR I Test pin (Normally open. Built-in pull down resistor.) (Connect to ground.)
166 HDI I Test pin (Connect to ground.)
167 TD65 I Test pin (Built-in pull up resistor.) (Open)
168 HCK I Test pin (Connect to ground.)
169 VSS — Ground
170 XLD I Test pin (Connect to VDD.)
171 RAMXROM I Test pin (Connect to ground.)
172 TD66 I Test pin (Built-in pull up resistor.) (Open)
173 HDO O Test output pin (Open)
174 BUSY O Test output pin (Open)
175 XFFTSYME O Test output pin (Open)
176 TD67 I Test pin (Built-in pull up resistor.) (Open)
177 XFFTFS O Test output pin (Open)
178 XSYM O Test output pin (Open)
179 AXXSEL I Test pin (Normally open. Built-in pull down resistor.) (Connect to ground.)
180 TD68 I Test pin (Built-in pull up resistor.) (Open)
181 ACLK O 3.072 MHz clock output.
182 VDD — Power supply pin (+3.3 V)
183 VSS — Ground
184 ADAT I/O Channel decoder monitor output (At AXXOUT=“H” set up, output.)
185 TD69 I Test pin (Built-in pull up resistor.) (Open)
186 AVLD I/O Channel decoder monitor output (At AXXOUT=“H” set up, output.)
187 ACTL I/O Channel decoder monitor output (At AXXOUT=“H” set up, output.)
188 CIFS I/O Channel decoder monitor output (At AXXOUT=“H” set up, output.) (Open)
189 TD70 I Test pin (Built-in pull up resistor.) (Open)
190 VFICID O FIC valid output
191 CRCERR O CRC result of FIC (H : CRC error) (Open)
192 – 194 TD39, 71, 40 I Test pin (Built-in pull up resistor.) (Open)
195 VSS — Ground
196 TD41 I Test pin (Connect to ground.)
197 – 199 TD42, 72, 43 I Test pin (Built-in pull up resistor.) (Open)

– 14 –
Pin No. Pin Name I/O Pin Description
200, 201 TD44, 45 I Test pin (Built-in pull up resistor.) (Connect to ground.)
202 TD73 I Test pin (Built-in pull up resistor.) (Open)
203 SCTL I Control input from system control (IC401).
204 SCLK I Serial data transfer clock input from system control (IC401).
205 SDIN I Serial data input from system control (IC401).
206 TD74 I Test pin (Built-in pull up resistor.) (Open)
207 SDOT O Serial data output to system control (IC401).
208 VDD — Power supply pin (+3.3 V)

– 15 –
• IC302 CXD2710R (DYNAMIC RANGE CONTROL)
Pin No. Pin Name I/O Pin Description
1 AMPIN I Loop filter amplifier input for PLL.
2 AMPOUT O Loop filter amplifier output for PLL.
3 VDD — Power supply pin (+5 V)
4 VSS — Ground
5 AVSS1 — Ground for PLL.
6 VCOC I VCO control signal input
7 AVDD1 — VCO power supply pin for PLL. (+5V)
8 VCOOUT O VCO output for PLL. (OPEN)
9 MCK1 I Master clock input (768Fs)
10 MCK2 I Master clock input (384Fs) (Fixed at “H”)
11 MCKOUT O Master clock output (384Fs)
12 MCKSEL I MCK1/internal VCO select pin (“H” : MCK1, “L” : internal VCO) (Fixed at “H”.)
13 MUTE I Mute signal input of serial interface from system control (IC401). (L : Mute on)
14 DIN I Program data seriai input from system control (IC401).
15 VSS — Ground
16 SCK I Program data shift clock input from system control (IC401).
17 LD I Program data load input from system control (IC401).
18 DOUT O Intenal data serial output to system control (IC401).
19 BUSY O Data transfer busy signal output to system control (IC401).
20 CLR I Reset signal input from system control (IC401).
21 – 27 TEST I Test pin (Connect to ground.)
28 VDD — Power supply pin (+5 V)
29 VSS — Ground
30 – 38 TEST I Test pin (Connect to ground.)
39 TEST — Test pin (Open)
40 VSS — Ground
41 – 52 TEST — Test pin (Open)
53 VDD — Power supply pin (+5 V)
54 VSS — Ground
55 – 64 TEST — Test pin (Open)
65 VSS — Ground
66 – 74 TEST — Test pin (Open)
75 EBDIR I Test pin (Connect to ground.)
76 UBDIR I Test pin (Connect to ground.)
77 TEST I Test pin (Connect to ground.)
78 VDD — Power supply pin (+5 V)
79 VSS — Ground
80 – 82 TEST I Test pin (Connect to ground.)
83 AVDD2 — Power supply pin for DRAM. (+5 V)
84 AVSS2 — Ground for D-RAM.
85 AVDD3 — Power supply pin for DRAM. (+5 V)
86 AVSS3 — Ground for DRAM.
87 SOUT3 O Serial data (1 sampling, 2 channel) output (Open)
88 SOUT2 O Serial data (1 sampling, 2 channel) output (Open)
89 SOUT1 O Serial data (1 sampling, 2 channel) output
90 VSS — Ground
91 S3DI I Serial data (1 sampling, 2 channel) output (Connect to ground.)
92 S2DI I Serial data (1 sampling, 2 channel) output (Connect to ground.)
93 S1DI I Serial data (1 sampling, 2 channel) input
94 BCK I Bit clock input of the serial I/O data.
95 LRCK I Sampling clock input of the serial I/O data.
96 PCPOUT O Error output of PLL phase comparator. (Open)

– 16 –
Pin No. Pin Name I/O Pin Description
97 V O Frequency divider output for PLL. (Open)
98 VAR I PLL phase comparator variable input (Connect to ground.)
99 REF I PLL phase comparator reference input (Connect to ground.)
100 PD O PLL phase comparator charge pump output (Open)

– 17 –
• IC401 HD6432655H01FN (SYSTEM CONTROL)
Pin No. Pin Name I/O Pin Description
1 DAB LOCKIN I Lock input for PLL.
2 PG4 — Connect to ground.
3 VSS — Ground
4 NIL — Ground
5 VCC — Power supply pin (+5V)
6 – 9 A0 – 3 O Address data signal output
10 VSS — Ground
11 – 18 A4 – 11 O Address data signal output
19 VSS — Ground
20 – 26 A12 – 18 O Address data signal output
27 PA3 I Test pin (Connect to ground.)
28 VSS — Ground
29 PA4 I Test pin (Connect to ground.)
30 PA5 I Connect to ground.
31 PA6 I Reserve IRQ PULL UP signal input
32 MPEGHREQ I Reserve IRQ PULL UP signal input
33 MPEGREQ I MPEG interruption signal input
34 MREQ I Interruption input from PRIMO synchronization.
35, 36 VSS — Ground
37 XVFICID I PRIMO frame interruption signal input (24 ms)
38 BUSON I Interruption input from serial bus.
39 VCC — Power supply pin (+5 V)
40 – 43 D0 – 3 I/O Data bus signal input/output
44 VSS — Ground
45 – 52 D4 – 11 I/O Data bus signal input/output
53 VSS — Ground
54 – 57 D12 – 15 I/O Data bus signal input/output
58 VCC — Power supply pin (+5 V)
59 MBUSSO O M bus data signal output
60 UNISO O Serial bus data signal output
61 MBUSSI I M bus data signal input
62 UNISI I Serial bus data signal input
63 MBUSCKO O M bus clock signal output
64 UNICKI I Serial bus clock signal input
65 VSS — Ground
66 FSCONV ERRIN I FSCONV error signal input
67, 68 VSS — Ground
69 DRC BUSYIN I DRC status read signal input
70 XMPEG RST O MPEG reset signal output (Reserve)
71 SEL G O Data select signal output. L : Data change
72 S OUT O Serial bus data signal output
73 S CKO O Serial bus clock signal output
74 – 76 SEL 2 – 0 O Data select signal output
77 DAC MUT O DAC mute signal output. H : Mute on
78 XA MUT O Analog mute signal output. L : Mute on
79 XDRC MUT O DRC mute signal output. L : Mute on
80 WDTOVF — Watch dog (Open)
81 SYSRST I System reset signal input
82 BU IN I Battry power supply check signal input
83 STBY I Standby signal input
84 VCC — Power supply pin (+5 V)
85 XTAL I System clock signal input (18.432 kHz)

– 18 –
Pin No. Pin Name I/O Pin Description
86 EXTAL O System clock signal output (18.432 kHz)
87 VSS — Ground
88 Ø — Test pin (Open)
89 VCC — Power supply pin (+5 V)
90 AS O Address strobe signal output (Open)
91 RD O Read signal output
92 HWR O High light signal output
93 LWR O Low light signal output
94 LNKOFF O Serial bus link signal output. H : Link off, L : Link on
95 XUNI SEL CTL O Audio select signal output. L : Communication, H : DAB
96 ERR XFLASH O External output terminal for power supply. L : Communication, H : BER
97 EXTSO O Communication data signal output
98 EXTSI I Communication data signal input
99, 100 VSS — Ground
101 P5 2 O Test pin (Open)
102 MBUS CTL O M BUS mode control signal output. H : Address, L : DATA
103 AVCC — Power supply pin (+5V)
104 VREF I/O Reference voltage signal input/output
105 BU IN I Battry power supply check signal input
106 S IN I Serial data signal input
107 HR FLGIN I HR FLG signal input
108 AOUT CTRLIN I Audio out set up signal input. L : Digital, L : Analog
109 P4 4 I Reserve input pin
110 P4 5 I Reserve input pin
111 TEST MODEIN I Test mode select signal input. H : Test mode
112 AGC WATCHIN I AGC A/D signal input
113 AVSS — Ground
114 VSS — Ground
115 POWER DON O Digital power supply ON/OFF select signal output
116 SLAVE ON O Slave power supply ON/OFF select signal output
117 POWERAON O Analog power supply ON/OFF select signal output
118 DAB SEKOUT O Channel seek signal output
119 DAB BAND O L band, band III signal output
120 ANTREM O ANT remote ON/OFF select signal output. H : ON
121 I2CSO O PLL signal output
122 I2CCKO O PLL signal output
123 – 125 MD0 – 2 I CPU mode set up signal input
126 PG0 O Output port reserve signal output
127 XROM CS O Chip enable signal output
128 XRAM CS O Chip enable signal output

– 19 – – 20 –
Note on Schematic Diagram:
• All capacitors are in µF unless otherwise noted. pF: µµF
50 WV or less are not indicated except for electrolytics
and tantalums.
• All resistors are in Ωand 1/4W or less unless otherwise
specified.
• % : indicates tolerance.
•¢: internal component.
• : Analog ground.
• : Digital ground.
•U: B+ Line.
•H: adjustment for repair.
• Power voltage is connect to master unit, and dc 14.4V
andfedwithregulateddcpowersupplyfrommasterunit’s
ACC and BATT cords. (See page 2.)
• Voltages are taken with aVOM (Input impedance 10 MΩ).
Voltage variations may be noted due to normal produc-
tion tolerances.
• Signal path.
F: FM
Note on Printed Wiring Board:
•X: parts extracted from the component side.
•p: parts mounted on the conductor side.
•®:Through hole.
•¢: internal component.
•b: Pattern from the side which enables seeing.
(The other layer’s patterns are not indicated.)
Caution:
Pattern face side: Partsonthepatternfacesideseen fromthe
(Side B) pattern face are indicated.
Parts face side: Parts on the parts face side seen from the
(Side A) parts face are indicated.
THIS NOTE IS COMMON FOR PRINTEDWIRING BOARD
AND SCHEMATIC DIAGRAM.
(In addition to this, the necessary note is
printed in each block.)
• Semiconductor Location
D101 B-11
D102 B-14
(D501) L-11
(D503) L-8
D504 M-8
D505 L-8
D506 L-11
D507 L-11
D508 L-6
D509 L-6
D510 L-5
D511 L-5
D601 L-18
(D602) H-17
(D603) L-17
(D604) H-18
D605 H-14
(D607) L-12
(D608) L-13
D609 J-11
D610 J-11
(D611) H-14
(D612) H-13
(D613) L-13
(D614) L-12
(D615) M-13
(D616) J-12
D617 J-13
(D618) L-17
IC101 D-11
IC102 D-13
IC103 B-13
IC201 H-6
IC202 H-9
IC204 I-10
IC205 H-10
(IC206) F-8
IC207 H-8
IC301 G-2
IC302 D-2
IC303 G-3
IC401 D-6
IC402 D-9
IC403 A-6
IC404 C-7
IC405 C-3
IC406 B-9
IC500 K-2
IC501 I-3
IC502 K-2
IC503 K-5
IC504 K-3
IC505 K-7
(IC601) K-18
IC602 G-18
IC603 H-16
(IC604) J-18
IC605 I-12
IC606 K-12
IC607 I-11
IC608 J-11
IC609 H-12
IC610 H-12
(IC611) I-18
IC612 G-12
IC701 I-1
IC702 L-3
(IC703) M-4
(IC704) M-2
Q101 E-11
Q102 B-14
Q103 C-13
Q104 D-13
Q105 B-13
Q106 B-11
Q107 B-12
Q108 B-10
Q109 B-14
Q110 A-14
Q111 A-15
Q501 L-8
Q502 K-8
(Q503) L-6
Q504 K-10
Q505 K-6
(Q601) I-18
(Q602) J-18
(Q603) H-18
(Q606) I-16
(Q607) H-15
(Q608) G-14
(Q609) H-13
(Q610) H-13
Q611 L-12
Q613 H-15
Ref. No. Location Ref. No. Location
( ) : SIDE B

XT-100DAB
– 21 – – 22 –
4-4. PRINTEDWIRING BOARD • Refer to page 20 for Semiconductor Location.

XT-100DAB
– 23 – – 24 –

XT-100DAB
– 25 – – 26 –
4-5. SCHEMATIC DIAGRAM — MAIN BOARD (1/4) — • Refer to page 34 for IC Block Diagrams.
(Page 30)
(Page 27)