ST STM32H7 3 Series Installation and operating instructions

June 2017 DocID029918 Rev 1 1/48
1
AN4938
Application note
Getting started with STM32H7x3 hardware development
Introduction
This application note is intended for system designers who develop applications based on
STM32H7x3 microcontroller line (STM32H743xx or STM32H753xx) and need an
implementation overview of the following hardware features:
•Power supply
•Package selection
•Clock management
•Reset control
•Boot mode settings
•Debug management.
This document describes the minimum hardware resources required to develop an
application based on an STM32H743xx or STM32H753xx microcontroller.
Reference documents
The following documents are available on www.st.com:
• STM32H743xx data brief
• STM32H753xx data brief
• Oscillator design guide for STM8S, STM8A and STM32 microcontrollers application note
(AN2867)
•STM32 microcontroller system memory boot mode application note (AN2606).
www.st.com

Contents AN4938
2/48 DocID029918 Rev 1
Contents
1 Power supplies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
1.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
1.1.1 Independent analog supply and reference voltage . . . . . . . . . . . . . . . . . 7
1.1.2 USB transceiver independent power supply . . . . . . . . . . . . . . . . . . . . . . 7
1.1.3 Battery backup domain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
1.1.4 LDO voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
1.2 Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
1.3 Reset and power supply supervisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
1.3.1 Power-on reset (POR)/power-down reset (PDR) . . . . . . . . . . . . . . . . . . 13
1.3.2 Programmable voltage detector (PVD) . . . . . . . . . . . . . . . . . . . . . . . . . 13
1.3.3 Analog voltage detector (AVD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
1.3.4 System reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
1.3.5 Internal reset ON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
1.3.6 Internal reset OFF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
1.3.7 Bypass mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
2 Alternate function mapping to pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3 Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.1 HSE oscillator clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.1.1 External user clock (HSE bypass) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.1.2 External crystal/ceramic resonator (HSE crystal) . . . . . . . . . . . . . . . . . 20
3.2 LSE oscillator clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.2.1 External clock (LSE bypass) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.2.2 External crystal/ceramic resonator (LSE crystal) . . . . . . . . . . . . . . . . . . 21
3.3 Clock security system (CSS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
4 Boot configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
4.1 Boot mode selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
4.2 Boot pin connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
4.3 System bootloader mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
5 Debug management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
5.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

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AN4938 Contents
4
5.2 SWJ debug port (serial wire and JTAG) . . . . . . . . . . . . . . . . . . . . . . . . . . 26
5.2.1 TPIU trace port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
5.2.2 External debug trigger . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
5.3 Pinout and debug port pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
5.3.1 SWJ debug port pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
5.3.2 Flexible SWJ-DP pin assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
5.3.3 Internal pull-up and pull-down on JTAG pins . . . . . . . . . . . . . . . . . . . . . 29
5.3.4 SWJ debug port connection with standard JTAG connector . . . . . . . . . 29
6 Recommendations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
6.1 Printed circuit board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
6.2 Component position . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
6.3 Ground and power supply (VSS,VDD) . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
6.4 Decoupling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
6.5 Other signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
6.6 Unused I/Os and features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
7 Reference design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
7.1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
7.1.1 Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
7.1.2 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
7.1.3 Boot mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
7.1.4 SWJ interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
7.1.5 Power supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
7.2 Component references . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
8 Recommended PCB routing guidelines for
STM32H743/753xx devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
8.1 PCB stack-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
8.2 Crystal oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
8.3 Power supply decoupling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
8.4 High speed signal layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
8.4.1 SDMMC bus interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
8.4.2 Flexible memory controller (FMC) interface . . . . . . . . . . . . . . . . . . . . . . 42
8.4.3 Quadrature serial parallel interface (QUADSPI) . . . . . . . . . . . . . . . . . . 43
8.4.4 Embedded trace macrocell (ETM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

Contents AN4938
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9 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
10 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

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AN4938 List of tables
5
List of tables
Table 1. Boot modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Table 2. STM32H743/753xx bootloader communication peripherals . . . . . . . . . . . . . . . . . . . . . . . . 24
Table 3. TPIU trace pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Table 4. External debug trigger pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Table 5. SWJ debug port pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Table 6. Flexible SWJ-DP assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Table 7. Mandatory components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Table 8. Optional components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Table 9. Reference connection for all packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Table 10. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

List of figures AN4938
6/48 DocID029918 Rev 1
List of figures
Figure 1. VDD33USB connected to VDD power supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Figure 2. VDD33USB connected to external power supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Figure 3. VDD50USB power supply. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Figure 4. Power supply overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 5. Power on reset/power down reset waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 6. PVD threshold. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 7. Reset circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 8. Power supply supervisor interconnection with internal reset OFF . . . . . . . . . . . . . . . . . . . 16
Figure 9. NRST circuitry timing example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 10. STM32CubeMX example screen-shot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 11. HSE external clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 12. HSE crystal/ceramic resonators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 13. LSE external clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 14. LSE crystal/ceramic resonators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 15. Boot mode selection implementation example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 16. Host to board connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Figure 17. JTAG connector implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Figure 18. Typical layout for VDD/VSS pair. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Figure 19. STM32H753XI reference schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Figure 20. Four layer PCB stack-up example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Figure 21. Six layer PCB stack-up example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Figure 22. Decoupling capacitor placement depending on package type . . . . . . . . . . . . . . . . . . . . . . 41
Figure 23. Example of decoupling capacitor placed underneath the STM32H743/753xx . . . . . . . . . . 41

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AN4938 Power supplies
47
1 Power supplies
1.1 Introduction
STM32H743/753xx devices require a 1.71 to 3.6 V operating voltage supply (VDD), which
can be reduced down to 1.62 V by using an external power supervisor and connecting
PDR_ON pin to VSS (refer to the datasheets for details).
The digital power can be supplied either by a internal linear voltage regulator or directly by
an external supply voltage. This digital power voltage can be set dynamically at different
values ranging from 0.7 to 1.2 V, the highest value allowing to achieve the maximum
performance.
The real-time clock (RTC), the RTC backup registers, and the backup SRAM (BKP SRAM)
can be powered from the VBAT voltage (1.2 to 3.6 V) when the main VDD supply is powered
OFF.
1.1.1 Independent analog supply and reference voltage
To improve analog peripheral performance, the analog peripherals feature an independent
power supply which can be separately filtered and shielded from noise on the PCB:
•The analog supply voltage input is available on a separate VDDA pin.
•An isolated supply ground connection is provided on the pin VSSA.
To ensure a better accuracy of low-voltage inputs, the user can connect a separate external
reference voltage on VREF+. The voltage applied to VREF+ ranges from 1.8 V to VDDA.
When available (depending on the package), VREF– pin must be externally tied to VSSA.
VDDA minimum value (VDDA_MIN) depends on the analog peripheral and on whether a
reference voltage is provided or not:
•If no analog peripheral is used, VDDAmin equals 0 V.
•When an ADC or a comparator is used, VDDA_MIN equals 1.62 V.
•When a DAC is used, VDDA_MIN equals 1.8V.
•When an OPAMP is used, VDDA_MIN equals 2.0 V.
•When a reference voltage (VREFBUF_OUT) is provided by the device on VREF+ pin,
VDDA_MIN depends on the required level for this voltage.
1.1.2 USB transceiver independent power supply
There are different ways to supply the USB transceivers, depending on VDD33USB and
VDD50USB availability:
•When the VDD50USB pin is available, this pin can be used to supply an internal
regulator dedicated to USB transceivers. In this case, VDD50USB pin should receive a
voltage ranging from 4.0 to 5.5 V, typically supplied from the VBUS line of the USB
connector. The regulated power (3.0 to 3.6 V) is available on VDD33USB.
In this configuration VDD50USB voltage can rise indifferently after or before VDD power
supply (see Figure 3).
An external capacitor must be connected to VDD33USB.

Power supplies AN4938
8/48 DocID029918 Rev 1
•When the VDD33USB pin is available, this pin can be used to supply the internal
transceiver. In this case, VDD33USB pin should receive a voltage ranging from 3.0 to
3.6 V. If VDD50USB is also available, it must be connected to VDD33USB. As an
example, when the device is powered at 1.8 V, an independent 3.3 V power supply can
be applied to VDD33USB.
When VDD33USB is connected to a separate power supply, it is independent from VDD
and VDDA. It must be the last supply applied and the first supply switched OFF. The
following conditions must be respected (see Figure 2):
– During the power-on and power-down phases (VDD < VDD minimum value),
VDD33USB should always be lower than VDD.
–V
DD33USB rising and falling time specifications must be respected (refer to table
power-up/power-down operating conditions (regulator ON) and table power-
up/power-down operating conditions (regulator OFF) provided in the device
datasheets).
– In operating mode, VDD33USB can be either lower or higher than VDD:
If a USB interface is used (USB OTG_HS/OTG_FS), the associated GPIOs
powered by VDD33USB operate between VDD33USB_MIN and VDD33USB_MAX(see
Figure 2).
VDD33USB supplies both USB OTG_HS and USB OTG_FS transceivers. If only
one USB transceiver is used in the application, the GPIOs associated to the other
USB transceiver are still supplied by VDD33USB.
If no USB interface is used (USB OTG_HS/OTG_FS), the associated GPIOs
powered by VDD33USB operate in VDD range (between VDD_MIN and VDD_MAX).
In the above two configurations, an external capacitor must be connected to
VDD33USB.
•When neither VDD33USB nor VDD50USB is available, VDD pins are use to supply
USB transceivers and must be in the range of 3.0 to 3.6 V for the transceiver to operate
correctly.
Figure 1. VDD33USB connected to VDD power supply
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DocID029918 Rev 1 9/48
AN4938 Power supplies
47
Figure 2. VDD33USB connected to external power supply
Figure 3. VDD50USB power supply
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Power supplies AN4938
10/48 DocID029918 Rev 1
1.1.3 Battery backup domain
Backup domain description
To retain the content of the RTC backup registers, backup SRAM, and supply the RTC when
VDD is turned off, VBAT pin can be connected to an optional 1.2-3.6 V standby voltage
supplied by a battery. Otherwise, VBAT must be connected to another source, such as VDD.
When the backup domain is supplied by VBAT (analog switch connected to VBAT since VDD
is not present), the following functions are available:
•PC14 and PC15 can be used as LSE pins only.
•PC13 can be used as tamper pin (TAMP1).
•PI8 can be used as tamper pin (TAMP2).
•PC1 can be used as tamper pin (TAMP3).
During tRSTTEMPO (temporization at VDD startup) or after a power-down reset (PDR) is
detected, the power switch between VBAT and VDD remains connected to VBAT
.
During the startup phase, if VDD is established in less than tRSTTEMPO and it is higher than
VBAT + 0.6 V, a current may be injected into VBAT pin through an internal diode connected
between VDD and the power switch (VBAT). If the power supply/battery connected to the
VBAT pin cannot support this current injection, it is strongly recommended to connect an
external low-drop diode between this power supply and the VBAT pin.
Refer to the device datasheets for the actual value of tRSTTEMPO.
Battery charging
When VDD is present, the external battery connected to VBAT can be charged through an
internal resistance. This operation can be performed either through an internal 5 kΩor
1.5 kΩresistor. The resistor value can be configured by software.
Battery charging is automatically disabled in VBAT mode.
1.1.4 LDO voltage regulator
The LDO voltage regulator is always enabled after reset with a default output level set to
1.0 V (VOS3). The LDO can operate in three different modes depending on the application
operating modes:
•In Run mode, the regulator supplies full power to the core and the digital domain.
•In Stop mode, the regulator supplies low power to the core and to the digital domain,
thus preserving the contents of the registers and SRAM.
•In Standby mode, the regulator is powered down. The contents of the registers and
SRAM are lost except for those related to the standby circuitry and the backup domain.
In Run and Stop mode, the LDO voltage regulator can be dynamical scaled by software to
different voltage levels: VOS1, VOS2, and VOS3, SVOS3, SVOS4 or SVOS5.
The LDO regulator requires a capacitor on VCAP pins.