ST SPC58NG-DISP User manual

Introduction
The SPC58NG-DISP discovery board is the hardware platform to evaluate and develop applications with the SPC58NG84E7
microcontroller at budget price.
This document describes the hardware architecture of the board and how it is possible to enable specific functions.
SPC58NG-DISP discovery board
UM2255
User manual
UM2255 - Rev 3 - February 2021
For further information contact your local STMicroelectronics sales office.
www.st.com

1SPC58NG-DISP
Figure 1. SPC58NG-DISP
The SPC58NG-DISP discovery board is based on the microcontroller SPC58NG84E7, a high performance
e200z4d triple core 32-bit Power Architecture® technology CPU, 6 MB Flash with HSM cryptography in an
eTQFP176 package.
The several interfaces including GPI/O's, peripherals such as DSPI, LINFlexD (LIN and UART), FlexRay, M_CAN
ISO CAN-FD and two ethernet ports make the SPC570S-DISP an excellent starter kit for the customer to quickly
evaluate the microcontroller as well as to develop and debug application.
Free ready-to-run application firmware examples are available inside SPC5Studio web page (www.st.com/
spc5studio) to support quick evaluation and development.
The PCB, the components and all HW parts assembled in this board meet the requirements of the applicable
RoHS directives.
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SPC58NG-DISP
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1.1 I/O interface and connectors
• 2 ethernet ports 100BASE-TX
• 1 CAN FD port with DB9 connector
• 1 CAN + 1 LIN/UART +1 SPI
• 2 FlexRay channels
• JTAG (header 2 x 7 pin)
• 4 LED’s user
• 4 DIP switches
• 2 user push buttons
• 12 V DC power supply (external PSU)
• RESET push button
• 40 MHz crystal
• Option: LCD TFT display (320 x 240) with touch screen
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I/O interface and connectors
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2SPC58NG-DISP block diagram
Figure 2. SPC58NG-DISP block diagram
SPC58NG84E7
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SPC58NG-DISP block diagram
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3Hardware overview
Figure 3. SPC58NG-DISP: HW overview
3.1 Power supply section
The Figure 4 shows the PSU block diagram.
The DC input source is 12 V and the three voltage regulators generate 5 V, 3.3 V and 1.2 V supply voltages.
The LEDs D1, D2 and D3 are used to monitor the output of each voltage regulator as well as the test points J2,
J3, J5 and J13 to allow measuring the voltage levels 12 V, 5 V, 3.3 V and 1.2 V respectively.
Figure 4. PSU section – block diagram
5 V
3.3 V
1.2 V
12 V PSU
input linear regulator
5 V
switching regulator
1.2 V
switching regulator
3.3 V
12 V DC
input
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Hardware overview
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3.1.1 Power supply - jumper configuration
U2 provides 3.3 V output voltage used to supply the VDD_HV pins. The test point J5 can be used to monitor the
VDD_HV supply voltage level.
The VDD_LV pin can be supplied using an internal regulator and a ballast BJT or providing the supply by using an
external source. In the default configuration the jumpers are set to supply VDD_LV with the external source (U3)
The VDD_LV power supply configuration can be easily configured setting the soldering jumpers as summarized in
the table here below.
Table 1. Power supply - jumper configuration
Configuration JP100 JP101 JP102 R100
External supply (default) Open 1-3 1-2 Removed
Internal regulator + external BJT Closed 1-2 1-3 Assembled
Figure 5. Microcontroller power supply configuration
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Power supply section
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3.2 Microcontroller section
3.2.1 Programmer/debugger JTAG port
A standard 14 pin JTAG port is available for programming and debugging (Figure 6).
Figure 6. JTAG connector
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Microcontroller section
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3.3 User LEDs and user buttons
In the board, the following functions are available:
• 4 LEDs (Figure 7)
• 2 push buttons (Figure 8)
• 4 DIP switches (Figure 9)
Figure 7. User LEDs
Figure 8. User push buttons
Figure 9. Dip switches
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User LEDs and user buttons
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3.4 Ethernet configuration
Figure 10. Ethernet configuration
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Ethernet configuration
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3.4.1 Ethernet MII / RMII configuration
Table 2. Ethernet MII jumper configuration
Default configuration - MII
Jumper Jumper setting
JP205 1-2
JP201 1-2
JP211 1-2
JP209 1-2
JP210 1-2
JP208 1-2
Table 3. Ethernet RMII jumper configuration
Default configuration - RMII
Jumper Jumper setting
JP205 1-3
JP201 1-3
JP211 1-3
JP209 1-3
JP210 1-3
JP208 1-3
X200 Assembled
X203 Assembled
3.4.2 Ethernet PHY serial management
Table 4. Ethernet - Configuration for separated management
Configuration for separated management
MDC0, MDIO0 linked to ETH0
MDC1, MDIO1 linked to ETH1
JP203 1-2
JP204 1-2
Table 5. Ethernet - Configuration for share management
Configuration for shared management
MDC0, MDIO0 linked to ETH0 and ETH1
ETH0 = address 1
ETH1 = address 3
JP203 1-3
JP204 1-3
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Ethernet configuration
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