Tektronix 7623A User manual

Tektronix
COMMITTED TO EXCELLENCE
7623A/R7623A
STORAGE
OSCILLOSCOPE
WITH OPTIONS
SERVICE
INSTRUCTION MANUAL

WARRANTY
Al TEKTRONIX insiruments are warranted against
defective materials and workmanship for one year.
Any questions with respect to the warraniy should
be taken up with your TEK TRONIX Field Engineer of
representative.
AU requests for repairs and replacement parts
should be directed to the TEKTRONIY Field Office
oc representative in your area. This will assure you
the fastest possible service. Please include the
instrument Type Number or Part Number and Serial
Number with all requests for parts or service.
Specifications and price change privileges reserved.
Copyright | 1974 by Tektronix, Inc., Beaverton,
Oregon. Printed in the United States of America. All
rights reserved. Contents of this publication may not
be reproduced in any torm without permission of
Tektronix, Inc.
ULS.A. and foreign TEKTRONIX producis covered
hy U.S. and foreign patents and/or patenis pending.
TEKTRONIX is a registered trademark of Tektronix,
inc.

7623A/R7623A Service
TABLE OF CONTENTS
LIST OF ILLUSTRATIONS
LIST OF TABLES PAGE
SECTION 1 OPERATING INFORMATION
PRELIMINARY OPERATION 1-1
AC POWER SOURCES 1-1
AC POWER CORD 1-1
OPERATING VOLTAGE 1-1
OPERATING TEMPERATURE 1-3
RACKMOUNTING 1-3
PLUG-IN UNITS 1-4
PLUG-IN INSTALLATION AND REMOVAL 1-4
CONTROLS AND CONNECTORS 1-5
FRONT PANEL CONTROLS AND CONNECTORS 1-6
REAR PANEL CONTROLS AND CONNECTORS 1-8
GENERAL OPERATING INFORMATION 1-10
INTENSITY CONTROL 1-10
DISPLAY FOCUS 1-10
GRATICULE 1-10
LIGHT FILTER 1-11
BEAMFINDER 1-11
READOUT MODES 1-12
DISPLAY PHOTOGRAPHY 1-12
STORAGE 1-13
CARE OF STORAGE SCREEN 1-14
VERTICAL MODE 1-15
TRIGGER SOURCE 1-16
X-¥ OPERATION 1-17
INTENSITY MODULATION 1-17
RASTER DISPLAY 1-18
CALIBRATOR 1-18
SIGNALS OUT 1-19
APPLICATIONS 1-20
SECTION 2 SPECIFICATIONS
INTRODUCTION 2-1
STANDARD ACCESSORIES 2-9

7623A/R7623A Service
SECTION 3
TABLE OF CONTENTS (cont.)
THEORY OF OPERATION
LOGIC FUNDAMENTALS
SYMBOLS
LOGIC POLARITY
INPUT/OUTPUT TABLES
NON DIGITAL DEVICES
BLOCK DIAGRAM
THEORY OF OPERATION
MAIN INTERFACE >
LOGIC CIRCUIT ®
Z-AXIS LOGIC
CLOCK GENERATOR
VERTICAL CHOPPED BLANKING
CHOP COUNTER
VERTICAL MODE CONTROL
VERTICAL BINARY
PLUG-IN BINARY
OUTPUT BUFFERS
TRIGGER SELECTOR ©@>
TRIGGER MODE AND ADD SIGNALS
TRIGGER CHANNEL SWITCH
TRIGGER OUTPUT AMPLIFIER
VERTICAL SIGNAL BUFFER
VERTICAL INTERFACE >
VERTICAL CHANNEL SWITCH
AUXILIARY Y-AXIS INPUT AMPLIFIER
DELAY-LINE BUFFER
DELAY LINE
VERTICAL AMPLIFIER <@>
CENTERING AND READOUT AMPLIFIER
INPUT AMPLIFIER
BEAMFINDER NETWORK
OUTPUT AMPLIFIER
HORIZONTAL AMPLIFIER <6>
HORIZONTAL CHANNEL SWITCH
RIGHT OUTPUT AMPLIFIER
LEFT OUTPUT AMPLIFIER
PAGE
3-2
3-2
3-5
3-5
3-5
3-5
3-9
3-9
3-9
3-11
3-12
3-15
3-17
3-18
3-20
3-21
3-21
3-21
3-23
3-24
3-25
3-25
3-25
3-26
3-26
3-27
3-27
3-27
3-28
3-28
3-28
3-29
3-29
3-30
3-30

7623A/R7623A Service
TABLE OF CONTENTS (cont.)
PAGE
OUTPUT SIGNALS <> 3-31
VERT SIG OUT 3-31
+ GATE OUT 3-31
+ SAWTOOTH OUT 3-31
CRT CIRCUIT <7> 3-31
HIGH VOLTAGE REGULATION 3-31
AUTO FOCUS DC RESTORER 3-33
AUTO FOCUS 3-34
CONTROL GRID DC RESTORER 3-34
Z-AXIS AMPLIFIER 3-34
CRT CONTROL CIRCUITS 3-35
LOW-VOLTAGE POWER SUPPLY 3-35
POWER INPUT 3-35
—50-VOLT SUPPLY 3-38
—-15-VOLT SUPPLY 3-40
+5-VOLT SUPPLY 3-40
+15-VOLT SUPPLY 3-40
+50-VOLT SUPPLY 3-40
+130-VOLT SUPPLY 3-40
GRATICULE LIGHT SUPPLY 3-41
CALIBRATOR 0) 3-41
READOUT SYSTEM <> 3-43
INTRODUCTION 3-43
THREE-COMPARTMENT MAINFRAMES 3-43
DISPLAY FORMAT 3-44
DEVELOPING THE DISPLAY 3-44
TIMER 3-51
TIME-SLOT COUNTER 3-53
WORD TRIGGER 3-54
CHANNEL COUNTER 3-54
READOUT CONTROL 3-54
SINGLE-SHOT LOCKOUT 3-55
ENCODING THE DATA 3-56
COLUMN AND ROW DATA SWITCHES 3-59
DISPLAY-SKIP GENERATOR 3-60
COLUMN AND ROW DECODERS 3-60
ZEROS LOGIC AND MEMORY 3-61

7623A/R7623A Service
TABLE OF CONTENTS (cont.)
PAGE
CHARACTER GENERATORS 3-64
DECIMAL POINT LOGIC AND CHARACTER POSITION COUNTER
3-64
FORMAT GENERATOR 3-65
Y-OUTPUT AMPLIFIER 3-67
X-OUTPUT AMPLIFIER 3-67
DISPLAY SEQUENCE 3-67
STORAGE SYSTEM <> 3-68
Loic 3-68
OPERATIONAL AMPLIFIERS 3-73
SECTION 4 MAINTENANCE
PRELIMINARY INFORMATION 44
PANEL REMOVAL 4-4
POWER UNIT REMOVAL 4-2
PREVENTIVE MAINTENANCE 43
CLEANING 4-3
LUBRICATION 4-4
VISUAL INSPECTION 45
SEMICONDUCTOR CHECKS 45
RECALIBRATION 45
TROUBLESHOOTING 45
TROUBLESHOOTING AIDS 4-5
TROUBLESHOOTING EQUIPMENT 48
TROUBLESHOOTING TECHNIQUES 4-8
CORRECTIVE MAINTENANCE 4-13
OBTAINING REPLACEMENT PARTS 4-13
SOLDERING TECHNIQUES 4-13
COMPONENT REPLACEMENT 4-14
SEMICONDUCTOR REPLACEMENT 4-18
CATHODE-RAY TUBE REPLACEMENT 4-20
SWITCH REPLACEMENT 4-21
GRATICULE-BULB REPLACEMENT 4-22
POWER TRANSFORMER REPLACEMENT 4-22
HIGH VOLTAGE COMPARTMENT 4-22
FUSE REPLACEMENT 4-23
RECALIBRATION AFTER REPAIR 4-23
INSTRUMENT REPACKAGING 4-23

7623A/R7623A Service
TABLE OF CONTENTS (cont.)
SECTION 5 PERFORMANCE CHECK/CALIBRATION
PRELIMINARY INFORMATION
CALIBRATION INTERVAL
TEKTRONIX FIELD SERVICE
USING THIS PROCEDURE
TEST EQUIPMENT REQUIRED
SPECIAL CALIBRATION FIXTURES
CALIBRATION EQUIPMENT ALTERNATIVES
SIGNAL CONNECTIONS
WARM-UP AND TEMPERATURE REQUIREMENTS
PART I--PERFORMANCE CHECK
INTRODUCTION
OUTLINE FOR PART I-PERFORMANCE CHECK
PART H—CALIBRATION
INTRODUCTION
OUTLINE FOR PART II--CALIBRATION
SECTION 6 OPTIONS
SECTION 7 ELECTRICAL PARTS LIST
SECTION 8 DIAGRAMS
SECTION 9 MECHANICAL PARTS LIST
CHANGE INFORMATION
PAGE
5-1
5-1
5-1
5-1
5-1
5-2
5-2
5-2
5-2
5-6
5-6
5-6
5-26
5-26
5-26

vi
7623A/R7623A Service
LIST OF ILLUSTRATIONS
Frontispiece
Figure 1-1. Location of voltage-selector jumper.
Figure 1-2. Front panel controls and connectors.
Figure 1-3. Rear panel controls and connectors.
Figure 1-4. Definition of measurement lines on the graticule.
Figure 1-5. Location of Readout Mode switch.
Figure 1-6. Location of Calibrator jumper on Storage circuit board.
Figure 3-1. Block diagram 7623A.
Figure 3-2. Logic circuit block diagram.
Figure 3-3. Z-Axis logic block diagram.
Figure 3-4. (A) Clock Generator stage of U55A. (B) Idealized waveforms from Clock
Generator stage.
Figure 3-5. (A) Input and output pins for Vertical Chopped Blanking stage. (B) idealized
waveforms for Vertical Chopped Blanking stage.
Figure 3-6. (A) Logic diagram for Vertical Chopped Blanking stage. (B) Table of input/output
combinations for Vertical Chopped Blanking stage.
Figure 3-7. Detailed togic diagram of Chop Counter stage.
Figure 3-8. Idealized input and output waveforms for Chop Counter stage
Figure 3-9. Logic diagram of Vertical Mode Control and Vertical Mode Buffer Amplifier
stages.
Figure 3-10. Logic diagram of Vertical Binary stage.
Figure 3-11. Idealized waveforms showing relationship between input and output waveforms
for Vertical Binary and Plug-In Binary stages when operating in ALT mode.
Figure 3-12. Logic diagram of Plug-In Binary and Plug-In Alternate Buffer stage.
Figure 3-13. Detailed block diagram of Trigger Selector circuit along with simplified diagram
of trigger source selection circuitry.
Figure 3-14. Input levels at pin 4 of U324.
Figure 3-15. Input/output table for Trigger Channel Switch stage.
Figure 3-16. Vertical Interface detailed block diagram.
Figure 3-17. Input/output table for Vertical Channel Switch.
Figure 3-18. Vertical Amplifier detailed block diagram.
Figure 3-19. Horizontal Amplifier detailed block diagram.
Figure 3-20. CRT circuit detailed block diagram.
Figure 3-21. Low-Voltage Power Supply detailed block diagram.
Figure 3-22. Schematic illustrating voltage drop between power supply output and load due
to resistance of interconnecting wire.
Figure 3-23. Calibrator detailed block diagram.
Figure 3-24. Location of readout words on the crt identifying the originating plug-in unit
and channel (one complete frame shown).
PAGE
1-2
1-5
1-9
1-11
1-13
1-20
3-8
3-10
3-11
3-16
3-17
3-17
3-19
3-19
3-20
3-21
3-22
3-23
3-24
3-25
3-26
3-27
3-29
3-32
3-36
3-39
3-41
3-44

7623A/R7623A Service
LIST OF ILLUSTRATIONS (cont.)
PAGE
Figure 3-25. Character Selection Matrix for 7623A Readout System. 3-46
Figure 3-26. Typical readout display where only channel 2 of the Right Vertical and 3-47
Horizontal units is displayed.
Figure 3-27. Detailed block diagram of the Readout System. 3-48
Figure 3-28. Output waveforms of Timer stage. 3-50
Figure 3-29, Detail of output at pins 12, 13, 14, and 16 of U2126. 3-51
Figure 3-30. Timer stage operation when Display-Skip condition occurs. 3-52
Figure 3-31. Time relationship of the time-slot (TS) pulses produced by U2159. 3-53
Figure 3-32. Typical encoding scheme for voltage-sensing amplifier plug-in unit. Coding 3-57
shown for deflection factor of 100 microvolts.
Figure 3-33. Idealized current waveforms of: (A) Row analog data, (B) Column analog data. 3-58
Figure 3-34. Block representation of memory sequence in U2232. 3-61
Figure 3-35. Typical output waveforms for Zeros Logic and Memory stage operation (at pin 3-62
7 of U2232).
Figure 3-36. Readout word relating 10 possible character locations to the decimal point 3-65
instructions that can be encoded, and the resultant crt display.
Figure 3-37. Flow chart for character generation by the Readout System. 3-66
Figure 3-38. Storage circuit simplified block diagram. 3-68
Figure 3-39. Time relationship of Storage logic pulses. 3-69
Figure 3-40. BISTABLE mode Storage waveforms. 3-70
Figure 3-41. VAR PERSIST mode Storage waveforms. 3-71
Figure 3-42. FAST BISTABLE mode Storage waveforms. 3-72
Figure 3-43. FAST VAR PERSIST made Storage waveforms. 3-74
Figure 4-1. Power Unit removal. 4-2
Figure 4-2. Location of circuit boards in the 7623A. 46
Figure 4-3. Location of circuit boards in the R7623A. 4-7
Figure
4-4. Circuit isolation troubleshooting chart. 4-10
Figure 4-5. Location of screws holding Low Voltage sub-chassis. 4-17
Figure 4-6. Location of screws holding Signals Out rear panel. 4-18
Figure 5-1. Typical crt display when checking X-Y phase shift. 5-15
Figure 5-2. Location of Calibrator AC/DC jumper. 5-17
Figure 5-3. Location of High-Voltage Test Point. 5-30
Figure 5-4. Location of adjustments in High-Voltage cover. 5-32
Figure 5-5. Typical crt display when checking X-Y phase shift. 5-43
Figure 5-6. Location of Calibrator AC/DC jumper. 5-46
vii

7623A/R7623A Service
LIST OF ILLUSTRATIONS (cont.)
Section 8 figures are located near their associated diagrams on the foldout pages.
Figure 8-1.
Figure 8-2.
Figure 8-3.
Figure 8-4.
Figure 8-5.
Figure 8-6.
Figure 8-7.
Figure 8-8.
Figure 8-9.
Figure 8-10.
Figure 8-11.
Figure 8-12.
Figure 8-13.
Figure 8-14.
Figure 8-15.
Figure 8-16.
Figure 8-17.
Figure 8-18.
Figure 8-19.
Figure 8-20.
Figure 8-21.
Figure 8-22.
Figure 8-23.
Figure 8-24.
viii
Semiconductor lead configurations.
A1-Main Interface Board.
A2-Logic Board.
A3-Trigger Selector Board.
A4-Vertical Interface Board.
A5-Vertical Amplifier Board (front).
A5-Vertical Amplifier Board (rear).
A6-Horizontal Amplifier Board.
A7-Output Signals Board.
A8-Z-Axis Board.
A9-Anode Board.
A10-High-Voltage Board.
A11-Low-Voltage Rectifier Board.
A12-Low-Voltage Regulator Board.
A13-Readout Board.
A14-Storage Board.
Adjustment locations-Low-Voltage Regulator board.
Adjustment locations-Z-Axis board.
Adjustment locations-High-Voltage board.
Adjustment locations-Vertical Amplifier board.
Adjustment locations-Horizontal Amplifier board.
Adjustment locations-Signals Out board.
Adjustment locations-Readout board,
Adjustment locations-Storage board.