Teridian 73M1903 User manual

73M1903 MODEM ANALOG FRONT END DEMO BOARD User’s Manual
Revision 1.2 1 of 32
© Copyright 2005 TERIDIAN Semiconductor Corporation
TERIDIAN 73M1903
Modem Analog Front End
Demo Board
USER’S MANUAL
July 15, 2005
Version 1.2
TERIDIAN Semiconductor Corporation
6440 Oak Canyon Rd.
Irvine, CA 92618-5201
Ph: 714-508-8800 ▪Fax: [phone]
http://www.teridiansemi.com/

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© Copyright 2005 TERIDIAN Semiconductor Corporation
TERIDIAN Semiconductor Corporation makes no warranty for the use of its products, other than expressly contained in the
Company’s warranty detailed in the TERIDIAN Semiconductor Corporation standard Terms and Conditions. The company assumes
no responsibility for any errors which may appear in this document, reserves the right to change devices or specifications detailed
herein at any time without notice and does not make any commitment to update the information contained herein.

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73M1903
MODEM ANALOG FRONT END IC
DEMO BOARD
USER’S MANUAL
July 15, 2005
Revision 1.2

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Table of Contents
1GETTING STARTED ........................................................................................................................................ 7
1.1 General............................................................................................................................................................. 7
1.2 Safety and ESD Notes..................................................................................................................................... 7
1.3 DEMO BOARD LOOK ...................................................................................................................................... 7
2SYSTEM DESCRIPTION ................................................................................................................................ 11
2.1 MAFE INTERFACE......................................................................................................................................... 11
2.2 73M1903 Register map.................................................................................................................................. 13
2.3 73M1903 system initialization ...................................................................................................................... 14
3HARDWARE DESCRIPTION.......................................................................................................................... 17
3.1 Board SETTING: Jumpers and connectors................................................................................................. 17
3.2 Board Hardware Specifications ................................................................................................................... 20
4APPENDIX ...................................................................................................................................................... 21
4.1 example of typical sample rate SETTINGs.................................................................................................. 21
4.2 Demo Board Schematic Diagram................................................................................................................. 22
4.3 Demo Board BILLs of materials................................................................................................................... 25
4.4 Demo Board PCB LAYOUT........................................................................................................................... 28
4.5 73M1903 pin description............................................................................................................................... 31

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List of Figures
Figure 1-1: 73M1903 Demo Board................................................................................................................................. 8
Figure 1-2: TERIDIAN 73M1903 Demo Board connected to a Host System ................................................................. 8
Figure 1-3: Block diagram for the TERIDIAN 73M1903 Demo Board ........................................................................... 9
Figure 2-1: 73M1903 MAFE Interface signals.............................................................................................................. 11
Figure 2-2: MAFE Timing diagram ............................................................................................................................... 12
Figure 2-3: Serial Port Timing ...................................................................................................................................... 13
Figure 3-1: 73M1903 Demo board connectors and Jumper locations.......................................................................... 17
Figure 3-2: PCB Dimensions........................................................................................................................................ 20
Figure 4-1: Schematic Diagram of US low speed DAA ................................................................................................ 22
Figure 4-2: Schematic Diagram of US high speed DAA............................................................................................... 23
Figure 4-3: Schematic diagram of CTR21 DAA ........................................................................................................... 24
Figure 4-4:TERIDIAN 73M1903 DEMO BOARD: Silk Screen Top .............................................................................. 28
Figure 4-5: TERIDIAN 73M1903 DEMO BOARD: Top Signal Layer............................................................................ 28
Figure 4-6: TERIDIAN 73M1903 DEMO BOARD: Bottom Signal Layer....................................................................... 29
Figure 4-7: TERIDIAN 73M1903 DEMO BOARD: Supply Plane.................................................................................. 29
Figure 4-8: TERIDIAN 73M1903 DEMO BOARD: Ground Plane................................................................................. 30
List of Tables
Table 2-1: 73M1903 Demo Board jumpers and connectors......................................................................................... 13
Table 3-1: 73M1903 Demo Board Connectors............................................................................................................. 18
Table 3-2: 73M1903 Demo Board Jumpers ................................................................................................................. 18
Table 3-3: 73M1903 Demo Board jumper settings....................................................................................................... 19
Table 3-4: JP2 Pin assignments .................................................................................................................................. 19
Table 4-1: Typical sample rate setting examples ......................................................................................................... 21
Table 4-2:US Low Speed Bill of Materials.................................................................................................................... 25
Table 4-3: US high speed Bill of Materials ................................................................................................................... 26
Table 4-4: CTR 21 Bill of Materials .............................................................................................................................. 27

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1 GETTING STARTED
1.1 GENERAL
The TERIDIAN Semiconductor Corp. (TSC) 73M1903 Demo Board is a Modem Analog Front End
demonstration board with on board DAA for evaluating the 73M1903 device that can support up to
V.90/V.92 modulation and demodulation on high-performance DSP or CPU systems available in the
market. It incorporates a 73M1903 integrated circuit, a low speed U.S., high speed U.S., or CTR-21
compatible DAA telephone network interface. The Demo Board allows the evaluation of the 73M1903
Modem Analog Front End chip for universal modem and Fax applications, interfacing to DSPs or other
high performance processors. It is not intended for use with general-purpose controllers.
1.2 SAFETY AND ESD NOTES
THE 73M1903 DEMO BOARD IS ESD SENSITIVE! ESD PRECAUTIONS SHOULD
BE TAKEN WHEN HANDLING THE DEMO BOARD!
1.3 DEMO BOARD LOOK
The TERIDIAN Semiconductor Corporation (TSC) 73M1903 Demo Board shown in Figure 1-2 has a 20-
pin right angle connector to plug on to a target DSP or CPU system. It has a 3.3V power receptacle for
powering on board circuits from an external power supply or can be jumpered to receive power form the
host connector.
1

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Figure 1-1: 73M1903 Demo Board
Figure 1-2: TERIDIAN 73M1903 Demo Board connected to a Host System

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73M1903
SCLK
FSB
SDIN
TXAP
TXAN
RXAP
RXAN DAA
GPIO5(OH)
GPIO4(RING)
SDOUT PHONE
Line
POWER
SUPPLY
RESET
XTAL
73M1903 Evaluation board
OH
RING
Figure 1-3: Block diagram for the TERIDIAN 73M1903 Demo Board

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2 SYSTEM DESCRIPTION
2.1 MAFE INTERFACE
The Modem Analog Front End (MAFE) Interface is a serial port integrated into the TERIDIAN
TERIDIAN73M1903 device to interface to a host processor or a DSP. This serial data port is a bi-
directional port that can be supported by most DSPs with a synchronous serial port or GPIO that can be
configured as a serial port. The MAFE operates as a “master” device meaning it controls the timing and
data flow. The processor or DSP sends and receives data and control information based on the FS and
SCLK signals provided by the 73M1903.
SCLK
FSB
OSCIN
SDIN
SDOUT
73M1903
(Master)
Type
SckMod
"1/0"
"1/0"
FSB
SCLK
SDIN
SDOUT
MCLK
HOST
(Slave)
Figure 2-1: 73M1903 MAFE Interface signals
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TX15 TX14 TX13 TX12 TX11 TX10 TX9 TX8 TX7 TX6 TX5 TX4 TX3 TX2 TX1 TX0
RX15 RX14 RX13 RX12 RX11 RX10 RX9 RX8 RX7 RX6 RX5 RX4 RX3 RX2 RX1 RX0
SCLK
SDOUT
SDIN
FSB
TX15 TX14 TX13 TX12 TX11 TX10 TX9 TX8 TX7 TX6 TX5 TX4 TX3 TX2 TX1 TX0
RX15 RX14 RX13 RX12 RX11 RX10 RX9 RX8 RX7 RX6 RX5 RX4 RX3 RX2 RX1 RX0
SCLK
SDOUT
SDIN
FSB
Data Frame with Early Frame Sync
Data Frame with Late Frame Sync
R/W A6 A5 A4 A3 A2 A1 A0 DI7 DI6 DI5 DI4 DI3 DI2 DI1 DI0
0 0 0 0 0 0 0 0 DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0
Control Frame Data format
SCLK
SDOUT
SDIN
FSB
Figure 2-2: MAFE Timing diagram

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SCLK
SDOUT
SDIN
FSB
TXD
RXD
CTRL-DI
CTRL-DO
TXD
RXD
CTRL-DI
CTRL-DO
CONTROL FRAME
DATA FRAME
ONE SAMPLE PERIOD
CONTROL FRAMEDATA FRAME
SCLK
SDOUT
SDIN
FSB
TXD
RXD
TXD
RXD
CTRL-DI
CTRL-DO
D0=0 D0=1
TXD
RXD
TXD
RXD
D0=0
ONE SAMPLE PERIOD
HARDWARE CONTROLLED CONTROL FRAME
SOFTWARE CONTROLLED CONTROL FRAME
Figure 2-3: Serial Port Timing
2.2 73M1903 REGISTER MAP
The following table shows the memory map of addressable registers in the 73M1903. Each register and
bits can be read or written by a host processor or a DSP using the control frames over the MAFE
interface. All registers and their bits are described in detail in 73M1903 datasheet. For more information,
please refer to the datasheet.
ADRESS Default BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
00 08h ENFE - TXBST1 TXBST0 TXDIS RXG1 RXG0 RXGAIN
01 00h TMEN DIGLB ANALB INTLB - RXPULL SPOS HC
02 FFh GPIO7 GPIO 6 GPIO 5 GPIO 4 GPIO 3 GPIO 2 GPIO 1 GPIO 0
03 FFh DIR7 DIR6 DIR5 DIR4 DIR3 DIR2 DIR1 DIR0
04 00h ENGPIO7 ENGPIO6 ENGPIO5 ENGPIO4 ENGPIO3 ENGPIO2 ENGPIO1 ENGPIO0
05 00h POL7 POL6 POL5 POL4 POL3 POL2 POL1 POL0
06 40h Rev3 Rev2 Rev1 Rev0 - Trim(2) Trim(1) Trim(0)
07 00h - - - - - - - -
08 00h Pseq7 Pseq6 Pseq5 Pseq4 Pseq3 Pseq2 Pseq1 Pseq0
09 0Ah Prst2 Prst1 Prst0 Pdvsr4 Pdvsr3 Pdvsr2 Pdvsr1 Pdvsr0
0A 22h Ichp3 Ichp2 Ichp1 Ichp0 FL Kvco2 Kvco1 Kvco0
0B 12h Unused Ndvsr6 Ndvsr5 Ndvsr4 Ndvsr3 Ndvsr2 Ndvsr1 Ndvsr0
0C 00h Nseq7 Nseq6 Nseq5 Nseq4 Nseq3 Nseq2 Nseq1 Nseq0
0D C0h Xtal1 Xtal0 LokdetEn ThLk0 - Nrst2 Nrst1 Nrst0
0E 00h Frcvco PwdnPLL Lokdet - - - - -
0F-7F - - - - - - - -
Table 2-1: 73M1903 Demo Board jumpers and connectors

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2.3 73M1903 SYSTEM INITIALIZATION
The following example shows the sequence to bring the 73M1903 device out of reset and to start up after
power up.
NOTE: The TERIDIAN73M1903 device does not have an automatic power on reset circuit. After the
power has stabilized, a reset signal should be asserted from the host by pulling the reset pin low for
100ns or longer. The 73M1903 device will be ready to use within 100us after the removal of the reset
pulse from this pin.
RESET 73M1903 Device
1. Power up the system
2. Wait for 3.3V power to be stable
3. Hold RESET pin low for 100ns, then return to high state
4. Wait for 100us for PLL, OSC to be stabilized
Initialing the 73M1903 Device from an unknown state
A. FRAME SYNCHRONIZATION
1. RESET HC bit (Reg01 bit 0) in a frame sequence
2. RESET HC bit (Reg01 bit 0) in next frame sequence
The 73M1903 is guaranteed to be in software-controlled control frame mode. All the MAFE serial data
will be data unless the host requests a control frame by setting bit 0 of data.
B. CONTROL FRAME GENERATION
SOFTWARE CONTROLLED CONTROL FRAME
1. Set TXD Bit 0 to 1 to request a control frame.
2. Write or read the 73M1903 register using the MAFE control data format.
3. Make sure to clear TXD bit 0 to 0 if another control frame is not needed.
HARDWARE CONTROLLED CONTROL FRAME
1. Set TXD Bit 0 to 1 to request a subsequent control frame.
2. SET HC bit (Reg01 bit0) using the MAFE control data format in the next frame.
There will now be alternating data and control frames. It will be necessary to keep track of whether
the 73M1903 is in a data or control frame from this point forward.
Example 1. Using Software controlled control Frame (Note: CTRL_FRAME = 0x0001):
static const U16 init_afe_config[] = // MUST HAVE Data(LSB=1), Control, Data(LSB=1),Control,….
{
CTRL2|0x00, CTRL2|0x00, // Force to Software controlled control frame
CTRL_FRAME, CTRL13|0x00, // Force to Xtal clock
CTRL_FRAME, CTRL1|ENFE, // Enable Analog
CTRL_FRAME, CTRL2|0x00, // Software controlled control frame
CTRL_FRAME, GPIO|0x00,
CTRL_FRAME, GDIR|0xD0, // GPIO 7,6,4=in 5,3,2,1,0=output
CTRL_FRAME, GIE|0x00,
CTRL_FRAME, GIP|0x00,
CTRL_FRAME, BGTRIM|0x00,
CTRL_FRAME, TEST|0x00,
CTRL_FRAME, CTRL08|AFE_CTRL08, // Timing NCO set up
CTRL_FRAME, CTRL09|AFE_CTRL09,
CTRL_FRAME, CTRL10|AFE_CTRL10,
CTRL_FRAME, CTRL11|AFE_CTRL11,
CTRL_FRAME, CTRL12H|AFE_CTRL12H,
CTRL_FRAME, CTRL12L|AFE_CTRL12L,
CTRL_FRAME, RWB|GPIO, // Delay for 2 sample cycle time to
CTRL_FRAME, RWB|GPIO, // let PLL settle before Lockdet

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CTRL_FRAME, CTRL13|AFE_CTRL13
};
Example 2. Using Automatic control Frame (Hardware controlled control frame):
static const U16 init_afe_config[] = // MUST HAVE Dummy Data, Control, Dummy Data…..
FRAMES
{
CTRL2|0x00, CTRL2|0x00, // Force to Software controlled control frame
CTRL_FRAME, CTRL13|0x00, // Force to Xtal clock
CTRL_FRAME, CTRL1|ENFE|HC, // Enable Analog
0x0000, GPIO|0x00, // Forces DATA to be 0x0000
0x0000, GDIR|0xD0, // GPIO 7,6,4=in 5,3,2,1,0=output
0x0000, GIE|0x00,
0x0000, GIP|0x00,
0x0000, BGTRIM|0x00,
0x0000, TEST|0x00,
0x0000, CTRL08|AFE_CTRL08, // Timing NCO set up
0x0000, CTRL09|AFE_CTRL09,
0x0000, CTRL10|AFE_CTRL10,
0x0000, CTRL11|AFE_CTRL11,
0x0000, CTRL12H|AFE_CTRL12H,
0x0000, CTRL12L|AFE_CTRL12L,
0x0000, RWB|GPIO, // Delay for 2 sample cycle time to
0x0000, RWB|GPIO, // let PLL settle before Lockdet
0x0000, CTRL13|AFE_CTRL13
};

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3 HARDWARE DESCRIPTION
3.1 BOARD SETTING: JUMPERS AND CONNECTORS
Figure 3-1 shows the connectors and jumpers available on 73M1903 Demo Boards. JS1 is the
main connector for communicating with a host processor or DSP board. The pins of this interface
connector are configurable by 0 Ohm resistors. R26 through R47 are option-setting resistors.
Tables 3-2 and 3-3 describe the details of the jumper settings and 0 Ohm resistor population
options. J5 is a modular connector for phone line connection and J4 is for power connection from
the main board or an external power supply.
J5
JS1
JP2
J
2
J
1
J
P
1
J
P
3
J4
Jumper Resistors
Figure 3-1: 73M1903 Demo board connectors and Jumper locations
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Schematic &
PCB reference Name Description
JS1 0.100” 10X2 position
socket
20 pin connector to interface 73M1903 Demo Board to a
HOST controller main board.
JP2 HEADER 5X2 10 pin interface connector/MAFE test points/interface
J5 RJ-11 Telephone line connector
J4 3.3V external supply Plug for connecting external 3.3 V DC power supply
Table 3-1: 73M1903 Demo Board Connectors
Schematic &
PCB reference Name Description
J1 Ring detector
output
Three-pin header that allows selection of the Ring detector
output to connect to either GPIO4 of 73M1903 or to a Host
CPU GPIO through JS1 or JP25.
1-2: Ring detector output is fed to 73M1903 GPIO4. (73M1903
GPIO4 must be configured as an input.)
2-3: Ring detector output is directed to a host controller
through either JS1 or JP25
J2 Off-hook control Three-pin header that allows selection of the Off-hook control
by 73M1903 GPIO5 or by a Host CPU GPIO through JS1 or
JP25.
1-2: Off-hook is controlled by 73M1903 GPIO5. (73M1903
GPIO5 must be configured as an output.)
2-3: Off-hook is controlled by a host output through either JS1
or JP25.
JP1 FS Mode 2-pin header to select the behavior of FSB. When left open it
is pulled high by and internal pull-up. FSB will be a pulse at
the beginning of each data or control frame. When JP1
installed, FSB will be low during the transmission or reception
of the 16 bits of data, then high until the start of the next frame.
FSB will also be low during each control frame. In most
applications JP1 is left open.
JP3 SCLKmode JP3 controls the operation of the SCLK signal. When JP3 is
left open SCLK will be continuous. When JP3 is installed,
SCLK will be a burst of 32 clocks after each FSB. In most
applications JP3 is left open.
Table 3-2: 73M1903 Demo Board Jumpers

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The following table describes the connection options for JS1. JS1 can be to be used in applications
where the 73M1903 demo board is plugged directly into a target application or adaptor board. It also
allows flexibility in the assignment of the signals to the connector. If a ribbon cable connection is
preferred, JP2 can be used instead.
Schematic &
PCB reference Signal JS1 Pin Connection
R26 AFEIN JS1 connector pin 17 to be used as AFEIN.
R27 AFEIN JS1 connector pin 15 to be used as AFEIN.
R30 RINGD JS1 connector pin15 to be used as RINGD.
R31 HOOK JS1 connector pin 13 to be used as HOOK.
R32 AFEOUT JS1 connector pin 5 to be used as AFEOUT.
R33 AFEOUT JS1 connector pin 16 to be used as AFEOUT.
R34 AFEOUT JS1 connector pin 11 to be used as AFEOUT.
R35 FS JS1 connector pin 9 to be used as FS.
R36 FS JS1 connector pin 7 to be used as FS.
R37 FS JS1 connector pin 18 to be used as FS.
R38 RESET JS1 connector pin 4 to be used as RESET.
R39 AFEIN JS1 connector pin 4 to be used as AFEIN.
R40 SCLK JS1 connector pin 17 to be used as SCLK.
R41 SCLK JS1 connector pin 6 to be used as SCLK.
R42 SCLK JS1 connector pin 7 to be used as RESET.
R43 VCCD JS1 connector pin 2 to be used as VCCD. (3.3V Digital supply)
R44 GNDD JS1 connector pin 20 to be used as Digital Signal ground.
R45 RINGD JS1 connector pin 9 to be used as RINGD.
R46 LIUCK JS1 connector pin 12 to be used as LIUCK.
R47 HOOK JS1 connector pin 10 to be used as HOOK.
Table 3-3: 73M1903 Demo Board jumper settings.
Only one jumper should be used per signal. Bold signals are the defaults when the board is shipped.
The jumpers used depend on the way different features are supported. It is assumed that the GPIO will
be used for Hook control and Ring detection. J1 and J2 should be set accordingly.
JP2 is an alternative MAFE interface connector with the following pin assignments.
Pin Name Pin Name
1 LIUCK 6 SCLK
2 RINGD 7 AFEIN
3 HOOK 8 AFEOUT
4 FSB 9 RESET
5 NC 10 GND
Table 3-4: JP2 Pin assignments

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3.2 BOARD HARDWARE SPECIFICATIONS
PWR
RJ11
20P CONN
TRANS
Conn
4.00
2.00
0.69
0.62
1.17 1.18
0.27
0.35
0.33
0.20 0.15
Figure 3-2: PCB Dimensions
PCB Dimensions
• Size 4.00x2.00”
• Height w/ components and solder 0.61”
Environmental
• Operating Temperature -40 to +75°C
(function of crystal oscillator affected outside –10°C to +60°C)
• Storage Temperature -65 to 150°C
Power Supply
• DC Input Voltage (powered from DC supply) 3.3VDC ±0.5V
• Supply Current 25mA (off hook) typical