Teridian 73S1210F User manual

Simplifying System Integration
TM
73S1210F
Evaluation Board User Guide
August 18, 2009
Rev. 1.2
UG_1210F_035
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73S1210F Evaluation Board User Guide UG_1210F_035
2 Rev. 1.2
© 2009 Teridian Semiconductor Corporation. All rights reserved.
Teridian Semiconductor Corporation is a registered trademark of Teridian Semiconductor Corporation.
Simplifying System Integration is a trademark of Teridian Semiconductor Corporation.
Microsoft, Windows and Vista are registered trademarks of Microsoft Corporation.
Signum is a trademark of Signum Systems Corporation.
Keil is a trademark of ARM® Ltd.
All other trademarks are the property of their respective owners.
Teridian Semiconductor Corporation makes no warranty for the use of its products, other than expressly
contained in the Company’s warranty detailed in the Teridian Semiconductor Corporation standard Terms
and Conditions. The company assumes no responsibility for any errors which may appear in this
document, reserves the right to change devices or specifications detailed herein at any time without
notice and does not make any commitment to update the information contained herein. Accordingly, the
reader is cautioned to verify that this document is current by comparing it to the latest version on
http://www.teridian.com or by checking with your sales representative.
Teridian Semiconductor Corp., 6440 Oak Canyon, Suite 100, Irvine, CA 92618
TEL [phone], FAX [phone], http://www.teridian.com
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UG_1210F_035 73S1210F Evaluation Board User Guide
Rev. 1.2 3
Table of Contents
1Introduction ...................................................................................................................................4
1.1 Evaluation Kit Contents.........................................................................................................5
1.2 Evaluation Board Features....................................................................................................5
1.3 Recommended Equipment and Test Tools............................................................................5
2Evaluation Board Setup.................................................................................................................6
2.1 Connecting the Evaluation Board with an Emulation Tool......................................................7
2.2 Loading User Code into the Evaluation Board .......................................................................8
3Using the PCCID Application......................................................................................................10
3.1 Host Demonstration Software Installation............................................................................10
4Evaluation Board Hardware Description....................................................................................11
4.1 Jumpers, Switches and Modules.........................................................................................11
4.2 Test Points .........................................................................................................................16
4.3 Schematic...........................................................................................................................17
4.4 PCB Layouts.......................................................................................................................18
4.5 Bill of Materials ...................................................................................................................24
4.6 Schematic Information ........................................................................................................26
4.6.1 Reset Circuit..............................................................................................................26
4.6.2 Oscillator...................................................................................................................26
4.6.3 LCD ..........................................................................................................................27
4.6.4 Smart Card Interface .................................................................................................28
5Ordering Information...................................................................................................................29
6Related Documentation...............................................................................................................29
7Contact Information.....................................................................................................................29
Revision History..................................................................................................................................30
Figures
Figure 1: 1210F Evaluation Board............................................................................................................4
Figure 2: 73S1210F Evaluation Board Basic Connections........................................................................6
Figure 3: 73S1210F Evaluation Board Basic Connections with ADM-51 ICE............................................7
Figure 4: EmulatorWindow Showing RESETand ERASE Buttons...........................................................9
Figure 5: Emulator Window Showing Erased Flash Memory and File Load Menu.....................................9
Figure 6: 73S1210F Evaluation Board Jumper, Switch and Module Locations........................................15
Figure 7: 73S1210F Evaluation Board Electrical Schematic ...................................................................17
Figure 8: 73S1210F Evaluation Board Top View (Silkscreen).................................................................18
Figure 9: 73S1210F Evaluation Board Bottom View (Silkscreen)............................................................19
Figure 10: 73S1210F Evaluation Board Top Signal Layer ......................................................................20
Figure 11: 73S1210F Evaluation Board Middle Layer 1 – Ground Plane.................................................21
Figure 12: 73S1210F Evaluation Board Middle Layer 2 – Supply Plane .................................................22
Figure 13: 73S1210F Evaluation Board Bottom Signal Layer .................................................................23
Figure 14: External Components for RESET..........................................................................................26
Figure 15: Oscillator Circuit....................................................................................................................26
Figure 16: LCD Connections..................................................................................................................27
Figure 17: Smart Card Connections.......................................................................................................28
Tables
Table 1: Flash Programming Interface Signals.........................................................................................8
Table 2: Evaluation Board Jumper, Switch and Module Description .......................................................11
Table 3: Evaluation Board Test Point Description...................................................................................16
Table 4: 73S1210F Evaluation Board Bill of Materials............................................................................24
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73S1210F Evaluation Board User Guide UG_1210F_035
4 Rev. 1.2
1 Introduction
The Teridian Semiconductor Corporation (TSC) 73S1210F Evaluation Board is used to demonstrate the
capabilities of the 73S1210F Smart Card Controller devices. It has been designed to operate either as a
standalone or as a development platform.
The 73S1210F Evaluation Board can be programmed to run any of the Teridian turnkey applications or a
user-developed custom application. Teridian provides its USB CCID application preloaded on the board
and an EMV testing application on the CD.
Applications can be downloaded through the In-Circuit-Emulator (ICE) or through the TSC Flash
Programmer Model TFP2. As a development tool, the evaluation board can operate in conjunction with
an ICE to develop and debug 73S1210F based embedded applications.
The 73S1210F Evaluation Board uses the same PWB as the 73S1217F. The 73S1217F has
some features that the73S1210F does not contain. These include the 32 kHz oscillator and
USB interface. These features are depopulated on the 73S1210F Evaluation Board.
Figure 1: 1210F Evaluation Board
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UG_1210F_035 73S1210F Evaluation Board User Guide
Rev. 1.2 5
1.1 Evaluation Kit Contents
The 73S1210F Evaluation Kit contains the following:
•73S1210F Evaluation Board: 4-layer, rectangular PCB as shown in Figure 1(identification number
E1217FN12B1 Rev B), containing the 73S1210F with the preloaded Pseudo-CCID (PCCID) program.
•5 VDC/1,000 mA universal wall transformer with 1.0 mm plug ID (CUI Inc. – EPAS-101W-05).
•Serial cable: DB9, male/female, 2 meter length (Digi-Key AE1379-ND).
•CD containing documentation (data sheet, and user guides), Software API libraries, evaluation code,
and utilities.
•The 73S1210F Evaluation Board Lite QuickStart Guide document.
1.2 Evaluation Board Features
The 73S1210F Evaluation Board (see Figure 1) includes the following:
•RS-232 interface
•Dual smart card interface
•ICE/Programmer interface
•2 line x 16 character LCDmodule
•6 x 5 Keypad
•1 LED
1.3 Recommended Equipment and Test Tools
The following equipment and tools (not provided) are recommended for use with the 73S1210F
Evaluation Kit:
•For functional evaluation: PC with Microsoft®Windows®XP or Vista®equipped with an RS232 (COM)
port with DB9 connector.
•For software development (MPU code)
Signum™ ICE (In Circuit Emulator): ADM-51. Refer to
http://signum.temp.veriohosting.com/Signum.htm.
Keil™ 8051 C Compiler Kit: CA51. Refer to http://www.keil.com/c51/ca51kit.htm, and
http://www.keil.com/product/sales.htm
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73S1210F Evaluation Board User Guide UG_1210F_035
6 Rev. 1.2
2 Evaluation Board Setup
Figure 2shows the basic connections of the evaluation board with the external equipment.
The power supply can come from two sources:
•A regulated lab power supply connected to the banana plugs J2, J3 and J5.
•Any AC-DC converter block, able to generate a DC power supply of 2.7 V min / 6.5 V max / 400 mA.
The communication with an external host is accommodated via a standard RS-232 serial interface
(TX/RX only).
The board is loaded by default with the PCCID application. It requires a PC to be connected through its
serial port. When powered-up, the board is able to run with the PC Exerciser host application. Refer to
the 73S1210F Evaluation Board Quick Start Guide to setup and run the PCCID application.
Figure 2: 73S1210F Evaluation Board Basic Connections
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UG_1210F_035 73S1210F Evaluation Board User Guide
Rev. 1.2 7
2.1 Connecting the Evaluation Board with an Emulation Tool
The 73S1210F Evaluation Board has been designed to operate with an In-Circuit-Emulator (ICE) from
Signum Systems (model ADM-51). Figure 3shows the connections between the ICE and the evaluation
board. The Signum System POD has a ribbon cable that must be directly attached to connector J11.
Signum Systems offers different POD options depending on user needs. The standard pod allows users
to perform typical emulator functions such as symbolic debugging, in-line breakpoints, memory
examination/modification, etc. Other pod options enable code trace capability and/or complex
breakpoints at an additional cost.
Figure 3: 73S1210F Evaluation Board Basic Connections with ADM-51 ICE
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73S1210F Evaluation Board User Guide UG_1210F_035
8 Rev. 1.2
2.2 Loading User Code into the Evaluation Board
Hardware Interface for Programming
The signals listed in Table 1are necessary for communication between the TFP2 or ICE and the
73S1210F.
Table 1: Flash Programming Interface Signals
Signal Direction Function
E_TCLK Output from 73S1217F Data clock
E_RXTX Bi-directional Data input/output
E_RST
1
Bi-directional Flash Downloader Reset (active low)
1
The E_RST signal should only be driven by the TFP2 when enabling these
interface signals. The TFP2 must release E_RST at all other times.
These signals, along with 3.3 V and GND are available on the emulator header J11. Production modules
may be equipped with much simpler programming connectors, e.g. a 5x1 header.
Programming of the flash memory requires either the Signum Systems ADM51 in-circuit emulator or the
Flash Download Board Module (FDBM) provided by Teridian.
Loading Code with the In-Circuit Emulator
If firmware exists in the 73S1210F flash memory, the memory must be erased before loading a new file
into memory. In order to erase the flash memory, the RESET button in the emulator software must be
clicked followed by the ERASE button (see Figure 4).
Once the flash memory is erased, the new file can be loaded using the Load command in the File menu.
The dialog boxshown in Figure 5makes it possible to select the file to be loaded by clicking the Browse
button. Once the file is selected, pressing the OK button loads the file into the flash memory of the IC.
At this point, the emulator probe (cable) can be removed. Once the 73S1210F device is reset using the
reset button on the evaluation board, the new code starts executing.
Loading Code with the TSC Flash Programmer Model TFP2
Follow the instructions given in the TSC Flash Programmer Model TFP2 User's Manual.
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UG_1210F_035 73S1210F Evaluation Board User Guide
Rev. 1.2 9
Figure 4: Emulator Window Showing RESET and ERASE Buttons
Figure 5: Emulator Window Showing Erased Flash Memory and File Load Menu
RESET
BUTTON
ERASE
BUTTON
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73S1210F Evaluation Board User Guide UG_1210F_035
10 Rev. 1.2
3 Using the PCCID Application
The PCCID firmware is pre-installed on the 73S1210F Evaluation Board. It requires a PC with the serial
RS-232 port. When powered-up, the board is able to run the PCCID demonstration host application which
allows:
•Smart card activation and deactivation, in ISO or EMV mode.
•Smart card APDU commands to be exchanged with the smart card inserted in the board.
•Starting a test sequence in order to test and evaluate the board performance against an EMV test
environment.
3.1 Host Demonstration Software Installation
Installation on Windows XP
Follow these steps to install the software on a PC running Windows XP:
•Extract “PCCID Vz.zz Release.zip” (where z.zz is the latest version of the firmware release).
oCreate an install directory. For example: “C:\TSC\”.
oUnzip “PCCID Vz.zz Release.zip” to the just created folder. All applications and documentation
needed to run the board with a Windows PC will be loaded to this folder.
•Plug the supplied adapter into the 5V DC jack and a wall outlet.
•Connect the serial cable between the host system and the 73S1210F Evaluation Board.
•Press the ON/OFF switch to turn the board on.
•Run “TSCP-CCID.exe” (located in the path - x:\yyy\ PCCID Vz.zz Release\Host
Applications\Windows App\App\Bin\Release) on the host system to execute the host demonstration
application (where xrefers to the drive, yyy refers to the directory the installation .zip file was
expanded to and z.zz is the latest version of the firmware release).
At this point the application window should appear. For additional information regarding the use of the
Teridian Host application, refer to the Pseudo-CCID Host GUI Users Guide (UG_12xxF_037).
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UG_1210F_035 73S1210F Evaluation Board User Guide
Rev. 1.2 11
4 Evaluation Board Hardware Description
4.1 Jumpers, Switches and Modules
Table 2 describes the73S1210F Evaluation Board jumpers, switches and modules. The Item # in Table 2
references Figure 6.
Table 2: Evaluation Board Jumper, Switch and Module Description
Item
#
Schematic
and
Silkscreen
Reference
Default
setting Name Use
1 J2, J3, J5 No
Connect Banana plugs for
external regulated
power supply
Must be used to connect an external power
supply. These inputs are intended to allow
control of the input supply voltage of the board.
JP5 must be in position “EXT VPC” when using
VPC and JP8 must be in position “EXT” when
using the VBAT power supply inputs.
The evaluation board is sensitive to the polarity:
One red plug is +2.7/6.5 V for external VPC and the other red plug is +4.0/6.5 V for VBAT. The
black plug is ground.
2 JP2 +5V 73S8010R VPC select Selects VPC power supply source for the
73S8010R device between VP on the 73S1210F
and +5 V from JP1 pin 2.
3 J11 Not
Inserted In-Circuit Emulator
connector This connector must be used when using an external In-Circuit Emulator (SIGNUM 8052
ADM51 ICE). Refer to the Electrical Schematic for
pin assignment.
4 PJ1 Connect DC jack Plug to connect an external DC block. Must be
used in conjunction with appropriate settings of
S1, JP1 and JP6 (see details above).
Power supply features are:
Voltage: 2.7 V to 6.5 V
Current: 400 mA
5 JP6 VDD RS-232 Xcvr enable
jumper
Selects between VDD (always enabled) and a
test point (with pull down) to allow the RS232
transceiver chip to be shut down.
6 P1 Connect DB9 RS232 female
socket This socket allows connection of an RS232 cable to a computer. Use crossed wired (RX/TX)
cable. The evaluation board has an on-board
level shifter (U7) to allow direct connection to a
computer.
Connection to an RS232 link is required when
using the pre-downloaded PCCID application.
7 JP3 Inserted RS-232 Xcvr power Power supply jumper for the RS232 transceiver
chip. Can be removed to obtain accurate power
measurements.
8 D2, D3 LEDs: These LEDs (D2, D3) reflect the activity on the
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73S1210F Evaluation Board User Guide UG_1210F_035
12 Rev. 1.2
Item
#
Schematic
and
Silkscreen
Reference
Default
setting Name Use
Serial link activity
serial link (RS232 or serial).
•D2 reflects the activity on the RX line (Data
going TO the 73S1210F)
•D3 reflects the activity on the TX line (Data
going FROM the 73S1210F)
9 U5 LCD Module On-board LCD module:
•2 lines of 16 characters, each character dot
matrix is 5x7.
•Includes an embedded Hitachi HD44780 LCD
driver, controlled from the on-board 73S1210F
USR interface.
10 RV1 Adjustable resistor to
adjust LCD brightness Can be used to adjust the brightness of the on- board LCD module.
11 S2 to S26,
S27 to S32 On-board keypad 5x6 keyboard directly connected to the on-board 73S1210F IC (68-pin only). The assignment of
the keys, as silk-printed on the PCB, is the one
supported by the TSC Application Programming
Interface.
12 – Board reference and
serial number
Should be mentioned in any communication with
TSC Application Engineers when requesting
support.
13 D8 VDD power indicator
Indicates when the 73S1210F is turned on (VDD
= 3.3 V).
14 S33 ON/OFF switch Switch used to turn on and off the 73S1210F.
The switch is overridden when VBUS is applied
(VDD is always on).
When VDD is on and the switch is pressed, the
73S1210F will activate the OFF_REQ signal and
the 73S1210F must set the SCPWRDN or
PWRDN bits to shutoff VDD.
15 JP7 ON/OFF Power ON/OFF select
jumper This jumper will select between the ON/OFF
switch and ground. When the switch is selected,
the VDD power will toggle between on and off
(see item #16). When ground is selected, the
VDD will turn on automatically upon application
of VPC to the 73S1210F.
16 – Breadboard area This breadboard area allows engineers to add
their own circuitry / connection of peripherals
when prototyping and developing a 73S1210F
based application. User I/Os, GPIOs, interrupt
pins and power supply pins are located close to
this area to allow easy connection.
17 JP9 OFF_REQ INT3 select Selects the source for INT3 between the
73S8010R and the OFF_REQ pin on the
73S1210F. Should be set opposite of JP21.
18 JP21 8010R
INT INT2 select Selects the source for INT2 between the
73S8010R and the OFF_REQ pin on the
73S1210F. Should be set opposite of JP9.
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UG_1210F_035 73S1210F Evaluation Board User Guide
Rev. 1.2 13
Item
#
Schematic
and
Silkscreen
Reference
Default
setting Name Use
19 JP13 Not
Inserted Jumper: USR7/SDA
select This jumper selects which signal is connected to the daughter board connector pin USR7:
•In position “USR7”, the 73S1210F USR7
signal is connected to the daughter card pin
USR7.
•In position “SDA”, the I2C SDA signal is
connected to the daughter card pin USR7.
This allows the SDA line to connect to an
SDA pin on a 73S8010Rdaughter card.
20 JP14 Not
Inserted Jumper: USR7/SDA
select This jumper allows the on board 73S8010R AUX2 pin to be connected to USR5 if needed. If
not needed, the jumper should be removed.
21 U4 On board 73S8010R The board contains a built-in 73S8010R that is
connected to the external smart card interface of
the 73S1210F. This device can be disconnected
from the 73S1210F if not used, by removing
jumpers JP12 and JP21.
22 J7,J8 Optional 73S80xxX
Daughter Board
interface
When developing applications that require more
than 2 smart card interfaces, an optional daughter
board can be populated to use the 73S1210F
external smart card interface (lines SCIO and
SCK), in conjunction with the USR(0:7) port and
the INT2 interrupt input of the 73S1210F). Refer
to the Electrical Schematic for pin assignment.
23 J9, J10 SIM / SAM and Smart
Card connectors –
external interface (#2)
Allows the evaluation board to communicate with
a smart card using either the standard (credit
card size) or SIM/SAM format. This slot is
connected to the 73S1210F external card
interface # 2.
Note that J10 is wired is parallel to the smart
card connector J9 (underneath the PCB). Both
connectors cannot be populated at the same
time.
24 JP11 Not
Inserted Jumper: USR6/SCL
select This jumper selects which signal is connected to the daughter board connector pin USR6:
•In position “USR6”, the 73S1210F USR6
signal is connected to the daughter card pin
USR6.
•In position “SCL”, the I2C SCL signal is
connected to the daughter card pin USR6.
This allows the SCL line to connect to an SCL
pin on a 73S8010R daughter card.
25 JP10 Not
Inserted Jumper: USR6/AUX1
select This jumper allows the on board 73S8010R AUX1 pin to be connected to USR6 if needed. If
not needed the jumper should be removed.
26 S27 Reset button Evaluation board main reset: Asserts a hardware
reset to the on-board 73S1210F IC.
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73S1210F Evaluation Board User Guide UG_1210F_035
14 Rev. 1.2
Item
#
Schematic
and
Silkscreen
Reference
Default
setting Name Use
27 JP12 Inserted LED0 jumper
In normal use, a jumper must be inserted in this
header to connect the LEDs to the LED pins of
the 73S1210F. This jumper can be replaced by
a µA / mA-meter to measure the actual current
drawn by the LED output of the 73S1210F.
28 JP15 GND Jumper: security fuse
control This jumper should be removed at all times. Connecting the jumper will allow the security
fuses to be blown under firmware control. Refer
to the 73S1210F Data Sheet for further
information about the security fuse.
29 JP20 Not
Inserted Analog select Selects the analog input between TP32 and the
VBAT input voltage (via resistor divider).
30 JP8 Not
Inserted VBAT select Selects the VBAT input between an external
supply on J3 or the unregulated 5 V on PJ1.
31 J1, J4 SIM / SAM and Smart
Card connectors –
internal interface (#1)
Allows the evaluation board to communicate with
a smart card using either the standard (credit
card size) or SIM/SAM format: This slot is
connected to the 73S1210F built-in card
interface # 1.
J1 is wired in parallel to the smart card connector
J4 (underneath the PCB). Both connectors
cannot be used at the same time.
32 JP4 Inserted VDD jumper The VDD
supply jumper can be replaced with an
current meter to measure the power
consumption on VDD.
33 JP1 5V Unreg Jumper:
5V power supply
selection
This jumper selects the 5.0 V power supply. It
selects either the unregulated 5 V supply from
PJ1 or the 5.0 V from the USB VBUS:
•In position “5V UNREG”, the evaluation
board 5.0 V is powered from the PJ1
connector.
•In position “VBUS”, the evaluation board is
powered from USB VBUS.
34 JP5 5V Unreg Jumper:
VPC power supply
selection
This jumper selects the VPC power supply. It
selects either the power supply connected to
plug J2 or the 5 V unregulated supply on the PJ1
connector.
•In position “5V UNREG”, the evaluation
board VPC is connected to 5 V coming in on
PJ1.
•In position “EXT VPC”, the evaluation board
VPC is powered from the voltage applied on
the plug J2.
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UG_1210F_035 73S1210F Evaluation Board User Guide
Rev. 1.2 15
123456789
10
11
22 21 20
19
18
17
16 15 14 13 12
23
24
25
26
27
28
30
29
31
32
33
34
Figure 6: 73S1210F Evaluation Board Jumper, Switch and Module Locations
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73S1210F Evaluation Board User’s Guide UG_1210F_035
16 Rev. 1.2
4.2 Test Points
The test point numbers listed in Table 3refer to the test point numbers shown in the electrical schematic
and in the silkscreen of the PCB.
Table 3: Evaluation Board Test Point Description
Test
Point # Name Use
TP1 LIN Test point to monitor Inductor operation.
TP2 Shutdown Test point to control the enable input on the RX-232 transceiver chip.
TP4 VPC Single-pin test point. VPC signal directly connected to the 73S1210F and its
decoupling capacitors. Can be used to measure integrity of the power
supply of the DC-DC converters of the 73S1210F.
TP6 VDD
2-pin test point, with one ground and one VDD signal directly connected to
the 73S1210F and its decoupling capacitors. Can be used to measure the
integrity of the digital power supply of the 73S1210F, or to add a decoupling
capacitor.
TP10 Smart Card
Contacts –
Interface #1
Header for measurement of the card signals, close to the card connectors.
Contains the card signals VCC1, RST1, CLK1, C81 and C41. Each contact
has its own ground pin on the header.
TP11 to
TP17 GND Ground test points. Can be used for grounding of lab equipment probes.
TP18 Card Detect –
Interface #1 Card detect signal coming directly from the card connectors.
TP21 USR(7:0) Standard 9/8-bit user I/O port of the 73S1210F.
Some of the user I/Os are shared by the extension 73S80xx
daughter board when using an external smart card interface, and
the LCD interface. Only one should be used at a time.
TP22 USB – N/A USB is not available and TP22 is not populated with the 73S1210F.
TP24 VBUS – N/A USB is not available and TP24 is not populated with the 73S1210F.
TP25 Smart Card
Contacts –
Interface #2
Header for measurement of the card signals, close to the card connectors.
Contains the card signals VCC2, RST2, CLK2, C42 and C82. Each contact
has its own ground pin on the header.
TP27 ROW[0:5] The row pins used for the keypad interface.
TP29 COL[0:4] The column pins used for the keypad interface.
TP30 INT2
INT3 Interrupt input #2 and #3 of the 73S1210F. This header is close to the
breadboard area for easy wiring.
TP31 RX, TX The TX and RX serial UART I/O signals (3.3 V digital logic level).
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UG_1210F_035 73S1210F Evaluation Board User Guide
Rev. 1.2 17
4.3 Schematic
1
2 3
4
5 6
7 8
9
10 11
12
13 14
15 16
17
18 19
20
J12 PROTO TYPE AREA
1
2
3
JP16
1
TP1
Y1
12.000MHz
1
TP4
R8
10
12
S27
SW
VDD
OSC_IN_12OSC_IN_12 OSC_OUT_12OSC_OUT_12
OSC_IN_12
OSC_OUT_12
OSC_IN_32
OSC_OUT_32
1
G5
1
2
3
JP9
GND
COL4
+C28
4.7uF
1
2
3
JP21
COL2
COL3
COL1
COL0
RST_EMUL
C30
0.1uF
1
2
3
JP2
5V
1
2
3
4
5
6
TP27
HEADER 6
R34
1M
+
C29
1uF
4
GND
GND
SIO
8010R INT
RXD
ANALOG IN
1
G6
POWER
IO
RXD 1
2
TP31
TXD
VCC
SCLK
VBAT (4.0 - 6.5VDC)
USR2
USR7
C39
22pF
J3
Banana
L1
10uH
VBAT
EXT
GND
ROW4ROW4
+5VDC
VPC
VP
RESET
8
3
TERIDIAN LOGO
F3
1
2
3
JP15
HEADER 3_0
GND
USR7
C18
1uF
STATUS INDICATOR
VBAT
SELECT
+C27
10uF
SCx_CLK and Vcc tracks
should be routed away
from other Smart card
signalsand should be
surrounded by GND.
USR5
SMARTCARD
SLOT #2
RXD
C14, C15, C16, C18,
C20 and C21 should be
located close to the
Smart Card Connector
INT2
MOUNT HOLES FOR STAND OFFS
2
DNI
1 2
34
TP22
HEADER 2X2
1
2
3
4
5
6
7
8
9
10
J7
TSM_110_01_L_SV
VDD
C37
11
22
33
PJ1
+5VDC
VDD
TXD
INT3
VBAT
VDD 68
RESET
1
SEC
2
ISBR
3
SCL
5
SDA
6
NC/X32OUT
7
NC/X32IN
8
GND
9
X12IN
10
X12OUT
11
COL0
12
COL1
13
COL2
14
ANAIN
15
COL3
16
RXD
17
TXD
18
COL4
19
USR7
20
ROW0
21
ROW1
22
USR6
23
ROW2
24
GND
25
NC/DP
26
NC/DM
27
VDD
28
USR5
29
USR4
30
USR3
31
USR2
32
ROW3
33
USR1
34
USR0 35
ROW4 36
ROW5 37
ERST 38
TCLK 39
VDD 40
TBUS3 41
GND 42
RXTX 43
TBUS2 44
SCLK 45
TBUS1 46
SIO 47
INT3 48
INT2 49
TBUS0 50
TEST 51
OFF_REQ 52
PRES 53
VP 54
CLK 55
GND 56
RST 57
VCC 58
C8/AUX2 59
C4/AUX1 60
I/O 61
VBUS 62
ON_OFF 63
VBAT 64
VPC 65
LIN 66
GND 67
SLUG 69
LED0
4
U6
1217/10
1
2
3
JP11
1
2
3JP13
SDA
SCL
R17 R16 R15
VDD
D8
LED
TBUS[1]
R35
680
VPC
+5VDC
UnReg
GND
USR1
.
CLK
SCx_CLK and Vcc tracks
should be routed away
from other Smart card
signalsand should be
surrounded by GND.
+5V SOURCE
SELECT
1
6
2
7
3
8
4
9
5
P1
DB9_RS232
C43
1000pF
INT2
C33
0.1uF
TBUS[0]
SIO
B
RXTX
ROW5ROW5ROW5ROW5ROW5ROW5
UP
1
2
3
JP1
These test pins should be located between two rows (4
pads each) of SC connector and signal pins locate within
5mm from pads.
CLK track should be routed away from RST and C4.
CLK
F
F2
1
TP2
Y2
32.768kHz
SC8
C35
0.1uF
C32
0.1uF
ISYNC/BRKRQ
5V
C2 should be as
close as possible
to pin 66
+5V
(RED)
C34
0.1uF
ON_OFF
X
CLR
W
INT3
USR0
USR7/SDA
C1
1
C2
2
C3
3
C5
4
C6
5
C7
6
SW1
7
SW2
8
J1
SIM/SAM Connector
LCD
BRIGHTNESS
ADJUST
VDD
VPC (2.7-6.5VDC)
C8
VPC
CARD DET
USR3
USR5
EXTERNAL POWER
SUPPLY
VBUS
GND
OPTIONAL LCD DISPLAY SYSTEM
16 CHARACTER BY 2 LINES
Z
C3, C4 and C5
should be as
close as possible
to VDD pins on U6
30-SWITCH
KEYPAD
C31
0.1uF
5 VDC
UnReg
VCC
ROW1ROW1ROW1ROW1ROW1ROW1
F1
C16
0.47uF
(BLK) USR1
TXD
INT2
1
2
JP3
HEADER 2
VDD
1
G7
VDD
12
3 4
5 6
7 8
910
11 12
TP25
HEADER 2 x 4
+5VDC
UnReg
SCLK
/
DNI
ROW0
1
2
TP6
5V
D- 2
D+ 3
GND 4
VCC 1
GND 5
GND 6
J6
USB_CONN_4
C22
22pF
VDD
C3
0.1uF
ROW5
C4
0.1uF
ROW4
VDD
C5
0.1uF
1
2
JP4
HEADER 2
+C2
10uF
+C7
10uF
C38
22pF
1 2
3 4
56
7 8
910
11 12
TP10
HEADER 2 x 4
C1
1
C2
2
C3
3
C5
4
C6
5
C7
6
SW1
7
SW2
8
J10
SIM/SAM Connector
1
TP18
SEC
1
G8
VO
3VDD
2
DB0
7
NC
15
GND
1
RS
4
R/W*
5
E
6
DB7
14 DB6
13 DB5
12 DB4
11 DB3
10 DB2
9DB1
8
U5
MDL-16265
RXD
TXD
ROW3
ROW2
ROW1
VBUS
ROW0
COL4
COL3
R2 24
VDD
USR7
USR2
USR0
USR1
USR3
1
23
45
67
89
10 11
12 13
14 15
16 17
18 19
20
J11
Emulator IF
USR4
USR6
USR5
COL2
SAD0
1
SAD1
2
SAD2
3
GND
4
N/C
5
VPC
6
N/C
7
AUX2
12
N/C
8
N/C
9
PRES
10
I/O
11
AUX1
13
GND
14 CLK 15
RST 16
VCC 17
VDD_ADJ 18
SCL 19
SDA 20
VDD 21
GND 22
INT 23
AUX2UC 28
AUX1UC 27
XTALOUT 25
XTALIN 24
I/OUC 26
73S8010R
U4
COL1
COL0
INT3
INT2 1
2
TP30
TCLK
1
2
JP14 HEADER 2
1
2
JP10
HEADER 2
1
TP35
1
G9
VDD
ROW2ROW2ROW2ROW2ROW2ROW2
C1+ 28
C1- 25
C2+ 1
C2- 3
T1IN 24
T2IN 23
T3IN 22
T4IN 19
T5IN 17
R1OUTBF 16
R1OUT 21
R2OUT 20
R3OUT 18
GND
2MBAUD
15
SHDNB
14 ENB
13 R3IN
11 R2IN
9R1IN
8
T1OUT
5
T2OUT
6
T3OUT
7
T4OUT
10
T5OUT
12
V-
4
V+
27
VCC 26
U7
MAX3237CAI
R4 100k
R12
3k
R13
3k
SCLSCL
VDD
1
G1
R11 62
Unpopulated
& unlabled
R14 62
R18 62
R19 62
R23 62
R21 62
R20 62
1 3
S2
SW_MOM
R22 62
USR2
USR1
USR4
USR3
USR5
USR0
USR6
VDD
VDD
ROW3ROW3ROW3ROW3ROW3ROW3
C20
27p
VCC
1
RST
2
CLK
3
C4
4
GND
5
VPP
6
I/O
7
C8
8
SW-1
9
SW-2
10
J9
Smart Card Connector
C41
22pF
C21
27p
C15
27p
SDA
SCL
GNDGND
VBATVBATVBAT
C17
0.1uF R5
200k
VDD
OSC_OUT_32OSC_OUT_32OSC_OUT_32OSC_OUT_32
USR6USR6USR6USR6
1
2 3
JP6
(RED)
R25
10k
USR6/SCL
GND
GND USR0
VBUSVBUS
SC4
+3.3V
ROW5
INT3
ANALOG SELECT
GND
USR2
ON_OFF
1
C
D+
SCLSCLSCLSCLSCLSCLSCLSCLSCLSCLSCLSCLSCLSCLSCLSCLSCLSCL
GND
1 3
S3
SW_MOM
1
TP11
EXT
VPC
1 3
S4
SW_MOM
IO
Place R11, R14, R18,
R19, R20, R21, R22
and R23 close to U6
Length and width of USB D+ and D- tracks
should be matched and routed away from
smart card CLK and VCCs
ROW3
13
S5
SW_MOM
1 3
S6
SW_MOM
C40
22pF
USR4
6
PWR_ON
Layout TP10 & TP25 as 8x2 header and TP23 and TP26 as 4x2
header. Populate 2pin header to every other rows such as
pin1-2, pin5-6, pin9-10 and pin13-14 for TP10 and TP25.
ROW1
C4
SERIAL
PORT
+C1
10uF
5
8010 VPC
SELECT
DOWN
13
S33
SW_MOM
GND
1
2 3
JP7
OSC_IN_32OSC_IN_32OSC_IN_32OSC_IN_32
GND
GND
GND
C42
22pF
SDASDASDASDASDASDA
E
OFF_REQ
7
R3 24
ROW2
ENTER
C14
27p
Y
D+
9
VBATVBAT
VBUS_MONVBUS_MONVBUS_MONVBUS_MONVBUS_MONVBUS_MON
1
TP12
USR7
AUX1
AUX2
D4
LED
AUX1
AUX2
LED0
VDD
J2
Banana
R10
10k
1
2
3
JP5
13
S7
SW_MOM
1 2
JP12
HEADER 2
1 3
S12
SW_MOM
1
TP13
5V
1 3
S17
SW_MOM
13
S22
SW_MOM
13
S28
SW_MOM
13
S8
SW_MOM
1 3
S13
SW_MOM
13
S18
SW_MOM
13
S23
SW_MOM
13
S29
SW_MOM
1
TP14
1 3
S9
SW_MOM
13
S14
SW_MOM
13
S19
SW_MOM
R26
10k
1
SY M1
Logo
13
S24
SW_MOM
1 3
S30
SW_MOM
1 3
S10
SW_MOM
1 3
S15
SW_MOM
13
S20
SW_MOM
1
TP15
13
S25
SW_MOM
1 2
JP23
HEADER 2
13
S31
SW_MOM
13
S11
SW_MOM
1 3
S16
SW_MOM
1 3
S21
SW_MOM
13
S26
SW_MOM
1 3
S32
SW_MOM
1
TP16
VPC
USR0
USR1
USR2
1 2
D1
MBR0520L
1
TP17
USR5
USR4
USR3
GND
AUX2
5V
SIO
5V
AUX1
INT2
SCLK 1
2
3
4
5
6
7
8
9
10
J8
TSM_110_01_L_SV
C23
22pF
VCC
1
RST
2
CLK
3
C4
4
GND
5
VPP
6
I/O
7
C8
8
SW-1
9
SW-2
10
J4
Smart Card Connector
C24
22pF
C25
22pF
GND
1
G2
SHUTDOWN
SMARTCARD
SLOT #1
SC I/F EXPANSION
USR1
C4
GND
USR2
INT2
TXD
+5VDC
VBUS
1
2 3
JP20
J5
Banana
USR7
USR6
USR5
TBUS[2]
USR4
TBUS[3]TBUS[3]
USR3
DNI
1
2
3
4
5
6
7
8
TP21
HEADER 8
DNI
R24
10k
1
TP3
0VP
COL0 COL1COL1 COL3
COL2
USR4
D-
ON/CE
D
R6 0
1
TP32
R1 0
1
G3
R7 680
R9 680
RXD
1
TP24
DPLUS
DMINUS
VDD
GND
COL4
VDD
D2
LED
D3
LED
DNI
VBUS_MONVBUS_MONVBUS_MONVBUS_MONVBUS_MONVBUS_MON
VBAT
RST
D-
R27
470
1
2 3
JP8
C28 should
be as close
as possible
to pin 55
GND
RST
VCC tracks should be
wider than 0.5mm.
+5V
DMINUS
DPLUS
USR5
+5V
USR6
GND
C8
A
SEC
USR3
USR0
D5
5.1V
1
G4
+5VDC
1
2
3
4
5
TP29
HEADER 5
ROW3
ROW5
ROW2
ROW0
ROW1
ROW4
C26
0.1uF
5V
8010 VPC
SELECT
1 3
2
CW
RV1
10K
VP
+5V
Figure 7: 73S1210F Evaluation Board Electrical Schematic
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73S1210F Evaluation Board User Guide UG_1210F_035
18 Rev. 1.2
4.4 PCB Layouts
Figure 8: 73S1210F Evaluation Board Top View (Silkscreen)
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UG_1210F_035 73S1210F Evaluation Board User Guide
Rev. 1.2 19
Figure 9: 73S1210F Evaluation Board Bottom View (Silkscreen)
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73S1210F Evaluation Board User Guide UG_1210F_035
20 Rev. 1.2
Figure 10: 73S1210F Evaluation Board Top Signal Layer
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