Teridian 73S1210F User manual

Simplifying System Integration
TM
73S1210F
Multi-SAM Evaluation Board Lite
User Guide
August 20, 2009
Rev. 1.0
UG_1210F_036

73S1210F Multi-SAM Evaluation Board Lite User Guide UG_1210F_036
2 Rev. 1.0
© 2009 Teridian Semiconductor Corporation. All rights reserved.
Teridian Semiconductor Corporation is a registered trademark of Teridian Semiconductor Corporation.
Simplifying System Integration is a trademark of Teridian Semiconductor Corporation.
Microsoft, Windows and Vista are registered trademarks of Microsoft Corporation.
Signum is a trademark of Signum Systems Corporation.
Keil is a trademark of ARM®Ltd.
Linux is a registered trademark of Linus Torvalds.
Slackware is a registered trademark of Patrick Volkerding and Slackware Linux, Inc.
Fedora is a registered trademark of RedHat, Inc.
All other trademarks are the property of their respective owners.
Teridian Semiconductor Corporation makes no warranty for the use of its products, other than expressly
contained in the Company’s warranty detailed in the Teridian Semiconductor Corporation standard Terms
and Conditions. The company assumes no responsibility for any errors which may appear in this
document, reserves the right to change devices or specifications detailed herein at any time without
notice and does not make any commitment to update the information contained herein. Accordingly, the
reader is cautioned to verify that this document is current by comparing it to the latest version on
http://www.teridian.com or by checking with your sales representative.
Teridian Semiconductor Corp., 6440 Oak Canyon, Suite 100, Irvine, CA 92618
TEL [phone], FAX [phone], http://www.teridian.com

73S1210F Multi-SAM Evaluation Board Lite User Guide UG_1210F_036
Rev. 1.0 3
Table of Contents
1Introduction ...................................................................................................................................4
1.1 Evaluation Kit Contents.........................................................................................................5
1.2 Evaluation Board Features....................................................................................................5
1.3 Recommended Equipment and Test Tools............................................................................5
2Evaluation Board Basic Setup......................................................................................................6
2.1 Connecting the Evaluation Board with an Emulation Tool......................................................7
2.2 Loading User Code into the Evaluation Board .......................................................................7
3Using the PCCID Application........................................................................................................9
3.1 Host Demonstration Software Installation..............................................................................9
4Evaluation Board Hardware Description....................................................................................11
4.1 Jumpers, Switches and Modules.........................................................................................11
4.2 Schematic...........................................................................................................................15
4.3 PCB Layouts.......................................................................................................................16
4.4 Bill of Materials ...................................................................................................................22
4.5 Schematic Information ........................................................................................................24
4.5.1 Reset Circuit..............................................................................................................24
4.5.2 Oscillator...................................................................................................................24
4.5.3 Smart Card Interface .................................................................................................24
4.5.4 Multiplexer Configuration...........................................................................................25
4.6 Multi-SAM Limitations.........................................................................................................27
5Ordering Information...................................................................................................................27
6Related Documentation...............................................................................................................27
7Contact Information.....................................................................................................................27
Revision History..................................................................................................................................28
Figures
Figure 1: 73S1210F Multi-SAM Evaluation Board Lite..............................................................................4
Figure 2: 73S1210F Multi-SAM Evaluation Board Lite Basic Connections................................................6
Figure 3: EmulatorWindowShowing RESET and ERASE Buttons...........................................................8
Figure 4: Emulator Window Showing Erased Flash Memory and File Load Menu.....................................8
Figure 5: 73S1210F Multi-SAM Evaluation Board Lite Jumper, Switch and Test Point Locations............14
Figure 6: 73S1210F Multi-SAM Evaluation Board Lite Electrical Schematic............................................15
Figure 7: 73S1210F Multi-SAM Evaluation Board Lite Top View (Silkscreen) .........................................16
Figure 8: 73S1210F Multi-SAM Evaluation Board Lite Bottom View (Silkscreen) ....................................17
Figure 9: 73S1210F Multi-SAM Evaluation Board Lite Top Signal Layer.................................................18
Figure 10: 73S1210F Multi-SAM Evaluation Board Lite Middle Layer 1 – Ground Plane.........................19
Figure 11: 73S1210F Multi-SAM Evaluation Board Lite Middle Layer 2 – Supply Plane..........................20
Figure 12: 73S1210F Multi-SAM Evaluation Board Lite Bottom Signal Layer..........................................21
Figure 13: External Components for RESET..........................................................................................24
Figure 14: Oscillator Circuit....................................................................................................................24
Figure 15: Smart Card Connections.......................................................................................................25
Figure 16: Multiplexer Circuit .................................................................................................................26
Tables
Table 1: Flash Programming Interface Signals.........................................................................................7
Table 2: 73S1210F Multi-SAM Evaluation Board Lite Jumper, Switch and Module Description ...............11
Table 3: 73S1210F Multi-SAM Evaluation Board Lite Bill of Materials.....................................................22

73S1210F Multi-SAM Evaluation Board Lite User Guide UG_1210F_036
4 Rev. 1.0
1 Introduction
The Teridian Semiconductor Corporation (TSC) 73S1210F Multi-SAM Evaluation Board Lite is a platform
that demonstrates the capabilities of the 73S1210F Smart Card Controller device. It has been designed
to operate either as a standalone or as a development platform.
The Multi-SAM (MS) board is a special configuration that uses a single 8010C interface device to support
up to five smart cards; one full size (credit card) and up to four SIM/SAM cards This multi-SIM/SAM
configuration imposes usage limitations which are described in Section 4.6.
The 73S1210F Multi-SAM Evaluation Board Lite can be programmed to run any of the Teridian turnkey
applications or a user-developed custom application. Teridian provides its Pseudo-CCID application
preloaded on the board and an EVM testing application on the CD.
Applications can be downloaded through the In-Circuit Emulator (ICE) or through the TSC Flash
Programmer Model TFP2. As a development tool, the evaluation board has been designed to operate in
conjunction with an ICE to develop and debug 73S1210F based embedded applications.
Figure 1: 73S1210F Multi-SAM Evaluation Board Lite

73S1210F Multi-SAM Evaluation Board Lite User Guide UG_1210F_036
Rev. 1.0 5
1.1 Evaluation Kit Contents
The 73S1210F Multi-SAM Evaluation Board Lite Kit contains the following:
•73S1210F ELMS board containing the 73S1210F with preloaded turnkey program PCCID (4-layer,
rectangular PWB).
•5 VDC/1,000 mA universal wall transformer with 2.5 mm plug ID (CUI Inc. – EPS050100-P6P).
•Serial cable: DB9, male/female, 2 meter length (Digi-Key AE1379-ND).
•CD containing documentation (data sheet, and user guides), software API libraries, evaluation code,
and utilities.
•The 73S1210F Multi-SAM Evaluation Board Lite Quick Start Guide.
1.2 Evaluation Board Features
The 73S1210F Multi-SAM Evaluation Board Lite (see Figure 1) includes the following:
•RS-232 interface
•Single full size and four SIM/SAM smart card interfaces
•ICE/Programmer interface
•Power interface
•ON/OFF switch
•1 LED
1.3 Recommended Equipment and Test Tools
The following equipment and tools (not provided) are recommended for use with the 73S1210F
Multi-SAM Evaluation Board Lite:
•For functional evaluation: PC with Microsoft®Windows®XP or Vista®, or a workstation running Linux®
equipped with a serial RS-232 (COM) port via DB9 connector.
•For software development (MPU code)
Signum™ ICE (In Circuit Emulator): ADM-51. Refer to
http://signum.temp.veriohosting.com/Signum.htm.
Keil™ 8051 C Compiler Kit: CA51. Refer to http://www.keil.com/c51/ca51kit.htm and
http://www.keil.com/product/sales.htm.

73S1210F Multi-SAM Evaluation Board Lite User Guide UG_1210F_036
6 Rev. 1.0
2 Evaluation Board Basic Setup
Figure 2 shows the basic connections of the evaluation board with the external equipment.
The power supply input (VBAT) provides back-up power for those applications capable of using it. When
a power supply is connected to VBAT, the ON/OFF switch, S2, turns the power supply to the 73S1210F
on or off.
•Connect PJ1 on the board to any AC-DC converter block able to generate a DC power supply of 2.7
V to 6.5 V and 400 mA.
The communication to an external host is accommodated via a standard RS-232 serial interface (TX/RX
only)
Figure 2: 73S1210F Multi-SAM Evaluation Board Lite Basic Connections

73S1210F Multi-SAM Evaluation Board Lite User Guide UG_1210F_036
Rev. 1.0 7
2.1 Connecting the Evaluation Board with an Emulation Tool
The 73S1210F Multi-SAM Evaluation Board Lite has been designed to operate with an In-Circuit
Emulator (ICE) from Signum Systems (model ADM-51). The Signum System POD has a ribbon cable
that must be directly attached to connector J2.
Signum Systems offers different POD options depending on user needs. The standard pod allows users to
perform typical emulator functions such as symbolic debugging, in-line breakpoints, memory examination
and/or modification, etc. Other pod options enable code trace capability and/or complex breakpoints at an
additional cost.
When using an ICE, theboard must be externally powered (and turned on via theON/OFF
switch. The power LED D4 will indicate the power status.
2.2 Loading User Code into the Evaluation Board
Hardware Interface for Programming
The signals listed in Table 1are necessary for communication between the TFP2 or ICE and the
73S1210F.
Table 1: Flash Programming Interface Signals
Signal Direction Function
E_TCLK Output from 73S1210F Data clock
E_RXTX Bi-directional Data input/output
E_RST
1
Bi-directional Flash Downloader Reset (active low)
1
The E_RST signal should only be driven by the TFP2 when enabling these
interface signals. The TFP2 must release E_RST at all other times.
These signals, along with 3.3 V and GND are available on the emulator header J2. Production modules
may be equipped with much simpler programming connectors, e.g. a 5x1 header.
Programming of the flash memory requires either the Signum Systems ADM51 in-circuit emulator or the
TSC Flash Programmer Model TFP2 provided by Teridian.
Loading Code with the In-Circuit Emulator
If firmware exists in the 73S1210F flash memory, the memory must be erased before loading a new file
into memory. In order to erase the flash memory, the RESET button in the emulator software must be
clicked followed by the ERASE button (see Figure 3).
Once the flash memory is erased, the new file can be loaded using the Load command in the File menu.
The dialog boxshown in Figure 4makes it possible to select the file to be loaded by clicking the Browse
button. Once the file is selected, pressing the OK button loads the file into the flash memory of the IC.
At this point, the emulator probe (cable) can be removed. Once the 73S1210F device is reset using the
reset button on the evaluation board, the new code starts executing.
Loading Code with the TSC Flash Programmer Model TFP2
Follow the instructions given in the TSC Flash Programmer Model TFP2 User’s Manual.

73S1210F Multi-SAM Evaluation Board Lite User Guide UG_1210F_036
8 Rev. 1.0
Figure 3: Emulator Window Showing RESET and ERASE Buttons
Figure 4: Emulator Window Showing Erased Flash Memory and File Load Menu
RESET
BUTTON
ERASE
BUTTON

73S1210F Multi-SAM Evaluation Board Lite User Guide UG_1210F_036
Rev. 1.0 9
3 Using the PCCID Application
The PCCID firmware is pre-installed on the 73S1210F Multi-SAM Evaluation Board Lite. It requires a PC
with the serial RS-232 port. When powered-up, the board is able to run the PCCID demonstration host
application which allows:
•Smart card activation and deactivation, in ISO or EMV mode.
•Smart card APDU commands to be exchanged with the smart card inserted in the board.
•Starting a test sequence in order to test and evaluate the board performance against an EMV test
environment.
The Multi-SAM configuration requires special firmware to control the selection of the SAM slots. This
firmware controls 73S1210F pins USR4 and USR5 to select theproper input on the 4:1 analog
multiplexer. These builds are described in the firmware documentation as ‘Single 8010’ since a single
8010 controls the four SAM interfaces
3.1 Host Demonstration Software Installation
Installation on Windows XP
Follow these steps to install the software on a PC running Windows XP:
•Extract “PCCID Vz.zz Release.zip” (where z.zz is the latest version of the firmware release).
oCreate an install directory. For example: “C:\TSC\”.
oUnzip “PCCID Vz.zz Release.zip” to the just created folder. All applications and documentation
needed to run the board with a Windows PC will be loaded to this folder.
•Plug the supplied adapter into the 5V DC jack and a wall outlet.
•Connect the serial cable between the host system and the 73S1210F Multi-SAM Evaluation Board
Lite.
•Press the ON/OFF switch to turn the board on.
•Run “TSCP-CCID.exe” (located in the path - x:\yyy\ PCCID Vz.zz Release\Host
Applications\Windows App\App\Bin\Release) on the host system to execute the host demonstration
application (where xrefers to the drive, yyy refers to the directory the installation .zip file was
expanded to and z.zz is the latest version of the firmware release).
At this point the application window should appear. For additional information regarding the use of the
Teridian Host application, refer to the Pseudo-CCID Host GUI Users Guide (UG_12xxF_052).

73S1210F Multi-SAM Evaluation Board Lite User Guide UG_1210F_036
10 Rev. 1.0

73S1210F Multi-SAM Evaluation Board Lite User Guide UG_1210F_036
Rev. 1.0 11
4 Evaluation Board Hardware Description
4.1 Jumpers, Switches and Modules
Table 2 describes the73S1210F Multi-SAM Evaluation Board Lite jumpers, switches and test points. The
Item # in Table 2 references Figure 5.The default setting column refers to setup for running PCCID
application.
Table 2: 73S1210F Multi-SAM Evaluation Board Lite Jumper, Switch and Module Description
Item
#
Schematic
and
Silkscreen
Reference
Default
setting Name Use
1 PJ1 Connect DC Jack Input power jack. Should be configured for VPC.
Power input mustbe between 2.7V and 6.5V and
capable of providing 400 mA.. Requires the use of
the On/Off switch to turn on the 72S1210F.
2 J2 No
Connect In-Circuit Emulator connector This connector must be used when using an external In-Circuit Emulator (SIGNUM 8052 ADM51 ICE).
Refer to the Electrical Schematic for pin assignment.
3 JP7 VDD Serial transceiver
enable jumper Jumper controls RS-232 transceiver shutdown function. There are three possible configurations:
Removed; places RS-232 transceiver chip in
shutdown.
Inserted VDD (pin 2-3); enables RS-232
transceiver
Inserted USR6 (pin 1-2); allows USR6 pin to
control RS-232 transceiver shutdown
4 D5 RXD LED Reflects the activity on the serial RX: Data going
TO the 73S1210F.
5 D6 TXD LED Reflects the activity on the serial TX: Data going
FROM the 73S1210F.
6 P1 Connect DB9 RS232 female
socket This socket allows connection of an RS232 cable
to a computer. Use a crossed wires (RX/TX)
cable. The evaluation board has an on-board
level shifter (U7) to allow direct connection to a
computer.
Connection of a RS232 link is required when using
the pre-downloaded application.
7 JP2 Insert RXD LED jumper Jumper inserted enables RX LED. Jumper
removed disables RX LED.
8 JP3 Insert TXD LED jumper Jumper inserted enables TX LED. Jumper
removed disables TX LED.
9 J7 SIM/SAM Card
connector #4 Allows the Multi-SAM Evaluation Board Lite to
communicate with a smart card using a SIM/SAM
format: This slot is designated as #4 of the
external 8010C multiplexed slots connected via
the 73S1210F external card interface
10 TP9 VDDFLT test point Test point used for monitoring VDDFLT voltage.

73S1210F Multi-SAM Evaluation Board Lite User Guide UG_1210F_036
12 Rev. 1.0
Item
#
Schematic
and
Silkscreen
Reference
Default
setting Name Use
11 J6 SIM/SAM Card
connector #3 Allows the Multi-SAM Evaluation Board Lite to
communicate with a smart card using a SIM/SAM
format: This slot is designated as #3 of the
external 8010C multiplexed slots connected via
the 73S1210F external card interface.
12 J5 SIM/SAM Card
connector #2 Allows the Multi-SAM Evaluation Board Lite to
communicate with a smart card using a SIM/SAM
format: This slot is designated as #2 of the
external 8010C multiplexed slots connected via
the 73S1210F external card interface.
13 - Board Reference and
serial number Should be mentioned in any communication with
TSC Application Engineers when request for
support.
14 J4 SIM/SAM Card
connector #1 Allows the Multi-SAM Evaluation Board Lite to
communicate with a smart card using a SIM/SAM
format: This slot is designated as #1 of the
external 8010C multiplexed slots connected via
the 73S1210F external card interface.
15 TP13 CLK test point 8010C CLK output test point.
16 TP11 I/O test point 8010C I/O output test point.
17 TP12 RST test point 8010C RST output test point.
18 TP10 VCC test point 8010C VCC output test point.
19 TP3 USR test points USR pin test points.
20 D4 Power LED Power LED comes on with VDD. Disabled by
removing JP4.
21 JP4 Insert Power LED disable Inserting jumper enables power LED with VDD.
Removing jumper disabled power LED.
22 TP6 VDD test point VDD test point with ground.
23 D1 LED0 73S1210F LED0 output LED.
24 J1 Smart Card connector Allows the Multi-SAM Evaluation Board Lite to
communicate with a smart card using a standard
(credit card size) format: This slot is connected to
the 73S1210F internal card interface.
25
S1 Reset button Multi-SAM Evaluation Board Lite main reset:
Asserts a hardware reset to the on-board 73S1210
IC.
26 S2 On / Off button When using battery power (o
n PJ1), turnson or off
(toggles) power to the 73S1210F device.
27 TP8 VP test point Test point used for monitoring VP voltage. VP is
5.5V when the 72S1210F is on.
28 TP2 1210 smart card test
points Test points to monitor 73S1210F smart card signals.

73S1210F Multi-SAM Evaluation Board Lite User Guide UG_1210F_036
Rev. 1.0 13
Item
#
Schematic
and
Silkscreen
Reference
Default
setting Name Use
29 TP7 VPC test point Test point to monitor VPC. VPC is the input power
source to the internal voltage converter. See the
73S1210F Data Sheet for further information.
30 JP5 VPC VPC2 Select Jumper for 8010C input power select.
31 JP6 VPC VPC/VBAT Select Jumper to select input power to 1210 between
VPC and VBAT.
32 TP1 Power test point Input power (PJ1) test point.

73S1210F Multi-SAM Evaluation Board Lite User Guide UG_1215F_036
14 Rev. 1.8
Figure 5: 73S1210F Multi-SAM Evaluation Board Lite Jumper, Switch and Test Point Locations

UG_1215F_036 73S1210F Multi-SAM Evaluation Board Lite User Guide
Rev. 1.8 15
4.2 Schematic
P1
DB9_RS232
1
6
2
7
3
8
4
9
5
INT3
C22
0.1uF
CLK
Y1
32.768kHz
C23
0.1uF
C20
0.1uF
C33 should be as
close as possible
to pin 65
C21
0.1uF
VDD
ON_OFF
C8
USR5
USR3
C30, C31 and C32
should be as
close as possible
to VDD pins on U4
C19
0.1uF
VCC
C7
0.47uF
USR1
TXD
+5 VDC
UnReg
VPC
TP6
1
2
J3
USB_CONN_4
D- 2
D+ 3
GND 4
VCC 1
GND 5
GND 6
C12
27pF
C30
0.1uF
C31
0.1uF
VDD
C32
0.1uF
TP2
HEADER 2 x 6
12
34
5 6
78
910
11 12
RXD
VDD
R20 24
USR7
USR0
USR2
USR3
USR1
USR6
USR4
USR5
USR1
USR2
USR0
USR3
Do not install R6, R8, R11 and R12
VDD
R11 0
R6 0
R8 0
R12 0
C14
.1uF
U3
MAX3237CAI
C1+ 28
C1- 25
C2+ 1
C2- 3
T1IN 24
T2IN 23
T3IN 22
T4IN 19
T5IN 17
R1OUTBF 16
R1OUT 21
R2OUT 20
R3OUT 18
GND
2MBAUD
15
SHDNB
14 ENB
13 R3IN
11 R2IN
9R1IN
8
T1OU T
5
T2OU T
6
T3OU T
7
T4OU T
10
T5OU T
12
V-
4
V+
27
VCC 26
R22 100k
VDD
DPLUSDPLUSDPLUSDPLUSDPLUSDPLUSDPLUSDPLUSDPLUSDPLUSDPLUSDPLUSDPLUSDPLUSDPLUSDPLUSDPLUSDPLUSDPLUSDPLUSDPLUSDPLUSDPLUSDPLUSDPLUSDPLUSDPLUSDPLUSDPLUSDPLUSDPLUSDPLUSDPLUSDPLUSDPLUSDPLUS
C42
1uF
VBUSVBUSVBUSVBUSVBUSVBUSVBUSVBUSVBUSVBUSVBUSVBUS
C33
10uF
JP8
1
2
C6
27p
Power Notes:
1. For bus power configuration, set JP5 to VBUS
2. For self power, set JP5 to VPC
C43
1uF
JP5
1
2 3
VPC
VBUS
VPC2 SOURCE
SELECT
VPC2
C44
1uF
Power Notes (USB applicatons only):
1. For bus power configuration, install JP
2. For self power do not install JP
C47
NC
C35
1uF
+
C34
2.2uF
C36
0.033uF
C34 and C35 to be
placed within 1cm
of U5
VBUS
R33
100k
R31
3k
R30
3k
C48
27pF
TP9
1
2
C45
27pF
VBUS ENABLE
R26
R28
VDD
VCC
VDD
TP3 to TP8 to be placed
very close to the pads
of J5
C40
NC
INTB
J1 and J3 are placed on the bottom.
J2 and J4 are placed on the top side.
J7 SIM/SAM Connec tor #4
C1 1
C2 2
C3 3 C5 4
C6 5
C7 6
SW1 7
SW2 8
CLK
J1 and J3 must be aligned with J8 and
J9 on the 12xx evaluation board
respectivly in order for this board
to be stacked on it.
VCC
VDDF_ADJ
J1 must be aligned with J2 and
J3 must be aligned with J4 in
order for this daughter board to
be stacked on another.
CLK
RST
I/O
VDD
SDASDA
SCL
TP10
1
2
R32 0TP12
1
2
TP11
1
2TP13
1
2
DNI
DNI
C39
0.1uF
C37 0.1uF
R34
100k R35
100k
EN9
0 1M_
1 4
> > > > > > > > 1
2 3 4
< < < < < < < <MUX/ DX
9 >
<>
<
VDD
GND
VEE
U7
4052
6
10
9
12 14
15
11
1 5
2 43
13
8
16 7
+
C38 10uF
VPC2
U6
73S8010C
GND
1
LIN
2
VPC
3
NC
4
PWRDN
5
NC
6
PRES
7
NC
8
I/O
9
AUX2
10
AUX1
11
GND
12
CLK
13
RST
14
VCC
15
NC
16
VDDF_ADJ 17
SCL 18
SDA 19
VDD 20
GND 21
INT 22
XTALI N 23
XTALOUT 24
NC 25
I/OUC 26
AUX1UC 27
AUX2UC 28
SAD0 29
SAD1 30 SAD2 31
NC 32
SLUG 33
J6 SIM/SAM Connec tor #3
C1 1
C2 2 C3 3
C5 4
C6 5 C7 6
SW1 7
SW2 8
J5 SIM/SAM Connec tor #2
C1 1
C2 2
C3 3 C5 4
C6 5
C7 6
SW1 7
SW2 8
C50
27pF
U5
LP3982
OUT
1
IN
2
GND
3
OUT
4N/C 5
CC 6
SHDN 7
FAULT 8
J4 SIM/SAM Connec tor #1
C1 1
C2 2
C3 3 C5 4
C6 5
C7 6
SW1 7
SW2 8
R37
100k R38
100k R39
100k
R40
100k
Apply 3.3V to pin 10 voltage to J3 or J4
R29 47K
VBAT
R36
100k
C41
1uF
VDD
RST
C49
27pF
L2 10uH
C1, C2, C8, C9 and L1
must be placed within
5mm of the U1 pins and
connected by thick
track (wider than
0.5mm)
C46
27pF
VDD
C29
0.1uF R23
200k
OSC_OUT_32OSC_OUT_32OSC_OUT_32OSC_OUT_32
USR0
USR2
Length and width of USB D+ and D- tracks
should be matched and routed away from
smart card CLK and VCCs
Place R'S close to U4
C4
USR4
SERIAL
PORT
OSC_IN_32OSC_IN_32OSC_IN_32OSC_IN_32
GND
R21 24
C5
27p
D+
TBUS[3]TBUS[3]
ISYNC/BRKRQ
JP4
1 2
D1
LED
C25
22pF
VDD
LED0
VDD
C24
22pF
TBUS[0]
R5
10k
VDD
USR6
232 SHDN
SEL
J2
Emulator IF
1
23
45
67
89
10 11
12 13
14 15
16 17
18 19
20
JP7
HEADER 3_0
1 2
3
VDD
R7 62
R9 62
R10 62
R13 62
R17 62
R15 62
R14 62
R16 62
C27
22pF
C26
22pF
TBUS[1]
C28
22pF
TBUS[2]
RXTX
TCLK
RST_EMUL
SY M1
Logo
1
VBUS_MON
Enable
VPC
J1
Smart Card Connector
VCC
1
RST
2
CLK
3
C4
4
GND
5
VPP
6
I/O
7
C8
8
SW-1
9
SW-2
10
C16
27pF
C11
22pF
C10
22pF
SMARTCARD
SLOT #1
USR7
USR2
USR1
USR5USR5USR5USR5
USR6
R3
100K
USR3USR3USR3USR3
USR4USR4USR4USR4
TP3
HEADER 8
1
2
3
4
5
6
7
8
VPC/VBAT
SELECT
JP6
1
2 3
TP8
1
VP
R25
200k
R1 0
R18 680
R19 680
DPLUS
VDD
DMINUS
D5
LED
D6
LED
POWER LED
Disable
RST
GND
C9 should
be as close
as possible
to pin 54
D-
VCC tracks should be
wider than 0.5mm.
DMINUS
R27 47K
USR6
USR0
+5VDC
MOUNT HOLES FOR STAND OFFS
G1
1
G2
1
G4
1
G3
1
C9
4.7uF
TP7
1
JP2
1 2
RXD LED
Disable
S2
SW
12
VPC
VBAT
TXDTXDTXDTXDTXDTXDTXDTXD
VBUS
Y2
12.000MHz
R4
10
TXD LED
Disable
S1
SW
12
VDD
OSC_IN_12OSC_IN_12
JP3
1 2
OSC_IN_12
OSC_OUT_12OSC_OUT_12
OSC_IN_32
OSC_OUT_12
OSC_OUT_32
R2
1M
IO
POWER
USR7
L1
10uH
JP1
1 2
RESET
STATUS INDICATOR
+C13
10uF
C5 C6 and C7 should be
located close to the
Smart Card Connector
RXD
PJ1
DC IN
11
22
33
TP1
1
U4
73S1210F
VDD 68
RESET
1
SEC
2
ISBR
3
SCL
5
SDA
6
NC/X32OUT
7
NC/X32IN
8
GND
9
X12IN
10
X12OUT
11
COL0
12
COL1
13
COL2
14
ANAIN
15
COL3
16
RXD
17
TXD
18
COL4
19
USR7
20
ROW0
21
ROW1
22
USR6
23
ROW2
24
GND
25
DP
26
DM
27
VDD
28
USR5
29
USR4
30
USR3
31
USR2
32
ROW3
33
USR1
34
USR0 35
ROW4 36
ROW5 37
ERST 38
TCLK 39
VDD 40
TBUS3 41
GND 42
RXTX 43
TBUS2 44
SCLK 45
TBUS1 46
SIO 47
INT3 48
INT2 49
TBUS0 50
TEST 51
OFF_REQ 52
PRES 53
VP 54
CLK 55
GND 56
RST 57
VCC 58
AUX2 59
AUX1 60
I/O 61
VBUS 62
ON_OFF 63
VBAT 64
VPC 65
LIN 66
GND 67
SLUG 69
LED0
4
VDD
D4
LED
R24
680
CLK and Vcc tracks should be
routed away from other Smart
card signals and should be
surrounded by GND.
C17
1000pF
Figure 6: 73S1210F Multi-SAM Evaluation Board Lite Electrical Schematic

73S1210F Multi-SAM Evaluation Board Lite User Guide UG_1215F_036
16 Rev. 1.8
4.3 PCB Layouts
Figure 7: 73S1210F Multi-SAM Evaluation Board Lite Top View (Silkscreen)

UG_1215F_036 73S1210F Multi-SAM Evaluation Board Lite User Guide
Rev. 1.8 17
Figure 8: 73S1210F Multi-SAM Evaluation Board Lite Bottom View (Silkscreen)

73S1210F Multi-SAM Evaluation Board Lite User Guide UG_1215F_036
18 Rev. 1.8
Figure 9: 73S1210F Multi-SAM Evaluation Board Lite Top Signal Layer

UG_1215F_036 73S1210F Multi-SAM Evaluation Board Lite User Guide
Rev. 1.8 19
Figure 10: 73S1210FMulti-SAM Evaluation Board Lite Middle Layer 1 – Ground Plane

73S1210F Multi-SAM Evaluation Board Lite User Guide UG_1215F_036
20 Rev. 1.8
Figure 11: 73S1210FMulti-SAM Evaluation Board Lite Middle Layer 2 – Supply Plane