Texas Instruments Sitara AM1335 Series User manual

Sitara™ AM335x ARM®Cortex™-A8
Microprocessors (MPUs)
Silicon Revisions 2.1, 2.0, 1.0
Silicon Errata
Literature Number: SPRZ360F
October 2011–Revised November 2013

Contents
1 Introduction ........................................................................................................................ 3
1.1 AM335x Device and Development Support Tool Nomenclature .................................................. 3
1.2 Revision Identification ................................................................................................... 4
2 All Errata Listed With Silicon Revision Number ...................................................................... 6
3 Usage Notes and Known Design Exceptions to Functional Specifications ................................. 8
3.1 Usage Notes ............................................................................................................. 8
3.1.1 LCD: Color Assignments of LCD_DATA Terminals ..................................................... 8
3.1.2 DDR3: JEDEC Compliance for Maximum Self-Refresh Command Limit ............................ 8
3.1.3 Boot: USB Boot ROM Code Uses Default DATAPOLARITY .......................................... 9
3.1.4 Boot: Multiplexed Signals GPMC_WAIT0, GMII2_CRS, and RMII2_CRS_DV Cause NAND Boot
Issue ........................................................................................................... 9
3.1.5 Pin Multiplexing: Valid IO Sets and Restrictions ....................................................... 10
3.1.6 Boot: Multiplexed Signals GPMC_WAIT0 and GMII2_CRS Cause NAND Boot Issue ........... 10
3.1.7 OSC1: RTC_XTALIN Terminal Has an Internal Pull-up Resistor When OSC1 is Disabled ...... 11
3.2 Known Design Exceptions to Functional Specifications .......................................................... 12
Revision History ......................................................................................................................... 38
2Table of Contents SPRZ360F–October 2011–Revised November 2013
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Silicon Errata
SPRZ360F–October 2011–Revised November 2013
Sitara™ AM335x ARM®Cortex™-A8
Microprocessors (MPUs)
(Silicon Revision 2.1, 2.0, 1.0)
1 Introduction
This document describes the known exceptions to the functional specifications for the Sitara™ AM335x
ARM®Cortex™-A8 Microprocessors (MPUs). [See the Sitara AM335x ARM Cortex-A8 Microprocessors
(MPUs) data manual (literature number SPRS717).]
For additional information, see the latest version of the Sitara AM335x ARM Cortex-A8 Microprocessors
(MPUs) Technical Reference Manual (literature number SPRUH73).
1.1 AM335x Device and Development Support Tool Nomenclature
To designate the stages in the product development cycle, TI assigns prefixes to the part numbers of all
microprocessors (MPUs) and support tools. Each device has one of three prefixes: X, P, or null (no prefix)
(for example, XAM3358ZCE). Texas Instruments recommends two of three possible prefix designators for
its support tools: TMDX and TMDS. These prefixes represent evolutionary stages of product development
from engineering prototypes (TMDX) through fully qualified production devices and tools (TMDS).
Device development evolutionary flow:
X — Experimental device that is not necessarily representative of the final device's electrical
specifications and may not use production assembly flow.
P — Prototype device that is not necessarily the final silicon die and may not necessarily meet final
electrical specifications.
null — Production version of the silicon die that is fully qualified.
Support tool development evolutionary flow:
TMDX — Development-support product that has not yet completed Texas Instruments internal
qualification testing.
TMDS — Fully-qualified development-support product.
X and P devices and TMDX development-support tools are shipped against the following disclaimer:
"Developmental product is intended for internal evaluation purposes."
Production devices and TMDS development-support tools have been characterized fully, and the quality
and reliability of the device have been demonstrated fully. TI's standard warranty applies.
Predictions show that prototype devices (X or P) have a greater failure rate than the standard production
devices. Texas Instruments recommends that these devices not be used in any production system
because their expected end-use failure rate still is undefined. Only qualified production devices are to be
used.
Sitara is a trademark of Texas Instruments.
Cortex is a trademark of ARM Ltd or its subsidiaries.
ARM is a registered trademark of ARM Ltd or its subsidiaries.
All other trademarks are the property of their respective owners.
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Lot Trace Code
XAM3352AZCE
YMLLLLS
962 ZCE
G1
Device Revision Lot Trace Code
XAM3359AZCZ
YMLLLLS
962 ZCZ
G1
Device Revision
Introduction www.ti.com
1.2 Revision Identification
The device revision can be determined by the symbols marked on the top of the package. Figure 1
provides an example of the AM335x device markings.
Figure 1. Example of Device Revision Codes for the AM335x Microprocessor
NOTES:
(A) Non-qualified devices are marked with the letters "X" or "P" at the beginning of the device name, while
qualified devices have a "blank" at the beginning of the device name.
(B) The AM3352 and AM3359 devices shown in this device marking example are two of several valid part
numbers for the AM335x family of devices.
(C) The device revision code is the device revision (A, B, and so on).
(D) YM denotes year and month.
(E) LLLL denotes Lot Trace Code.
(F) 962 is a generic family marking ID.
(G) G1 denotes green, lead-free.
(H) ZCE or ZCZ is the package designator.
(I) S denotes Assembly Site Code.
(J) On some "X" devices, the device speed may not be shown.
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www.ti.com Introduction
Silicon revision is identified by a code marked on the package. The code is of the format AM3352x or
AM3358x, where "x" denotes the silicon revision. Table 1 lists the information associated with each silicon
revision for each device type. For more details on device nomenclature, see the device-specific data
manual.
Table 1. Production Device Revision Codes
DEVICE REVISION CODE SILICON REVISION COMMENTS
(blank) 1.0 Silicon revision is new
A 2.0 Silicon revision 2.0
B 2.1 Silicon revision 2.1
Each silicon revision uses a specific revision of TI's ARM®Cortex™-A8 processor. The ARM Cortex-A8
processor variant and revision can be read from the Main ID Register. The DEVREV field (bits 31-28) of
the Device_ID register located at address 0x44E10600 provides a 4-bit binary value that represents the
device revision. The ROM code revision can be read from address 2BFFCh. The ROM code version
consists of two decimal numbers: major and minor. The major number is always 22, minor number counts
ROM code version. The ROM code version is coded as hexadecimal readable values; for example, ROM
version 22.02 is coded as 0000 2202h. Table 2 shows the ARM Cortex-A8 Variant and Revision, Device
Revision, and ROM Code Revision values for each silicon revision of the device.
Table 2. Silicon Revision Variables
SILICON ARM CORTEX-A8 DEVICE ROM
REVISION VARIANT AND REVISION REVISION REVISION
1.0 r3p2 0000 22.02
2.0 r3p2 0001 22.03
2.1 r3p2 0010 22.03
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All Errata Listed With Silicon Revision Number www.ti.com
2 All Errata Listed With Silicon Revision Number
Advisories are numbered in the order in which they were added to this document. Some advisory numbers
may be moved to the next revision and others may have been removed because the design exception
was fixed or documented in the device-specific data manual or peripheral user's guide. When items are
moved or deleted, the remaining numbers remain the same and are not re-sequenced.
Table 3. All Usage Notes
SILICON REVISION AFFECTED
NUMBER TITLE 1.0 2.0 2.1
Section 3.1.1 LCD: Color Assignments of LCD_DATA Terminals X X X
DDR3: JEDEC Compliance for Maximum Self-Refresh
Section 3.1.2 XXX
Command Limit
Section 3.1.3 Boot: USB Boot ROM Code Uses Default DATAPOLARITY X X X
Boot: Multiplexed Signals GPMC_WAIT0, GMII2_CRS, and
Section 3.1.4 X
RMII2_CRS_DV Cause NAND Boot Issue
Section 3.1.5 Pin Multiplexing: Valid IO Sets and Restrictions X X X
Boot: Multiplexed Signals GPMC_WAIT0 and GMII2_CRS
Section 3.1.6 X X
Cause NAND Boot Issue
OSC1: RTC_XTALIN Terminal Has an Internal Pull-up
Section 3.1.7 XXX
Resistor When OSC1 is Disabled
Table 4. All Design Exceptions to Functional Specifications
SILICON REVISION AFFECTED
NUMBER TITLE 1.0 2.0 2.1
DDR2, DDR3, mDDR PHY: Control and Status Registers
Advisory 1.0.1 XXX
Configured for Write Only
Debug Subsystem: EMU[4:2] Signals Are Not Available by
Advisory 1.0.2 XXX
Default After Reset
Debug Subsystem: Internal Inputs Tied-off to the Wrong
Advisory 1.0.3 XXX
Value
Advisory 1.0.4 PRU-ICSS: Clock Domain Crossing (CDC) Issue X
Advisory 1.0.5 RTC: 32.768-kHZ Clock is Gating Off X
EXTINTn: Input Function of the EXTINTn Terminal is
Advisory 1.0.6 X
Inverted
Advisory 1.0.7 Boot: Ethernet Boot ROM Code PHY Link Speed Detection X
Boot: Ethernet Boot ROM Code Sends an Incorrect Vendor
Advisory 1.0.8 X
Class Identifier in BOOTP Packet
Ethernet Media Access Controller and Switch Subsystem:
Advisory 1.0.9 C0_TX_PEND and C0_RX_PEND Interrupts Not Connected X
to ARM Cortex-A8
GMII_SEL Register: RGMII1_IDMODE and
Advisory 1.0.10 RGMII2_IDMODE Bits Reset to Non-supported Mode of X
Operation
USB: Attached Non-compliant USB Device that Responds
Advisory 1.0.11 X
to Spurious Invalid Short Packet May Lock Up Bus
UART: Extra Assertion of FIFO Transmit DMA Request,
Advisory 1.0.12 XXX
UARTi_DMA_TX
USB: Data May be Lost When USB Subsystem is Operating
Advisory 1.0.13 in DMA Mode and More Than One Endpoint is Transferring X
Data
GMII_SEL and CPSW Related Pad Control Registers:
Advisory 1.0.14 Context of These Registers is Lost During Transitions of X
PD_PER
ARM Cortex-A8: OPP50 Operation on MPU Domain Not
Advisory 1.0.15 X
Supported
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www.ti.com All Errata Listed With Silicon Revision Number
Table 4. All Design Exceptions to Functional Specifications (continued)
SILICON REVISION AFFECTED
NUMBER TITLE 1.0 2.0 2.1
RMII: 50-MHz RMII Reference Clock Output Does Not
Advisory 1.0.16 XXX
Satisfy Clock Input Requirements of RMII Ethernet PHYs
Advisory 1.0.17 VDDS_DDR: High-Power Consumption During DeepSleep0 X
ROM: Ethernet Boot Code Does Not Change Default
Advisory 1.0.18 Direction of RMII1 Reference Clock When Booting from X
Ethernet Using RMII
DDR3: Fully-Automated Hardware READ and WRITE
Advisory 1.0.19 XXX
Leveling Not Supported
Boot: USB Boot ROM Code Overlapping Data in TXFIFO
Advisory 1.0.20 X
and RXFIFO
SmartReflex: Limited Support Due to Issue Described in
Advisory 1.0.21 X
Advisory 1.0.15
EMIF: Dynamic Voltage Frequency Scaling (DVFS) is Not
Advisory 1.0.22 XXX
Supported
Ethernet Media Access Controller and Switch Subsystem:
Advisory 1.0.23 XXX
Reset Isolation Feature is Not Supported
Boot: System Boot is Not Reliable if Reset is Asserted
Advisory 1.0.24 XXX
While Operating in OPP50
Boot: System Boot Temporarily Stalls if an Attempt to Boot
Advisory 1.0.25 XXX
from Ethernet is Not Successful
Advisory 1.0.26 I2C: SDA and SCL Open-Drain Output Buffer Issue X X
Advisory 1.0.27 LCDC: LIDD DMA Mode Issue X X X
LCDC: Raster Mode, Hardware Auto Underflow Restart
Advisory 1.0.28 XXX
Does Not Work
Latch-up Performance: Latch-up Performance Limits for
Advisory 1.0.29 X X
Silicon Revsions 1.0 and 2.0
OSC0 and OSC1: Noise Immunity Improved When Crystal
Advisory 1.0.30 XXX
Circuit is Connected Directly to PCB Digital Ground
Advisory 1.0.31 TSC_ADC: False Pen-up Interrupts X X X
TSC_ADC: Terminals May be Temporarily Connected
Advisory 1.0.32 Together Through Internal Paths During Power-up X X X
Sequence
USB Host: USB Low-Speed Receive-to-Transmit Inter-
Advisory 1.0.33 XXX
Packet Delay
USB2PHY: Register Accesses After a USB Subsystem Soft
Advisory 1.0.34 XXX
Reset May Lock Up the Entire System
UART: Transactions to MDR1 Register May Cause
Advisory 1.0.35 XXX
Undesired Effect on UART Operation
EMU0 and EMU1: Terminals Must Be Pulled High Before
Advisory 1.0.36 XXX
ICEPick Samples
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23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 76543210
PIXEL_n
000 0 0000R[7:3] G[7:2] B[7:3]
16-bit panel
24-bit panel
23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 76543210
PIXEL_n
B[0] G[0] R[0] B[1] G[1] R[1] B[2] R[2] B[7:3] G[7:2] R[7:3]
16-bit panel
24-bit panel
Usage Notes and Known Design Exceptions to Functional Specifications www.ti.com
3 Usage Notes and Known Design Exceptions to Functional Specifications
3.1 Usage Notes
This document contains Usage Notes. Usage Notes highlight and describe particular situations where the
device's behavior may not match presumed or documented behavior. This may include behaviors that
affect device performance or functional correctness. These notes may be incorporated into future
documentation updates for the device (such as the device-specific data manual), and the behaviors they
describe may or may not be altered in future device revisions.
3.1.1 LCD: Color Assignments of LCD_DATA Terminals
The blue and red color assignments to the LCD data pins are reversed when operating in RGB888
(24bpp) mode compared to RGB565 (16bpp) mode. In order to correctly display RGB888 data from the
SGX, or any source formatted as RGB in memory, it is necessary to connect the LCD panel as shown in
Figure 2. Using the LCD Controller with this connection scheme limits the use of RGB565 mode. Any data
generated for the RGB565 mode requires the red and blue color data values be swapped in order to
display the correct color.
Figure 2. RGB888 Mode LCD Controller Output Pin Mapping (LCD_DATA[23:0])
When operating the LCD Controller in RGB565 mode the LCD panel should be connected as shown in
Figure 3. Using the LCD Controller with this connection scheme limits the use of RGB888 mode. Any data
generated for the RGB888 mode requires the red and blue color data values be swapped in order to
display the correct color.
Figure 3. RGB565 Mode LCD Controller Output Pin Mapping (LCD_DATA[23:0])
3.1.2 DDR3: JEDEC Compliance for Maximum Self-Refresh Command Limit
When using DDR3 EMIF Self-Refresh, it is possible to violate the maximum refresh command requirement
specified in the JEDEC standard DDR3 SDRAM Specification (JESD79-3E, July 2010). This requirement
states that the DDR3 EMIF controller should issue no more than 16 refresh commands within any 15.6-μs
interval.
To avoid this requirement violation, when using the DDR3 EMIF and Self-Refresh (setting LP_MODE =
0x2 field in the PMCR), the SR_TIM value in the PMCR must to be programmed to a value greater than or
equal to 0x9.
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3.1.3 Boot: USB Boot ROM Code Uses Default DATAPOLARITY
The AM335x USB PHYs supports a DATAPOLARITY feature that allows the data plus (DP) and data
minus (DM) data signals to be swapped. This feature was added to simplify PCB layout.
In some cases, the DP and DM data signals may need to cross over each other to connect to the
respective USB connector pins. Crossing these signals on the PCB may cause signal integrity issues if not
implemented properly since they must be routed as high-speed differential transmission lines. The
DATAPOLARITY feature in the USB PHYs can be used resolve this issue.
The DATAPOLARITY feature is controlled by DATAPOLARITY_INV (bit 23) of the respective USB_CTRL
register.
The USB boot ROM code uses the default value for DATAPOLARITY_INV when booting from USB.
Therefore, the PCB must be designed to use the default DATAPOLARITY if the system must support USB
boot.
3.1.4 Boot: Multiplexed Signals GPMC_WAIT0, GMII2_CRS, and RMII2_CRS_DV Cause NAND Boot
Issue
The AM335x device multiplexes the GPMC_WAIT0, GMII2_CRS, and RMII2_CRS_DV signals on the
same terminal. This causes a problem when the system must support NAND boot while an MII or RMII
Ethernet PHY is connected to port 2 of the Ethernet media access controller and switch (CPSW). The
GPMC_WAIT0 signal is required for NAND boot. The GMII2_CRS or RMII2_CRS_DV signal is required by
the respective MII or RMII Ethernet PHY and the only pin multiplexing option for these signals is
GPMC_WAIT0.
In this case, there are two sources that need to be connected to the GPMC_WAIT0 terminal. The NAND
READY or BUSY output must source the GPMC_WAIT0 terminal during NAND boot and the MII CRS or
RMII CRS_DV output must source the GPMC_WAIT0 terminal when the application software is using port
2 of the CPSW. Therefore, a GPIO-controlled external 2-to-1 multiplexer must be implemented in the
system to select between the two sources. The GPIO selected to control the 2-to-1 multiplexer needs to
have an internal or external resistor that selects the NAND READY or BUSY output as soon as power is
applied and remains in that state until the application software initializes the CPSW.
The TI TS5A3157 SPDT analog switch is an example device that can be used as a 2-to-1 multiplexer.
This device inserts minimum propagation delay to the signal path since it is an analog switch. The
propagation delay inserted by the 2-to-1 multiplexer must be analyzed to confirm it does not cause timing
violations for the respective interface.
The NAND, Ethernet PHY, AM335x VDDSHV1, AM335x VDDSHV3 (when using the ZCZ package), and
2-to-1 multiplexer IO power supply domains may need to operate at the same voltage since they share
common signals.
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3.1.5 Pin Multiplexing: Valid IO Sets and Restrictions
The AM335x device contains many peripheral interfaces. In order to reduce package size and lower
overall system cost while maintaining maximum functionality, many of the AM335x terminals can multiplex
up to eight signal functions. Although there are many combinations of pin multiplexing that are possible,
only a certain number of sets, called IO Sets, are valid due to timing limitations. These valid IO Sets were
carefully chosen to provide many possible application scenarios for the user.
Texas Instruments has developed a Windows®-based application called Pin Mux Utility that helps a
system designer select the appropriate pin-multiplexing configuration for their AM335x-based product
design. The Pin Mux Utility provides a way to select valid IO Sets of specific peripheral interfaces to
ensure the pin multiplexing configuration selected for a design only uses valid IO Sets supported by the
AM335x device.
A few IO Sets have additional restrictions not defined in the Pin Mux Utility. These additional restrictions
are described below:
• MMC0, MMC1, MMC2 Interfaces
– Only Standard (STD) and High Speed (HS) modes are supported. SDR12, SDR25, SDR50 modes
as defined in SD3.0 specification are not supported.
• GEMAC_CPSW Interface
– Operation of GEMAC_CPSW is not supported for OPP50.
3.1.6 Boot: Multiplexed Signals GPMC_WAIT0 and GMII2_CRS Cause NAND Boot Issue
The AM335x device multiplexes the GPMC_WAIT0 and GMII2_CRS signals on the same terminal. This
causes a problem when the system must support NAND boot while an MII Ethernet PHY is connected to
port 2 of the Ethernet media access controller and switch (CPSW). The GPMC_WAIT0 signal is required
for NAND boot. The GMII2_CRS signal is required by the MII Ethernet PHY and the only pin multiplexing
option for these signals is GPMC_WAIT0.
In this case, there are two sources that need to be connected to the GPMC_WAIT0 terminal. The NAND
READY or BUSY output must source the GPMC_WAIT0 terminal during NAND boot and the MII CRS
output must source the GPMC_WAIT0 terminal when the application software is using port 2 of the
CPSW. Therefore, a GPIO-controlled external 2-to-1 multiplexer must be implemented in the system to
select between the two sources. The GPIO selected to control the 2-to-1 multiplexer needs to have an
internal or external resistor that selects the NAND READY or BUSY output as soon as power is applied
and remains in that state until the application software initializes the CPSW.
The TI TS5A3157 SPDT analog switch is an example device that can be used as a 2-to-1 multiplexer.
This device inserts minimum propagation delay to the signal path since it is an analog switch. The
propagation delay inserted by the 2-to-1 multiplexer must be analyzed to confirm it does not cause timing
violations for the respective interface.
The NAND, Ethernet PHY, AM335x VDDSHV1, AM335x VDDSHV3 (when using the ZCZ package), and
2-to-1 multiplexer IO power supply domains may need to operate at the same voltage since they share
common signals.
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www.ti.com Usage Notes and Known Design Exceptions to Functional Specifications
3.1.7 OSC1: RTC_XTALIN Terminal Has an Internal Pull-up Resistor When OSC1 is Disabled
The RTC_XTALIN terminal has an internal pull-up resistor that is turned on when OSC1 is disabled. OSC1
is disabled by default after power is applied.
This internal pull-up resistor was not properly documented in data sheet revisions D and earlier. These
early data sheet revisions recommended an external pull-down resistor to be connected to the
RTC_XTALIN terminal if OSC1 was not used. The recommendation should have been to leave this
terminal open-circuit when not using OSC1.
Connecting an external pull-down to the RTC_XTALIN terminal may cause unexpected leakage current.
The current recommendation is to remove any external pull-down resistor from the RTC_XTALIN terminal
and leave this terminal open-circuit when not using OSC1.
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3.2 Known Design Exceptions to Functional Specifications
The following advisories are known design exceptions to functional specifications. Advisories are
numbered in the order in which they were added to this document. Some advisory numbers may be
moved to the next revision and others may have been removed because the design exception was fixed
or documented in the device-specific data manual or peripheral user's guide. When items are moved or
deleted, the remaining numbers remain the same and are not re-sequenced.
Advisory 1.0.1 DDR2, DDR3, mDDR PHY: Control and Status Registers Configured for Write Only
Revisions Affected 2.1, 2.0, 1.0
Details The DDR2, DDR3, mDDR PHY control and status registers mapped in address range
0x44e12000-0x44E123FF are configured for write-only operations, so the contents of
these register cannot be read.
These registers must be configured by performing write-only operations.
Workarounds There is no workaround for this issue.
Advisory 1.0.2 Debug Subsystem: EMU[4:2] Signals Are Not Available by Default After Reset
Revisions Affected 2.1, 2.0, 1.0
Details All Debug subsystem components should remain unchanged when warm reset is
asserted. For example, warm reset should not affect export of debug trace messages on
the EMU[4:0] signals.
The AM335x EMU[4:2] signals can not be used to export trace messages from the
Debug subsystem since AM335x does support warm reset and the EMU[4:2] signals are
not assigned to pins after reset is asserted.
Workarounds Do not assert warm reset while performing trace functions.
Advisory 1.0.3 Debug Subsystem: Internal Inputs Tied-off to the Wrong Value
Revisions Affected 2.1, 2.0, 1.0
Details Internal inputs dbg_dpio_attr_dp_app_owner[4:0] and dbg_dpio_attr_dp_debug_only[4:0]
to the Debug subsystem are used to report which EMU[4:0] signals can currently be
used to export trace messages. These inputs were tied-off to the wrong value. The tie-off
values used always indicates EMU[4:2] signals are not available and EMU[1:0] signals
are available to export trace messages.
This should not cause a problem for EMU[4:2] since these signals can not be used to
export trace messages for the reason explained in advisory 1.3. However, the AM335x
pins used for EMU[1:0] signals may be configured as GPIO. The Debug subsystem
would not know these signals are not available for exporting trace messages when these
pins are configured as GPIO.
Workarounds Do not configure the AM335x EMU[1:0] pins to operate as GPIO if you need to export
trace messages.
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Advisory 1.0.4 PRU-ICSS: Clock Domain Crossing (CDC) Issue
Revisions Affected 1.0
Details The PRU-ICSS has a clock domain crossing issue when the MII receive multiplexer is
configured to connect PR1_MII1 signals to PRU0 and PR1_MII0 signals to PRU1.
The multiplexer logic always uses the PR1_MII_MR0_CLK input to synchronize the
PRU0 MII receive signals and the PR1_MII_MR1_CLK input to synchronize the PRU1
MII receive signals. This cause the wrong clock to be used when the MII receive
multiplexer is configured to connect PR1_MII1 signals to PRU0 and PR1_MII0 signals to
PRU1.
As a result of this issue, support for EtherCAT media redundancy is not available.
Workarounds There is no workaround for this issue.
Advisory 1.0.5 RTC: 32.768-kHZ Clock is Gating Off
Revisions Affected 1.0
Details The RTC has a clock gating issue that stops the internal 32.768-kHz clock when the
VDD_CORE voltage domain drops below the recommended operating range or the
PWRONRSTn input terminal is held low. This issue has the following side effects:
• The RTC counters stop incrementing when the 32.768-kHz clock is gated. This
causes the RTC to lose time while the clock is gated.
• A wakeup event applied to the EXT_WAKEUP input terminal is masked if the
EXT_WAKEUP_DB_EN bit in the RTC PMIC register (0x98) is set to 1 which enables
the de-bounce function for the EXT_WAKEUP input. This occurs because the
32.768-kHz clock is being used to clock the de-bounce circuit.
Workarounds Do not turn off the VDD_CORE power source or source a logic low to the PWRONRSTn
input while expecting RTC to keep an accurate time.
Do not enable the de-bounce circuit on the EXT_WAKEUP input if an external wakeup
event needs to be detected while the 32.768-kHz clock is gated.
Advisory 1.0.6 EXTINTn: Input Function of the EXTINTn Terminal is Inverted
Revisions Affected 1.0
Details The EXTINTn input is active high.
Workarounds Use an active high interrupt source or use an external inverter to change the polarity of
any active low interrupt source.
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Advisory 1.0.7 Boot: Ethernet Boot ROM Code PHY Link Speed Detection
Revisions Affected 1.0
Details The device ROM code relies on the external PHY's Control Register (Register 0),
specifically bits 0.6 [Speed Selection (MSB)] and 0.13 [Speed Selection (LSB)], to
determine the operating speed of the link.
If the external PHY does not update its link speed selection bits to reflect the current
operating speed, the ROM code incorrectly assumes the PHY is operating at the speed
indicated by the link speed selection bits and configure the device Ethernet MAC to the
wrong speed. For example, if the default value of the PHY link speed selection bits
indicates 100 Mbps, when the PHY is actually operating at 1 Gbps, the ROM incorrectly
configures the device Ethernet MAC for 100 Mbps mode.
The IEEE 802.3 specification states: When the Auto-Negotiation Enable (bit 0.12) is
enabled, bits 0.6 and 0.13 can be read or written to, but the state of bits 0.6 and 0.13
have no effect on the link configuration, and it is not necessary for bits 0.6 and 0.13 to
reflect the operating speed of the link when it is read. While some PHYs update the link
speed in these bits to reflect the current operating speed, other PHYs do not update
these bits because it is not mandatory according to the specification.
Workarounds When using Ethernet boot, an external PHY that updates the Register 0 link speed
selection bits (0.6 and 0.13) to reflect the current operating speed is required.
Advisory 1.0.8 Boot: Ethernet Boot ROM Code Sends an Incorrect Vendor Class Identifier in
BOOTP Packet
Revisions Affected: 1.0
Details: When using Ethernet boot, the device ROM code should send a BOOTP request with a
unique identifier to distinguish itself from other devices on the same network. Instead,
the ROM code sends the same identifier, "DM814x ROM v1.0", for all devices (DM814x,
DM816x, and AM335x); hence, the download host attempting to bootstrap the devices
can no longer determine which device is requesting the code to be downloaded.
Applications using the DM814x, DM816x, and AM335x devices cannot coexist in the
same network if they are booted from Ethernet.
Workaround: There is no workaround for this issue.
For some applications, it might be necessary to uniquely identify and service BOOTP
packets from a client. The recommended approach to uniquely identify clients is to use
the MAC address. Every device comes with a unique MAC address. A list of MAC
addresses and the device type can be made available to the host in advance, so that the
host can take device-specific action when it receives a BOOTP packet from a MAC
address on the host's list.
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Advisory 1.0.9 Ethernet Media Access Controller and Switch Subsystem: C0_TX_PEND and
C0_RX_PEND Interrupts Not Connected to ARM Cortex-A8
Revisions Affected 1.0
Details The Ethernet Media Access Controller/Switch (CPSW) subsystem C0_TX_PEND and
C0_RX_PEND interrupt outputs provide a single transmit interrupt that combines
transmit channel interrupts TXPEND[7:0] and a single receive interrupt that combines
receive channel interrupts RXPEND[7:0]. The TXPEND[0] and RXPEND[0] interrupt
outputs are connected to the ARM Cortex-A8 interrupt controller (INTC) rather than the
C0_TX_PEND and C0_RX_PEND interrupt outputs. This only allows channel 0 to
interrupt the ARM Cortex-A8.
The C0_TX_PEND and C0_RX_PEND interrupt outputs are the only interrupt outputs
that support interrupt pacing. If transmit channel interrupts 1-7, receive channel interrupts
1-7, or interrupt pacing is required, the following workaround must be implemented.
Workarounds DMTIMER Workaround
The C0_TX_PEND and C0_RX_PEND interrupts can be re-routed to the ARM Cortex-A8
through two of the AM335x timers. TIMER5 and TIMER6 can be used when configured
to operate in capture mode. The time captured while operating in this mode is not
relevant, since the capture event notification to the ARM Cortex-A8 represents the
original causal interrupts coming from the EMAC and Switch subsystem.
The re-routed interrupts path are:
• ARM Cortex-A8: TINT5 (interrupt 93) <-- TIMER5 Capture Event <-- [Event Capture
Mux: event 8] <-- EMAC and Switch: C0_RX_PEND
• ARM Cortex-A8: TINT6 (interrupt 94) <-- TIMER6 Capture Event <-- [Event Capture
Mux: event 9] <-- EMAC and Switch: C0_TX_PEND
Configuration
The following configurations are required to use timer capture module interrupts:
• TIMER5 and TIMER6 are enabled with capture mode during initialization.
– Set bit 2 of the TIMER5 IRQENABLE set register located at 0x4804_602C to 1b.
– Set bit 2 of the TIMER6 IRQENABLE set register located at 0x4804_802C to 1b.
• Write the value 0x908 to the TIMER_EVT_CAPT register located at 0x44E1_0FD0 to
select EMAC and Switch event 8 (C0_RX_PEND) for TIMER 5 and EMAC and
Switch event 9 (C0_TX_PEND) for TIMER6.
• Configure TIMER5 and TIMER6 to single-capture mode by resetting the
CAPT_MODE bit of each TCLR register.
– Reset bit 13 of the TIMER5 TCLR register located at 0x4804_6038 to 0b.
– Reset bit 13 of the TIMER6 TCLR register located at 0x4804_8038 to 0b.
• Select rising-edge transition by setting the TCM bit of the TCLR register.
– Set bit 8 of the TIMER5 TCLR register located at 0x4804_6038 to 1b.
– Set bit 8 of the TIMER6 TCLR register located at 0x4804_8038 to 1b.
• Use ARM Cortex-A8 interrupt 93 for C0_RX_PEND and interrupt 94 for
C0_TX_PEND instead of interrupts 41 and 42.
Interrupt Servicing
The following is the recommended procedure for servicing interrupts. This method clears
and re-enables the interrupts properly to ensure no interrupts are missed by the
DMTimer edge detection logic. This procedure applies for both receive and transmit
interrupts.
• Clear the timer capture interrupt by writing 1 to the TCAR_IT_FLAG bit of the
respective IRQSTATUS register.
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– Clear the TIMER5 interrupt by setting bit 2 of the TIMER5 IRQSTATUS register
located at 0x4804_6028 to 1b.
– Clear the TIMER6 interrupt by setting bit 2 of the TIMER6 IRQSTATUS register
located at 0x4804_8028 to 1b.
• Disable all CPSW interrupts by clearing the C0_xx_EN field in the respective
C0_RX_EN/C0_TX_EN register.
• Acknowledge the interrupt by writing the appropriate RX or TX vector to the
CPDMA_EOI_VECTOR register.
• Process all received or transmitted packets.
• Enable the desired CPSW interrupts in the C0_xx_EN field in the respective
C0_RX_EN/C0_TX_EN register.
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Advisory 1.0.10 GMII_SEL Register: RGMII1_IDMODE and RGMII2_IDMODE Bits Reset to Non-
supported Mode of Operation
Revisions Affected 1.0
Details The reset state of RGMII1_IDMODE (bit 4) and RGMII2_IDMODE (bit 5) in the
GMII_SEL register enables internal delay mode on the transmit clock of the respective
RGMII port. The AM335x device does not support internal delay mode, so
RGMII1_IDMODE and RGMII2_IDMODE must be set to 1b.
Workarounds Many RGMII Ethernet PHYs provide an internal delay mode that may be enabled to
insert delays required to meet the setup and hold timing requirements of the AM335x
device and attached RGMII PHY. A timing analysis is recommended before the printed
circuit board (PCB) design has been completed, in case it is necessary to insert
additional delays on the RGMII signals connecting the AM335x device and attached
RGMII PHY.
It is necessary to insert PCB delays if the RGMII PHY being connected to the AM335x
device does not support internal delay mode. A complete timing analysis is required to
determine the optimum delay of each PCB signal trace.
17
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Advisory 1.0.11 USB: Attached Non-compliant USB Device that Responds to Spurious Invalid
Short Packet May Lock Up Bus
Revisions Affected 1.0
Details The integrated USB PHY (analog transceiver) has a timing error that turns on its receiver
too early and occasionally detects the end of its own transmit data as receive data. This
causes the USB controller to transmit an invalid short packet. Normally this invalid short
packet would be ignored by the attached USB device and the data transmission would
continue as expected.
At least one mass storage class USB device has been found to be non-compliant to the
USB specification, by responding to this packet. This non-compliant response (NACK) to
the invalid short packet violates USB protocol and causes the bus to hang.
Poor signal integrity of the differential signal pair used to connect the attached USB
device may contribute to this issue. Impedance discontinuities and mismatched
terminations on the differential signal pair may cause reflections to propagate longer
than expected, which allows the transceiver to detect these reflections of its own transmit
data as receive data.
Workarounds There is no workaround for this issue.
To prevent an unexpected response to any invalid short packets, attach only USB
devices that are compliant with the USB specification.
To minimize reflections, it is also recommended that the USB DP and DM signals are
routed as a 90-Ωdifferential pair transmission line with minimum impedance
discontinuities and proper terminations.
Advisory 1.0.12 UART: Extra Assertion of FIFO Transmit DMA Request, UARTi_DMA_TX
Revisions Affected 2.1, 2.0, 1.0
Details A UART transmit request with a DMA THRESHOLD default configuration of 64 bytes
results in an extra DMA request assertion when the FIFO TX_FULL is switched from
high to low.
Workarounds To avoid an extra DMA request assertion, use:
TX_THRESHOLD + TRIGGER_LEVEL ≤63 (TX FIFO Size - 1).
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Advisory 1.0.13 USB: Data May be Lost When USB Subsystem is Operating in DMA Mode and
More Than One Endpoint is Transferring Data
Revisions Affected 1.0
Details Data loss may occur due to a USB data toggle synchronization error that occurs when
an internal data toggle counter is erroneously reset from the DATA1 state to the DATA0
state while the USB subsystem is actively receiving data from more than one endpoint.
The erroneous reset of the data toggle counter occurs because the associated logic in
the USB subsystem DMA contains an error that does not support the correct data toggle
update with data transfers from multiple endpoints.
If the DATA1 state is erroneously reset to the DATA0 state immediately following a USB
transaction in which the PID is DATA0, the transmitter and receiver become de-
synchronized. This data toggle synchronization error causes the receiver, per the USB
specification, to silently discard the non-synchronized packet, which causes the packet
and any data contain therein to be lost.
NOTE: For more information related to the definition of DATA0 and DATA1 PIDs
and functional requirements of data toggle synchronization, see sections
8.4.4 and 8.6 of the Universal Serial Bus Specification Revision 2.0.
Workarounds • Operating in USB host mode - The workaround involves detecting and correcting the
data toggle mismatch by software after receiving each USB packet. In order to
implement this workaround, the CPPI4.1 DMA must be configured to operate in
transparent mode; generic RNDIS mode cannot be used. Software must save the
previous data toggle value then compare the current data toggle value and the saved
value to detect a data toggle mismatch. If a synchronization error is detected, it must
be corrected by simultaneously writing 1b to the data toggle write enable and data
toggle bits in the respective RxCSR registers.
• Operating in USB device mode - There is no workaround for this mode of operation.
19
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Advisory 1.0.14 GMII_SEL and CPSW Related Pad Control Registers: Context of These Registers is
Lost During Transitions of PD_PER
Revisions Affected 1.0
Details The GMII_SEL and CPSW related pad control registers listed below are reset to their
default state during transitions of peripheral power domain (PD_PER) while the
ISO_CONTROL bit in the RESET_ISO register is set to its default value (0b). This
occurs when the AM335x device enters or exits DeepSleep0.
REGISTER NAME REGISTER ADDRESS
GMII_SEL 0x44E1_0650
CONF_GPMC_A0 0x44E1_0840
CONF_GPMC_A1 0x44E1_0844
CONF_GPMC_A2 0x44E1_0848
CONF_GPMC_A3 0x44E1_084C
CONF_GPMC_A4 0x44E1_0850
CONF_GPMC_A5 0x44E1_0854
CONF_GPMC_A6 0x44E1_0858
CONF_GPMC_A7 0x44E1_085C
CONF_GPMC_A8 0x44E1_0860
CONF_GPMC_A9 0x44E1_0864
CONF_GPMC_A10 0x44E1_0868
CONF_GPMC_A11 0x44E1_086C
CONF_GPMC_WAIT0 0x44E1_0870
CONF_GPMC_WPN 0x44E1_0874
CONF_GPMC_BEN1 0x44E1_0878
CONF_MII1_COL 0x44E1_0908
CONF_MII1_CRS 0x44E1_090C
CONF_MII1_RX_ER 0x44E1_0910
CONF_MII1_TX_EN 0x44E1_0914
CONF_MII1_RX_DV 0x44E1_0918
CONF_MII1_TXD3 0x44E1_091C
CONF_MII1_TXD2 0x44E1_0920
CONF_MII1_TXD1 0x44E1_0924
CONF_MII1_TXD0 0x44E1_0928
CONF_MII1_TX_CLK 0x44E1_092C
CONF_MII1_RX_CLK 0x44E1_0930
CONF_MII1_RXD3 0x44E1_0934
CONF_MII1_RXD2 0x44E1_0938
CONF_MII1_RXD1 0x44E1_093C
CONF_MII1_RXD0 0x44E1_0940
CONF_RMII1_REF_CLK 0x44E1_0944
CONF_MDIO 0x44E1_0948
CONF_MDC 0x44E1_094C
Workarounds Re-initialize these registers after exiting DeepSleep0.
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