Texas Instruments PGA411-Q1 EVM User manual

PGA411-Q1
EXC
SIN
COS
&
MCU
I/O
Resolver Sensor Resolver to Digital Interface System Control
Copyright © 2016, Texas Instruments Incorporated
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An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
PGA411-Q1
SLASE76E –NOVEMBER 2015–REVISED AUGUST 2017
PGA411-Q1 Resolver Sensor Interface
1
1 Features
1• Qualified for Automotive Applications
• AEC-Q100 Qualified With the Following Results:
– Device Temperature Grade 1: –40°C to
+125°C Ambient Operating Temperature
Range
– Device HBM ESD Classification Level 2
– Device CDM ESD Classification Level C4B
• Resolver-to-Digital Converter (RDC)
• Exciter Preamplifier and Power Amplifier
• Exciter-Boost Power Supply With Spread
Spectrum
• Analog Front-End
• Automatic Offset Calibration
• Type-II PI Controller Tracking Loop
• Parallel, Encoder, or SPI Data Output
• Analog Data Output
• SafeTI™ Semiconductor Component
– Designed for Functional Safety Applications
– Developed According to the Requirements of
ISO 26262
• Automatic and Manual Phase Correction
• Sensor-Input Fault Detection
• Diagnostics Interrupt Output
• Internal and External Oscillator
• Analog and Logic Built-In Self-Test for Fault
Detection
• 64-Pin HTQFP PowerPAD™ IC Package
2 Applications
• Motor Control
• HEV/EV Motor Inverters
• Electrical Power Steering
• Integrated Start-Stop Generators
• Servo Drives
• AC Drives
• Industrial Robots
• CNC Machinery
• Elevators and Lifts
• Injection Molding Machinery
3 Description
The PGA411-Q1 device is a resolver-to-digital
converter, with an integrated exciter-amplifier and
boost-regulator power supply, that is capable of both
exciting and reading the sine and cosine angle from a
resolver sensor. The integration of the exciter
amplifier and boost supply with protection in the
PGA411-Q1 device enables cost reductions of the bill
of materials (BOM) and space reductions on the
printed-circuit board (PCB) because of the elimination
of most external and passive components.
The PGA411-Q1 device also has an internal clock for
generating a sine wave used for sensor excitation.
The architecture of the analog front-end (AFE) allows
the user to output 10 bits or 12 bits of resolution for
the angle position and velocity. Because of high
integration, the PGA411-Q1 device has diagnostics
and protection on each internal block inside the
device. The integrated diagnostics monitor can signal
a fault condition through a dedicated pin which can
be used as a MCU interrupt. These features allow
flexibility in both resolver sensor choice and platform
scalability. Additionally, the PGA411-Q1 was
designed according to the requirements of ISO 26262
for functional safety applications.
Device Information(1)
PART
NUMBER PACKAGE BODY SIZE (NOM)
PGA411-Q1 HTQFP (64) 10.00 mm × 10.00 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Simplified System Diagram

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Table of Contents
1 Features.................................................................. 1
2 Applications ........................................................... 1
3 Description............................................................. 1
4 Revision History..................................................... 2
5 Pin Configuration and Functions......................... 4
6 Specifications......................................................... 6
6.1 Absolute Maximum Ratings ...................................... 6
6.2 ESD Ratings.............................................................. 6
6.3 Recommended Operating Conditions....................... 6
6.4 Thermal Information.................................................. 7
6.5 Exciter Output, Amplifier, and Power Supply
Characteristics ........................................................... 7
6.6 Analog Front-End Characteristics............................. 8
6.7 Digital Tracking Loop Characteristics ....................... 9
6.8 Diagnostics Monitor Characteristics.......................... 9
6.9 VDD Regulator Characteristics ................................ 12
6.10 Digital I/O Characteristics ..................................... 12
6.11 Oscillator Characteristics ...................................... 13
6.12 Output Data Interface Characteristics................... 13
6.13 SPI Interface Timing Requirements...................... 13
6.14 Timing Diagrams................................................... 14
6.15 Typical Characteristics.......................................... 15
7 Detailed Description............................................ 17
7.1 Overview................................................................. 17
7.2 Functional Block Diagram....................................... 17
7.3 Feature Description................................................. 18
7.4 Device Functional Modes........................................ 45
7.5 Programming........................................................... 54
7.6 Register Maps......................................................... 57
8 Application and Implementation ........................ 84
8.1 Application Information............................................ 84
8.2 Typical Application ................................................. 84
8.3 System Examples ................................................... 92
8.4 Initialization Set Up ................................................. 95
9 Power Supply Recommendations...................... 95
9.1 Sequencing VIO and VCC...................................... 96
10 Layout................................................................... 96
10.1 Layout Guidelines ................................................. 96
10.2 Layout Example .................................................... 96
11 Device and Documentation Support................. 99
11.1 Documentation Support ........................................ 99
11.2 Community Resource............................................ 99
11.3 Trademarks........................................................... 99
11.4 Electrostatic Discharge Caution............................ 99
11.5 Glossary................................................................ 99
12 Mechanical, Packaging, and Orderable
Information........................................................... 99
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision D (April 2016) to Revision E Page
• Updated data sheet text to the latest TI documentation and translation standards............................................................... 1
• Changed the Electrical Characteristics test conditions from: VIN = 4.5 to: VIN = 4.75............................................................ 8
• Changed the VIZx parameter and unit information.................................................................................................................. 8
• Removed the common-mode voltage output parameter from the Analog Front-End Characteristics table........................... 8
• Updated Figure 2.................................................................................................................................................................. 14
• Added content to the Exciter Signal Preamplifier section ................................................................................................... 20
• Added content to the Exciter Output Power Amplifier section ............................................................................................. 20
• Updated Figure 14 and added Table 1................................................................................................................................. 21
• Added new content to the Automatic Offset Correction section .......................................................................................... 26
• Updated Figure 20 ............................................................................................................................................................... 28
• Changed the undervoltage threshold of the 7-VRMS output-mode of operation from: 7 V to: 6 V ........................................ 35
• Removed content from the Exciter-Output Current Limit section......................................................................................... 35
• Added image and new content to the Digital Parallel Output section.................................................................................. 38
• Added new content to the ORD Clock section .................................................................................................................... 40
• Removed the ENFLOOPE option from the data sheet ........................................................................................................ 44
• Updated DEV_CONFIG1 data split info in Table 7 .............................................................................................................. 50
• Updated register description for Bit 4-3 ............................................................................................................................... 64
• Updated Table 41 and Table 42........................................................................................................................................... 86

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Changes from Revision C (March 2016) to Revision D Page
• Added the resistor to ground production statement in the Analog Output section and Pin Functions table and added
the resistor to the PGA411-Q1 Typical Application Diagram image ................................................................................... 43
• Changed the factory setting from 003Fh (00111111b) to 00CEh (11001110b) for the DEV_CLCRC register in the
User EEPROM Space SPI Mapping table and in the DEV_CLCRC Register section......................................................... 80
• Added a note to the Power Supply Recommendations section about the input supply when connected to VCC and
QVCC pins ........................................................................................................................................................................... 96
Changes from Revision B (December 2015) to Revision C Page
• Changed the device status from Product Preview to Production Data ................................................................................. 1

Thermal
Pad
64 OUTZ17NCS
1OUTA 48 ORD9
63 XOUT18SCLK
2OUTB 47 ORD1
62 XIN19SDI
3ECLKSEL 46 ORD11
61 VIO2SDO
4VCCSW 45 ORD12
6 VCC 21DGND
5BMODE 44 ORDCLK
59 NC22OE1
6VSW 43 OSIN
58 VDD 23NC
7NC 42 IZ4
57 ORD24VEXT
8PGND 41 IZ2
56 ORD125NC
9ORS 4 QGND
55 ORD226OE2
1VEXTS 39 QVCC
54 ORD327PBKG
11TEST 38 IZ1
53 ORD428AMODE
12NRESET 37 IZ3
52 ORD529OMODE
13INHB 36 OCOS
51 ORD63AOUT
14FAULTRES 35 COMAFE
5 ORD731VA
15PRD 34 IE1
49 ORD832VA1
16FAULT 33 IE2
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5 Pin Configuration and Functions
PAP Package
64-Pin HTQFP With Exposed Thermal Pad
Top View
NC - No internal connection
(1) I = input; O = output; I/O = input and output; P = power
Pin Functions
PIN TYPE(1) LOGIC
INPUT OR
OUTPUT DESCRIPTION
NAME NO.
AMODE 28 I Input Accelerated mode select
AOUT 30 O — ORD (angle and velocity) analog output. Use for testing only, in production connect to
ground.
BMODE0 5 I Input Resolution select, input low is 10-bit mode, input high is 12-bit mode
COMAFE 35 O — Common-mode output for the analog front-end (AFE)
DGND 21 P — Digital ground
ECLKSEL 3 I Input Clock select input
FAULT 16 O Output Fault-detection signal output (open-drain structure)
FAULTRES 14 I Input Fault reset input (faults are reset when this pin is LOW)
IE1 34 I — Positive input to the AFE from the resolver exciter coil
IE2 33 I — Negative input to the AFE from the resolver exciter coil
INHB 13 I Input Inhibit function and output data hold

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Pin Functions (continued)
PIN TYPE(1) LOGIC
INPUT OR
OUTPUT DESCRIPTION
NAME NO.
IZ1 38 I — Positive input to the AFE from the resolver cosine coil
IZ2 41 I — Positive input to the AFE from the resolver sine coil
IZ3 37 I — Negative input to the AFE from the resolver cosine coil
IZ4 42 I — Negative input to the AFE from the resolver sine coil
NC
7
I — Not connected (connect to ground)
23
25
59
NCS 17 I Input Chip select for the serial peripheral interface (SPI)
NRESET 12 I Input Reset input
OCOS 36 O — Resolver cosine output
OE1 22 O — Exciter-amplifier positive output
OE2 26 O — Exciter-amplifier negative output
OMODE 29 I Input Data output format select
ORD0 57 O Output Data output, 0 for parallel angle and velocity. Encoder output U
ORD1 56 O Output Data output, 1 for parallel angle and velocity. Encoder output V
ORD10 47 O Output Data output, 10 for parallel angle and velocity
ORD11 46 O Output Data output, 11 for parallel angle and velocity
ORD12 45 O Output Optional pin (data output, 12 for parallel angle and velocity - unused)
ORDCLK 44 O Output ORD Clock
ORD2 55 O Output Data output select 2 for parallel angle and velocity. Encoder output W
ORD3 54 O Output Data output select 3 for parallel angle and velocity. Encoder output U1
ORD4 53 O Output Data output select 4 for parallel angle and velocity. Encoder output V1
ORD5 52 O Output Data output select 5 for parallel angle and velocity. Encoder output W1
ORD6 51 O Output Data output select 6 for parallel angle and velocity. Encoder output A
ORD7 50 O Output Data output select 7 for parallel angle and velocity. Encoder output B
ORD8 49 O Output Data output select 8 for parallel angle and velocity. Encoder output Z
ORD9 48 O Output Data output select 9 for parallel angle and velocity
ORS 9 O — Exciter preamplifier output
OSIN 43 O — Resolver sine output
OUTA 1 O Output Incremental encoder, output A
OUTB 2 O Output Incremental encoder, output B
OUTZ 64 O Output Incremental encoder, output Z
PBKG 27 P — Ground
PGND 8 P — Power ground
PRD 15 O Output Data parity output
QGND 40 P — Power supply ground (quiet, used for AFE)
QVCC 39 P — Power supply input (quiet, used for AFE)
SCLK 18 I Input SPI clock
SDI 19 I Input SPI data input
SDO 20 O Output SPI data output
TEST 11 I/O — Test input and output (I/O). Texas Instruments reserved pin. Connect this pin to
ground.
VA0 31 I Input Data output select 0 for angle and velocity
VA1 32 I Input Data output select 1 for angle and velocity
VCC 60 P — Power supply input

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Pin Functions (continued)
PIN TYPE(1) LOGIC
INPUT OR
OUTPUT DESCRIPTION
NAME NO.
VCCSW 4 P — Boost DC-DC inverter-supply input
VDD 58 P — Output for the regulated digital power supply
VEXT 24 P — Exciter-amplifier supply input
VEXTS 10 I — Sense input for the boost supply and diagnostics.
VIO 61 P — Logic I/O voltage-level supply input
VSW 6 O — Boost DC-DC inverter FET drain
XIN 62 I — Crystal input
XOUT 63 O — Crystal output
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) MIN MAX UNIT
Input voltage
VEXTS, OE1, OE2 –0.3 40
V
VCCSW, VSW, VEXT, IZ1, IZ2, IZ3, IZ4 –0.3 20
VDD, XIN, XOUT –0.3 2
PGND, DGND, GND –0.3 0.3
All Other pins –0.3 5.5
Operating junction temperature –40 150 °C
Storage temperature, Tstg –65 150 °C
(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
6.2 ESD Ratings VALUE UNIT
V(ESD) Electrostatic discharge
Human-body model (HBM), per AEC Q100-002(1) ±2000
V
Charged-device model (CDM), per AEC
Q100-011
All pins ±500
Corner pins (1, 16, 17, 32, 33,
48, 49, and 64) ±750
6.3 Recommended Operating Conditions
Over operating free-air temperature range (unless otherwise noted). MIN NOM MAX UNIT
VCC / QVCC Supply input voltage 4.75 5 5.25 V
VEXT Exciter supply
input VEXT 4-VRMS mode 11 12 13 V
7-VRMS mode 14 15 16
VCCSW Boost regulator
input VCCSW 4.75 8.5 V
VIO I/O supply
input VIO VVIO = 3.3 V 2.97 3.3 3.63 V
VVIO = 5 V 4.5 5 5.25
VIZ Differential
amplitude input IZ1, IZ2, IZ3, IZ4 (VIZ1 - VIZ3); (VIZ2 - VIZ4) 2 3 VPP
TAOperating fee-air temperature –40 125 °C
TJOperating junction temperature –40 150 °C

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(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
6.4 Thermal Information
THERMAL METRIC(1) PGA411-Q1 UNITPAP (HTQFP)
64 PINS
RθJA Junction-to-ambient thermal resistance 25.5 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 10.9 °C/W
RθJB Junction-to-board thermal resistance 9.1 °C/W
ψJT Junction-to-top characterization parameter 0.3 °C/W
ψJB Junction-to-board characterization parameter 9.1 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance 0.4 °C/W
6.5 Exciter Output, Amplifier, and Power Supply Characteristics
VCC = 4.75 to 5.25 V, TA= –40°C to +125°C (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
EXCITER SIGNAL OUTPUT (PREAMPLIFIER)
AEXC Exciter preamplifier gain SPI programmable 1.15 1.9 V/V
fEXC Exciter output frequency
range SELFEXT = 0x00; System clock used; fOSC = 20 MHz 9 10 11 kHz
SELFEXT = 0x07; System clock used; fOSC = 20 MHz 18 20 22
VORS Signal output voltage ORS signal with respect to COMAFE voltage; GAIN = 1.5;
CORS = 0.47 nF; IORS = ± 10 µA 1.5 2 VPeak
VCOMAFE Common-mode voltage
output COMAFE pin; CCOMAFE = 10 nF 2.25 2.5 2.75 V
EXCITER POWER SUPPLY
VEXCPS Exciter power-supply output
voltage
MODEVEXT = 0x00; IEXTPS = 150 mA; VCCSW ≥4.75 V;
nBOOST_FF = 1 8 10 12
V
MODEVEXT = 0x01; IEXTPS = 150 mA; VCCSW ≥4.75 V;
nBOOST_FF = 1 9 11 13
MODEVEXT = 0x02; IEXTPS = 150 mA; VCCSW ≥5 V;
nBOOST_FF = 1 10 12 14
MODEVEXT = 0x03; IEXTPS = 150 mA; VCCSW ≥5 V;
nBOOST_FF = 1 11 13 15
MODEVEXT = 0x04; IEXTPS = 150 mA; VCCSW ≥5 V;
nBOOST_FF = 1 12 14 16
MODEVEXT = 0x05; IEXTPS = 150 mA; VCCSW ≥6 V;
nBOOST_FF = 1 13 15 17
MODEVEXT = 0x06; IEXTPS = 150 mA; VCCSW ≥6 V;
nBOOST_FF = 1 14 16 18
MODEVEXT = 0x07; IEXTPS = 150 mA; VCCSW ≥7 V;
nBOOST_FF = 1 15 17 19
fEXTPS Exciter power-supply
switching frequency With 10% spread spectrum 414 kHz
LEXCPS Exciter power-supply
inductor range 56 µH
CEXCPS Exciter power-supply
capacitor range 10 µF

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Exciter Output, Amplifier, and Power Supply Characteristics (continued)
VCC = 4.75 to 5.25 V, TA= –40°C to +125°C (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
EXCITER AMPLIFIER
VEXCO Exciter-amplifier differential
output voltage
4-VRMS mode; EXTOUT_GL = 0x00 7.12 8.38
VPP
4-VRMS mode; EXTOUT_GL = 0x01 7.44 8.75
4-VRMS mode; EXTOUT_GL = 0x02 7.74 9.11
4-VRMS mode; EXTOUT_GL = 0x03 8.05 9.47
4-VRMS mode; EXTOUT_GL = 0x04 8.36 9.84
4-VRMS mode; EXTOUT_GL = 0x05 8.67 10.2
4-VRMS mode; EXTOUT_GL = 0x06 8.98 10.57
4-VRMS mode; EXTOUT_GL = 0x07 9.29 10.93
4-VRMS mode; EXTOUT_GL = 0x08 9.61 11.3
4-VRMS mode; EXTOUT_GL = 0x09 9.91 11.66
4-VRMS mode; EXTOUT_GL = 0x0A 10.23 12.03
4-VRMS mode; EXTOUT_GL = 0x0B 10.53 12.39
4-VRMS mode; EXTOUT_GL = 0x0C 10.84 12.75
4-VRMS mode; EXTOUT_GL = 0x0D 11.15 13.12
4-VRMS mode; EXTOUT_GL = 0x0E 11.46 13.48
4-VRMS mode; EXTOUT_GL = 0x0F 11.77 13.85
7-VRMS mode; EXTOUT_GL = 0x00 12.49 14.69
7-VRMS mode; EXTOUT_GL = 0x01 13.03 15.33
7-VRMS mode; EXTOUT_GL = 0x02 13.57 15.97
7-VRMS mode; EXTOUT_GL = 0x03 14.12 16.61
7-VRMS mode; EXTOUT_GL = 0x04 14.65 17.24
7-VRMS mode; EXTOUT_GL = 0x05 15.20 17.88
7-VRMS mode; EXTOUT_GL = 0x06 15.74 18.52
7-VRMS mode; EXTOUT_GL = 0x07 16.29 19.16
7-VRMS mode; EXTOUT_GL = 0x08 16.83 19.8
7-VRMS mode; EXTOUT_GL = 0x09 17.37 20.44
7-VRMS mode; EXTOUT_GL = 0x0A 17.92 21.08
7-VRMS mode; EXTOUT_GL = 0x0B 18.46 21.72
7-VRMS mode; EXTOUT_GL = 0x0C 19 22.35
7-VRMS mode; EXTOUT_GL = 0x0D 19.54 22.99
7-VRMS mode; EXTOUT_GL = 0x0E 20.09 23.63
7-VRMS mode; EXTOUT_GL = 0x0F 20.63 24.27
VREXC Exciter-amplifier reference
voltage SPI programmable using EXTOUT bits 0.5 2 V
IQEXC Exciter-amplifier quiescent
current 1 15 mA
IEXCO Exciter amplifier output
current range (OE1-OE2) = 20 VPP 145 mA
IEXCREV Exciter amplifier output
reverse current Reverse current to VEXT, OE1 or OE2 shorted to battery (battery must be greater than 180% of VEXT) 15 mA
6.6 Analog Front-End Characteristics
Over operating free-air temperature range, VIN = 4.75 to 5.25 V, TA= –40°C to +125°C (unless otherwise noted).
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
EXCITER SIGNAL MONITOR (IE1, IE2)
VIECM Input voltage range 0.5 4.5 V
fIEIN Input frequency range 8 24 kHz
REIN Input resistance 30 40 50 kΩ
SIN AND COS INPUT GAIN AMPLIFIER (IZ1, IZ3), (IZ2, IZ4), (OSIN, OCOS)
SGAIN(CGAIN) SIN and COS Amplifier Gain
COMAFE = 2.5 V; GAINCOS = GAINSIN = 0x00 0.735 0.75 0.765
V/V
COMAFE = 2.5 V; GAINCOS = GAINSIN = 0x01 0.98 1 1.02
COMAFE = 2.5 V; GAINCOS = GAINSIN = 0x02 2.205 2.25 2.295
COMAFE = 2.5 V; GAINCOS = GAINSIN = 0x03 3.43 3.5 3.57
VIZx IZx input voltage range (pk-
pk) SGAIN = 0.75; CGAIN = 0.75 COMAFE=2.5 V 3 Vpp

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Analog Front-End Characteristics (continued)
Over operating free-air temperature range, VIN = 4.75 to 5.25 V, TA= –40°C to +125°C (unless otherwise noted).
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
IIZx IZx input current range At VIZX = 1 V and 4 V –150 150 µA
RIZx IZx input resistance (internal) 15 20 25 kΩ
CMRRSIN(COS)Commond-mode rejection
ratio 45 dB
PSRRsin(cos) Supply rejection ratio 60 dB
VOS(VOC) Output voltage range OSIN pin; OCOS pin; IOUT = 10 µA 0.5 4.5 V
(1) Refers to a differential angle change.
(2) Digital Tracking Loop Settings: Dki = 0x4; Dkp = 0x4; Mkp = 0x2 (Mkp used only when AMODE = H)
6.7 Digital Tracking Loop Characteristics
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
OMODE1 Output data resolution 1 BMODE0=L 10 bit
OMODE2 Output data resolution 2 BMODE0=H 12 bit
TR1 Maximum tracking rate 1 10-bit mode 200 000 rpm
TR2 Maximum tracking rate 2 12-bit mode 72 000 rpm
ACL1 Maximum angular
acceleration 1 10-bit mode 200 000 rad / s2
ACL2 Maximum angular
acceleration 2 12-bit mode 50 000 rad / s2
ACC1 Maximum angular accuracy
1(1) 10-bit mode ±10.56 arc min
ACC2 Maximum angular accuracy
2(1) 12-bit mode ±2.64 arc min
INL1 Integral linearity 1 10-bit mode; OHYS = 1 –2 2 LSB
INL2 Integral linearity 2 12-bit mode; OHYS = 1 –8 8 LSB
DNL1 Differential linearity 1 10-bit mode; OHYS = 1 –1 1 LSB
DNL2 Differential linearity 2 12-bit mode; OHYS = 1 –2 3 LSB
tDLT1 Settling time 1(2) AMODE=H; 180-degree step input; 10-bit mode 0.1 1.5 3.5 ms
AMODE=H; 180-degree step input; 12-bit mode 0.1 3 7
tDLT2 Settling time 2(2) AMODE=L; 180-degree step input; 10-bit mode 11 15 18 ms
AMODE=L; 180-degree step input; 12-bit mode 45 60 65
tRESP Phase delay response fIN = 10 000 rpm –0.4 0.4 deg
PhADJ Exciter to SIN and COS
phase adjustment range
Manual mode; fEXC= 10 kHz –44.5 44.5
degManual mode; fEXC= 20 kHz –89.2 89.2
Auto mode –89.2 89.2
PhADJ_STEP
Exciter to SIN and COS
phase adjustment range step
size
Manual mode; fEXC= 10 kHz 1.44
deg
Manual mode; fEXC= 20 kHz 2.88
Auto mode; fEXC= 10 kHz 0.36
Auto mode; fEXC= 20 kHz 0.72
6.8 Diagnostics Monitor Characteristics
VCC = 4.75 to 5.25 V, TA= –40°C to +125°C (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
GENERAL
VCCOV VCC overvoltage threshold SPI flag; Exciter disabled 5.4 5.75 5.92 V
VCCUV VCC undervoltage threshold NPOR asserted 4.28 4.41 4.54 V
tVCCOVUV VCC overvoltage and
undervoltage deglitch time 4.2 5.2 6.2 µs
VDD REGULATOR
VVDD Digital functional voltage range VDD pin 1.623 1.984 V
VDDOV VDD overvoltage threshold SPI flag; Exciter disabled 2 2.2 2.4 V
VDDUV VDD undervoltage threshold SPI flag; NPOR asserted 1.23 1.35 1.53 V
tVDDOVUV VDD overvoltage and
undervoltage deglitch time 4.2 5.2 6.2 µs
IVDDLIM VDD current limit VCC = 4.75 to 5.25 V; SPI flag; Maximum current draw from VDD
for external consumption is 10 mA 10 100 250 mA

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Diagnostics Monitor Characteristics (continued)
VCC = 4.75 to 5.25 V, TA= –40°C to +125°C (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
tVDDOC VDD overcurrent deglitch time 4.2 5.2 6.2 µs
EXCITER POWER SUPPLY
OVEXCPS Exciter power-supply
overvoltage threshold SPI flag 110 115 122 % VEXCPS
UVEXCPS Exciter power-supply
undervoltage threshold 75 82.5 85 % VEXCPS
COVEXCPS Critical overvoltage threshold Power supply disabled 180 % VEXCPS
CUVEXCPS Critical undervoltage threshold Power supply disabled 15 % VEXCPS
tEXCPS Exciter power-supply fault
deglitch time 9.2 10.2 11.2 us
EXCITER AMPLIFIER
SOVEXC Single-ended overvoltage Exciter disabled 110 115 120 %VEXC
OVEXC Differential overvoltage
threshold 4 Vrms mode; Exciter disabled; SPI flag 6.8 8 9.2 V
7 Vrms mode; Exciter disabled; SPI flag 11.9 14 16.1
UVEXC Differential undervoltage
threshold 4 Vrms mode; Exciter disabled; SPI flag 2.55 3 3.45 V
7 Vrms mode; Exciter disabled; SPI flag 5.1 6 6.9
IEXCOLIM(OE1-OE2)
Exciter amplifier output current-
limit high level (from OE1 into
OE2)
EXTILIMTH_H1_2 = 0x0 100 150 190
mA
EXTILIMTH_H1_2 = 0x1 110 165 210
EXTILIMTH_H1_2 = 0x2 120 180 230
EXTILIMTH_H1_2 = 0x3 130 200 250
EXTILIMTH_H1_2 = 0x4 150 225 281
EXTILIMTH_H1_2 = 0x5 170 260 320
EXTILIMTH_H1_2 = 0x6 200 300 370
EXTILIMTH_H1_2 = 0x7 230 360 440
IEXCOLIM(OE2-OE1)
Exciter amplifier output current-
limit low level (from OE2 into
OE1)
EXTILIMTH_L1_2 = 0x0 90 140 181
mA
EXTILIMTH_L1_2 = 0x1 100 150 200
EXTILIMTH_L1_2 = 0x2 110 165 220
EXTILIMTH_L1_2 = 0x3 120 180 231
EXTILIMTH_L1_2 = 0x4 140 200 260
EXTILIMTH_L1_2 = 0x5 160 230 550
EXTILIMTH_L1_2 = 0x6 180 550 830
EXTILIMTH_L1_2 = 0x7 210 550 830
tEXCOV Exciter-amplifier overvoltage
deglitch time SPI programmable using EXTOVT bits 1.2 15.2 µs
tEXCUV Exciter-amplifier undervoltage
deglitch time EXTUV_CFG=10; SPI programmable using EXTUVT bits 1.2 15.2 µs
EXTUV_CFG=0x; SPI programmable using EXTUVT bits 55 405 µs
tEXCOLIM Exciter-amplifier output current-
limit deglitch time 4.2 5.2 6.2 µs
ANALOG FRONT-END
OVIZX Input overvoltage threshold
IZ1, IZ2, IZ3, IZ4 pins; Reported by SPI flags; OVIZH = 0x0 72 75 78
%VCC
IZ1, IZ2, IZ3, IZ4 pins; Reported by SPI flags; OVIZH = 0x1 77 80 83
IZ1, IZ2, IZ3, IZ4 pins; Reported by SPI flags; OVIZH = 0x2 82 85 88
IZ1, IZ2, IZ3, IZ4 pins; Reported by SPI flags; OVIZH = 0x3 87 90 93
UVIZX Input undervoltage threshold
IZ1, IZ2, IZ3, IZ4 pins; Reported by SPI flags; OVIZL = 0x0 22 25 28
%VCC
IZ1, IZ2, IZ3, IZ4 pins; Reported by SPI flags; OVIZL = 0x1 17 20 23
IZ1, IZ2, IZ3, IZ4 pins; Reported by SPI flags; OVIZL = 0x2 12 15 18
IZ1, IZ2, IZ3, IZ4 pins; Reported by SPI flags; OVIZL = 0x3 7 10 13
tOVUV_IZX Input overvoltage and
undervoltage deglitch time SPI programmable using IZTHL bits(Independent) 1.2 15.2 µs
VSHRTP Positive input short-circuit
voltage
OSIN, OCOS pins; Reported by SPI flags; OSHORTH = 0x0 50.4 52.5 54.6
%VCC
OSIN, OCOS pins; Reported by SPI flags; OSHORTH = 0x1 52.8 55 57.2
OSIN, OCOS pins; Reported by SPI flags; OSHORTH = 0x2 55.2 57.5 59.8
OSIN, OCOS pins; Reported by SPI flags; OSHORTH = 0x3 57.6 60 62.4
OSIN, OCOS pins; Reported by SPI flags; OSHORTH = 0x4 60 62.5 65
OSIN, OCOS pins; Reported by SPI flags; OSHORTH = 0x5 62.4 65 67.6
OSIN, OCOS pins; Reported by SPI flags; OSHORTH = 0x6 64.8 67.5 70.2
OSIN, OCOS pins; Reported by SPI flags; OSHORTH = 0x7 67.2 70 72.8

11
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Diagnostics Monitor Characteristics (continued)
VCC = 4.75 to 5.25 V, TA= –40°C to +125°C (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VSHRTN Negative input short-circuit
voltage
OSIN, OCOS pins; Reported by SPI flags; OSHORTL = 0x0 45.6 47.5 49.4
%VCC
OSIN, OCOS pins; Reported by SPI flags; OSHORTL = 0x1 43.2 45 46.8
OSIN, OCOS pins; Reported by SPI flags; OSHORTL = 0x2 40.8 42.5 44.2
OSIN, OCOS pins; Reported by SPI flags; OSHORTL = 0x3 38.4 40 41.6
OSIN, OCOS pins; Reported by SPI flags; OSHORTL = 0x4 36 37.5 39
OSIN, OCOS pins; Reported by SPI flags; OSHORTL = 0x5 33.6 35 36.4
OSIN, OCOS pins; Reported by SPI flags; OSHORTL = 0x6 31.2 32.5 33.8
OSIN, OCOS pins; Reported by SPI flags; OSHORTL = 0x7 28.8 30 31.2
VOPNP Positive input open-circuit
voltage
OSIN, OCOS pins; Reported by SPI flags; OOPENTHH = 0x0 72 75 78
%VCC
OSIN, OCOS pins; Reported by SPI flags; OOPENTHH = 0x1 74.4 77.5 80.6
OSIN, OCOS pins; Reported by SPI flags; OOPENTHH = 0x2 76.8 80 83.2
OSIN, OCOS pins; Reported by SPI flags; OOPENTHH = 0x3 79.2 82.5 85.8
OSIN, OCOS pins; Reported by SPI flags; OOPENTHH = 0x4 81.6 85 88.4
OSIN, OCOS pins; Reported by SPI flags; OOPENTHH = 0x5 84 87.5 91
OSIN, OCOS pins; Reported by SPI flags; OOPENTHH = 0x6 86.4 90 93.6
OSIN, OCOS pins; Reported by SPI flags; OOPENTHH = 0x7 88.8 92.5 96.2
VOPNN Negative input open-circuit
voltage
OSIN, OCOS pins; Reported by SPI flags; OOPENTHL = 0x0 22.5 25 27.5
%VCC
OSIN, OCOS pins; Reported by SPI flags; OOPENTHL = 0x1 20.3 22.5 24.8
OSIN, OCOS pins; Reported by SPI flags; OOPENTHL = 0x2 18 20 22
OSIN, OCOS pins; Reported by SPI flags; OOPENTHL = 0x3 15.8 17.5 19.3
OSIN, OCOS pins; Reported by SPI flags; OOPENTHL = 0x4 13.5 15 16.5
OSIN, OCOS pins; Reported by SPI flags; OOPENTHL = 0x5 11.3 12.5 13.8
OSIN, OCOS pins; Reported by SPI flags; OOPENTHL = 0x6 9 10 11
OSIN, OCOS pins; Reported by SPI flags; OOPENTHL = 0x7 6.8 7.5 8.3
tSHRT Input short deglitch time SPI programmable using TSHORT bits (Each setting has ±10-
µs tolerance) 35 140 µs
tOPN Input open deglitch time SPI programmable using TOPEN bits (Each setting has ±10-µs
tolerance) 35 140 µs
DERRP_IEX Exciter signal-monitor positive
duty error (IE1 - IE2) signal; Reported by SPI flag 80 %fEXC
DERRN_IEX Exciter signal-monitor negative
duty error (IE1 - IE2) signal; Reported by SPI flag 20 %fEXC
tERR_IEX Exciter signal-monitor duty-error
deglitch SPI programmable using TEXTMON bits (Each setting has ±10- µs tolerance) 35 140 µs
VMSENH Input integrity check high
threshold
IZ1, IZ2, IZ3, IZ4 pins; VCC = 5 V; This threshold is a percentage
of VCC; Reported by SPI flags; DVMSENH = 0x0 2.44 2.6 2.73
V
IZ1, IZ2, IZ3, IZ4 pins; VCC = 5 V; This threshold is a percentage
of VCC; Reported by SPI flags; DVMSENH = 0x1 2.59 2.75 2.88
IZ1, IZ2, IZ3, IZ4 pins; VCC = 5 V; This threshold is a percentage
of VCC; Reported by SPI flags; DVMSENH = 0x2 2.73 2.9 3.04
IZ1, IZ2, IZ3, IZ4 pins; VCC = 5 V; This threshold is a percentage
of VCC; Reported by SPI flags; DVMSENH = 0x3 2.87 3.05 3.19
IZ1, IZ2, IZ3, IZ4 pins; VCC = 5 V; This threshold is a percentage
of VCC; Reported by SPI flags; DVMSENH = 0x4 3.01 3.2 3.35
IZ1, IZ2, IZ3, IZ4 pins; VCC = 5 V; This threshold is a percentage
of VCC; Reported by SPI flags; DVMSENH = 0x5 3.15 3.35 3.5
IZ1, IZ2, IZ3, IZ4 pins; VCC = 5 V; This threshold is a percentage
of VCC; Reported by SPI flags; DVMSENH = 0x6 3.29 3.5 3.66
IZ1, IZ2, IZ3, IZ4 pins; VCC = 5 V; This threshold is a percentage
of VCC; Reported by SPI flags; DVMSENH = 0x7 3.42 3.65 3.81

12
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Diagnostics Monitor Characteristics (continued)
VCC = 4.75 to 5.25 V, TA= –40°C to +125°C (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VMSENL Input integrity check low
threshold
IZ1, IZ2, IZ3, IZ4 pins; VCC = 5 V; This threshold is a percentage
of VCC; Reported by SPI flags; DVMSENHL = 0x0 2.27 2.4 2.52
V
IZ1, IZ2, IZ3, IZ4 pins; VCC = 5 V; This threshold is a percentage
of VCC; Reported by SPI flags; DVMSENHL = 0x1 2.12 2.25 2.37
IZ1, IZ2, IZ3, IZ4 pins; VCC = 5 V; This threshold is a percentage
of VCC; Reported by SPI flags; DVMSENHL = 0x2 1.98 2.1 2.21
IZ1, IZ2, IZ3, IZ4 pins; VCC = 5 V; This threshold is a percentage
of VCC; Reported by SPI flags; DVMSENHL = 0x3 1.84 1.95 2.06
IZ1, IZ2, IZ3, IZ4 pins; VCC = 5 V; This threshold is a percentage
of VCC; Reported by SPI flags; DVMSENHL = 0x4 1.7 1.8 1.9
IZ1, IZ2, IZ3, IZ4 pins; VCC = 5 V; This threshold is a percentage
of VCC; Reported by SPI flags; DVMSENHL = 0x5 1.55 1.65 1.75
IZ1, IZ2, IZ3, IZ4 pins; VCC = 5 V; This threshold is a percentage
of VCC; Reported by SPI flags; DVMSENHL = 0x6 1.41 1.50 1.6
IZ1, IZ2, IZ3, IZ4 pins; VCC = 5 V; This threshold is a percentage
of VCC; Reported by SPI flags; DVMSENHL = 0x7 1.26 1.35 1.44
tSENHL Input integrity check deglitch
time 4.2 5.2 6.2 µs
DIGITAL TRACKING LOOP
VLERRH Tracking-loop error signal high
threshold Reported by SPI flag; SPI programmable 0.1 0.8 V
VLERRL Tracking-loop error signal low
threshold Reported by SPI flag; SPI programmable –0.8 -0.1 V
tLERR Tracking-loop error window SPI programmable using TRDHL bits; AMODE = H 2 8 ms
SPI programmable using TRDHL bits; AMODE = L 90 180 ms
THERMAL PROTECTION
TSDEXC_WR Exciter thermal warning SPI flag 125 155 °C
TSDEXC_SD Exciter thermal shutdown Exciter disabled ; SPI flag 155 175 200 °C
TSDVDD_WR VDD regulator thermal warning SPI flag 125 155 °C
TSDVDD_SD VDD regulator thermal shutdown NPOR asserted 155 175 200 °C
6.9 VDD Regulator Characteristics
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VVDD VDD output voltage 1.69 1.8 1.91 V
IVDD VDD output current range 10 mA
Lr1VDD Line regulation IVDD = 0 to 10 mA; Exciter power-supply enabled 90 110 %VVDD
Lr2VDD Load regulation IVDD = 0 to 10 mA; VCC = 4.5 to 5.5 V 90 110 %VVDD
CVDD VDD external capacity VDD pin 100 nF
(1) Parameter specified by design.
6.10 Digital I/O Characteristics
VCC = 4.75 to 5.25 V; VVIO = 3.3 to 5 V TA= –40°C to +125°C (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
LOGIC OUTPUT
VOH Output-level high logic ILOAD = 3 mA 90 %VVIO
VOL Output-level low logic ILOAD = - 3 mA 10 %VVIO
TODLY_H Transition low-to-high delay time CLOAD = 50 pF(1) 40 ns
TODLY_L Transition high-to-low delay time CLOAD = 50 pF(1) 40 ns
ROPD Internal pulldown resistance VPIN = 5 V 40 100 160 kΩ
LOGIC OUTPUT (OPEN DRAIN)
VOLOD Output-level low logic REXT_PU = 4.7 kΩ400 mv
TODLY_H_OD Transition low-to-high delay time REXT_PU = 4.7 kΩ; CLOAD = 50 pF(1) 200 µs
TODLY_L_OD Transition high-to-low delay time REXT_PU = 4.7 kΩ; CLOAD = 50 pF(1) 1 µs
RPUOD Internal pullup resistance FAULT pin; VPIN = 0 V 40 100 160 kΩ
LOGIC INPUT
VIH High logic-level input threshold 70 %VVIO
VIL Low logic-level input threshold 30 %VVIO

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Digital I/O Characteristics (continued)
VCC = 4.75 to 5.25 V; VVIO = 3.3 to 5 V TA= –40°C to +125°C (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
TIDLY_H Transition low-to-high delay
time(1) 40 ns
TIDLY_L Transition high-to-low delay
time(1) 40 ns
RPD Internal pulldown resistance VPIN = 5 V 40 100 160 kΩ
RPU Internal pullup resistance NCS pin; VPIN= 0 V 40 100 160 kΩ
(1) Parameter specified by design
6.11 Oscillator Characteristics
VCC = 4.75 to 5.25 V, TA= –40°C to +125°C (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
fOSC_E External oscillator frequency 20-MHz XTAL; ECLKSEL = H(1) 20 MHz
fOSC_I Internal oscillator frequency 18.4 20 21.6 MHz
EOSC System-clock out-of-range
threshold NPOR asserted –30% 40%
tPOR Device start-up time From VDD_UV = L(1) 1.5 ms
6.12 Output Data Interface Characteristics
Over operating free-air temperature range, VIN = 4.75 to 5.25 V, TA= –40°C to +125°C (unless otherwise noted).
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
PARALLEL DIGITAL OUTPUT (ORD[11:0])
RATEORD_DA
TA Parallel-data output rate 10 MHz
tORD_DATA Parallel-data output update time 100 ns
EMULATED ENCODER OUTPUT (OUTA, OUTB, OUTZ, OUTU, OUTV, OUTW, OUTU1, OUTV1, OUTW1)
ABZ10BIT_RES OUTA and OUTB resolution in
10-bit mode 256 pulses/rotation
ABZ12BIT_REZ OUTA and OUTB resolution in
12-bit mode 1024 pulses/rotation
ABZOUTZ OUTZ resolution (10-bit mode or
12-bit mode) 1 pulses/rotation
ABZRPM Maximum rotation supported by
emulated encoder mode 200 000 RPM
tABZ Rise and fall times of emulated
encoder outputs 160 200 us
ANALOG OUTPUT MONITOR
RESMON_DAC Analog output DAC resolution 10 Bit
VMON_DAC Analog output-voltage range 0.5 4.5 V
6.13 SPI Interface Timing Requirements
VCC = 4.75 to 5.25 V, TA= –40°C to +125°C (unless otherwise noted) MIN NOM MAX UNIT
fSPI SPI clock (SCLK) frequency VVIO = 3.3 V; CSDO = 50 pF; SPI clock tolerance
= ± 10% 8 MHz
twhigh High time: SCLK logic high time duration 55 ns
twlow Low time: SCLK logic low time duration 55 ns
tsu_cs NCS setup time: Time delay between falling edge of NCS and rising edge of SCLK 55 ns
th_cs Hold time: Time between the falling edge of SCLK and rising edge of NCS 55 ns
tpd_soen Delay time: Time delay from falling edge of NCS to data valid at SDO 55 ns
tpd_sodis Delay time: Time delay from rising edge of NCS to SDO transition to tri-state 55 ns
tsu_si SDI setup time: Setup time of SDI before the falling edge of SCLK 15 ns
th_si Hold time: Time between the falling edge of SCLK to SDI valid 15 ns
tpd_so Propagation delay from rising edge of SCLK to SDO CSDO = 50 pF 45 ns
tw_cs SPI transfer inactive time (time between two transfers) during which NCS must remain high 200 ns

NRESET
nPOR
70 µs
STATE Diagnostics
LBIST
EEPROM Data
Download
Approx. 200 µs
ABIST
Initial Auto
Calibration
Approx. 200 µs
(Reset)
2.3 ms
Diagnostics
5.2 ms
Normal
Boost Reg
Enable
Exciter
Enable
Tracking L
Enable
Normal
ORD
[12:0]
CRC
1.3 µs
100 ms
Wait
Wait
100 ms
Wait
Wait CRC
1.3 µs
2 ms
100 ns
Data Update
Wait
2 ms Auto Calibration
Approx.
2.3 ms
Normal
CRC
1.3 µs Wait
2 ms
100 ms
Wait Auto Calibration
Approx.
2.3 ms
Normal
CRC
1.3 µs Wait
2 ms
100 ms
Wait
Data Update Data Update
. . .
th_cs
SCLK
SDO
NCS
tw_cs
SDI
tpd_sodis
tsu_cs twhigh twlow
tsu_si
tpd_soen tpd_so
th_si
tsu_cs
tsu_si
tpd_soen tpd_so
14
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6.14 Timing Diagrams
Figure 1. SPI Timing Diagram
Figure 2. Power-Up Timing Diagram

Time (ms)
Angle Output (Degrees)
0 2 4 6 8 10 12 14 16 18 20
0
2
4
6
8
10
12
14
16
D005
Time (ms)
Angle Output (Degrees)
0 2 4 6 8 10 12 14 16 18 20
0
50
100
150
200
250
300
350
D006
Time (ms)
Angle Output (Degrees)
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5
0
2
4
6
8
10
12
D003
Time (ms)
Angle Output (Degrees)
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5
0
50
100
150
200
250
300
350
400
D004
Time (ms)
Angle Output (Degrees)
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5
0
2
4
6
8
10
12
D001
Time (ms)
Angle Output (Degrees)
0 2 4 6 8 10 12 14 16 18 20
0
50
100
150
200
250
300
350
D002
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6.15 Typical Characteristics
AMODE = 0 AMODE = 0
Figure 3. 10° Step Response in 10-Bit Mode Figure 4. 180° Step Response in 10-Bit Mode
AMODE = 1 AMODE = 1
Figure 5. 10° Step Response in 10-Bit Mode Figure 6. 180° Step Response in 10-Bit Mode
AMODE = 0 AMODE = 0
Figure 7. 10° Step Response in 12-Bit Mode Figure 8. 180° Step Response in 12-Bit Mode

Time (ms)
Angle Output (Degrees)
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5
0
2
4
6
8
10
12
D007
Time (ms)
Angle output (Degrees)
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5
0
50
100
150
200
250
300
350
D008
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Typical Characteristics (continued)
AMODE = 1 AMODE = 1
Figure 9. 10° Step Response in 12-Bit Mode Figure 10. 180° Step Response in 12-Bit Mode

Analog Front End
Exciter Power Supply(1)
(Boost Regulator)
VDD
LDO Regulator
Exciter Amplifier
VCCSW
VSW
VEXTS
VEXT
PGND
NCS
SCLK
SDI
SDO
Digital core
Digital I/O
Digital Tracking
Loop
NPOR Clock Monitor
Diagnostics
Diagnostics
Temp
Sense
Exciter Signal
Generator
Fault Reporting
Registers
State Machine
SPI IF
V-ERR
+ +
OE1 OE2
VDD
VCC QVCC
ORD11
ORD10
ORD9 ORD8 ORD6 ORD7 ORD5 ORD4 ORD2 ORD3 ORD0 ORD1 OUTA
OUTZ
OUTB
DAC
ORS
PRD
16
FAULT FAULTRES XOUT XIN
AMODE
OMODE
VA0
VA1
INHB
5
VIO
IZ1
IZ3
IZ2
IZ4
+
+
OSIN
OCOS
IE1
IE2
+
COMAFE
AOUT
DAC
BMODE0
External Oscillator
ECLKSEL
QGND
DGND
PBKG
COMAFE
NRESET
Logic
Diag.
Diagnostics
Temp
Sense
Diagnostics Bus
20-MHz Internal Oscillator
ORDCLK
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7 Detailed Description
7.1 Overview
The PGA411-Q1 device is a resolver sensor interface device with an integrated exciter amplifier and boost power
supply. The PGA411-Q1 device is capable of running with either 10-bit or 12-bit resolution. The internal boost
power supply for the exciter can be used from 10 V to 17 V which enables the exciter output to be adjustable
between 4-VRMS or 7-VRMS mode. The integrated exciter amplifier enables up to 145 mA of excitation current with
an exciter frequency from 10 kHz to 20 kHz.
The analog front-end (AFE) along with the digital tracking loop performs the resolver-to-digital-converter
functionality. The AFE uses the cosine and sine signals and amplifies them by differential input amplifiers with
programmable gain. The tracking loop is based on a Type-II Pi-controller architecture which enables the device
to support up to 200 000 RPM in 10-bit mode.
Each block inside the device has dedicated diagnostics for fault coverage. All of the fault conditions are reported
out through the SPI registers with a dedicated FAULT pin that can be used to interrupt a microcontroller unit
(MCU) when a fault is detected in the system. The PGA411-Q1 device has programmable features that allow
system flexibility when working with a wide range of resolver sensors.
7.2 Functional Block Diagram

PWM
Control
VCCSW
VSW
PGND
VEXTS
+
PGND
RSENSE
Diagnostics Output
Level Adjust
To Digital
±
+
±
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7.3 Feature Description
7.3.1 Exciter Amplifier Power Supply
The exciter power supply implemented in the PGA411-Q1 device is supplied by the VCCSW pin for the internal
driver logic and error correction and the VSW pin as a switch pin for creating a higher voltage rail. Both of these
pins can be supplied by the same power supply when connected to the main device supply, VCC, or these can be
connected to a separate power source. A stabilization loop feedback pin, VEXTS, is implemented and should be
connected to the output of the exciter power supply. Figure 11 shows the block diagram of the exciter power
supply (boost regulator).
Figure 11. Exciter Power-Supply Block Diagram
The switching frequency for the exciter power supply is 414 kHz (±10% spread spectrum) while the output
voltage selection occurs by setting the MODEVEXT bits in the DEV_CONFIG1 register. Regardless of the exciter
output mode (4 VRMS or 7 VRMS), the exciter power supply can be adjusted for an output voltage from 10 V to 17
V. If the application requires a typical boost current above 100 mA, the nBoost_FF bit in DEV_OVUV4 should be
set. This bit affects the boost regulator feedback control.
The VCCSW input voltage that is needed depends on the output voltage setting and current requirements of the
resolver sensor being used. If the sensor requires high current and high voltage, then VCCSW may need to be
higher than the typical PGA411-Q1 supply voltage of 5 V.
The exciter power-supply diagnostics are split between the diagnostics monitor and internal exciter power-supply
diagnostics.
The diagnostics monitor inside the exciter power supply tracks the following:
• The output overvoltage fault reported by the FBSTOV flag in the DEV_STAT4 register. During this fault the
device proceeds to the FAULT state. The typical value for setting the FBSTOV fault is 115% of the nominal
selected output voltage.
• The power supply temperature. See the Thermal Protection section for more information.
The internal exciter power-supply diagnostics include the following:
Critical overvoltage – Disables the exciter power supply. The typical threshold value for this fault is when the
output voltage is more than 175% of the nominal selected output voltage.

DAC
9-Bit Balanced
Sine Generator
From
Digital
+
+
EXTOUT_GL
Variable Gain Preamplifier
+
ORS
EXTMODE + EXTOUT
Power Amplifier
A = 1
OE1
OE2
ORS Buffer AMP
To Digital Diagnostics
±
±
±
+
±
+
±
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Feature Description (continued)
Critical undervoltage – Disables the exciter power supply. The typical threshold value for this fault is when the
output voltage is less than 50% of the nominal selected output voltage.
Output current-limit lower threshold at 600 mA – Immediately turns off the switch (low-side FET) for the
remaining time of the current switch cycle. After the current cycle expires, the switch continues
normal operation.
Output current-limit upper threshold at 2000 mA – Immediately turns off the switch (low-side FET) for three
consecutive switch cycles before resuming normal operation. If the condition persists and is still
present after three retries the switch is disabled for 2 ms before resuming normal operation.
Both current limits are masked for seven switching cycles when the exciter power supply is initially enabled.
All diagnostics are passed through a 5-µs deglitch.
7.3.2 Exciter Signal Generation
The PGA411-Q1 exciter signal path is optimized for driving highly inductive loads such as the exciter coil of the
resolver sensor. The signal path is designed for 4-VRMS or 7-VRMS operation selected by the EXTMODE bits in
the DEV_PHASE_CFG register. These bits are also the main enable control for the full exciter signal generation
path. When the EXTMODE bit is set to 00 or 11, the exciter signal path is disabled causing the PGA411-Q1
device to signal a FAULT condition. The exciter preamplifier offers the ability to adjust the exciter output signal to
compensate for the variations of the transfer ratio for the resolver sensor. Furthermore, the exciter output pins
OE1 and OE2 are protected against undervoltage, overvoltage, mutual short, short to battery, short to GND, and
overcurrent. Other diagnostics include exciter signal monitoring in the AFE and overtemperature protection. See
the Detailed Design Procedure section for more information on the calculation of the output voltage for the exciter
signal path.
Figure 12 shows the exciter-signal generation circuit which consists of three major blocks.
Figure 12. Exciter Signal Generation Circuit
7.3.2.1 Exciter Signal Generator
The exciter signal is generated by reading a digital sine wave stored in the device memory and then passed
through a 9-bit differentially balanced DAC for generating a differential analog-exciter signal. The exciter
frequency signal is from 10 kHz to 20 kHz and selected by the SELFEXT bits in the DEV_CONFIG1 register. See
the Clock Generation section for more information on the exciter clocking.

0t
VORS
VDAC × EXTOUT_GL
Vmax
4.5
0.5
2.5
Vmin
VCOMAFE
EXTOUT
20
PGA411-Q1
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Product Folder Links: PGA411-Q1
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Feature Description (continued)
7.3.2.2 Exciter Signal Preamplifier
The differentially balanced preamplifier conditions the exciter signal to the appropriate level for further output
amplification. In the preamplifier block, the amplification level of the exciter signal can be adjusted while the
common-mode voltage is defined by the voltage at the COMAFE pin (typically 2.5 V). The preamplifier gain is
selectable though the EXTOUT_GL bits in the DEV_OVUV1 register and affects both the preamplifier ORS
output and the power amplifier outputs as shown in Figure 13. The preamplifier can be common-mode offset
adjusted by the EXTOUT bits in the DEV_PHASE_CFG register between the limits of 0.5 V to 2 V expressed as
foot-room voltage.
Figure 13. Exciter Preamplifier Gain
For signal monitoring or different exciter topologies, the output signal from the exciter preamplifier is available at
the ORS pin of the PGA411-Q1 device. The output voltage is referenced to the voltage on the COMAFE pin. An
external power amplifier such as the ALM2402-Q1 can be connected to the ORS pin to drive very high current
sensors.
The ORS output of the exciter preamplifier is controlled by the XEXT_AMP bit in the DEV_OVUV2 register.
When this bit is set to 1, external amplifier mode is selected which enables the ORS output and disables the
internal output-power amplifier. However the default state of this bit is 0 which means that the ORS output is
disabled and the internal output-power amplifier is enabled.
7.3.2.3 Exciter Output Power Amplifier
The internal output-power amplifier consists of two identical class-AB amplifier units that are independently input
inverted to form a bridge-tied load (BTL) output topology. The exciter coil of the resolver sensor is connected at
the output of the power amplifier (essentially between the OE1 and OE2 pins).
Power to the exciter power amplifier is supplied by the VEXT and PGND pins. The applied voltage should not, in
any case, exceed the maximum rating of these pins.
To avoid output saturation (clipping), the power amplifier can be common-mode offset adjusted by the EXTOUT
bits in the DEV_PHASE_CFG register. Figure 14 shows the common-mode offset, and table X shows the
measured offset for each EXTOUT and EXTMODE setting. Some combinations of EXTOUT, EXTMODE, and
EXTOUT_GL will cause clipping on the OE1 and OE2 outputs.