Texas Instruments TMS320C3x User manual

TMS320C3x
User’s Guide
Literature Number: SPRU031E
2558539-9761 revision L
July 1997
Printed on Recycled Paper

IMPORTANT NOTICE
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applicableatthetimeofsaleinaccordancewithTI’sstandardwarranty.Testingandotherquality
control techniques are utilized to the extent TI deems necessary to support this warranty.
Specific testing of all parameters of each device is not necessarily performed, except those
mandated by government requirements.
Certain applications using semiconductor products may involve potential risks of death,
personal injury, or severe property or environmental damage (“Critical Applications”).
TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, INTENDED, AUTHORIZED, OR
WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT APPLICATIONS, DEVICES
OR SYSTEMS OR OTHER CRITICAL APPLICATIONS.
Inclusion of TI products in such applications is understood to be fully at the risk of the customer.
UseofTIproducts in such applications requires the written approvalofanappropriate TI officer.
Questions concerning potential risk applications should be directed to TI through a local SC
sales office.
In order to minimize risks associated with the customer’s applications, adequate design and
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TI assumes no liability for applications assistance, customer product design, software
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Copyright 1997, Texas Instruments Incorporated

iii
Preface
Read This First
About This Manual
This user’sguide serves as an applications reference book for theTMS320C3x
generationof digital signal processors (DSPs). These include the TMS320C30,
TMS320C31, TMS320LC31, and TMS320C32. Throughout the book, all refer-
ences to ’C3x refer collectively to the ’C30, ’C31, ’LC31 and ’C32.
This book provides information to assist managers and hardware/software
engineers in application development. It includes example code and hard-
ware connections for various applications.
The guide shows how to use the instructions set, the architecture, and the ’C3x
interface. It presents examples for frequently used applications and discusses
more involved examples and applications. It also defines the principles involved
in many applications and gives the corresponding assembly language code for
instructionalpurposesandforimmediateuse.Wheneverthe detailedexplanation
oftheunderlyingtheoryis tooextensivetobeincludedin thismanual,appropriate
references are given for further information.
Notational Conventions
This document uses the following conventions.
- Program listings, program examples, and interactive displays are shown in
a special typeface. Examples use a bold version of the special
typeface for emphasis; interactive displays use a bold version of the
specialtypefacetodistinguishcommandsthatyouenterfromitemsthatthe
systemdisplays(suchasprompts,commandoutput,errormessages,etc.).
Here is a sample program listing:
0011 0005 0001 .field 1, 2
0012 0005 0003 .field 3, 4
0013 0005 0006 .field 6, 3
0014 0006 .even
Here is an example of a system prompt and a command that you might
enter:
C: csr –a /user/ti/simuboard/utilities

Notational Conventions
iv
- In syntax descriptions, the instruction, command, or directive is in bold
typeface and parameters are in an italic typeface . Portions of a syntax that
areinbold must beenteredas shown;portionsofasyntax thatarein
italics
describe the type of information that must be entered. Here is an example
of a directive syntax:
.asect ” section name ”, address
The directive .asect has two parameters, indicated by section name and
address . When you use .asect, the first parameter is an actual section
name, enclosed in double quotes; the second parameter is an address.
- Square brackets ( [and ]) identify an optional parameter. If you use an
optional parameter, you specify the information within the brackets; you
donotenterthebracketsthemselves.Hereisanexampleofaninstruction
that has an optional parameter:
LALK
16-bit constant [, shift]
The LALK instruction has two parameters. The first parameter, 16-bit
constant , is required. The second parameter, shift , is optional. As this syntax
shows, if you use the optional second parameter, you must precede it with a
comma.
Square brackets are also used as part of the pathname specification for
VMS pathnames; in this case, the brackets are actually part of the path-
name (they are not optional).
- Braces( {and} )indicatealist.Thesymbol|(readas or )separatesitems
within the list. Here is an example of a list:
{ * | *+ | *– }
This provides three choices: *, *+, or *–.
Unless the list is enclosed in square brackets, you must choose one item
from the list.
- Some directives can have a varying number of parameters. For example,
the.byte directivecan haveupto 100parameters.The syntaxforthis direc-
tive is:
.byte value
1
[, ... , value
n
]
This syntax shows that .byte has at least one value parameter, but you
may supply additional value parameters, separated by commas.

Information About Cautions / Related Documentation from Texas Instruments
v Read This First
Information About Cautions
This book contains cautions.
This is an example of a caution statement.
A caution statement describes a situation that could potentially
damage your software or equipment.
The information in a caution is provided for your protection. Please read each
caution carefully.
Related Documentation From Texas Instruments
The following books describe the TMS320 floating-point devices and related
support tools. To obtain a copy of any of these TI documents, call the Texas
Instruments Literature Response Center as indicated in the section If You
Need Assistance …on page vi. When ordering, please identify the book by its
title and literature number.
TMS320C3xGeneral PurposeApplications User’sGuide (literaturenumber
SPRU194) provides information to assist you in application development
for the TMS320C3x generation of digital signal processors (DSPs). It
includesexamplecodeand hardwareconnectionsfor variousappliances.
It also defines the principles involved in many applications and gives the
correspondingassemblylanguagecodeforinstructionalpurposesandfor
immediate use.
TMS320C3x/C4x Assembly Language Tools User’s Guide (literature
number SPRU035) describes the assembly language tools (assembler,
linker, and other tools used to develop assembly language code),
assembler directives, macros, common object file format, and symbolic
debugging directives for the ’C3x and ’C4x generations of devices.
TMS320C3x/C4x Optimizing C Compiler User’s Guide (literature number
SPRU034) describes the TMS320 floating-point C compiler. This C compiler
accepts ANSI standard C source code and produces TMS320 assembly
language source code for the ’C3x and ’C4x generations of devices.

Related Documentation from Texas Instruments / References
vi
TMS320C3x C Source Debugger User’s Guide (literature number
SPRU053)tellsyouhowtoinvokethe’C3xemulator,evaluationmodule,
and simulator versions of the C source debugger interface. This book
discusses various aspects of the debugger interface, including window
management, command entry, code execution, data management, and
breakpoints. It also includes a tutorial that introduces basic debugger
functionality.
TMS320 DSP Development Support Reference Guide (literature number
SPRU011)describestheTMS320familyofdigitalsignalprocessorsand
the tools that support these devices. Included are code-generation tools
(compilers, assemblers, linkers, etc.) and system integration and debug
tools(simulators,emulators,evaluationmodules,etc.).Alsocoveredare
available documentation, seminars, the university program, and factory
repair and exchange.
TMS320 Third-Party Support Reference Guide (literature number
SPRU052)alphabeticallylistsover100 third parties that providevarious
products that serve the family of TMS320 digital signal processors. A
myriadofproductsandapplicationsareoffered—softwareandhardware
development tools, speech recognition, image processing, noise can-
cellation, modems, etc.
References
The publications in the following reference list contain useful information
regarding functions, operations, and applications of digital signal processing
(DSP). These books also provide other references to many useful technical
papers.ThereferencelistisorganizedintocategoriesofgeneralDSP,speech,
image processing, and digital control theory and is alphabetized by author.
- General Digital Signal Processing
Antoniou, Andreas, Digital Filters: Analysis and Design . New York, NY:
McGraw-Hill Company, Inc., 1979.
Bateman, A., and Yates, W., Digital Signal Processing Design . Salt Lake
City, Utah: W. H. Freeman and Company, 1990.
Brigham, E. Oran, The Fast Fourier Transform. Englewood Cliffs, NJ:
Prentice-Hall, Inc., 1974.
Burrus,C.S.,andParks,T.W., DFT/FFTandConvolutionAlgorithms. New
York, NY: John Wiley and Sons, Inc., 1984.
Chassaing, R., and Horning, D.,
Digital Signal Processing with the
TMS320C25.
New York, NY: John Wiley and Sons, Inc., 1990.
DigitalSignalProcessingApplicationswiththeTMS320Family,Vol.I. Tex-
as Instruments, 1986; Prentice-Hall, Inc., 1987.

References
vii Read This First
Digital Signal Processing Applications with the TMS320 Family, Vol. III.
Texas Instruments, 1990; Prentice-Hall, Inc., 1990.
Gold, Bernard, and Rader, C.M. ,Digital Processing ofSignals. New York,
NY: McGraw-Hill Company, Inc., 1969.
Hamming, R.W.,
Digital Filters . Englewood Cliffs, NJ: Prentice-Hall, Inc.,
1977.
Hutchins, B., and Parks, T., A Digital Signal Processing Laboratory Using
the TMS320C25
. Englewood Cliffs, NJ: Prentice-Hall, Inc., 1990.
IEEE ASSP DSP Committee (Editor), Programs for Digital Signal Processing.
New York, NY: IEEE Press, 1979.
Jackson, Leland B., Digital Filters and Signal Processing. Hingham, MA:
Kluwer Academic Publishers, 1986.
Jones, D.L., and Parks, T.W.,
A Digital Signal Processing Laboratory Using
the TMS32010. Englewood Cliffs, NJ: Prentice-Hall, Inc., 1987.
Lim, Jae, and Oppenheim, Alan V. (Editors), Advanced Topics in Signal
Processing
. Englewood Cliffs, NJ: Prentice-Hall, Inc., 1988.
Morris, L. Robert, Digital Signal Processing Software. Ottawa, Canada:
Carleton University, 1983.
Oppenheim, Alan V. (Editor),
Applications of Digital Signal Processing.
Englewood Cliffs, NJ: Prentice-Hall, Inc., 1978.
Oppenheim,AlanV.,andSchafer,R.W., DigitalSignalProcessing. Engle-
wood Cliffs, NJ: Prentice-Hall, Inc., 1975.
Oppenheim, Alan V., and Schafer, R.W.,
Discrete-Time Signal Processing.
Englewood Cliffs, NJ: Prentice-Hall, Inc., 1989.
Oppenheim, Alan V., and Willsky, A.N., with Young, I.T., Signals and
Systems. Englewood Cliffs, NJ: Prentice-Hall, Inc., 1983.
Parks,T.W.,andBurrus,C.S.,
DigitalFilterDesign. NewYork,NY:JohnWiley
and Sons, Inc., 1987.
Rabiner,LawrenceR.,andGold,Bernard, TheoryandApplicationofDigital
Signal Processing . Englewood Cliffs, NJ: Prentice-Hall, Inc., 1975.
Treichler,J.R.,Johnson,Jr.,C.R.,andLarimore,M.G.,
TheoryandDesign
of Adaptive Filters . New York, NY: John Wiley and Sons, Inc., 1987.
- Speech
Gray, A.H., and Markel, J.D., Linear Prediction of Speech . New York, NY:
Springer-Verlag, 1976.
Jayant, N.S., and Noll, Peter,
Digital Coding of Waveforms . Englewood
Cliffs, NJ: Prentice-Hall, Inc., 1984.
Papamichalis, Panos, Practical Approaches to Speech Coding. Engle-
wood Cliffs, NJ: Prentice-Hall, Inc., 1987.

References
viii
Parsons, Thomas., Voice and Speech Processing. New York, NY:
McGraw Hill Company, Inc., 1987.
Rabiner, Lawrence R., and Schafer, R.W.,
Digital Processing of Speech
Signals.
Englewood Cliffs, NJ: Prentice-Hall, Inc., 1978.
Shaughnessy, Douglas.,
Speech Communication. Reading, MA: Addison-
Wesley, 1987.
- Image Processing
Andrews, H.C., and Hunt, B.R.,
Digital Image Restoration . Englewood
Cliffs, NJ: Prentice-Hall, Inc., 1977.
Gonzales,RafaelC.,andWintz,Paul, DigitalImageProcessing. Reading,
MA: Addison-Wesley Publishing Company, Inc., 1977.
Pratt,WilliamK.,
DigitalImageProcessing .NewYork,NY:JohnWileyand
Sons, 1978.
- Multirate DSP
Crochiere, R.E., and Rabiner, L.R.,
Multirate Digital Signal Processing .
Englewood Cliffs, NJ: Prentice-Hall, Inc., 1983.
Vaidyanathan,P.P., MultirateSystemsandFilterBanks .EnglewoodCliffs,
NJ: Prentice-Hall, Inc.
- Digital Control Theory
Dote,Y., ServoMotorandMotionControlUsingDigitalSignalProcessors .
Englewood Cliffs, NJ: Prentice-Hall, Inc., 1990.
Jacquot, R., Modern Digital Control Systems. New York, NY: Marcel Dekker,
Inc., 1981.
Katz, P., Digital Control Using Microprocessors . Englewood Cliffs, NJ:
Prentice-Hall, Inc., 1981.
Kuo, B.C.,
Digital Control Systems. New York, NY: Holt, Reinholt and
Winston, Inc., 1980.
Moroney,P., IssuesintheImplementationofDigitalFeedbackCompensa-
tors. Cambridge, MA: The MIT Press, 1983.
Phillips, C., and Nagle, H., Digital Control System Analysis and Design.
Englewood Cliffs, NJ: Prentice-Hall, Inc., 1984.
- Adaptive Signal Processing
Haykin, S., Adaptive Filter Theory. Englewood Cliffs, NJ: Prentice-Hall,
Inc., 1991.
Widrow, B., and Stearns, S.D. Adaptive Signal Processing. Englewood
Cliffs, NJ: Prentice-Hall, Inc., 1985.

References
ix Read This First
- Array Signal Processing
Haykin,S.,Justice,J.H.,Owsley,N.L.,Yen,J.L.,andKak,A.C. ArraySignal
Processing. Englewood Cliffs, NJ: Prentice-Hall, Inc., 1985.
Hudson, J.E.
Adaptive Array Principles. New York, NY: John Wiley and
Sons, 1981.
Monzingo,R.A., and Miller,J.W. Introduction to Adaptive Arrays. NewYork,
NY: John Wiley and Sons, 1980.

If You Need Assistance
x
If You Need Assistance . . .
- World-Wide Web Sites
TI Online http://www.ti.com
Semiconductor Product Information Center (PIC) http://www.ti.com/sc/docs/pic/home.htm
DSP Solutions http://www.ti.com/dsps
320 Hotline On-line t http://www.ti.com/sc/docs/dsps/support.htm
Microcontroller Home Page http://www.ti.com/sc/micro
Networking Home Page http://www.ti.com/sc/docs/network/nbuhomex.htm
- North America, South America, Central America
Product Information Center (PIC) [phone]
TI Literature Response Center U.S.A. [phone]
Software Registration/Upgrades [phone] Fax: [phone]
U.S.A. Factory Repair/Hardware Upgrades [phone]
U.S. Technical Training Organization [phone]
Microcontroller Hotline [phone] Fax: [phone] Email: [e-mail]
Microcontroller Modem BBS [phone] 8-N-1
DSP Hotline [phone] Fax: [phone] Email: [email protected]
DSP Modem BBS [phone]
DSP Internet BBS via anonymous ftp to ftp://ftp.ti.com/pub/tms320bbs
Networking Hotline Fax: [phone]
Email: [email protected]
- Europe, Middle East, Africa
European Product Information Center (EPIC) Hotlines:
Multi-Language Support [phone] Fax: [phone] Email: [email protected]
Deutsch [phone] or [phone]
English [phone]
Francais [phone]
Italiano [phone]
EPIC Modem BBS [phone]
European Factory Repair [phone]
Europe Customer Training Helpline Fax: [phone]
- Asia-Pacific
Literature Response Center [phone] Fax: [phone]
Hong Kong DSP Hotline [phone] Fax: [phone]
Korea DSP Hotline [phone] Fax: [phone]
Korea DSP Modem BBS [phone]
Singapore DSP Hotline Fax: [phone]
Taiwan DSP Hotline [phone] Fax: [phone]
Taiwan DSP Modem BBS [phone]
Taiwan DSP Internet BBS via anonymous ftp to ftp://dsp.ee.tit.edu.tw/pub/TI/
- Japan
Product Information Center +0120-81-0026 (in Japan) Fax: [phone] (in Japan)
+03-3457-0972 or (INTL) 813-3457-0972 Fax: [phone] or (INTL) 813-3457-1259
DSP Hotline [phone] or (INTL) 813-3769-8735 Fax: [phone] or (INTL) 813-3457-7071
DSP BBS via Nifty-Serve Type “Go TIASP”

If You Need Assistance / Trademarks
xi Read This First
- Documentation
Whenmakingsuggestions orreportingerrors indocumentation,please includethefollowing informationthatis onthetitle
page: the full title of the book, the publication date, and the literature number.
Mail: Texas Instruments Incorporated Email: [email protected]
Technical Documentation Services, MS 702
P.O. Box 1443
Houston, Texas 77251-1443
Note: When calling a Literature Response Center to order documentation, please specify the literature number of the
book.
Trademarks
ABEL is a trademark of DATA I/O.
CodeView, MS, MS-DOS, MS-Windows, and Presentation Manager are registered trademarks of
Microsoft Corporation.
DEC, Digital DX, Ultrix, VAX, and VMS are trademarks of Digital Equipment Corporation.
HPGL is registered trademark of Hewlett Packard Company.
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SPARC, Sun 3, Sun 4, Sun Workstation, SunView, and SunWindows are trademark of SPARC International,
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UNIX is a registered trademark in the United States and other countries, licensed exclusively through
X/Open Company Limited.

Contents
xiii
Contents
1 Introduction 1-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
A general description of the TMS320C30, TMS320C31, and TMS320C32, their key features,
and typical applications.
1.1 TMS320C3x Devices 1-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.1.1 TMS320C3x Key Specifications 1-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.1.2 TMS320C30 1-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.1.3 TMS320C31 and TMS320LC31 1-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.1.4 TMS320C32 1-4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.2 Typical Applications 1-7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2 Architectural Overview 2-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Functional block diagram, ’C3x design description, hardware components, device operation,
and instruction set summary.
2.1 Overview 2-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.2 Central Processing Unit (CPU) 2-6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.2.1 Floating-Point/Integer Multiplier 2-8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.2.2 Arithmetic Logic Unit (ALU) and Internal Buses 2-8. . . . . . . . . . . . . . . . . . . . . . . . . .
2.2.3 Auxiliary Register Arithmetic Units (ARAUs) 2-8. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.3 CPU Primary Register File 2-9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.4 Other Registers 2-12. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.5 Memory Organization 2-13. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.5.1 RAM, ROM, and Cache 2-13. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.5.2 Memory Addressing Modes 2-17. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.6 Internal Bus Operation 2-18. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.7 External Memory Interface 2-19. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.7.1 TMS320C32 16- and 32-Bit Program Memory 2-19. . . . . . . . . . . . . . . . . . . . . . . . . .
2.7.2 TMS320C32 8-, 16-, and 32-Bit Data Memory 2-20. . . . . . . . . . . . . . . . . . . . . . . . . .
2.8 Interrupts 2-21. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.9 Peripherals 2-22. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.9.1 Timers 2-23. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.9.2 Serial Ports 2-23. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.10 Direct Memory Access (DMA) 2-24. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.11 TMS320C30, TMS320C31, and TMS320C32 Differences 2-26. . . . . . . . . . . . . . . . . . . . . . .

Contents
xiv
3 CPU Registers 3-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Description of the registers in the CPU register file.
3.1 CPU Multiport Register File 3-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.1.1 Extended-Precision Registers (R7–R0) 3-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.1.2 Auxiliary Registers (AR7–AR0) 3-4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.1.3 Data-Page Pointer (DP) 3-4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.1.4 Index Registers (IR0, IR1) 3-4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.1.5 Block Size (BK) Register 3-4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.1.6 System-Stack Pointer (SP) 3-4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.1.7 Status (ST) Register 3-5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.1.8 CPU/DMA Interrupt-Enable (IE) Register 3-9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.1.9 CPU Interrupt Flag (IF) Register 3-11. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.1.10 I/O Flag (IOF) Register 3-16. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.1.11 Repeat-Counter (RC) and Block-Repeat (RS, RE) Registers 3-17. . . . . . . . . . . . .
3.2 Other Registers 3-18. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.2.1 Program-Counter (PC) Register 3-18. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.2.2 Instruction Register (IR) 3-18. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.3 Reserved Bits and Compatibility 3-19. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4 Memory and the Instruction Cache 4-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Description of memory maps with explanation of instruction cache architecture, algorithm,
and control bits.
4.1 Memory 4-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.1.1 Memory Maps 4-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.1.2 Peripheral Bus Memory Map 4-9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.2 Reset/Interrupt/Trap Vector Map 4-14. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.3 Instruction Cache 4-19. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.3.1 Instruction-Cache Architecture 4-19. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.3.2 Instruction-Cache Algorithm 4-21. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.3.3 Cache Control Bits 4-22. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5 Data Formats and Floating-Point Operation 5-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Description of signed and unsigned integer and floating-point formats. Discussion of floating-
point multiplication, addition, subtraction, normalization, rounding, and conversions.
5.1 Integer Formats 5-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.1.1 Short-Integer Format 5-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.1.2 Single-Precision Integer Format 5-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.2 Unsigned-Integer Formats 5-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.2.1 Short Unsigned-Integer Format 5-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.2.2 Single-Precision Unsigned-Integer Format 5-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.3 Floating-Point Formats 5-4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.3.1 Short Floating-Point Format 5-5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.3.2 TMS320C32 Short Floating-Point Format for External 16-Bit Data 5-6. . . . . . . . .

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5.3.3 Single-Precision Floating-Point Format 5-7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.3.4 Extended-Precision Floating-Point Format 5-8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.3.5 Determining the Decimal Equivalent of a TMS320C3x
Floating-Point Format 5-9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.3.6 Conversion Between Floating-Point Formats 5-12. . . . . . . . . . . . . . . . . . . . . . . . . . .
5.4 Floating-Point Conversion (IEEE Std. 754) 5-14. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.4.1 Converting IEEE Format to 2s-Complement TMS320C3x
Floating-Point Format 5-15. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.4.2 Converting 2s-Complement TMS320C3x Floating-Point Format
to IEEE Format 5-21. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.5 Floating-Point Multiplication 5-26. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.6 Floating-Point Addition and Subtraction 5-32. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.7 Normalization Using the NORM Instruction 5-37. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.8 Rounding (RND Instruction) 5-39. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.9 Floating-Point to Integer Conversion (FIX Instruction) 5-41. . . . . . . . . . . . . . . . . . . . . . . . . . .
5.10 Integer to Floating-Point Conversion (FLOAT Instruction) 5-43. . . . . . . . . . . . . . . . . . . . . . .
5.11 Fast Logarithms on a Floating-Point Device 5-44. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.11.1 Example of Fast Logarithm on a Floating-Point Device 5-45. . . . . . . . . . . . . . . . . .
5.11.2 Points to Consider 5-47. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6 Addressing Modes 6-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operation, encoding, and implementation of addressing modes; format descriptions;
system stack management.
6.1 Addressing Types 6-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.2 Register Addressing 6-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.3 Direct Addressing 6-4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.4 Indirect Addressing 6-5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.5 Immediate Addressing 6-18. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.6 PC-Relative Addressing 6-19. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.7 Circular Addressing 6-21. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.8 Bit-Reversed Addressing 6-26. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.9 Aligning Buffers With the TMS320 Floating-Point DSP Assembly Language Tools 6-28. . . .
6.10 System and User Stack Management 6-29. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.10.1 System-Stack Pointer 6-29. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.10.2 Stacks 6-30. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.10.3 Queues 6-31. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7 Program Flow Control 7-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Software control of program flow with repeat modes and branching; interlocked operations;
reset and interrupts.
7.1 Repeat Modes 7-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.1.1 Repeat-Mode Control Bits 7-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.1.2 Repeat-Mode Operation 7-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.1.3 RPTB Instruction 7-4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Contents
xvi
7.1.4 RPTS Instruction 7-5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.1.5 Repeat-Mode Restrictions 7-6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.1.6 RC Register Value After Repeat Mode Completes 7-7. . . . . . . . . . . . . . . . . . . . . . .
7.1.7 Nested Block Repeats 7-8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.2 Delayed Branches 7-9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.3 Calls, Traps, and Returns 7-11. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.4 Interlocked Operations 7-13. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.4.1 Interrupting Interlocked Operations 7-15. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.4.2 Using Interlocked Operations 7-15. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.4.3 Pipeline Effects of Interlocked Instructions 7-19. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.5 Reset Operation 7-21. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.6 Interrupts 7-26. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.6.1 TMS320C30 and TMS320C31 Interrupt Vector Table 7-26. . . . . . . . . . . . . . . . . . . .
7.6.2 TMS320C32 Interrupt Vector Table 7-29. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.6.3 Interrupt Prioritization 7-31. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.6.4 CPU Interrupt Control Bits 7-32. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.6.5 Interrupt Flag Register Behavior 7-32. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.6.6 Interrupt Processing 7-33. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.6.7 CPU Interrupt Latency 7-35. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.6.8 External Interrupts 7-36. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.7 DMA Interrupts 7-38. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.7.1 DMA Interrupt Control Bits 7-38. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.7.2 DMA Interrupt Processing 7-39. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.7.3 CPU/DMA Interaction 7-40. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.7.4 TMS320C3x Interrupt Considerations 7-41. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.7.5 TMS320C30 Interrupt Considerations 7-44. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.8 Traps 7-47. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.8.1 Initialization of Traps and Interrupts 7-47. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.8.2 Operation of Traps 7-47. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.9 Power Management Modes 7-49. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.9.1 IDLE2 Power-Down Mode 7-49. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.9.2 LOPOWER 7-51. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8 Pipeline Operation 8-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Discussion of the pipeline of operations on the TMS320C3x
8.1 Pipeline Structure 8-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8.2 Pipeline Conflicts 8-4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8.2.1 Branch Conflicts 8-4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8.2.2 Register Conflicts 8-6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8.2.3 Memory Conflicts 8-8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8.3 Resolving Register Conflicts 8-19. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8.4 Memory Access for Maximum Performance 8-22. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8.5 Clocking Memory Accesses 8-24. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8.5.1 Program Fetches 8-24. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8.5.2 Data Loads and Stores 8-24. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Contents
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9 TMS320C30 and TMS320C31 External-Memory Interface 9-1. . . . . . . . . . . . . . . . . . . . . . . . . . . .
Descriptionofprimaryandexpansioninterfacesforthe’C30and’C31;externalinterfacetiming
diagrams; programmable wait-states and bank switching.
9.1 Overview 9-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
9.2 Memory Interface Signals 9-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
9.2.1 TMS320C30 Memory Interface Signals 9-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
9.2.2 TMS320C31 Memory Interface Signals 9-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
9.3 Memory Interface Control Registers 9-7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
9.3.1 Primary-Bus Control Register 9-7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
9.3.2 Expansion-Bus Control Register 9-9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
9.4 Programmable Wait States 9-10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
9.5 Programmable Bank Switching 9-12. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
9.6 External Memory Interface Timing 9-15. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
9.6.1 Primary-Bus Cycles 9-15. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
9.6.2 Expansion-Bus I/O Cycles 9-21. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
9.6.3 Hold Cycles 9-37. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
10 TMS320C32 Enhanced External Memory Interface 10-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Description of primary and expansion interfaces for the ’C32; external interface timing
diagrams; programmable wait-states and bank switching.
10.1 TMS320C32 Memory Features 10-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
10.2 TMS320C32 Memory Overview 10-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
10.2.1 External Memory Interface Overview 10-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
10.2.2 Program Memory Access 10-4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
10.2.3 Data Memory Access 10-5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
10.3 Configuration 10-7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
10.3.1 External Interface Control Registers 10-7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
10.3.2 Using Physical Memory Width and Data-Type Size Fields 10-13. . . . . . . . . . . . .
10.4 Programmable Wait States 10-15. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
10.5 Programmable Bank Switching 10-17. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
10.6 32-Bit-Wide Memory Interface 10-20. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
10.7 16-Bit-Wide Memory Interface 10-26. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
10.8 8-Bit-Wide Memory Interface 10-32. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
10.9 External Ready Timing Improvement 10-38. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
10.10 Bus Timing 10-39. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
10.10.1 STRB0 and STRB1 Bus Cycles 10-39. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
10.10.2 IOSTRB Bus Cycles 10-42. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
10.10.3 Inactive Bus States 10-51. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
11 Using the TMS320C31 and TMS320C32 Boot Loaders 11-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Description of the boot loader operations for the ’C31 and ’C32.
11.1 TMS320C31 Boot Loader 11-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
11.1.1 TMS320C31 Boot-Loader Description 11-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
11.1.2 TMS320C31 Boot-Loader Mode Selection 11-2. . . . . . . . . . . . . . . . . . . . . . . . . . . .

Contents
xviii
11.1.3 TMS320C31 Boot-Loading Sequence 11-4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
11.1.4 TMS320C31 Boot Data Stream Structure 11-7. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
11.1.5 Interrupt and Trap-Vector Mapping 11-11. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
11.1.6 TMS320C31 Boot-Loader Precautions 11-13. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
11.2 TMS320C32 Boot Loader 11-14. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
11.2.1 TMS320C32 Boot-Loader Description 11-14. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
11.2.2 TMS320C32 Boot-Loader Mode Selection 11-14. . . . . . . . . . . . . . . . . . . . . . . . . . .
11.2.3 TMS320C32 Boot-Loading Sequence 11-15. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
11.2.4 TMS320C32 Boot Data Stream Structure 11-20. . . . . . . . . . . . . . . . . . . . . . . . . . . .
11.2.5 Boot-Loader Hardware Interface 11-23. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
11.2.6 TMS320C32 Boot-Loader Precautions 11-23. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
12 Peripherals 12-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Description of the DMA controller, timers, and serial ports.
12.1 Timers 12-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
12.1.1 Timer Pins 12-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
12.1.2 Timer Control Registers 12-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
12.1.3 Timer Global-Control Register 12-4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
12.1.4 Timer-Period and Counter Registers 12-7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
12.1.5 Timer Pulse Generation 12-7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
12.1.6 Timer Operation Modes 12-10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
12.1.7 Using TCLKx as General-Purpose I/O Pins 12-12. . . . . . . . . . . . . . . . . . . . . . . . . .
12.1.8 Timer Interrupts 12-13. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
12.1.9 Timer Initialization/Reconfiguration 12-13. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
12.2 Serial Ports 12-15. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
12.2.1 Serial-Port Global-Control Register 12-17. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
12.2.2 FSX/DX/CLKX Port-Control Register 12-22. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
12.2.3 FSR/DR/CLKR Port-Control Register 12-23. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
12.2.4 Receive/Transmit Timer-Control Register 12-25. . . . . . . . . . . . . . . . . . . . . . . . . . . .
12.2.5 Receive/Transmit Timer-Counter Register 12-27. . . . . . . . . . . . . . . . . . . . . . . . . . .
12.2.6 Receive/Transmit Timer-Period Register 12-28. . . . . . . . . . . . . . . . . . . . . . . . . . . .
12.2.7 Data-Transmit Register 12-28. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
12.2.8 Data-Receive Register 12-28. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
12.2.9 Serial-Port Operation Configurations 12-29. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
12.2.10 Serial-Port Timing 12-31. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
12.2.11 Serial-Port Interrupt Sources 12-34. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
12.2.12 Serial-Port Functional Operation 12-35. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
12.2.13 Serial-Port Initialization/Reconfiguration 12-41. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
12.2.14 TMS320C3x Serial-Port Interface Examples 12-41. . . . . . . . . . . . . . . . . . . . . . . . .
12.3 DMA Controller 12-48. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
12.3.1 DMA Functional Description 12-48. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
12.3.2 DMA Basic Operation 12-50. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
12.3.3 DMA Registers 12-51. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
12.3.4 CPU/DMA Interrupt-Enable Register 12-59. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Contents
xix Contents
12.3.5 TMS320C32 DMA Internal Priority Schemes 12-62. . . . . . . . . . . . . . . . . . . . . . . . .
12.3.6 CPU and DMA Controller Arbitration 12-63. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
12.3.7 DMA and Interrupts 12-64. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
12.3.8 DMA Memory Transfer Timing 12-67. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
12.3.9 DMA Initialization/Reconfiguration 12-73. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
12.3.10 Hints for DMA Programming 12-73. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
12.3.11 DMA Programming Examples 12-74. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
13 Assembly Language Instructions 13-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Functional listing of instructions. Condition codes defined. Alphabetized individual instruction
set with examples.
13.1 Instruction Set 13-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
13.1.1 Load and Store Instructions 13-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
13.1.2 2-Operand Instructions 13-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
13.1.3 3-Operand Instructions 13-4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
13.1.4 Program-Control Instructions 13-4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
13.1.5 Low-Power Control Instructions 13-5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
13.1.6 Interlocked-Operations Instructions 13-5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
13.1.7 Parallel-Operations Instructions 13-6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
13.1.8 Illegal Instructions 13-9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
13.2 Instruction Set Summary 13-10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
13.3 Parallel Instruction Set Summary 13-17. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
13.4 Group Addressing Mode Instruction Encoding 13-20. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
13.4.1 General Addressing Modes 13-20. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
13.4.2 3-Operand Addressing Modes 13-24. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
13.4.3 Parallel Addressing Modes 13-25. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
13.4.4 Conditional-Branch Addressing Modes 13-27. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
13.5 Condition Codes and Flags 13-28. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
13.6 Individual Instructions 13-32. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
13.6.1 Symbols and Abbreviations 13-32. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
13.6.2 Optional Assembler Syntax 13-34. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
13.6.3 Individual Instruction Descriptions 13-37. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
A Instruction Opcodes A-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
List of the opcode fields for the TMS320C3x instructions.
B TMS320C31 Boot Loader Source Code B-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
C TMS320C32 Boot Loader Source Code C-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
C.1 Boot-Loader Source Code Description C-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
C.2 Boot-Loader Source Code Listing C-4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
D Glossary D-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Figures
xx
Figures
1–1 TMS320C3x Devices Block Diagram 1-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2–1 TMS320C30 Block Diagram 2-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2–2 TMS320C31 Block Diagram 2-4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2–3 TMS320C32 Block Diagram 2-5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2–4 Central Processing Unit (CPU) 2-7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2–5 Memory Organization of the TMS320C30 2-14. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2–6 Memory Organization of the TMS320C31 2-15. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2–7 Memory Organization of the TMS320C32 2-16. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2–8 TMS320C32-Supported Data Types and Sizes and External Memory Widths 2-20. . . . . . . .
2–9 Peripheral Modules 2-22. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2–10 DMA Controller 2-25. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3–1 Extended-Precision Register Floating-Point Format 3-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3–2 Extended-Precision Register Integer Format 3-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3–3 Status Register (TMS320C30 andTMS320C31) 3-5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3–4 Status Register (TMS320C32 Only) 3-5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3–5 CPU/DMA Interrupt-Enable (IE) Register (TMS320C30 and TMS320C31) 3-9. . . . . . . . . . .
3–6 CPU/DMA Interrupt-Enable (IE) Register (TMS320C32) 3-9. . . . . . . . . . . . . . . . . . . . . . . . . . . .
3–7 TMS320C30 CPU Interrupt Flag (IF) Register 3-12. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3–8 TMS320C31 CPU Interrupt Flag (IF) Register 3-12. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3–9 TMS320C32 CPU Interrupt Flag (IF) Register 3-12. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3–10 Effective Base Address of the Interrupt-Trap Vector Table 3-14. . . . . . . . . . . . . . . . . . . . . . . . .
3–11 Interrupt and Trap Vector Locations 3-15. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3–12 I/O Flag (IOF) Register 3-16. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4–1 TMS320C30 Memory Maps 4-4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4–2 TMS320C31 Memory Maps 4-6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4–3 TMS320C32 Memory Maps 4-8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4–4 TMS320C30 Peripheral Bus Memory-Mapped Registers 4-10. . . . . . . . . . . . . . . . . . . . . . . . . .
4–5 TMS320C31 Peripheral Bus Memory-Mapped Registers 4-11. . . . . . . . . . . . . . . . . . . . . . . . . .
4–6 TMS320C32 Peripheral Bus Memory-Mapped Registers 4-13. . . . . . . . . . . . . . . . . . . . . . . . . .
4–7 Reset, Interrupt, and Trap Vector Locations for the TMS320C30
Microprocessor Mode 4-15. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4–8 Reset, Interrupt, and Trap Vector Locations for theTMS320C31
Microprocessor Mode 4-16. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4–9 Interrupt and Trap Branch Instructions for the TMS320C31 Microcomputer Mode 4-17. . . . .
4–10 Interrupt and Trap Vector Locations for TMS320C32 4-18. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4–11 Address Partitioning for Cache Control Algorithm 4-19. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4–12 Instruction-Cache Architecture 4-20. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Figures
xxi Contents
5–1 Short-Integer Format and Sign-Extension of Short Integers 5-2. . . . . . . . . . . . . . . . . . . . . . . . .
5–2 Single-Precision Integer Format 5-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5–3 Short Unsigned-Integer Format and Zero Fill 5-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5–4 Single-Precision Unsigned-Integer Format 5-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5–5 General Floating-Point Format 5-4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5–6 Short Floating-Point Format 5-5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5–7 TMS320C32 Short Floating-Point Format for External 16-Bit Data 5-6. . . . . . . . . . . . . . . . . . .
5–8 Single-Precision Floating-Point Format 5-7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5–9 Extended-Precision Floating-Point Format 5-8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5–10 Converting from Short Floating-Point Format to Single-Precision
Floating-Point Format 5-12. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5–11 Converting from Short Floating-Point Format to Extended-Precision
Floating-Point Format 5-12. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5–12 Converting from Single-Precision Floating-Point Format to Extended-Precision
Floating-Point Format 5-13. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5–13 Converting from Extended-Precision Floating-Point Format to Single-Precision
Floating-Point Format 5-13. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5–14 IEEE Single-Precision Std. 754 Floating-Point Format 5-14. . . . . . . . . . . . . . . . . . . . . . . . . . . .
5–15 TMS320C3x Single-Precision 2s-Complement Floating-Point Format 5-15. . . . . . . . . . . . . . .
5–16 Flowchart for Floating-Point Multiplication 5-28. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5–17 Flowchart for Floating-Point Addition 5-33. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5–18 Flowchart for NORM Instruction Operation 5-38. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5–19 Flowchart for Floating-Point Rounding by the RND Instruction 5-40. . . . . . . . . . . . . . . . . . . . .
5–20 Flowchart for Floating-Point to Integer Conversion by FIX Instruction 5-42. . . . . . . . . . . . . . .
5–21 Flowchart for Integer to Floating-Point Conversion by FLOAT Instruction 5-43. . . . . . . . . . . .
5–22 Tabulated Values for Mantissa 5-46. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5–23 Fast Logarithm for FFT Displays 5-48. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6–1 Direct Addressing 6-4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6–2 Indirect Addressing Operand Encoding 6-6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6–3 Encoding for 24-Bit PC-Relative Addressing Mode 6-20. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6–4 Logical and Physical Representation of Circular Buffer 6-21. . . . . . . . . . . . . . . . . . . . . . . . . . . .
6–5 Logical and Physical Representation of Circular Buffer after Writing Three Values 6-21. . . .
6–6 Logical and Physical Representation of Circular Buffer after Writing Eight Values 6-22. . . . .
6–7 Circular Buffer Implementation 6-23. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6–8 Data Structure for FIR Filters 6-24. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6–9 System Stack Configuration 6-29. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6–10 Implementations of High-to-Low Memory Stacks 6-30. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6–11 Implementations of Low-to-High Memory Stacks 6-31. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7–1 CALL Response Timing 7-12. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7–2 Multiple TMS320C3xs Sharing Global Memory 7-17. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7–3 Zero-Logic Interconnect of TMS320C3x Devices 7-18. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7–4 Effective Base Address of the Interrupt-Trap-Vector Table 7-29. . . . . . . . . . . . . . . . . . . . . . . . .
7–5 IF Register Modification 7-33. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7–6 CPU Interrupt Processing 7-34. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7–7 Interrupt Logic Functional Diagram 7-37. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .