Jd15'
______
_
~
945407-9701
indication
of
which condition
(tank
low
or
tank
full) caused
the
interrupt are generated. The
seivice routine handling
the
storage
tank
system
then
uses
the
input
data
to
develop a control
signal
that
either opens
or
closes
the
input
valve
to
rectify
the
situation.
1.2
EQUIPMENT
OVERVIEW
Refer
to
figure
1-3
for a simplified diagram
of
the
data module. The module contains 16
flip-flops
that
are used
to
hold
the
data
supplied
by
the CPU and destined for some attached
device. In
the
send mode,
the
CPU supplies
output
data, a write clock signal, an address
that
specifies one
of
the
16 flip-flops, and a module enable signal. All
of
these controls act
to
set
or
clear the selected flip-flop
to
establish an interface with
the
attached
device. In
the
receive mode,
the CPU provides a select address and a module enable signal
to
read one
of
16
input
lines.
The
990
Computer
instruction repertoire includes single (SBO, SBZ, and TB) and multiple
(STCR and LDCR) bit instructions
that
exercise
the
data module in
both
the
send and receive
modes. The SBO and SBZ instructions set and clear, respectively,
the
addressed flip-flop;
the
TB
instruction tests
the
addressed
input
line. The LDCR instruction uses address increment logic
to
load from 1
to
16
of
the
flip-flops with serial data from
the
CPU. The STCR instruction uses
the
address increment logic
to
store
data
from 1
to
16
of
the
input
lines in contiguous
memory
locations.
When the module
is
wired
to
report interrupts, 2
of
the
16 flip-flops are used
to
store
the
interrupt itself and an
interrupt
mask. When
the
attached
device generates an interrupt, it
is
recorded in
the
interrupt
flip-flop and
the
interrupt
mask, controlled by
the
CPU,
either
enables
or
disables
the
transfer
of
the
interrupt
to
the
CPU.
1.2.1 TRANSMIT MODE. In
the
transmit mode,
the
CPU supplies an address (CRUBITl2-15)
that
specifies 1
of
the
16 flip-flops,
the
module enable signal
(IMODSELA-
), a write clock signal
(STORECLK-),
and
the
data bit
(CRUBITOUT-).
When
IMODSELA-
and
STORECLK-
are
both
TRUE (logic 0),
the
address decoder uses
the
address
to
select one
of
the
16 flip-flops and
the data bit
is
gated
into
it, through an open-collector driver, and
out
on
the
selected line. See
figure
1-3
for
the
output
logic.
1.2.2 RECEIVE MODE. In
the
receive mode,
the
CPU supplies
the
line address (CRUBITI2-15)
and
the
module enable signal
(IMODSELA-
).
The line address
is
decoded
by
the
multiplexer
and, when
IMODSELA-
is
true (logic 0),
the
input
bit
is
gated
through
an emitter-follower
transistor on
the
selected line, inverted three times and
submitted
to
the
CPU
as
CRUBITIN--.
See figure
1-3
for
the
input
logic.
1.2.3 INTERRUPT RESPONSE.
Interrupt
handling
is
selected
by
wiring
the
jumper
options
as
shown in Section II. Both types
of
interrupts (low-to-high and high-to-low) provide 15 normal
input
lines, 14 normal
output
lines, an
interrupt
line, and an
interrupt
mask. When an
interrupt
occurs, it
is
input
on
line
INl
5-.
The signal
is
inverted
either
once
or
twice (depending
upon
the
type
of
interrupt
the
module is wired for), submitted
to
a differentiating network,
and
clears
the
interrupt flip-flop.
If
interrupts are enabled
by
the
CPU (determined
by
the
interrupt
mask),
the
interrupt
is
inverted three times and
submitted
to
the
CPU as a low signal. See figure
1-3
for
the
interrupt
logic.
1-3 Digital Systems Division
