Texas Instruments 990 User manual
II
I
TEXAS
INSTRUMENTS
Improving Man's Effectiveness Through Electronics
Model
990
Computer
16
lnput/16
Output TTL Data Module
Depot Maintenance Manual.
MANUAL
NO. 945407-9701
ORIGINAL
ISSUE
1 AUGUST 1976
Digital Systems Division
I
I
~
Texas
Instruments Incorporated
1976
All
Rights
Reserved
The
infonnation and/or
drawings
set
forth
in
this
document
and
all
rights in
and
to inventions disclosed herein
and
patents
which
might
be
granted thereon disclos-
ing
or
employing
the materials,
methods,
techniques or apparatus described herein
are the exclusive property of
Texas
Instruments Incorporated.
INSERT
LATEST
CHANGED
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Note:
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portion of the text affected
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indicated
by
a vertical
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Model 990 Computer 16 Input/16 Output TTL Data Module Depot Maintenance
Manual (945407-9701)
Original Issue 1 August 1976
Total
number
of
pages
in
this
publication
is
42
consisting
of
the
following:
PAGE
NO.
Cover
Eff. Pages .
iii -
vi
1-1
-1-6
2-1
-2-2
3-1
-3-2
4-1
-4-10 .
5-1
-5-8
Alphabetical Index Div
Index-I -lndex-2
User's Resp
Bus. Reply
Cover Blank .
Cover
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PAGE
NO.
NO.
0
0
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NO. PAGE
NO.
CHANGE
NO.
Jdl.J\
______
_
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945407-9701
PREFACE
This manual provides maintenance instructions for the Texas Instruments 16
Input/
16
Output
TTL Data Module. The manual also provides the theory
of
operation for the module. The
information in the manual
is
divided into the following sections:
I. General Description -This section briefly describes the module, including its operation
and characteristics.
II. Installation -This section provides instructions for unpacking, inspecting, and
installing the module into a Model
990
Computer mainframe or expansion chassis.
III. Operating Instructions -This section provides programming instructions for
the
module and a description
of
how the software controls the operation
of
the module.
IV.
Theory
of
Operation -This section contains detailed block diagrams
of
the data
module, describes the module's interfaces with the Model 990 Computer and a
peripheral device, and provides a discussion
of
the
module's operation.
V.
Maintenance -This section provides troubleshooting and fault isolation procedures for
the module.
Alphabetical Index -The alphabetical index provides an alphabetical listing
of
key
words and concepts within the manual and locates them for easy reference.
Additional information related
to
the
16
Input/16
Output
TTL Data Module may be found in
the following documents:
Title
990 Computer Family Systems Handbook
Model 990/4 Computer System Hardware Reference
Manual
Model 990/10 Computer System Hardware Reference
Manual
Model 990 Computer Family Maintenance Drawings
iii/iv
Part
Number
945250-9701
945251-9701
945417-9701
945421-9701
and
945421-9702
Digital
Systems
Division
Jd75l
______
_
~
945407-9701
Paragraph
1.1
1.2
1.2.1
1.2.2
1.2.3
1.3
1.4
1.5
2.1
2.2
2.3
2.4
3.1
3.2
4.1
4.2
4.2.1
4.3
4.3.1
4.3.2
4.3.3
4.4
5.1
5.2
5.3
5.4
5.4.1
TABLE OF CONTENTS
Title
SECTION
I.
GENERAL DESCRIPTION
General
.....
Equipment Overview
Transmit Mode
Receive Mode . _
Interrupt
Response
Physical Characteristics
Electrical Characteristics
Module Address . . .
SECTION II. INSTALLATION
General
..
Unpacking
Inspection
Installation
SECTION III. OPERATING INSTRUCTIONS
General . . .
Programming
SECTION IV. THEORY
OF
OPERATION
General
.....
Data Module
Input
Logic .
Multiplexer . . . . . .
Data Module
Output
Logic
Output
Decoder . . . .
Output
Flip-Flops . . .
Output
Transistors . . .
Data Module
Interrupt
Logic
SECTION V. MAINTENANCE
General
Maintenance Philosophy
Special Test Equipment
Troubleshooting Procedures
Scoping Loops . . . . .
v
Page
1-2
1-3
1-3
1-3
1-3
1-5
1-5
1-5
2-1
2-1
2-1
2-2
3-1
3-1
4-1
4-1
4-1
4-1
4-1
4-8
4-8
4-8
5-1
5-1
5-1
5-4
54
Digital
Systems
Division
~~-~~~~~~~---
~
945407-9701
Figure
1-1
1-2
1-3
4-1
4-2
4-3
4-4
4-5
4-6
5-1
5-2
Table
1-1
1-2
1-3
2-1
4-1
4-2
5-1
5-2
5-3
LIST
OF
ILLUSTRATIONS
16
Input/16
Output
TTL
Data Module
Simplified
Control
System Example
Title
Simplified 16
lnput/16
Output
Data Module Diagram
Data Module
Input
Circuit and Timing
Data Selector/Multiplexer . . . . . . . .
Data Module
Output
Flip-Flop and Timing
4-Line-to-16-Line Decoder/Multiplexer
Dual D-Type Positive-Edge-Triggered Flip-Flops with Preset and Clear
Edge Triggered
Interrupt
Generation Logic
and
Signals
Model
990/4
Computer
Hot
Mockup System
Model
990/10
Computer
Hot
Mockup System . . . .
LIST
OF
TABLES
CRU
Interface Pin Assignments
External
Connector
Pin Assignment
Title
16 I/O
TTL
Data Module Electrical Characteristics
Jumper
Connections
Multiplexer
Input
Select for CRUBIT12-15
Decoder
Output
Select for
CRUBITl
2-15
Test Procedures . . . . . .
Output
Line Reference Chart
Input
Line Reference
Chart
.
vi
Page
1-1
1-2
1-4
4-2
4-4
4-5
4-7
4-8
4-9
5-2
5-3
Page
1-5
1-5
1-6
2-1
4-3
4-6
5-5
5-6
5-6
Digital
Systems
Division
J2r75'
______
_
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945407-9701
SECTION I
GENERAL
DESCRIPTION
1.1
GENERAL
The 16
Input/16
Output
TTL
Data Module (see figure 1-1) provwes a two-way
communication
path
between
a Texas
Instruments
990
Computer
and
attached
peripheral devices which are
operated
by
or
which genernte
TTL
level digital signals. l
he
module
may
be used in
any
Communications Register Unit (CRU)
port
within
the
CPU chassis,
or
it
may
be
used in a CRU
expansion chassis.
The
module
provides
16
input
and
16
output
lines. Each line
may
be
addressed
as
a single
independent
binary value
or
as a
member
of
a
group
of
from
2
to
16
lines"
Alternate
versions
of
the
module
provide 15
normal
inputs, 14
normal
outputs,
an
interrupt
line,
and
an
interrupt
mask. Data
module
inputs
and
outputs
are negative logic levels
that
switch
between
0 volts
and
a
positive voltage level. Each
output
is an
open
collector
transistor
capable
of
sinking
up
to
50
milliamperes at
up
to
30
volts. Pads are available
on
the
module
for installing pull-up resistors
or
resistor divider
networks
at each
output
of
the
module.
Each
input
is
connected
to
the
base
of
an emitter-follower
transistor
that
operates
at
TTL
levels. Pads
for
input
filter
capacitors
are also
available
on
the
module.
Use
of
the
data
module
in a simplified
control
system
is
shown
in figure 1-2. In this example,
the
computer
and
the
data
module
combine
to
sense
the
level
of
fluid in a storage
tank
and
to
control
the
operation
of
an
input
valve
to
reference levels. When
the
fluid reaches
one
of
the
prescribed references, an
interrupt
and an
FLOW
IN*
OPEN!CLOSE
OPEN/CLOSE
r
VALVE
VALVE
lt..1011""1""
I~,
r U I
I
VALVE
I
161/0
DATA
MODULE
I
MODEL
TANK
FULL
990
I
COMPUTER
I
INTERRUPT
STORAGE
TANK
TANK
FULL
I
FLOW
TANK
LOW
L
OUT
*FLOW
IN >
FLOW
OUT
(A)129473
Figure 1-2. Simplified Control System Example
1-1
Digital
Systems Division
945407-9701
1-2
-
::I
Q..
:;
0
\0
-
-
-
::I
§"
-
\0
-
-I
-
.~
~
Digital
Systems Division
Jd15'
______
_
~
945407-9701
indication
of
which condition
(tank
low
or
tank
full) caused
the
interrupt are generated. The
seivice routine handling
the
storage
tank
system
then
uses
the
input
data
to
develop a control
signal
that
either opens
or
closes
the
input
valve
to
rectify
the
situation.
1.2
EQUIPMENT
OVERVIEW
Refer
to
figure
1-3
for a simplified diagram
of
the
data module. The module contains 16
flip-flops
that
are used
to
hold
the
data
supplied
by
the CPU and destined for some attached
device. In
the
send mode,
the
CPU supplies
output
data, a write clock signal, an address
that
specifies one
of
the
16 flip-flops, and a module enable signal. All
of
these controls act
to
set
or
clear the selected flip-flop
to
establish an interface with
the
attached
device. In
the
receive mode,
the CPU provides a select address and a module enable signal
to
read one
of
16
input
lines.
The
990
Computer
instruction repertoire includes single (SBO, SBZ, and TB) and multiple
(STCR and LDCR) bit instructions
that
exercise
the
data module in
both
the
send and receive
modes. The SBO and SBZ instructions set and clear, respectively,
the
addressed flip-flop;
the
TB
instruction tests
the
addressed
input
line. The LDCR instruction uses address increment logic
to
load from 1
to
16
of
the
flip-flops with serial data from
the
CPU. The STCR instruction uses
the
address increment logic
to
store
data
from 1
to
16
of
the
input
lines in contiguous
memory
locations.
When the module
is
wired
to
report interrupts, 2
of
the
16 flip-flops are used
to
store
the
interrupt itself and an
interrupt
mask. When
the
attached
device generates an interrupt, it
is
recorded in
the
interrupt
flip-flop and
the
interrupt
mask, controlled by
the
CPU,
either
enables
or
disables
the
transfer
of
the
interrupt
to
the
CPU.
1.2.1 TRANSMIT MODE. In
the
transmit mode,
the
CPU supplies an address (CRUBITl2-15)
that
specifies 1
of
the
16 flip-flops,
the
module enable signal
(IMODSELA-
), a write clock signal
(STORECLK-),
and
the
data bit
(CRUBITOUT-).
When
IMODSELA-
and
STORECLK-
are
both
TRUE (logic 0),
the
address decoder uses
the
address
to
select one
of
the
16 flip-flops and
the data bit
is
gated
into
it, through an open-collector driver, and
out
on
the
selected line. See
figure
1-3
for
the
output
logic.
1.2.2 RECEIVE MODE. In
the
receive mode,
the
CPU supplies
the
line address (CRUBITI2-15)
and
the
module enable signal
(IMODSELA-
).
The line address
is
decoded
by
the
multiplexer
and, when
IMODSELA-
is
true (logic 0),
the
input
bit
is
gated
through
an emitter-follower
transistor on
the
selected line, inverted three times and
submitted
to
the
CPU
as
CRUBITIN--.
See figure
1-3
for
the
input
logic.
1.2.3 INTERRUPT RESPONSE.
Interrupt
handling
is
selected
by
wiring
the
jumper
options
as
shown in Section II. Both types
of
interrupts (low-to-high and high-to-low) provide 15 normal
input
lines, 14 normal
output
lines, an
interrupt
line, and an
interrupt
mask. When an
interrupt
occurs, it
is
input
on
line
INl
5-.
The signal
is
inverted
either
once
or
twice (depending
upon
the
type
of
interrupt
the
module is wired for), submitted
to
a differentiating network,
and
clears
the
interrupt flip-flop.
If
interrupts are enabled
by
the
CPU (determined
by
the
interrupt
mask),
the
interrupt
is
inverted three times and
submitted
to
the
CPU as a low signal. See figure
1-3
for
the
interrupt
logic.
1-3 Digital Systems Division
>
(CPUDATAOUT)
990
DATA
OUT
·
990
WRITE
CLOCK
(STORECLOCK)
MODULE
ADDRESS
BITS
(CRUBIT1
2-15)
DECODE
ENABLE
(CRUSELO)
L(CRUDATAIN)
990
DATA
IN
'Ii\
ENABLE
DECODE
SELECT
16
FLIP-FLOPS
Q
(OUTo_-)
__
_
..-~------------------(-IN_O_~_),._·--<
(A)
16
INPUT/16
(IN
15-)
OUTPUT
CONFIGURATION
~L
INTERRUPT
MASK
INTERRUPT
·---0...
)
(CRUDATA_o_u_T_)
_________________
--11.,.D
)
990
INTEH-
.
RU
PT
M.A.SK
DATA
INTERRUPT
TO
990
(A)
1
29474A
FF14 FF15
15DC
~--~---------------~---~-~---~CLK
Q Q
CLR
(CRU
INT-)
(IN
15-)
'
(B)
INTERRUPT
CONFIGURATION
Figure 1-3. Simplified 16 Input/16 Output Data Module Diagram
16
DATA
LINES
TO
PERIPHERAL
DEVICE(S)
16
LINES
OF
PERIPHERAL
DEVICE
DATA
JUMPER
OPTION
PERIPHERAL
INTERRUPT
~-------
~
945407-9701
1.3 PHYSICAL CHARACTERISTICS
The 16
Input/16
Output
TTL Data Module
is
implemented
on
a double-edge, half-size printed
circuit board
that
can be inserted
into
any CRU slot
of
any Model
990
Computer
chassis
or
CRU
expansion chassis.
It
is a double-sided board
that
measures 7.00 inches by 10.80 inches
high,
as
oriented in figure 1-1. The board is made
to
be inserted
into
an 80
contact
printed
circuit board slot
connector
located in
the
backpanel
of
the chassis (see table
1-1
for
the
pin
assignments). The generalized
TTL
interface
is
supplied
to
external devices through a 40-pin flat
cable connector
on
the
rear
of
the
card. The pin assignments for this
connector
are shown in
table 1-2.
i
.4
ELECTRiCAL CHARACTERiSTiCS
Table
1-3
lists
the
logic levels and electrical requirements for
the
16
Input/16
Output
TTL
Data
Module.
1.5 MODULE ADDRESS
The location
of
the
module within
the
computer
chassis
(or
expansion chassis) determines
the
CRU base address
that
the
module recognizes. Therefore, before selecting a chassis location,
determine
the
address
that
the
software handling
routine
expects the module
to
recognize.
Table 1-1. CRU Interface Pin Assignment
Pin Number Signal Name
Pl-14
TLIORES
Pl-18
CRUBITOUT
Pl-22
STORECLK
Pl-32
CRUBIT13
Pl-34
CRUBIT15
Pl-36
CRUBIT12
Pl-38
CRUBIT14
Pl-48
IMODSELA
Pl-60 CRUBITIN
Pl-66
INTERRUPTA
Pl-1,2,24,79,80 GROUND
Pl-3,4,77,78
+5
Volts
Table 1-2. External Connector Pin Assignment
Pin Number
P2-2
P2-3
P24
P2-5
P2-6
P2-7
P2-8
1-5
Signal Name
OUTO-
OUTI-
OUT2-
0UT3-
OUT4-
0UT5-
OUT6-
Digital Systems Division
~-------
~
945407-9701
Table 1-2. External Connector
Pin
A~igriment
(Continued)
Pin
Number Signal Name
P2-9
OUT7-
P2-10
OUT8-
P2-11
OUT9-
P2-12
OUTlO-
P2-13
OUTll-
P2-14
OUT12-
P2-15
OUT13-
P2-16
OUT14-
P2-17
OUT15-
P2-24
IN15-
P2-25
IN14-
P2-26
IN13-
P2-27
IN12-
P2-28
INll-
P2-29
INlO-
P2-30
IN9-
P2-31
IN8-
P2-32
IN7-
P2-33
IN6-
P2-34
INS-
P2-35
IN4-
P2-36
IN3-
P2-37
IN2-
P2-38
INl-
P2-39 INO-
P2-l ,20,2l,40 GROUND
P2-19,22
+5
Vo.Its
Table 1-3. 16
1/0
TTL Data Module Electrical Characteristics
Specification
Peripheral inputs
Module outputs
Power (from
CPU
or
expansion chassis)
1-6
Requirement
0.0 to 1.0 volts for logic 1
3.0 to 5.0 volts for logic 0
Open or 3.0 to 5.0 volts for logic 0
0.0 to 0.4 volts for logic 1
+S
Vdc at -0.53A
Digital
Systems Division
~~-------
~
945407-9701
SECTION II
INSTALLA
TI
ON
2.1
GENERAL
\his
section provides instructions for unpacking, inspecting, and installing a 16
Input/
16
Output
TTL
Data Module.
2.2
UNPACKING
The module
is
packed in one
box
and
is
wrapped in plastic bubble-pack wrapping. Visually
inspect
the
box
for signs
of
damage. Remove
the
module from
the
box. Verify
that
at least three
(six for Part Numbers 945145-0002 and 045145-0003) jumpers have been received (the jumpers
are plugged
into
the circuit board for shipping). Do
not
discard any
of
the
wrapping material
until all equipment has been accounted for.
2.3 INSPECTION
Perform
the
following steps prior
to
installing
the
module in a chassis slot:
1.
Visually inspect
the
circuit board for cracks, corrosion, loose components, and loose
connectors.
2. Remove all jumpers from
their
shipping locations.
3. According
to
the
pre-determined requirements for
the
module, insert
the
jumpeiS
into
the
proper
sockets. Table
2-1
gives
the
connectioris for all possible options.
945145-0001
No
Interrupt
ES
-
E6
El6
-
Ei8
El
7 -
El9
Table 2-1. Jumper Connections
945145-0002 945145-0003
One High
to
Low Interrupt One Low to
High
Interrupt
ES
-
E8
ES
-E8
E9 -EIO
E9
-EIO
E6 -E12
Ell
-E12
E7 -E13 E7 -E13
E16 -
El8
E16 -E18
El7-E19
E17-El9
2-1
945145-0004
No Interrupt
ES
-E6
El6
-E18
El
7 -
El9
Digital Systems Division .
~-------
~
945407-9701
2.4 INSTALLATION
After defining the location for the data module, checking the jumper configuration, and insuring
that
the
required voltages are available for
the
module, perform the following steps
to
install the
module in the desired location:
1.
Ensure
that
the
chassis power
is
off.
2.
Insert the circuit board, component side up, into the selected slot until the sides
of
the
board slide into
the
card guides on either side
of
the slot (one guide
is
the center card
guide, Part Number 945129-0001, which must have been installed before inserting the
circuit board).
3. Gently push
the
board straight in until the card edge connector engages
the
slotted
connector in
the
backpanel
of
the chassis.
4.
Insert
the
appropriate cable into
the
external device connector.
5.
Dress the cable
out
of
the
chassis (toward
the
center
of
a mainframe chassis, toward
the
bottom
of
an expansion chassis).
6. Connect the
other
end
of
the
cable
to
the desired peripheral device in accordance with
the installation instructions for the device.
2-2
Digital
Systems Division
Jdls-i,
______
_
~
945407-9701
SECTION III
OPERATING INSTRUCTIONS
3.1 GENERAL
Operation
of
the 16
Input/
16
Output
TTL Data Module consists entirely
of
the programming
required
to
perform the necessary interface with the attached peripheral device. The service
routines implemented to handle the interface use the SBO, SBZ, TB, LDCR, and STCR
instructions from the
990
Computer instruction repertoire (see the
990
Computer/TMS
9900
Microprocessor
Assembly
Language Programmers Guide, Manual Number 943441-9701
).
All
of
these instructions require the use
of
an effective CRU address
that
addresses bit 0
of
the module
under consideration. Since the module can be inserted into any
of
the available CRU chassis
locations, and the locations are wired for pre-established addresses,
the
base address becomes a
variable dependent upon the hardware configuration.
3.2 PROGRAMMING
The interface between the CPU and
the
module consists
of
16
addressable
1/0
bits. The
1/0
routines written
to
handle communications with the attached devices vary for each device type.
This
is
due
to
the differences in the controls accepted and
the
status returned
by
the
device.
Generally, the I/O routine must first establish communications with the device and
then
proceed
to
read/write on a character-by-character basis. At
the
same time,
the
routine must be prepared
for irregular status indicators and,
if
the
16
I/O TTL board
is
so wired, be capable
of
handling
interrupts.
The simplified control system example presented in Section I
is
a case where the single-bit CRU
instructions are used
to
control operation
of
the
data module interface. A service routine
of
the
following
type
would execute after
the
computer had been interrupted and
the
current machine
status saved:
TANKLO EQU
TANKFL
EQU
OPVALV EQU
START TB
JNE
TB
JNE
EXIT RTWP
OPEN
SBO
0
2
TANKLO
OPEN
TANKFL
CLOSE
OPVALV
Define label.
Define iabei.
Define label.
Is
fluid level
too
low?
If
yes,
jump
to
the
corrective routine.
Is
the tank full?
If
yes,
jump
to
the
corrective routine.
Interrupt corrected. Return to the interrupted
program and restore status.
Open the input valve
to
correct
the
fluid
low condition.
3-1
Digital
Systems
Division
.
~-------
~
945407-9701
JMP START Return
to
the start
of
the routine
to
see
if
the
problem has been corrected.
CLOSE SBZ OPVALV Close
the
valve.
JMP START Return
to
the
start
of
the
routine
to
see
if
the
problem has been corrected.
The multiple bit instructions, LDCR and STCR, are typically used in a service routine
that
handles data groups.
3-2 Digital
Systems
Division
~-------
~
945407-9701
SECTION IV
THEORY
OF
OPERATION
4.1 GENERAL
This section provides
the
theory
of
operation
of
the 16
Input/16
Output
TTL Data Module. A
general description
of
the
data module
is
given in Section I and it should be read first
if
the
reader
is
not familiar with
the
basic data module operation. The detailed description in this
section
is
accompanied by timing diagrams and abbreviated logic diagrams. Detailed logic
diagrams may be found in
the
Model
990
Computer Family Maintenance Drawings Manual,
Manual Numbers 945421-9701 and 945421-9702.
4.2 DATA MODULE INPUT LOGIC
Refer
to
figure
4-1
for a diagram
of
the data module
input
logic,
the
associated timing diagram,
and
the
pin numbers used
on
the
data module.
As
shown, the CPU provides the
data
module
with
+5
Vde and a common ground
that
can be tied in with the peripheral device. The
16
peripheral
input
lines are applied to
the
U3
multiplexer via individual emitter-follower transistors.
Capacitor pads are provided across
the
inputs for use when line noise
is
a problem. When the
user program decides
to
read one
of
the
input lines, the CPU develops address select lines
(CRUBITl 2-15) which are decoded
by
the
multiplexer (see table 4-1) and a data module enable
(IMODSELA-)
that
combine
to
select one
of
the
16
input
lines. The
input
data
is
inverted three
times and passed
to
the
CPU via
the
CRUBITIN-
line. A low (0 to 1
V)
or high (3
to
5
V)
input
signal becomes a high (logic 1)
or
low (logic 0) logic level, respectively, in
the
CPU.
4.2.1 MULTIPLEXER. The multiplexer
is
a 16-to-l data selector (see figure 4-2)
that
passes one
of
its inputs to a
output
gate each time
it
is
strobed
by
IMODSELA-
from the CPU. The input
passed
is
selected
by
the
CRU address bits, CRUBIT12-15, as shown in table 4-1. Once passed
to
the
output
of
the
multiplexer,
the
data is gated
to
the
CPU
if
IMODSELA-
=0.
4.3 DATA MODULE OUTPUT LOGIC
Refer
to
figure 4-3 for a diagram
of
the data module
output
logic,
the
associated timing
diagrams, and
the
pin numbers used
on
the
module.
-When
a program is required
to
transfer data
from
the
CPU
to
an attached peripheral device, the CPU must supply
the
data module with an
output
data bit (CRUBITOUT-), destination flip-flop select address (CRUBITl2-15), a data
module enable signal (IMODSELA-), and a write clock signal
(STORECLK-).
The IMODSELA-
and
STORECLK-
signals combine to gate
the
data bit into the selected flip-flop. The
CRUBIT12-15 signals are applied
to
the U
13
address decoder
to
select the destination flip-flop
(see table 4-2). The CPU
output
bit
is
inverted and stored in
the
selected flip-flop and
then
made
available
to
the
attached peripheral
after
two
more level inversions. The result
of
the
three
level
inversions
is
that
a logic 1
(2.4
V)
or
a logic 0 (0.4 V)
of
computer
output
data becomes a low
voltage (0.4 V
or
less)
or
an open circuit, respectively,
at
the
peripheral interface.
4.3.1 OUTPUT DECODER. The
Ul3
output
decoder
is
a 4-line-to-16-line decoder.
As
shown in
figure 4-4, it accepts
the
CRUBITl2-15 inputs and
the
IMODSELA-
and
STORECLK-
signals.
When
IMODSELA-
and
STORECLK-
are
both
low,
the
decoder reads the inputs and seiects the
appropriate
output
line.
4-1
Digital
Systems
Division
.
..&:;:..
I
N
P1-60
~·---
CRUBITINI
IMODSELA-
CRUBIT1
2-1
s
STABLE
AND=0111
I
---
IMODSELA-
CRUBIT
12-15
S
ABC
D
SN74150
U3
w
I I
...
,
..
_..
___
2sons
MIN
----1•~1
I I
VCC
A52222
012
3600HMS
i----~-----IN_7_--~
P2-E
R C
360 OHMS
NOTE:
C
MAY
BE
ADDED
FOR
NOISE
SUPPRESS
ION
~----1---
sv
ov
l
~~!--~------
sv
ov
~7~-------
/
____
!
____
~
_____l
______
\-----:~:
I I
ST
ABLE
BEFORE
IMODSELA-
=O
CRUBITIN
(A)132026A
~---------~
sv
ov
Figure 4-1. Data Module Input Circuit and Timing
~-------
~
945407-9701
Table
4-1.
Multiplexer Input Select for CRUBIT12-15
CRUBITl2-15 Input Selected
0000 INO-
0001
INI-
0010
IN2-
0011
IN3-
0100
IN4-
0101
INS-
0110
IN6-
0111
IN7-
1000
INS-
1001
IN9-
1010
INIO-
1011
INll-
1100
IN12-
1101
IN13-
1110
IN14-
1111
IN15-
4-3
Digital
Systems
Division
~-------
~
945407-9701
IMODSELA
CRUBIT15
CRUBIT14
CRUBIT13
CRUBIT12
(A)
133821
-
EO
El
E'2
E3
E4
ES
E6
E7
ES
E9
E10
E
11
E12
E13
E14
E15
9
B
7
6
5
4
3
2
1
23
22
21
20
19
18
17
16
15
.......
14
13
n
vcc
)24
I
I '
J
4~
"\_
, J
~
}
r-:
)
~
I
~
}--
~
)--i
"'~
~
·~
L-----i
:J
~
10
~
_J
.../"
DATAINA-
R.
I
r=t
~
~
"]
}--
··..-;
'
J
~
"\.
J
~
"\..
I
~
""'\
~
J
A
'-
~-
"]
J
1-..f
-J B
c-
-l c
..D::::.
r D
-
....
L
112
GND
Figure 4-2. Data Selector/Multiplexer
4-4
Digital Systems Division
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