Texas Instruments 990 User manual

II
I
TEXAS INSTRUMENTS
Improving Man's Effectiveness Through Electronics
Model 990 Computer
16 lnput/16 Output TTL Data Module
Depot Maintenance Manual.
MANUAL NO. 945407-9701
ORIGINAL ISSUE 1 AUGUST 1976
Digital Systems Division
I
I

~ Texas Instruments Incorporated 1976
All Rights Reserved
The infonnation and/or drawings set forth in this document and all rights in and
to inventions disclosed herein and patents which might be granted thereon disclos-
ing or employing the materials, methods, techniques or apparatus described herein
are the exclusive property of Texas Instruments Incorporated.
INSERT LATEST CHANGED PAGES DESTROY SUPERSEDED PAGES
LIST OF EFFECTIVE PAGES
Note: The portion of the text affected by the changes is
indicated by a vertical bar in the outer margins of
the page.
Model 990 Computer 16 Input/16 Output TTL Data Module Depot Maintenance
Manual (945407-9701)
Original Issue 1 August 1976
Total number of pages in this publication is 42 consisting of the following:
PAGE
NO.
Cover
Eff. Pages .
iii - vi
1-1 -1-6
2-1 -2-2
3-1 -3-2
4-1 -4-10 .
5-1 -5-8
Alphabetical Index Div
Index-I -lndex-2
User's Resp
Bus. Reply
Cover Blank .
Cover
CHANGE
PAGE
NO.
NO.
0
0
0
0
0
0
0
0
0
0
0
0
0
0
CHANGE
NO. PAGE NO.
CHANGE
NO.

Jdl.J\ ______ _
~ 945407-9701
PREFACE
This manual provides maintenance instructions for the Texas Instruments 16 Input/ 16 Output
TTL Data Module. The manual also provides the theory of operation for the module. The
information in the manual is divided into the following sections:
I. General Description -This section briefly describes the module, including its operation
and characteristics.
II. Installation -This section provides instructions for unpacking, inspecting, and
installing the module into a Model 990 Computer mainframe or expansion chassis.
III. Operating Instructions -This section provides programming instructions for the
module and a description of how the software controls the operation of the module.
IV. Theory of Operation -This section contains detailed block diagrams of the data
module, describes the module's interfaces with the Model 990 Computer and a
peripheral device, and provides a discussion of the module's operation.
V. Maintenance -This section provides troubleshooting and fault isolation procedures for
the module.
Alphabetical Index -The alphabetical index provides an alphabetical listing of key
words and concepts within the manual and locates them for easy reference.
Additional information related to the 16 Input/16 Output TTL Data Module may be found in
the following documents:
Title
990 Computer Family Systems Handbook
Model 990/4 Computer System Hardware Reference
Manual
Model 990/10 Computer System Hardware Reference
Manual
Model 990 Computer Family Maintenance Drawings
iii/iv
Part Number
945250-9701
945251-9701
945417-9701
945421-9701
and
945421-9702
Digital Systems Division

Jd75l ______ _
~ 945407-9701
Paragraph
1.1
1.2
1.2.1
1.2.2
1.2.3
1.3
1.4
1.5
2.1
2.2
2.3
2.4
3.1
3.2
4.1
4.2
4.2.1
4.3
4.3.1
4.3.2
4.3.3
4.4
5.1
5.2
5.3
5.4
5.4.1
TABLE OF CONTENTS
Title
SECTION I. GENERAL DESCRIPTION
General .....
Equipment Overview
Transmit Mode
Receive Mode . _
Interrupt Response
Physical Characteristics
Electrical Characteristics
Module Address . . .
SECTION II. INSTALLATION
General ..
Unpacking
Inspection
Installation
SECTION III. OPERATING INSTRUCTIONS
General . . .
Programming
SECTION IV. THEORY OF OPERATION
General .....
Data Module Input Logic .
Multiplexer . . . . . .
Data Module Output Logic
Output Decoder . . . .
Output Flip-Flops . . .
Output Transistors . . .
Data Module Interrupt Logic
SECTION V. MAINTENANCE
General
Maintenance Philosophy
Special Test Equipment
Troubleshooting Procedures
Scoping Loops . . . . .
v
Page
1-2
1-3
1-3
1-3
1-3
1-5
1-5
1-5
2-1
2-1
2-1
2-2
3-1
3-1
4-1
4-1
4-1
4-1
4-1
4-8
4-8
4-8
5-1
5-1
5-1
5-4
54
Digital Systems Division

~~-~~~~~~~---
~ 945407-9701
Figure
1-1
1-2
1-3
4-1
4-2
4-3
4-4
4-5
4-6
5-1
5-2
Table
1-1
1-2
1-3
2-1
4-1
4-2
5-1
5-2
5-3
LIST OF ILLUSTRATIONS
16 Input/16 Output TTL Data Module
Simplified Control System Example
Title
Simplified 16 lnput/16 Output Data Module Diagram
Data Module Input Circuit and Timing
Data Selector/Multiplexer . . . . . . . .
Data Module Output Flip-Flop and Timing
4-Line-to-16-Line Decoder/Multiplexer
Dual D-Type Positive-Edge-Triggered Flip-Flops with Preset and Clear
Edge Triggered Interrupt Generation Logic and Signals
Model 990/4 Computer Hot Mockup System
Model 990/10 Computer Hot Mockup System . . . .
LIST OF TABLES
CRU Interface Pin Assignments
External Connector Pin Assignment
Title
16 I/O TTL Data Module Electrical Characteristics
Jumper Connections
Multiplexer Input Select for CRUBIT12-15
Decoder Output Select for CRUBITl 2-15
Test Procedures . . . . . .
Output Line Reference Chart
Input Line Reference Chart .
vi
Page
1-1
1-2
1-4
4-2
4-4
4-5
4-7
4-8
4-9
5-2
5-3
Page
1-5
1-5
1-6
2-1
4-3
4-6
5-5
5-6
5-6
Digital Systems Division

J2r75' ______ _
~ 945407-9701
SECTION I
GENERAL DESCRIPTION
1.1 GENERAL
The 16 Input/16 Output TTL Data Module (see figure 1-1) provwes a two-way communication
path between a Texas Instruments 990 Computer and attached peripheral devices which are
operated by or which genernte TTL level digital signals. l he module may be used in any
Communications Register Unit (CRU) port within the CPU chassis, or it may be used in a CRU
expansion chassis.
The module provides 16 input and 16 output lines. Each line may be addressed as a single
independent binary value or as a member of a group of from 2 to 16 lines" Alternate versions of
the module provide 15 normal inputs, 14 normal outputs, an interrupt line, and an interrupt
mask. Data module inputs and outputs are negative logic levels that switch between 0 volts and a
positive voltage level. Each output is an open collector transistor capable of sinking up to 50
milliamperes at up to 30 volts. Pads are available on the module for installing pull-up resistors or
resistor divider networks at each output of the module. Each input is connected to the base of
an emitter-follower transistor that operates at TTL levels. Pads for input filter capacitors are also
available on the module.
Use of the data module in a simplified control system is shown in figure 1-2. In this example,
the computer and the data module combine to sense the level of fluid in a storage tank and to
control the operation of an input valve to
reference levels. When the fluid reaches one of the prescribed references, an interrupt and an
FLOW IN*
OPEN!CLOSE
OPEN/CLOSE
r
VALVE
VALVE
lt..1011""1""
I~, r U I
I
VALVE
I 161/0
DATA
MODULE I
MODEL
TANK FULL
990 I
COMPUTER
I
INTERRUPT
STORAGE
TANK
TANK
FULL
I
FLOW
TANK
LOW
L
OUT
*FLOW IN > FLOW OUT
(A)129473
Figure 1-2. Simplified Control System Example
1-1
Digital Systems Division

945407-9701
1-2
-
::I
Q..
:;
0
\0
-
-
-
::I
§"
-
\0
-
-I
-
.~
~
Digital Systems Division

Jd15' ______ _
~ 945407-9701
indication of which condition (tank low or tank full) caused the interrupt are generated. The
seivice routine handling the storage tank system then uses the input data to develop a control
signal that either opens or closes the input valve to rectify the situation.
1.2 EQUIPMENT OVERVIEW
Refer to figure 1-3 for a simplified diagram of the data module. The module contains 16
flip-flops that are used to hold the data supplied by the CPU and destined for some attached
device. In the send mode, the CPU supplies output data, a write clock signal, an address that
specifies one of the 16 flip-flops, and a module enable signal. All of these controls act to set or
clear the selected flip-flop to establish an interface with the attached device. In the receive mode,
the CPU provides a select address and a module enable signal to read one of 16 input lines.
The 990 Computer instruction repertoire includes single (SBO, SBZ, and TB) and multiple
(STCR and LDCR) bit instructions that exercise the data module in both the send and receive
modes. The SBO and SBZ instructions set and clear, respectively, the addressed flip-flop; the TB
instruction tests the addressed input line. The LDCR instruction uses address increment logic to
load from 1 to 16 of the flip-flops with serial data from the CPU. The STCR instruction uses the
address increment logic to store data from 1 to 16 of the input lines in contiguous memory
locations.
When the module is wired to report interrupts, 2 of the 16 flip-flops are used to store the
interrupt itself and an interrupt mask. When the attached device generates an interrupt, it is
recorded in the interrupt flip-flop and the interrupt mask, controlled by the CPU, either enables
or disables the transfer of the interrupt to the CPU.
1.2.1 TRANSMIT MODE. In the transmit mode, the CPU supplies an address (CRUBITl2-15)
that specifies 1 of the 16 flip-flops, the module enable signal (IMODSELA- ), a write clock signal
(STORECLK-), and the data bit (CRUBITOUT-). When IMODSELA- and STORECLK- are
both TRUE (logic 0), the address decoder uses the address to select one of the 16 flip-flops and
the data bit is gated into it, through an open-collector driver, and out on the selected line. See
figure 1-3 for the output logic.
1.2.2 RECEIVE MODE. In the receive mode, the CPU supplies the line address (CRUBITI2-15)
and the module enable signal (IMODSELA- ). The line address is decoded by the multiplexer
and, when IMODSELA- is true (logic 0), the input bit is gated through an emitter-follower
transistor on the selected line, inverted three times and submitted to the CPU as CRUBITIN--.
See figure 1-3 for the input logic.
1.2.3 INTERRUPT RESPONSE. Interrupt handling is selected by wiring the jumper options as
shown in Section II. Both types of interrupts (low-to-high and high-to-low) provide 15 normal
input lines, 14 normal output lines, an interrupt line, and an interrupt mask. When an interrupt
occurs, it is input on line INl 5-. The signal is inverted either once or twice (depending upon the
type of interrupt the module is wired for), submitted to a differentiating network, and clears the
interrupt flip-flop. If interrupts are enabled by the CPU (determined by the interrupt mask), the
interrupt is inverted three times and submitted to the CPU as a low signal. See figure 1-3 for the
interrupt logic.
1-3 Digital Systems Division

>
(CPUDATAOUT)
990 DATA OUT ·
990 WRITE
CLOCK
(STORECLOCK)
MODULE
ADDRESS BITS
(CRUBIT1 2-15)
DECODE
ENABLE
(CRUSELO)
L(CRUDATAIN)
990 DATA IN 'Ii\
ENABLE
DECODE
SELECT
16
FLIP-FLOPS
Q
(OUTo_-) __ _
..-~------------------(-IN_O_~_),._·--<
(A) 16 INPUT/16
(IN 15-)
OUTPUT CONFIGURATION ~L
INTERRUPT
MASK INTERRUPT ·---0...
)
(CRUDATA_o_u_T_) _________________ --11.,.D )
990 INTEH- .
RU PT M.A.SK
DATA
INTERRUPT
TO 990
(A) 1 29474A
FF14 FF15
15DC
~--~---------------~---~-~---~CLK Q Q
CLR
(CRU INT-)
(IN 15-) '
(B) INTERRUPT CONFIGURATION
Figure 1-3. Simplified 16 Input/16 Output Data Module Diagram
16 DATA LINES
TO PERIPHERAL
DEVICE(S)
16 LINES OF
PERIPHERAL
DEVICE DATA
JUMPER
OPTION
PERIPHERAL
INTERRUPT