Texas Instruments ISO7220 Series User manual

1 Introduction
User's GuideSLLU098A – June 2007 – Revised July 2009
Dual-Channel Digital Isolator EVM
Contents1 Introduction ................................................................................................................... 11.1 Overview ............................................................................................................. 21.2 Functional Configuration of the Dual-Channel Digital Isolator ................................................ 21.3 The EVM Signal Paths of the ISO7220x and ISO7221x Isolators ........................................... 31.4 The ISO7220x EVM Configuration ............................................................................... 51.5 The ISO7221x EVM Configuration ............................................................................... 62 EVM Setup and Operation .................................................................................................. 72.1 Overview ............................................................................................................. 7
List of Figures
1 The ISO7220x and ISO7221x Pinouts .................................................................................... 22 The ISO7220x Same-Channel Direction Schematic .................................................................... 33 The ISO7221x Opposing-Channel Direction Schematic ................................................................ 44 ISO7220x EVM, Top View ................................................................................................. 55 ISO7220x EVM, Bottom View ............................................................................................. 56 The ISO7221x EVM Top View ............................................................................................. 67 The ISO7221x EVM Bottom View ......................................................................................... 68 Basic EVM Operation ....................................................................................................... 79 Typical Input and Output Waveforms ..................................................................................... 7
List of Tables
1 ISO7220x EVM Connections ............................................................................................... 32 ISO7221x EVM Connections ............................................................................................... 4
This user's guide details the evaluation module (EVM) operation of the factory installed ISO7220Mdual-channel digital isolator. However, the EVM board may be reconfigured by a user for use with any ofthe ISO7220x or ISO7221x dual-channel isolators.
The EVM may be reconfigured for use with the ISO7220A, ISO7220B and ISO7220C same-channeldirection isolators and the ISO7221A, ISO7221A, ISO7221C and ISO7221M opposing-channel directionisolators.
This guide also explains the user configurable I/O loads for both dual-channel isolator EVM configurations,and presents a typical lab setup with input and output waveforms.
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1.1 Overview
1.2 Functional Configuration of the Dual-Channel Digital Isolator
ISO7221x
1
2
3
45
6
7
8
GND2
Vcc2
Vcc1
GND1
OUTB
INA
OUTA
INB
ISOLATION
ISO7220x
1
2
3
45
6
7
8
GND2
Vcc2
Vcc1
GND1
OUTB
INA OUTA
INB
ISOLATION
Introduction www.ti.com
The ISO7220x and ISO721x dual digital isolators have a logic input and output buffer separated by asilicon oxide (SiO
2
) insulation barrier. Used in conjunction with isolated power supplies, these devicesblock high voltage, isolate grounds, and prevent noise currents on a data bus or other circuits fromentering the local ground and interfering with or damaging sensitive circuitry.
A binary input signal is conditioned, translated to a balanced signal, and then differentiated by thecapacitive isolation barrier. Across the isolation barrier, a differential comparator receives the logictransition information, then sets or resets a flip-flop and the output circuit accordingly. A periodic updatepulse is sent across the barrier to ensure the proper dc level of the output. If this dc-refresh pulse is notreceived for more than 4 µs, the input is assumed to be unpowered or not functional, and the failsafecircuit drives the output to a logic-high state.
CAUTION
Note that although these devices provide galvanic isolation of up to 4000 V, thisEVM cannot be used for isolation voltage testing. It is designed for theexamination of device operating parameters only and will be damaged if highvoltage (> 5.5 V) is applied anywhere in the circuit.
The pin-outs of the dual-channel digital isolators are displayed in Figure 1 . The EVM comes with anISO7220M installed; however, the user may reconfigure the EVM for use with any of the footprints.
Figure 1. The ISO7220x and ISO7221x Pinouts
The ISO7220A, ISO7220B, ISO7220C, ISO7221A, ISO7221B and ISO7221C have TTL input thresholdsand an input noise filter that prevents transient pulses of up to 2 ns in duration from being passed to theoutput of the device.
The ISO7220M and ISO7221M have a CMOS Vcc/2 input threshold, but do not have the noise filter andthe additional propagation delay.
Dual-Channel Digital Isolator EVM2 SLLU098A – June 2007 – Revised July 2009Submit Documentation Feedback

1.3 The EVM Signal Paths of the ISO7220x and ISO7221x Isolators
1
2
3
45
6
7
8
ISO7220x
VCC1 (Banana Jack P1) VCC2 (Banana Jack P2)
C2 C3 C4 C5 C6 C11 C10 C9 C8 C7
INA
OUTB
SMA
J3
SMA
J4
GND1 (Banana Jack P3) GND2 (Banana Jack P4)
0W
50 W
INPUT OUTPUT
SMA
J1
INPUT
SMA
J2
OUTPUT
INB
OUTA
data
data data
data
0W
50 W
0W
0W
www.ti.com Introduction
This multifunctional EVM is designed with signal paths shown in Figure 1 ,Figure 2 , and Figure 3 for theevaluation of the ISO7220x and ISO7221x dual-channel isolators.
Figure 2. The ISO7220x Same-Channel Direction Schematic
Table 1. ISO7220x EVM Connections
Connection Label Description
J1 SMA connector to the INB input, pin 3J2 SMA connector to the OUTB output, pin 6J3 SMA connector to the INA input, pin 2J4 SMA connector to the OUTA output, pin 7P1 V
CC1
Input power supply banana jackP2 V
CC2
Output power supply banana jackP3 GND1 Input power ground connection banana jackP4 GND2 Output power ground connection banana jackJMP1 3-pin jumper V
CC1
, input, GND1JMP2 3-pin jumper (unused)JMP3 3-pin jumper – V
CC1
, input, GND1JMP4 3-pin jumper (unused)
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1
2
3
45
6
7
8
ISO7221x
VCC1 (Banana Jack P1) VCC2 (Banana Jack P2)
C2 C3 C4 C5 C6 C11 C10 C9 C8 C7
INA
OUTB
SMA
J3
SMA
J4
GND1 (Banana Jack P3) GND2 (Banana Jack P4)
0W
OUTPUT INPUT
SMA
J1 50 W
INPUT
SMA
J2
OUTPUT
INB
OUTA
data
data data
data
0W
50 W
0W
0W
Introduction www.ti.com
Figure 3. The ISO7221x Opposing-Channel Direction Schematic
Table 2. ISO7221x EVM Connections
Connection Label Description
J1 SMA connector to the INB input, pin 3J2 SMA connector to the OUTB output, pin 6J3 SMA connector to the OUTA output, pin 2J4 SMA connector to the INA input, pin 7P1 V
CC1
Input power supply banana jackP2 V
CC2
Output power supply banana jackP3 GND1 Input power ground connection banana jackP4 GND2 Output power ground connection banana jackJMP1 3-pin jumper V
CC1
, input, GND1JMP2 3-pin jumper (unused)JMP3 3-pin jumper (unused)JMP4 3-pin jumper V
CC2
, input, GND2
4Dual-Channel Digital Isolator EVM SLLU098A – June 2007 – Revised July 2009Submit Documentation Feedback

1.4 The ISO7220x EVM Configuration
INA
OUTB
R8
R4
R6
INB
OUTA
R2
INA
OUTB
R5
R1
OUTA
INB
www.ti.com Introduction
The ISO7220x EVM configuration has SMA connectors (J1 and J3) set up as the input to the INA (pin 2)and INB (pin 3) of the ISO7220M in Figure 1 and Figure 2 .R2 and R8 are 0- Ωinput series resistorsshown in Figure 4 , and are located next to the J1 and J3 input connectors. R1 and R5 are 50- Ωresistorsfrom each input to ground, and are located on the bottom of the board as shown in Figure 5 .
Figure 4. ISO7220x EVM, Top View
The output channel configuration of the ISO7220x EVM has the OUTA (pin 7) and OUTB (pin 6) ofFigure 1 and Figure 2 connected to SMA connector (J2 and J4) through 0- Ωseries resistor, R4 and R6.
Figure 5. ISO7220x EVM, Bottom View
The pads for R3, R7, C1, C12, C13 and C14 are available on the bottom of the EVM for varied loadingconditions if desired by a user.
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1.5 The ISO7221x EVM Configuration
INA
OUTB
R8
R4
R6
INB
OUTA
R2
INA
OUTB
R7
R1
OUTA
INB
Introduction www.ti.com
The ISO7221x EVM configuration has SMA connectors (J4 and J1) set up as the input to the INA (pin 7)and INB (pin 3) of the ISO7221x in Figure 1 and Figure 3 .R2 and R6 are 0- Ωinput series resistors shownin Figure 6 , and are located next to the J1 and J4 input connectors.
Figure 6. The ISO7221x EVM Top View
The output channel configuration of the ISO7221x EVM has the OUTA (pin 2) and OUTB (pin 6) ofFigure 1 and Figure 3 connected to SMA connector (J3 and J2) through 0- Ωseries resistor, R8 and R4.
R1 and R7 are 50- Ωresistors from each input to ground on the bottom of the board shown in Figure 7 .
Figure 7. The ISO7221x EVM Bottom View
The pads for R3, R5, C1, C12, C13 and C14 are available on the bottom of the EVM for varied loadingconditions if desired by a user.
Dual-Channel Digital Isolator EVM6 SLLU098A – June 2007 – Revised July 2009Submit Documentation Feedback

2 EVM Setup and Operation
2.1 Overview
J3
J2
P1 P3 P2 P4
Power Supply Power Supply
Tektronix
HFS9009
Pattern
Generator
Tektronix
784D
Scope
Vcc1Vcc2GND2
GND1
INPUT
OUTPUT
J4 OUTPUT
J1 INPUT
www.ti.com EVM Setup and Operation
This section includes the setup and operation of the EVM for parameter performance evaluation. Typicalwaveforms are included.
The basic setup in Figure 5 has the two power supplies required to evaluate isolator performance with3.3-V on one side and 5-V on the other. If both sides are to be evaluated at the same supply voltage, onlyone power supply is required and can be used to power both sides of the EVM.
CAUTION
Note that this EVM is for operating parameter performance evaluation only andnot designed for isolation voltage testing. Any voltage applied above the 5.5-Vmaximum recommended operating voltage of the digital isolators will damagethe EVM.
Figure 8. Basic EVM Operation
In Figure 8 , the J3 input to the EVM is a 20 MHz pulse displayed on channel 1 in Figure 9 . The J4 outputof the EVM is channel 2.
Figure 9. Typical Input and Output Waveforms
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EVALUATION BOARD/KIT IMPORTANT NOTICE
Texas Instruments (TI) provides the enclosed product(s) under the following conditions:This evaluation board/kit is intended for use for ENGINEERING DEVELOPMENT, DEMONSTRATION, OR EVALUATION PURPOSESONLY and is not considered by TI to be a finished end-product fit for general consumer use. Persons handling the product(s) must haveelectronics training and observe good engineering practice standards. As such, the goods being provided are not intended to be completein terms of required design-, marketing-, and/or manufacturing-related protective considerations, including product safety and environmentalmeasures typically found in end products that incorporate such semiconductor components or circuit boards. This evaluation board/kit doesnot fall within the scope of the European Union directives regarding electromagnetic compatibility, restricted substances (RoHS), recycling(WEEE), FCC, CE or UL, and therefore may not meet the technical requirements of these directives or other related directives.Should this evaluation board/kit not meet the specifications indicated in the User’s Guide, the board/kit may be returned within 30 days fromthe date of delivery for a full refund. THE FOREGOING WARRANTY IS THE EXCLUSIVE WARRANTY MADE BY SELLER TO BUYERAND IS IN LIEU OF ALL OTHER WARRANTIES, EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING ANY WARRANTY OFMERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE.The user assumes all responsibility and liability for proper and safe handling of the goods. Further, the user indemnifies TI from all claimsarising from the handling or use of the goods. Due to the open construction of the product, it is the user’s responsibility to take any and allappropriate precautions with regard to electrostatic discharge.EXCEPT TO THE EXTENT OF THE INDEMNITY SET FORTH ABOVE, NEITHER PARTY SHALL BE LIABLE TO THE OTHER FOR ANYINDIRECT, SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES.TI currently deals with a variety of customers for products, and therefore our arrangement with the user is not exclusive.
TI assumes no liability for applications assistance, customer product design, software performance, or infringement of patents orservices described herein.
Please read the User’s Guide and, specifically, the Warnings and Restrictions notice in the User’s Guide prior to handling the product. Thisnotice contains important safety information about temperatures and voltages. For additional information on TI’s environmental and/orsafety programs, please contact the TI application engineer or visit www.ti.com/esh .No license is granted under any patent right or other intellectual property right of TI covering or relating to any machine, process, orcombination in which such TI products or services might be or are used.FCC Warning
This evaluation board/kit is intended for use for ENGINEERING DEVELOPMENT, DEMONSTRATION, OR EVALUATION PURPOSESONLY and is not considered by TI to be a finished end-product fit for general consumer use. It generates, uses, and can radiate radiofrequency energy and has not been tested for compliance with the limits of computing devices pursuant to part 15 of FCC rules, which aredesigned to provide reasonable protection against radio frequency interference. Operation of this equipment in other environments maycause interference with radio communications, in which case the user at his own expense will be required to take whatever measures maybe required to correct this interference.
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EVM WARNINGS AND RESTRICTIONS
It is important to operate this EVM within the input voltage range of 0 V to 5.5 V and the output voltage range of 0 V to 6 V.Exceeding the specified input range may cause unexpected operation and/or irreversible damage to the EVM. If there are questionsconcerning the input range, please contact a TI field representative prior to connecting the input power.Applying loads outside of the specified output range may result in unintended operation and/or possible permanent damage to the EVM.Please consult the EVM User's Guide prior to connecting any load to the EVM output. If there is uncertainty as to the load specification,please contact a TI field representative.During normal operation, some circuit components may have case temperatures greater than 85 °C. The EVM is designed to operateproperly with certain components above 85 °C as long as the input and output ranges are maintained. These components include but arenot limited to linear regulators, switching transistors, pass transistors, and current sense resistors. These types of devices can be identifiedusing the EVM schematic located in the EVM User's Guide. When placing measurement probes near these devices during operation,please be aware that these devices may be very warm to the touch.
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265Copyright © 2009, Texas Instruments Incorporated

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