Texas Instruments ADS8353-Q1 User manual

User’s Guide
ADS8353Q1EVM-PDK Evaluation Module
ABSTRACT
This user's guide describes the characteristics, operation, and use of the ADS8353-Q1 evaluation module
(EVM) performance demonstration kit (PDK). This kit is an evaluation platform for the ADS8353-Q1 device,
which is a 16-bit, dual-channel, simultaneous-sampling, 600-kSPS, single-ended and pseudo-differential analog
input, successive approximation register (SAR) analog-to-digital converter (ADC) that features an easy-to-use
serial programming interface (SPI). The ADS8353Q1EVM-PDK eases evaluation with hardware, software, and
computer connectivity through the universal serial bus (USB) interface. This user's guide includes complete
circuit descriptions, schematic diagrams, and a bill of materials (BOM).
The following related documents are available through the Texas Instruments website.
Table 1-1. Related Documentation
Device Literature Number
ADS8353-Q1 SBAS931
OPA320-Q1 SLOS884
TPS7A47-Q1 SBVS118
REF34-Q1 SBAS901A
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Table of Contents
1 Overview..................................................................................................................................................................................3
1.1 ADS8353Q1EVM-PDK Features....................................................................................................................................... 3
1.2 ADS8353-Q1EVM Features...............................................................................................................................................3
2 Analog Interface......................................................................................................................................................................4
2.1 Connectors for Analog Inputs.............................................................................................................................................4
2.2 ADC Input Signal Driver..................................................................................................................................................... 5
3 Digital Interfaces.....................................................................................................................................................................6
3.1 SPI for the ADC Digital I/O.................................................................................................................................................6
4 Power Supplies....................................................................................................................................................................... 7
4.1 ADC Input Driver Configuration..........................................................................................................................................7
4.2 ADC Voltage Reference Configuration...............................................................................................................................7
5 ADS8353Q1EVM-PDK Initial Setup........................................................................................................................................8
5.1 Default Jumper Settings.....................................................................................................................................................8
5.2 EVM Graphical User Interface Software Installation.......................................................................................................... 9
6 ADS8353Q1EVM-PDK Operation.........................................................................................................................................12
6.1 EVM GUI Global Settings for ADC Control...................................................................................................................... 13
6.2 Time Domain Display Tool................................................................................................................................................14
6.3 Spectral Analysis Tool...................................................................................................................................................... 15
6.4 Histogram Analysis Tool...................................................................................................................................................16
7 Bill of Materials, Printed-Circuit Board Layout, and Schematics.....................................................................................17
7.1 Bill of Materials.................................................................................................................................................................17
7.2 PCB Layout...................................................................................................................................................................... 19
7.3 Schematics.......................................................................................................................................................................20
8 Revision History................................................................................................................................................................... 29
List of Figures
Figure 2-1. ADS8353-Q1EVM Analog Input Path........................................................................................................................5
Figure 5-1. ADS8353Q1EVM-PDK Jumper Locations................................................................................................................ 8
Figure 5-2. ADS835x EVM Software Installation Prompts...........................................................................................................9
Figure 5-3. Device Driver Installation Wizard Prompts.............................................................................................................. 10
Figure 5-4. LabVIEW Run-Time Engine Installation.................................................................................................................. 11
Figure 5-5. ADS835x EVM Software Installation Final Step...................................................................................................... 11
Figure 6-1. EVM-PDK Hardware Setup and LED Indicators..................................................................................................... 12
Figure 6-2. Launch the EVM GUI Software............................................................................................................................... 12
Figure 6-3. EVM GUI Global Input Parameters......................................................................................................................... 13
Figure 6-4. Time Domain Display Tool Options......................................................................................................................... 14
Figure 6-5. Spectral Analysis Tool............................................................................................................................................. 15
Figure 6-6. Histogram Analysis Tool.......................................................................................................................................... 16
Figure 7-1. ADS8353-Q1EVM PCB Layer 1: Top Layer............................................................................................................ 19
Figure 7-2. ADS8353-Q1EVM PCB Layer 2: GND Plane..........................................................................................................19
Figure 7-3. ADS8353-Q1EVM PCB Layer 3: Power Planes......................................................................................................19
Figure 7-4. ADS8353-Q1EVM PCB Layer 4: Bottom Layer...................................................................................................... 19
Figure 7-5. Schematic Diagram (Page 1) of the ADS8353-Q1EVM PCB..................................................................................20
Figure 7-6. Schematic Diagram (Page 2) of the ADS8353-Q1EVM PCB..................................................................................21
Figure 7-7. Schematic Diagram (Page 3) of the ADS8353-Q1EVM PCB..................................................................................22
List of Tables
Table 1-1. Related Documentation.............................................................................................................................................. 1
Table 2-1. Analog Input Connector Description........................................................................................................................... 4
Table 4-1. Jumper Settings for ADC Input Driver Configuration.................................................................................................. 7
Table 5-1. Default Jumper Configurations................................................................................................................................... 8
Table 6-1. External Source Requirements for Device Evaluation (SNR and THD)....................................................................15
Table 7-1. ADS8353-Q1EVM Bill of Materials........................................................................................................................... 17
Trademarks
LabVIEW™ is a trademark of National Instruments.
Microsoft® and Windows® are registered trademarks of Microsoft Corporation.
All trademarks are the property of their respective owners.
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1 Overview
The ADS8353Q1EVM-PDK evaluation kit includes the ADS8353-Q1EVM board and the precision host interface
(PHI) controller board that enables the accompanying computer software to communicate with the ADC over the
USB for data capture and analysis.
The ADS8353-Q1EVM board includes the ADS8353-Q1 SAR ADC, all the peripheral analog circuits, and the
components required to achieve optimum performance from the ADC.
The PHI controller board primarily serves three functions:
• Provides a communication interface from the EVM to the computer through a USB port
• Provides the digital input and output signals necessary to communicate with the ADS8353-Q1 device
• Supplies power to all active circuitry on the ADS8353-Q1EVM board
Along with the ADS8353-Q1EVM and PHI controller board, this evaluation kit includes an A-to-micro-B USB
cable to connect to a computer.
1.1 ADS8353Q1EVM-PDK Features
The ADS8353Q1EVM-PDK showcases the following features:
• Hardware and software required for diagnostic testing as well as accurate performance evaluation of the
ADS8353-Q1 ADC
• USB powered—no external power supply is required
• The PHI controller board provides a convenient communication interface to the ADS8353-Q1 ADC over USB
2.0 (or higher) for power delivery as well as digital input and output
• Easy-to-use evaluation software for Microsoft® Windows® 7, 64-bit operating systems
1.2 ADS8353-Q1EVM Features
The ADS8353-Q1EVM showcases the following features:
• Onboard low-noise, low-distortion ADC input drivers optimized to meet ADC performance
• Onboard ultra-low noise, low-dropout (LDO) regulators, to generate supplies for the operation amplifier and
ADC
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2 Analog Interface
The ADS8353-Q1 is a low-power, dual-channel, simultaneous-sampling ADC that supports single-ended and
pseudo-differential analog inputs. The ADS8353-Q1EVM uses an OPA320-Q1 to drive the analog inputs (AINP
and AINM) of the ADC. The ADS8353-Q1EVM is designed for easy interfacing to analog sources. This section
describes the front-end driver circuitry details, including jumper configurations for the analog input signal source.
2.1 Connectors for Analog Inputs
The ADS8353-Q1EVM has two 16-bit, simultaneous-sampling ADCs. The ADS835x EVM GUI can either be
configured for individual ADC data sampling or simultaneous sampling with both ADCs. The ADS8353-Q1EVM
is designed to interface to an external, analog source through either subminiature version A (SMA) connectors
or 100-mil headers. Jumpers J2, J3, J4, and J5 are the SMA connectors that allow for analog signal source
connectivity through coaxial cables. Alternatively, 100-mil jumper cables or mini-grabbers can be used to
connect analog sources to pin 1 of connectors JP1, JP2, JP3, and JP4. Table 2-1 lists the analog input
connectors for the individual ADCs.
Table 2-1. Analog Input Connector Description
Pin Number Signal Description
J2 and J3 INP Analog inputs provided at the SMA for ADC A
JP1[1] and JP2[1] INP Alternate location to provide the analog inputs for ADC A
J4 and J5 INP Analog inputs provided at the SMA for ADC B
JP3[1] and JP4[1] INP Alternate location to provide the analog inputs for ADC B
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2.2 ADC Input Signal Driver
The SAR ADC inputs terminate in switched-capacitor networks that create large instantaneous current loads
when the switches are closed, which effectively makes the ADC inputs dynamically low impedance. The analog
inputs of the ADC are therefore driven by an OPA320-Q1 used in a unity-gain buffer configuration to maintain
ADC performance with maximum loading at full device throughput of the ADS8353-Q1 of 600 kSPS.
2.2.1 Input Signal Path
Figure 2-1 shows the signal path for the analog inputs applied to the ADS8353-Q1EVM. A separate OPA320-Q1
amplifier is used in a unity-gain buffer configuration to drive the individual analog inputs (AINP and AINM) of
each ADC. There is onboard provisioning that enables configuring the OPA320-Q1 driver circuit to drive either
single-ended ADC inputs or pseudo-differential ADC inputs. An RC filter with values of 49 Ω and 3.3 nF was
selected to achieve a SINAD greater than 83 dB and a THD less than –100 dB for a 2-kHz sine-wave input at full
throughput of the ADS8353-Q1 of 600 kSPS.
AVDD
AVDD
OPA320-Q1
AINP
GND
ADS8353-Q1
ADC A
49

+
3.3nF
VIN
–
+
–AINM
49 
VDC
AVDD
AVDD
OPA320-Q1
AINP
GND
ADC B
Input Driver
49

+
VIN
–
+
–AINM
49

VDC
3.3nF
3.3nF
3.3nF
VDC is connected to GND for single ended configuration
VDC is connected to VREF/2 or VREF for pseudo-differential configuration
SPI
Interface
Figure 2-1. ADS8353-Q1EVM Analog Input Path
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3 Digital Interfaces
As discussed in Section 1, the ADS8353-Q1EVM interfaces with the PHI, which in turn communicates with the
computer over the USB. The PHI also communicates with the EEPROM over the I2C interface. The electrically
erasable programmable read-only memory (EEPROM) comes preprogrammed with the information required to
configure and initialize the ADS8353Q1EVM-PDK platform. When the hardware is initialized, the EEPROM is no
longer used.
3.1 SPI for the ADC Digital I/O
The ADS8353Q1EVM-PDK supports the interface and ADC input modes detailed in the ADS8353-Q1 data
sheet. The PHI is capable of operating at a 3.3-V logic level and is directly connected to the digital I/O lines of
the ADC.
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4 Power Supplies
The ADS8353-Q1 supports a wide range of operation on the analog supplies. The AVDD operates from 4.5 V
to 5.5 V. The DVDD operates from 1.65 V to 5.5 V, independent of the AVDD supply. The analog portion of the
ADS8353-Q1EVM operates from a 5.3-V supply (VA) generated using the TPS7A47-Q1 low-noise, low-dropout
regulator. The same supply is used to power the OPA320-Q1 front-end driver amplifiers.
The TPS7A47-Q1 regulator can be configured to generate a VA supply other than 5.3 V through programmable
pin settings. For more information, see the Detailed Description section of the TPS7A47-Q1 device data sheet.
The digital portion of the ADC operates from a 3.3-V EVM_DVDD supply from the PHI.
4.1 ADC Input Driver Configuration
The ADS8353-Q1 supports modes where the ADC inputs can be configured as single-ended or pseudo-
differential. The ADS8353-Q1 EVM allows the user to configure the ADC input driver amplifier either to drive
single-ended ADC inputs or pseudo-differential ADC inputs. In the single-ended configuration, the individual
ADC AINM pins are connected to ground and a unipolar signal is applied to AINP. In the pseudo-differential
configuration, the individual ADC AINM pins are driven with a DC voltage of either VREF / 2 (0 V to VREF range)
or VREF (0 V to 2 × VREF range). For various analog input full-scale ranges supported by the ADS8353-Q1 in
either single-ended or pseudo-differential mode, see the ADS8353-Q1 data sheet. Table 4-1 shows the jumper
configurations required for the single-ended and pseudo-differential configurations.
Table 4-1. Jumper Settings for ADC Input Driver Configuration
ADC Input Type ADC Input Full-Scale Range Default Jumper
Setting Required Jumper Setting
Single-ended analog inputs 0 V to VREF and 0 V to 2 × VREF
J6, J7 = Open Short pins J6[2-3] and J7[2-3]
JP6, JP7 = Open Open
Pseudo-differential analog
inputs
0 V to VREF
J6, J7 = Open Short pins J6[1-2] and J7[1-2]
JP6, JP7 = Open Short pins JP6[1-2] and JP7[1-2]
0 V to 2 × VREF
J6, J7 = Open Short pins J6[1-2] and J7[1-2]
JP6, JP7 = Open Open
4.2 ADC Voltage Reference Configuration
The ADS8353-Q1 has a low-noise, low-drift, 2.5-V internal voltage reference. By default, the ADS8353-Q1 EVM
is configured to work with the ADC internal reference voltage of 2.5 V. The same reference voltage is brought
on pin 1 of jumpers JP6 and JP7 that can be used to drive the ADC AINM pin when used in pseudo-differential
configuration (either in 0 V to VREF or 0 V to 2 × VREF analog input range).
There is also a provision for using an external voltage reference for the ADC. The external reference voltage can
be generated by populating the REF34-Q1 (U8), the two OPA320-Q1 (U9, U10) and biasing components around
U8, U9, and U10. By default, the external reference, amplifiers and biasing components around U8, U9, and U10
are not populated on the board. When using an external reference, the ADS8353-Q1 internal voltage reference
must be disabled and the device must be programmed to accept the external reference voltage on the REFIO_x
pins.
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5 ADS8353Q1EVM-PDK Initial Setup
This section explains the initial hardware and software setup procedure that must be completed for proper
operation of the ADS8353Q1EVM-PDK.
5.1 Default Jumper Settings
Figure 5-1 shows the silkscreen plot, which details the jumper locations for the ADS8353Q1EVM-PDK.
Figure 5-1. ADS8353Q1EVM-PDK Jumper Locations
Table 5-1 lists the functionality and default configuration of each jumper.
Table 5-1. Default Jumper Configurations
Reference Designator Default Configuration Description
JP1, JP2, JP3, JP4 Open Use pin 1 of these jumpers as an alternate location to provide the analog input to ADC A and
ADC B of the ADS8353-Q1.
JP5 Open Connect this jumper to disable EEPROM write protection.
JP6, JP7 Open Jumpers to feed either VREF or VREF / 2 to the OPA320-Q1 input driving the AINM pin of the ADC.
See Section 7.3 for more details.
J6, J7 Closed [2-3] Jumpers to configure the ADC inputs as single-ended or pseudo-differential. By default, jumpers
set to single-ended as AINM_A, AINM_B = GND. See Section 7.3 for more details.
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5.2 EVM Graphical User Interface Software Installation
The following steps describe how to install the software for the ADS835x EVM graphical user interface (GUI).
1. Download the latest version of the EVM GUI installer from the Order and start development section of
the ADS8353-Q1EVM-PDK Tool Folder, and run the GUI installer to install the EVM GUI software on your
computer.
CAUTION
Manually disable any antivirus software running on the computer before downloading the EVM
GUI installer onto the local hard disk. Failure to disable antivirus software, depending on the
antivirus settings, can cause an error message to appear or the installer.exe file can be deleted.
2. Accept the license agreements (Figure 5-2) and follow the on-screen instructions to complete the installation.
Figure 5-2. ADS835x EVM Software Installation Prompts
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3. As a part of the ADS835x EVM GUI installation, a prompt with a Device Driver Installation Wizard (Figure
5-3) appears on the screen. Click the Next button to proceed, then click the Finish button when the
installation is complete.
Figure 5-3. Device Driver Installation Wizard Prompts
Note
A notice can appear on the screen stating that Windows cannot verify the publisher of this driver
software. Select the Install this driver software anyway option.
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