Texas Instruments SWIFT TPS548A20 User manual

User’s Guide
TPS548A20 SWIFT™ Step-Down Converter Evaluation
Module User's Guide
Table of Contents
1 Introduction.............................................................................................................................................................................2
2 Description.............................................................................................................................................................................. 3
2.1 Typical Applications............................................................................................................................................................3
2.2 Features............................................................................................................................................................................. 3
3 Electrical Performance Specifications................................................................................................................................. 4
4 Schematic................................................................................................................................................................................5
5 Test Setup................................................................................................................................................................................7
5.1 Test Equipment.................................................................................................................................................................. 7
5.2 Recommended Test Setup.................................................................................................................................................8
6 Configurations........................................................................................................................................................................ 9
6.1 Switching Frequency Selection.......................................................................................................................................... 9
6.2 Mode Selection.................................................................................................................................................................. 9
6.3 VDD Pin Supply Selection................................................................................................................................................10
7 Test Procedure...................................................................................................................................................................... 11
7.1 Line and Load Regulation and Efficiency Measurement Procedure.................................................................................11
7.2 Control-Loop Gain and Phase-Measurement Procedure................................................................................................. 11
7.3 List of Test Points............................................................................................................................................................. 12
7.4 Equipment Shutdown....................................................................................................................................................... 12
8 EVM Assembly Drawing and PCB Layout.......................................................................................................................... 13
9 Bill of Materials..................................................................................................................................................................... 17
10 Revision History................................................................................................................................................................. 18
List of Figures
Figure 4-1. TPS548A20EVM-737 Schematic.............................................................................................................................. 6
Figure 5-1. Tip and Barrel Measurement for Output Voltage Ripple............................................................................................7
Figure 5-2. TPS548A20EVM-587 Top Layer for Test Setup........................................................................................................ 8
Figure 8-1. TPS548A20EVM-587 Top-Layer Assembly Drawing.............................................................................................. 13
Figure 8-2. TPS548A20EVM-587 Bottom-Layer Assembly Drawing.........................................................................................13
Figure 8-3. TPS548A20EVM-587 Top Layer, Copper................................................................................................................14
Figure 8-4. TPS548A20EVM-587 Layer Two, Copper...............................................................................................................14
Figure 8-5. TPS548A20EVM-587 Layer Three, Copper............................................................................................................15
Figure 8-6. TPS548A20EVM-587 Layer Four, Copper.............................................................................................................. 15
Figure 8-7. TPS548A20EVM-587 Layer Five, Copper.............................................................................................................. 16
Figure 8-8. TPS548A20EVM-587 Bottom Layer, Copper.......................................................................................................... 16
List of Tables
Table 3-1. TPS548A20EVM-737 Electrical Performance Specifications(1) .................................................................................4
Table 4-1. Device Pin-Out Difference Summary.......................................................................................................................... 5
Table 6-1. Switching Frequency Selection...................................................................................................................................9
Table 6-2. Mode Selection........................................................................................................................................................... 9
Table 6-3. Enable Selection....................................................................................................................................................... 10
Table 7-1. Test Point Functions..................................................................................................................................................12
Table 9-1. EVM Components List (Based on the Schematic, See Figure 4-1).......................................................................... 17
Trademarks
D-CAP3™ is a trademark of TI.
All trademarks are the property of their respective owners.
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1 Introduction
The TPS548A20EVM-737 evaluation module (EVM) uses the TPS548A20 device. The TPS548A20 device is a
D-CAP3™ mode, 15-A synchronous buck-converter with integrated MOSFETs. The device provides a fixed 1.2-V
output at up to 15 A from a 12-V input bus.
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2 Description
The TPS548A20EVM-737 is designed for a regulated 12-V bus to produce a regulated 1.2-V output at up to
15 A of load current. The TPS548A20EVM-737 is designed to demonstrate the TPS548A20 device in a typical
low-voltage application while providing a number of test points to evaluate the performance of the TPS548A20
device.
2.1 Typical Applications
• Servers and storage
• Workstations and desktops
• Telecommunication infrastructure
2.2 Features
The TPS548A20EVM-737 features include the following:
• 15-A DC steady-state output current
• Support for a prebias-output voltage at startup
• Jumper, J2, for enable function
• Jumper, J5, for auto-skip and forced-continuous-conduction-mode (FCCM) selection
• Jumper, J7, for extra 5-V input for further power saving purpose
• Convenient test points for probing critical waveforms
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3 Electrical Performance Specifications
Table 3-1. TPS548A20EVM-737 Electrical Performance Specifications(1)
PARAMETER TEST CONDITIONS MIN TYP MAX UNITS
INPUT CHARACTERISTICS
Voltage range VIN 5 12 18 V
Maximum input current VIN = 5 V, IO = 8 A 2.5 A
No load input current VIN = 12 V, IO = 0 A with auto-skip mode 1 mA
OUTPUT CHARACTERISTICS
Output voltage VOUT 1.2 V
Output voltage regulation Line regulation (VIN = 5 V – 14 V) with FCCM 0.2 %
Load regulation (VIN = 12 V, IO = 0 A – 8 A) with FCCM 0.5
Output voltage ripple VIN = 12 V, IO = 8 A with FCCM 10 mVpp
Output load current 0 15 A
Output over current 15 A
Soft-start 1 ms
SYSTEMS CHARACTERISTICS
Switching frequency VIN = 12 V, 1.2 V / 4 A 1000 kHz
Peak efficiency VIN = 12 V, 1.2 V / 8 A 88.5 %
Full load efficiency 86.9 %
Operating temperature 25 °C
(1) Jumpers set to default locations, See Section 6.
Electrical Performance Specifications www.ti.com
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4 Schematic
Figure 4-1 shows the schematic of the TPS548A20EVM-737 .
The TPS548A20 device is similar to the TPS549A20 device which offers PMBus interface. Table 4-1 lists the
differences in pin functions of the TPS548A20 and TPS549A20.
Table 4-1. Device Pin-Out Difference Summary
PIN NO. PIN NAMES
TPS549A20 TPS548A20
26 ALERT NC
27 SDA GND1
28 SCL GND1
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4.1
REG
SW
PGOOD
ADDR/RF
TRIP
AGND
MODE
PMBus Connector
Input: 8-14V
Output: 1.2V/0-6A
Ext. VDD
LabView Connector
1.00k
R3
1 2
3 4
5 6
7 8
9 10
J4
61301021121
100k
R2
30k
R10
0.1µF
C5
TP1
TP4
0
R8
TP3TP2
330µF
C15
DNP
1.91k
R7 DNP
0.1µF
C9
1µF
C20
22µF
C6
TP13
1uH
L1
RF 1
PGOOD 2
EN 3
VBST
4
NC 5
SW
6SW
7SW 8SW 9
PGND
10 PGND 11 PGND 12 PGND 13 PGND 14
VIN 15 VIN 16 VIN 17
NC 18
VDD 19
VREG 20
MODE 21
GND
22
FB
23
VO
24 TRIP 25
DNC 26
GND1
27 GND2 28
PAD
29
U1
TPS548A20RVER
1.00
R16
VREG
VREG
VIN
VOUT
SW
PGOOD
AG ND
AG ND
AG ND
VIN
VOUT
PGN D
AG ND
PGN D
PGN D
FB
VREG
PGN D
VREG
PGN D
PGN D
MODE
AG ND
VOUT
VREG
VDD
PGOOD
22µF
C19
22µF
C21
22µF
C22
22µF
C23
22µF
C10
22µF
C11
22µF
C12
22µF
C13
22µF
C14
330µF
C16
22µF
C1
22µF
C2
22µF
C3
22µF
C4 330µF
C24
330µF
C27
DNP
1nF
C17
470pF
C8
3.01
R9
TP15
0
R5
0.1µF
C7
TP6
TP7
TP9
300k
R4
TP10
100k
R15
100k
R14
TP11
0
R19
1µF
C25
TP14
1µF
C26
1µF
C18
1 2
3 4
5 6
7 8
9 10
J6
61301021121
1 2
3 4
5 6
7 8
9 10
J5
61301021121
PGND
SW
CHB CHA
10.0k
R20
10.0
R22
FB
VOUT
AG ND
FB
TP5
TP8
10.0k
R21
OPEN= ENABLE
EN
100k
R1
TP12
200k
R6
VDD
AGND
VDD
VIN
PGND
PGND
VOUT
VDD
1
2
J1
1
2
J2
SW
VOUT
VDD
VIN
20.0k
R11
150k
R12
AG ND
VREG
PGOOD
150k
R13
1
2
J7
1
2
J3
PGND
PGND
1
TPS548A20
NOTES:
PIN 26
PIN 27
PIN 28
TPS549A20
ALERT#
SDA
SCL
NC
GND1
GND2
IC
VARIANT PIN-OUT FOR U1
TABLE 1
Figure 4-1. TPS548A20EVM-737 Schematic
Schematic www.ti.com
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5 Test Setup
5.1 Test Equipment
Oscilloscope A digital or analog oscilloscope measures the output ripple. The oscilloscope must be set for
the following: 1-MΩ impedance, 20-MHz bandwidth, AC coupling, 1-µs per division horizontal
resolution, 20-mV per division vertical resolution. Test points TP7 and TP9 measure the output
ripple voltage by placing the oscilloscope probe tip through TP7 and holding the ground barrel
on TP9 as shown in Figure 5-1. Using a leaded ground connection can induce additional noise
due to the large ground loop.
Voltage Source The input voltage source VIN must be a 0 to 14-V variable-DC source capable of supplying 10
ADC. Connect VIN to J1 as shown in Figure 5-2.
Multimeters V1: VIN at TP1 (VIN) and TP4 (GND).
V2: VOUT at TP7 (VOUT) and TP9 (GND).
Output Load The output load must an electronic constant-resistance-mode load capable of 0 to 15 ADC at
1.2 V.
T 9P
T 7P
Metal Ground Barrel
Probe Tip
Figure 5-1. Tip and Barrel Measurement for Output Voltage Ripple
Recommended Wire Gauge:
1. VIN to J1 (12-V input)
• The recommended wire size is 1× AWG number 14 per input connection, with the total length of wire less
than 4 feet (2 feet input, 2 feet return).
2. J3 to LOAD
• The minimum recommended wire size is 2× AWG number 14, with the total length of wire less than 4 feet
(2 feet output, 2 feet return).
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5.2 Recommended Test Setup
Figure 5-2. TPS548A20EVM-587 Top Layer for Test Setup
Input Connections:
1. Prior to connecting the DC input-source, VIN, TI recommends to limit the source current from VIN to 10 A
maximum. Ensure that VIN is initially set to 0 V and connected as shown in Figure 5-2.
2. Connect the voltmeter V1 at TP1 (VIN) and TP4 (GND) to measure the input voltage.
Output Connections:
1. Connect the load to J3 and set the load to constant-resistance-mode to sink 0 ADC before VIN is applied.
2. Connect the voltmeter V2 at TP7 (VOUT) and TP9 (GND) to measure the output voltage.
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6 Configurations
All Jumper selections must be made prior to applying power to the EVM. Configure this EVM using the following
configuration selections.
6.1 Switching Frequency Selection
Switching frequency can be changed as shown in Table 6-1.
Table 6-1. Switching Frequency Selection
SWITCHING
FREQUENCY(1)
(ƒSW) (kHz)
RESISTOR DIVIDER RATIO
(RDR)
EXAMPLE RF FREQUENCY
COMBINATIONS
RRF_H (kΩ) RRF_L (kΩ)
1000 > 0.557 1 300
850 0.461 180 154
750 0.375 200 120
600 0.297 249 105
500 0.229 240 71.5
400 0.16 249 47.5
300 0.096 255 27
200 < 0.041 270 11.5
(1) Default Setting: 1 MHz.
For different switching frequency setting, please change R3 and R4 as shown in Table 6-1.
6.2 Mode Selection
The MODE can be set by J5.
Table 6-2. Mode Selection
JUMPER SET TO: MODE SELECTION
1 to 2 pin shorted FCCM with 2x RC time constant
3 to 4 pin shorted(1) FCCM(2) with 1x RC time constant(1)
5 to 6 pin shorted FCCM(2) with 2x RC time constant
7 to 8 pin shorted Auto-skip mode with 2× RC time constant
9 to 10 pin shorted Auto-skip mode with 1× RC time constant
(1) Default setting.
(2) The device enters FCCM after PGOOD goes high.
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6.3 VDD Pin Supply Selection
The controller can be enabled and disabled by J7.
Table 6-3. Enable Selection
SET ON CONNECTION ENABLE SELECTION
R19 = 0 Ω(1) VDD pin connected to VIN pins(1)
R19 = Open VDD pin disconnected to VIN pins
(1) Default setting: the VDD pin connected to the VIN pins through R19.
For power-up, input J7 with proper voltage. The VDD pin input voltage range is from 4.5 V to 25 V.
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7 Test Procedure
7.1 Line and Load Regulation and Efficiency Measurement Procedure
1. Set up the EVM as described in Section 5 and Figure 5-2.
2. Ensure the load is set to constant-resistance mode and to sink at 0 ADC.
3. Ensure all jumper setting are configured as shown in Section 6.
4. Ensure the jumper provided in the EVM shorts on J2 before VIN is applied.
5. Increase VIN from 0 to 12 V. Use V1 to measure input voltage.
6. Remove the jumper on J2 to enable the controller.
7. Use V2 to measure the VOUT voltage.
8. Vary the load from 0 to 10 ADC, VOUT must remain in load regulation.
9. Vary VIN from 8 to 14 V, VOUT must remain in line regulation.
10. To disable the converter, place the jumper on J2.
11. Decrease the load to 0 A
12. Decrease VIN to 0 V.
7.2 Control-Loop Gain and Phase-Measurement Procedure
The TPS548A20EVM-737 contains a 10-Ω series resistor in the feedback loop for loop response analysis.
1. Set up the EVM as described in Section 5 and Figure 5-2.
2. Connect the isolation transformer to the test points marked TP5 and TP8.
3. Connect the input-signal amplitude-measurement probe (channel A) to TP10. Connect the output-signal
amplitude-measurement probe (channel B) to TP11.
4. Connect the ground lead of channel A and channel B to TP15.
5. Inject around 20 mV or less signal through the isolation transformer.
6. To measure control-loop gain and phase margin, change the frequency from 100 Hz to 1 MHz using a 10-Hz
or less post filter.
7. Disconnect the isolation transformer from the bode-plot test points before making other measurements.
• Signal injection into feedback can interfere with the accuracy of other measurements.
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7.3 List of Test Points
Table 7-1. Test Point Functions
TEST POINTS NAME DESCRIPTION
TP1 VIN Converter input supply voltage
TP2 VREG LDO voltage
TP3 PGOOD Power good output
TP4 PGND Power ground
TP5 CHB Input B for loop injection
TP6 SW Switch Node
TP7 VOUT VOUT terminal +
TP8 CHA Input A for loop injection
TP9 PGND Power ground
TP10 RF RF pin
TP11 TRIP TRIP pin
TP12 EN Enable pin
TP13 VDD VDD pin
TP14 MODE MODE pin
TP15 AGND Analog ground
7.4 Equipment Shutdown
Follow these steps when shutting down the equipment.
1. Shut down load
2. Shut down VIN
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8 EVM Assembly Drawing and PCB Layout
The following figures show the design of the TPS548A20EVM-737 printed circuit board (see Figure 8-1, Figure
8-2, Figure 8-3, Figure 8-4, Figure 8-5, Figure 8-6, Figure 8-7, and Figure 8-8). The EVM has been designed
using a six-layer, 2-oz copper-circuit board.
Figure 8-1. TPS548A20EVM-587 Top-Layer Assembly Drawing
Figure 8-2. TPS548A20EVM-587 Bottom-Layer Assembly Drawing
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Figure 8-3. TPS548A20EVM-587 Top Layer, Copper
Figure 8-4. TPS548A20EVM-587 Layer Two, Copper
EVM Assembly Drawing and PCB Layout www.ti.com
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Figure 8-5. TPS548A20EVM-587 Layer Three, Copper
Figure 8-6. TPS548A20EVM-587 Layer Four, Copper
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Figure 8-7. TPS548A20EVM-587 Layer Five, Copper
Figure 8-8. TPS548A20EVM-587 Bottom Layer, Copper
EVM Assembly Drawing and PCB Layout www.ti.com
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9 Bill of Materials
Table 9-1. EVM Components List (Based on the Schematic, See Figure 4-1)
Designator Quantity Value Description Package Reference Part Number Manufacturer
C1, C2, C3, C4 4 22 µF Capacitor, ceramic, 25 V, X5R, 10% 1206 GRM31CR61E226KE15L Murata
C5 1 0.1 µF Capacitor, ceramic, 0.1 µF 25 V 10% X5R 0402 0402 GRM155R61E104KA87D Murata
C6, C10, C11, C12,
C13, C14, C19, C21,
C22, C23
10 22 µF Capacitor, ceramic, 6.3 V, X5R, 20% 1206 GRM31CR60J226KE19L Murata
C7 1 0.1 µF Capacitor, ceramic, 0.1 µF 50 V 10% X7R 0603 0603 GRM188R71H104KA93D Murata
C8 1 470 pF Capacitor, ceramic, 470 pF 50 V 10% X7R 0603 0603 GRM188R71H471KA01D Murata
C9, C17 0 Open Capacitor, ceramic, 50 V, X7R, 10% 0603 Standard Standard
C15, C16, C24, C27 0 Open Capacitor, POSCAP, SMT, 2.5 V, 330 µF, 8 mΩ 7343(D) 2R5TPE330M9 or 6TPE330MIL Sanyo
C18, C20, C25, C26 4 1 µF Capacitor, ceramic, 1 µF 16 V 10% X7R 0603 0603 GRM188R71C105KA12J Murata
FID1, FID2, FID3,
FID4, FID5, FID6 0 Fiducial mark. There is nothing to buy or mount. Fiducial N/A N/A
J1, J3 2 ED120/2DS Terminal Block, 2-pin, 15-A, 5,1 mm 0.4 × 0.35 inch ED120/2DS OST
J2 1 PEC02SAAN Header, Male 2-pin, 100-mil spacing, 0.1 × 2 inch PEC02SAAN Sullins
J4, J5, J6 3 PEC05DAAN Header, Male 2×5-pin, 100-mil spacing 0.1 × 2 × 5 inch PEC05DAAN Sullins
J7 1 ED555/2DS Terminal Block, 2-pin, 6-A, 3,5 mm 0.27 × 0.25 inch ED555/2DS OST
L1 1 1 µH Inductor, Power chokes SMD 6,6 × 7,1 mm PIMB065T-1R0MS Cyntec
LBL1 1 Thermal transfer printable labels, 0.650 (W) × 0.2 inch (H) — 10,000
per roll
PCB Label
0.65 (H) × 0.2 inch (W) THT-14-423-10 Brady
R1, R2, R14, R15 4 100k Resistor, 100 kΩ, 1%, 0.1 W, 0603 0603 CRCW0603100KFKEA Vishay-Dale
R3 1 1 kΩ Resistor, 1 kΩ, 1%, 0.1 W, 0603 0603 CRCW06031K00FKEA Vishay-Dale
R4 1 300 kΩ Resistor, 300 kΩ, 1%, 0.1 W, 0603 0603 RC0603FR-07300KL Yageo America
R5, R8, R19 3 0 Resistor, 0 Ω, 5%, 0.1 W, 0603 0603 CRCW06030000Z0EA Vishay-Dale
R6 1 200 kΩ Resistor, 200 kΩ, 1%, 0.1 W, 0603 0603 CRCW0603200KFKEA Vishay-Dale
R7 0 Open Resistor, Chip, 1/16 W, 1% 0603 Standard Standard
R9 1 3.01 Ω Resistor, 3.01 Ω, 1%, 0.125 W, 0805 0805 CRCW08053R01FKEA Vishay-Dale
R10 1 57.6 kΩ Resistor, 57.6 kΩ, 1%, 0.1 W, 0603 0603 RC0603FR-0757K6L Yageo America
R11 1 20.0 kΩ Resistor, 20.0 kΩ, 1%, 0.1 W, 0603 0603 CRCW060320K0FKEA Vishay-Dale
R12, R13 2 150 kΩ Resistor, 150 kΩ, 1%, 0.1 W, 0603 0603 CRCW0603150KFKEA Vishay-Dale
R16 1 1 Ω Resistor, 1 Ω, 1%, 0.1 W, 0603 0603 CRCW06031R00FKEA Vishay-Dale
R20, R21 2 10 kΩ Resistor, 10 kΩ, 1%, 0.1 W, 0603 0603 CRCW060310K0FKEA Vishay-Dale
R22 1 10 Ω Resistor, 10 Ω, 1%, 0.1 W, 0603 0603 CRCW060310R0FKEA Vishay-Dale
TP1, TP2, TP3, TP5,
TP6, TP7, TP8,
TP10, TP11, TP12,
TP13, TP14, TP15
13 5000 Test Point, red, thru hole color keyed 0.1 × 0.1 inch 5000 Keystone
TP4, TP9 2 5001 Test point, black, thru hole color keyed 0.1 × 0.1 inch 5001 Keystone
U1 1 TPS548A20RVE High-performance, 15-A single sync. step-down converter TPS548A20RVE TI
www.ti.com Bill of Materials
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10 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision * (December 2015) to Revision A (August 2021) Page
• Updated the numbering format for tables, figures, and cross-references throughout the document..................2
• Updated user's guide title................................................................................................................................... 2
Revision History www.ti.com
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STANDARD TERMS FOR EVALUATION MODULES
1. Delivery: TI delivers TI evaluation boards, kits, or modules, including any accompanying demonstration software, components, and/or
documentation which may be provided together or separately (collectively, an “EVM” or “EVMs”) to the User (“User”) in accordance
with the terms set forth herein. User's acceptance of the EVM is expressly subject to the following terms.
1.1 EVMs are intended solely for product or software developers for use in a research and development setting to facilitate feasibility
evaluation, experimentation, or scientific analysis of TI semiconductors products. EVMs have no direct function and are not
finished products. EVMs shall not be directly or indirectly assembled as a part or subassembly in any finished product. For
clarification, any software or software tools provided with the EVM (“Software”) shall not be subject to the terms and conditions
set forth herein but rather shall be subject to the applicable terms that accompany such Software
1.2 EVMs are not intended for consumer or household use. EVMs may not be sold, sublicensed, leased, rented, loaned, assigned,
or otherwise distributed for commercial purposes by Users, in whole or in part, or used in any finished product or production
system.
2Limited Warranty and Related Remedies/Disclaimers:
2.1 These terms do not apply to Software. The warranty, if any, for Software is covered in the applicable Software License
Agreement.
2.2 TI warrants that the TI EVM will conform to TI's published specifications for ninety (90) days after the date TI delivers such EVM
to User. Notwithstanding the foregoing, TI shall not be liable for a nonconforming EVM if (a) the nonconformity was caused by
neglect, misuse or mistreatment by an entity other than TI, including improper installation or testing, or for any EVMs that have
been altered or modified in any way by an entity other than TI, (b) the nonconformity resulted from User's design, specifications
or instructions for such EVMs or improper system design, or (c) User has not paid on time. Testing and other quality control
techniques are used to the extent TI deems necessary. TI does not test all parameters of each EVM.
User's claims against TI under this Section 2 are void if User fails to notify TI of any apparent defects in the EVMs within ten (10)
business days after delivery, or of any hidden defects with ten (10) business days after the defect has been detected.
2.3 TI's sole liability shall be at its option to repair or replace EVMs that fail to conform to the warranty set forth above, or credit
User's account for such EVM. TI's liability under this warranty shall be limited to EVMs that are returned during the warranty
period to the address designated by TI and that are determined by TI not to conform to such warranty. If TI elects to repair or
replace such EVM, TI shall have a reasonable time to repair such EVM or provide replacements. Repaired EVMs shall be
warranted for the remainder of the original warranty period. Replaced EVMs shall be warranted for a new full ninety (90) day
warranty period.
WARNING
Evaluation Kits are intended solely for use by technically qualified,
professional electronics experts who are familiar with the dangers
and application risks associated with handling electrical mechanical
components, systems, and subsystems.
User shall operate the Evaluation Kit within TI’s recommended
guidelines and any applicable legal or environmental requirements
as well as reasonable and customary safeguards. Failure to set up
and/or operate the Evaluation Kit within TI’s recommended
guidelines may result in personal injury or death or property
damage. Proper set up entails following TI’s instructions for
electrical ratings of interface circuits such as input, output and
electrical loads.
NOTE:
EXPOSURE TO ELECTROSTATIC DISCHARGE (ESD) MAY CAUSE DEGREDATION OR FAILURE OF THE EVALUATION
KIT; TI RECOMMENDS STORAGE OF THE EVALUATION KIT IN A PROTECTIVE ESD BAG.

www.ti.com
2
3Regulatory Notices:
3.1 United States
3.1.1 Notice applicable to EVMs not FCC-Approved:
FCC NOTICE: This kit is designed to allow product developers to evaluate electronic components, circuitry, or software
associated with the kit to determine whether to incorporate such items in a finished product and software developers to write
software applications for use with the end product. This kit is not a finished product and when assembled may not be resold or
otherwise marketed unless all required FCC equipment authorizations are first obtained. Operation is subject to the condition
that this product not cause harmful interference to licensed radio stations and that this product accept harmful interference.
Unless the assembled kit is designed to operate under part 15, part 18 or part 95 of this chapter, the operator of the kit must
operate under the authority of an FCC license holder or must secure an experimental authorization under part 5 of this chapter.
3.1.2 For EVMs annotated as FCC – FEDERAL COMMUNICATIONS COMMISSION Part 15 Compliant:
CAUTION
This device complies with part 15 of the FCC Rules. Operation is subject to the following two conditions: (1) This device may not
cause harmful interference, and (2) this device must accept any interference received, including interference that may cause
undesired operation.
Changes or modifications not expressly approved by the party responsible for compliance could void the user's authority to
operate the equipment.
FCC Interference Statement for Class A EVM devices
NOTE: This equipment has been tested and found to comply with the limits for a Class A digital device, pursuant to part 15 of
the FCC Rules. These limits are designed to provide reasonable protection against harmful interference when the equipment is
operated in a commercial environment. This equipment generates, uses, and can radiate radio frequency energy and, if not
installed and used in accordance with the instruction manual, may cause harmful interference to radio communications.
Operation of this equipment in a residential area is likely to cause harmful interference in which case the user will be required to
correct the interference at his own expense.
FCC Interference Statement for Class B EVM devices
NOTE: This equipment has been tested and found to comply with the limits for a Class B digital device, pursuant to part 15 of
the FCC Rules. These limits are designed to provide reasonable protection against harmful interference in a residential
installation. This equipment generates, uses and can radiate radio frequency energy and, if not installed and used in accordance
with the instructions, may cause harmful interference to radio communications. However, there is no guarantee that interference
will not occur in a particular installation. If this equipment does cause harmful interference to radio or television reception, which
can be determined by turning the equipment off and on, the user is encouraged to try to correct the interference by one or more
of the following measures:
•Reorient or relocate the receiving antenna.
•Increase the separation between the equipment and receiver.
•Connect the equipment into an outlet on a circuit different from that to which the receiver is connected.
•Consult the dealer or an experienced radio/TV technician for help.
3.2 Canada
3.2.1 For EVMs issued with an Industry Canada Certificate of Conformance to RSS-210 or RSS-247
Concerning EVMs Including Radio Transmitters:
This device complies with Industry Canada license-exempt RSSs. Operation is subject to the following two conditions:
(1) this device may not cause interference, and (2) this device must accept any interference, including interference that may
cause undesired operation of the device.
Concernant les EVMs avec appareils radio:
Le présent appareil est conforme aux CNR d'Industrie Canada applicables aux appareils radio exempts de licence. L'exploitation
est autorisée aux deux conditions suivantes: (1) l'appareil ne doit pas produire de brouillage, et (2) l'utilisateur de l'appareil doit
accepter tout brouillage radioélectrique subi, même si le brouillage est susceptible d'en compromettre le fonctionnement.
Concerning EVMs Including Detachable Antennas:
Under Industry Canada regulations, this radio transmitter may only operate using an antenna of a type and maximum (or lesser)
gain approved for the transmitter by Industry Canada. To reduce potential radio interference to other users, the antenna type
and its gain should be so chosen that the equivalent isotropically radiated power (e.i.r.p.) is not more than that necessary for
successful communication. This radio transmitter has been approved by Industry Canada to operate with the antenna types
listed in the user guide with the maximum permissible gain and required antenna impedance for each antenna type indicated.
Antenna types not included in this list, having a gain greater than the maximum gain indicated for that type, are strictly prohibited
for use with this device.