Texas Instruments XIO2001 User manual

XIO2001
Evaluation Module (EVM)
User's Guide
Literature Number: SCPU031February 2009

2 SCPU031 – February 2009Submit Documentation Feedback

Contents
1 Read This First .................................................................................................................... 41.1 About This Manual ........................................................................................................ 41.2 How to Use This Manual ................................................................................................. 41.3 Information About Cautions and Warnings ............................................................................ 41.4 Related Documentation from Texas Instruments ..................................................................... 42 Overview ............................................................................................................................. 53 EVM Features ...................................................................................................................... 53.1 PCI Express Connector .................................................................................................. 53.2 PCI Add-In Slots .......................................................................................................... 53.3 EEPROM Interface ....................................................................................................... 63.4 Test Header ................................................................................................................ 63.5 Clock Run ( CLKRUN) .................................................................................................... 73.6 JTAG Header .............................................................................................................. 73.7 LEDs ....................................................................................................................... 74 FAQ/Troubleshooting ........................................................................................................... 84.1 BIOS Fails to Assign Memory Window to Bridge ..................................................................... 84.2 ×16 Slots Only Support INTA ............................................................................................ 84.3 System Turns On When PCI Card Is Inserted Into EVM Or When EVM Is Plugged Into Slot.................. 84.4 What To Do If EVM Is Not Working .................................................................................... 85 Schematics ........................................................................................................................ 106 Bill of Materials ................................................................................................................. 14
Important Notices ............................................................................................................... 16
SCPU031 – February 2009 Table of Contents 3Submit Documentation Feedback

1 Read This First
1.1 About This Manual
1.2 How to Use This Manual
1.3 Information About Cautions and Warnings
1.4 Related Documentation from Texas Instruments
User's GuideSCPU031 – February 2009
XIO2001 Evaluation Module (EVM)
This manual describes the operation of the XIO2001 evaluation module (EVM) from Texas Instruments.
This document contains the following sections:•Overview
•EVM Features•FAQ/Troubleshooting
•Schematics
•Bill of Materials
This manual may contain cautions and warnings.
CAUTION
This is an example of a caution statement.
A caution statement describes a situation that could potentially damage yoursoftware or equipment.
WARNINGThis is an example of a warning statement.
A warning statement describes a situation that could potentiallycause harm to you.
Table 1 contains a list of data manuals that have detailed descriptions of the integrated circuits used in thedesign of the TAS3208EVM-LC. The data manuals can be obtained at www.ti.com .
XIO2001 Evaluation Module (EVM)4 SCPU031 – February 2009Submit Documentation Feedback

2 Overview
3 EVM Features
3.1 PCI Express Connector
3.2 PCI Add-In Slots
www.ti.com Overview
Table 1. Related TI Documentation
DOCUMENT LITERATURE NUMBER
XIO2001 Implementation Guide SCPA045XIO2001 Data Manual SCPS212
The XIO2001 evaluation board (EVM) implements a peripheral component interconnect (PCI) express toPCI bridge circuit using the Texas Instruments XIO2001 PCI Express to PCI Bus Translation Bridge.Designed as an ×1 add-in card, it is routed on FR4 as a 8-layer (4 signals, 2 power, and 2 ground) boardwith a 100- Ωdifferential impedance (50- Ωsingle-ended) using standard routing guidelines andrequirements .
(1)
Power for the XIO2001 EVM and any PCI add-in card connected to the EVM is provided or derived fromthe standard voltages provided on the PCI Express connector. Power for the 3.3-V rail is provided directlyfrom the add-in connector, 5-V and 12-V is provided from the IDE power connector, while regulators arepresent to derive 1.5-V for the XIO2001 and -12-V for the PCI connectors.
Upon request, gerber files for the EVM can be provided that illustrate techniques that achieve fan-out ofthe µ*BGA, use of split power planes, placement of filters and other critical components, and methodsused to match lengths on PCI and PCI Express signals on a standard 8-layer board.
Schematics and a Bill of Materials are provided to illustrate the design of this EVM.
Note: Observe proper ESD procedures when handling the EVM. Failure to observe properprocedures may result in damage either to the EVM or the XIO2001 silicon which may causethe board to malfunction.
(1)
As specified in PCI Express Electromechanical Specification, Revision 1.0a and PCI Local Bus Specification, Revision 2.3
The EVM is designed as a half-width PCI Express add-in card. The card fits into any standard ×1, ×2, ×4,×8, or ×16 add-in connector that is compliant with the PCI Express Electromechanical Specification,Revision 2.0 or earlier. In addition to the standard transmit-and-receive pairs, the connector must supply3.3 V, 12 V, PERST, a 100-MHz differential clock, and V
AUX
. The WAKE signal is also supported by theEVM although, as an optional pin, the system is not required to support this signal.
The height of the board is nonstandard due to the presence of PCI slots. Inserting PCI add-in cards intothe EVM will, in most cases, prohibit the EVM from being placed in a case. If possible, provide somemechanical support to the EVM. Otherwise, the weight of PCI add-in cards can strain the board in the PCIExpress add-in slot and may result in the board making poor contact with the connector. Poor connectorcontact can lead to signal integrity issues.
The XIO2001 EVM provides three standard PCI add-in slots. While reversible, these slots, as shipped, arekeyed as 5-V slots and provide a 5-V V
IO
clamping voltage that provides accessibility to any 5-V oruniversally keyed PCI add-in cards. All standard voltages (3.3 V, 5 V, 12 V, and –12 V) are providedthrough the PCI connectors, enabling standard PCI add-in cards to function without requiring externalpower.
Cards placed into the PCI add-in slots must be inserted into the slots in accordance with labeling on theEVM. Referencing the component side of the EVM as front and the PCI express edge connector as down,boards must be inserted with the component side of the board down and the mounting bracket to the leftof the EVM.
SCPU031 – February 2009 XIO2001 Evaluation Module (EVM) 5Submit Documentation Feedback

3.3 EEPROM Interface
3.4 Test Header
EVM Features www.ti.com
WARNINGInserting either a 3.3-V card or a universally keyed card into theEVM backwards will damage the EVM and possibly the add-in cardas well.
The PCI bus operates at 66 MHz only when 66-MHz-capable PCI add-in cards are placed in the socket. Ifa 33-MHz card is inserted into the socket, then the XIO2001 detects the presence of the lower speeddevice and automatically sets the bus speed to 33 MHz. If 66-MHz operation is desired, place no morethan two add-in cards into board slots. (This limitation is due to bus loading issues inherent to the PCIspecification.) If a third 66-MHz device is added to the bus, signal integrity may still permit properfunctioning of the interface, but such functionality cannot be assured and is beyond the scope of thisdocument.
Two of the reserved pins on the PCI add-in connectors are used to route PME and V
AUX
to any add-incards. These assignments, while not part of the PCI Local Bus Specification, are used by many in theindustry as de facto standards and must not interfere with any add-in cards. If cards are used that usethese terminals for other purposes, the following modifications may be made to the EVM to isolate thesignals from the PCI add-in connectors:•PME (routed to reserved terminal A19 on each connector). Remove resistors R55, R53, and R54 (forslots 0, 1, and 2, respectively).•V
AUX
(routed to reserved terminal A14 on each connector). Remove resistors R50, R51, and R52 (forslots 0, 1, and 2, respectively).
Each XIO2001 EVM provides an on-board EEPROM. As shipped, each EEPROM is programmed withvalues that will allow the EVM to function in most systems. The EEPROM interface is left asprogrammable (not write-protected) so that EEPROM contents may be modified for testing other optionalsettings. TI recommends that you do not change the EEPROM values. To change EEPROM contents, usethe EEPROM access registers as detailed in the XIO2001 data manual or request the WinROM accesstool.
Each XIO2001 EVM provides accessibility to the GPIO pins on the XIO2001. From header J1, all fiveGPIOs have external visibility and can be used in any manner consistent with their functionality as detailedin the XIO2001 data manual. All GPIO signals are labeled on the header and are terminated with anon-board pullup resistor.
By default, GPIO3 and GPIO4 are configured as the EEPROM interface which was detailed in theprevious section. The EEPROM interface can be removed from the XIO2001 by removing resistors R28and R29. This allows these GPIO pins to be used for another purpose, although any configuration done bythe EEPROM will then have to be done in some other fashion. While removing R28 and R29 willphysically disconnect the EEPROM from GPIO3/GPIO4, in order to release the pins from this functionality,GPIO4 (SCL) must be held low at the deassertion of PERST. As no pulldown is available for this purpose,the pin must be externally shorted at boot time (deassertion of reset) by shorting J1 pin 5 to J1 pin 11.Once the system has booted, this short may be removed and GPIO3 and GPIO4 will be available for otheruses.
Pin 9 on the J1 header is a global reset (GRST ) for the XIO2001. Driving this pin low will cause allregisters and state machines within the XIO2001 to return to a default power-up state. This pin generallymust remain disconnected.
Pin 10 is an access point for the PME signal and may be used to externally wire this signal to any PCIadd-in card that has the signal available but does not route the signal to pin A19 on the PCI expansionconnector.
6XIO2001 Evaluation Module (EVM) SCPU031 – February 2009Submit Documentation Feedback

3.5 Clock Run ( CLKRUN)
3.6 JTAG Header
3.7 LEDs
www.ti.com EVM Features
Pin 8 on header J1 is CLKREQ for the XIO2001. Driving this pin low will allow the REFCLK to stop whenthe XIO2001 is in PCI PM L1. The CLKREQ protocol as described in the PCI Express Base Specificationand Express Card standard is supported.
Pin 7 on header J1 is PERST for the XIO2001. When asserted, this signal generates an internal PCIExpress reset, clears all non-sticky bit registers and is deasserted when system power is stable.
Pin 12 on header J1 is PCLK66_SEL for the XIO2001 controlling the PCI clock frequency. When thissignal is pulled high, the PCI clock will operate at 33 or 66 Mz depending on the state of M66EN. Whenthis signal is low, the PCI clock will operate at 25 MHz or 50 MHz, depending on the state of M66EN. Mostapplications will pull this pin high.
Pin 2 on the connector is a 3.3-V test point and pin 11 is a ground test point. These signals may be usedto externally toggle GPIOs for any required testing.
The CLKRUN signal is a power-saving mechanism (defined in the PCI Mobile Design Guide) that stopsthe PCI bus clock when the bus is idle. Because devices that do not support this protocol are unable torestart the system clock, this feature is disabled by default on the XIO2001 EVM. This feature may beenabled to function with PCI add-in cards that also support this feature.
Enabling CLKRUN requires that resistor R24 be populated with a 0805 form factor 10-k Ωresistor. Whenthis option is populated at the de-assertion of the reset pin, GPIO0 will internally map to CLKRUN. Whenthis happens, GPIO0 will be unavailable for other purposes. An external wire must then be connected fromGPIO0/ CLKRUN (available on J1 pin 1) to all add-in cards being tested with this functionality.
Each XIO2001 EVM provides access to JTAG interface pins for boundary scan testing on test header JP1.The JTAG interface for the XI02001 complies with IEEE standard 1149 using the standard 5 pin interface(TCK, TDI, TDO, TMS and TRST). If boundary scan testing is not needed, TCK (JP1 pin 10) and TRST(JP1 pin 2) should be connected to GND (JP1 pins 1, 3, 5, 7 or 9). The remainder of the JTAG signals canbe left unconnected. By default the EVM is configured with 0 Ωoption resistors R40 and R77 that connectTRST and TCK to ground.
If boundary scan testing is needed, TI can provide the appropriate BDSL file upon request.
The XIO2001 EVM has LEDs onboard to indicate availability of power and status of certain control signals.The onboard LEDs are as follows:•LED1: 5 V power indicator•LED2: 3.3 V power indicator•LED4: 12 V power indicator•LED5: –12 V power indicator
SCPU031 – February 2009 XIO2001 Evaluation Module (EVM) 7Submit Documentation Feedback

4 FAQ/Troubleshooting
4.1 BIOS Fails to Assign Memory Window to Bridge
4.2 ×16 Slots Only Support INTA
4.3 System Turns On When PCI Card Is Inserted Into EVM Or When EVM Is Plugged Into Slot
4.4 What To Do If EVM Is Not Working
FAQ/Troubleshooting www.ti.com
To use the EVM•Plug the PCI add-in cards into the EVM, oriented as indicated on the board•Place the EVM into a PCI express add-in slot•Turn the system on
From the operating system perspective, the XIO2001 appears to be a standard PCI-to-PCI bridge (PCIheader type 1) and the OS will configure the bridge and any devices behind the bridge accordingly usinglegacy PCI configuration transactions. Following sections of this chapter describe issues that may impairuse of the bridge in a system.
Microsoft operating systems generally attempt to respect the resource allocations made by system BIOS.The XIO2001 requires a memory window in order to access some registers used by the device. If theMicrosoft OS determines that the BIOS failed to assign a memory window to the XIO2001, it will assumethat one cannot be assigned and that the device is nonfunctional. The OS will then assume the bridge isnot functional and will not enumerate devices behind the bus. Consequently, these devices will never beconfigured or assigned resources.
This failure can be determined by examining device manager in the OS. If failure has occurred, the bridgewill appear “banged out” and if the bridge properties are examined the OS will reveal this device cannotfind enough free resources that it can use. (Code 12) If you want to use this device, you will need todisable one of the other devices on this system.
As the x16 PCI express add-in slots are designed as a graphics expansion port, many only support asingle interrupt (INTA ), as this is the only interrupt that will be required by a graphics card. The XIO2001EVM supports all interrupts and balances interrupt loading by rotating the interrupts to each add-in slot asrequired by the PCI Local Bus Specification. Accordingly, any PCI add-in card behind the bridge thatasserts an interrupt other than INTA will not be serviced as the interrupt is not supported by the chipset.Consequently, the add-in card will fail. Any devices that do not require interrupts or that only assert INTA(as routed to the specific slot they are placed in) will still function normally.
As mentioned previously, PME is routed on the EVM to the various PCI slots through a reserved pin thatmany PCI add-in cards use for this purpose. On occasion, when a PCI card is inserted into the EVM(while the EVM is plugged into a board), the add-in card may be inserted in such a way as to pull the PMEline low on the EVM. When this happens, the XIO2001 sees a PCI device trying to wake the system andwill appropriately assert WAKE , which may cause the system to turn on.
Similarly, when the EVM is inserted into the slot, V
AUX
from the connector may not have had enough timeto pull the PME line high (as the on-board pullup resistors dictate), yet V
AUX
may have powered theXIO2001 which now samples PME as low and again wakes the system. This is a limitation of the inabilityto appropriately power the pullup resistors before the XIO2001 is powered. If this occurs, turn power to thesystem off and reboot to ensure the EVM receives a clean reset from the system.
XIO2001 Evaluation Module (EVM)8 SCPU031 – February 2009Submit Documentation Feedback

4.4.1 Check EVM Power
4.4.2 Check If Bridge Is Link Training
4.4.3 Check If Bridge Has Been Configured
www.ti.com FAQ/Troubleshooting
Diodes LED1, LED2, LED4 and LED5 show the status of the 5-V, 3.3-V, 12-V, and –12-V rails,respectively. 1.5 V may be probed on the top pad of C44 (directly next to U3), and –12 V may be probedfrom C100. A ground reference is available at J1 pin 11 and JP1 pins 2, 4, 6, 8 and 10. If any of thesevoltages fail, a problem is likely to occur with EVM functionality. The XIO2001 requires 3.3 V and 1.5 V;other voltages are supplied for use by PCI add-in cards, and PCI V
IO
is by default 5 V (which will causethe entire PCI bus to be clamped to 0.7 V if this voltage is not present). If any of these voltages fail, it islikely that the EVM won’t function because:•XIO2001 will not be powered•The add-in card will not be powered•Neither the XIO2001 or the add-in card will be powered
All voltages have resettable fuses to prevent overcurrent conditions, so if a particular power rail fails:•Detach all devices from the EVM•Remove the EVM from the system•Wait for 30 minutes before trying again
If the system does not boot, remove all PCI add-in cards from EVM and try again. If the system hangsbefore the OS loads, then probably the system and the EVM are having difficulty completing link training (probably an issue with signal integrity on the differential pairs). If a PCI Express analyzer is unavailable,then try a different express slot or a different system if possible. Re-check the 1.5-V rail and examine thedifferential clock on an oscilloscope to ensure it is clean.
If link training successfully completes, the system will boot and the XIO2001 will appear in the devicemanager. If the bridge does not appear in the device manager, then the system may not have detectedthe presence of the bridge, perform the previous checks again.
Also, if the PCI add-in cards have enough weight and there is no mechanical support, the EVM may flexand some components may crack or become disconnected. Check the coupling capacitors on the EVMtransmit lines (C102 and C103). These 0.1- µF 0402 components have a tendency to crack if enoughweight is put on the board; they will need to be replaced if they are damaged.
Once the bridge is communicating with the system, the BIOS and/or the OS are expected to configure thebridge for proper operation. As the bridge appears to software to be a standard PCI-to-PCI bridge, mostexisting BIOS and OS software must be capable of configuring the bridge with no special considerationsfor PCI Express. In addition to the memory window the bridge requests for internal resources, thefollowing items are required for bridge operation:•Command register – PCI offset 0 ×4 : The bus master enable (bit 2), memory enable (bit 1), and I/Oenable (bit 0) must be set to enable the bridge to send upstream transactions.•Cache line size register – PCI offset 0 ×C : Must be set to the cache line size for the system. Failure toset this bit will not cause the bridge to fail but will cause the bridge to limit all upstream transactions to1 DWord.
•Primary, secondary, and subordinate bus numbers– PCI offsets 0 ×18, 0 ×19, and 0 ×1A : The bridgemust have the bus numbers configured so that it can determine which transactions are targeting thebridge, which transactions are targeting devices directly attached to the bridge, and which transactionsare farther downstream from the bridge.•I/O base and limit registers and I/O base upper 16 bits and I/O limit upper 16 bits registers –PCI offsets0×1C, 0 ×1D, 0 ×30 and 0 ×32: If any devices downstream from the bridge require I/O resources, thebridge must be programmed with a window that contains the I/O resources of all devices downstream.Failure to program these windows will cause the bridge to respond to I/O transactions with a responseof Unsupported Request. Any transactions initiated on the secondary side of the bus that fall within thisrange will not be claimed by the bridge. The I/O window for the XIO2001 has a minimum size of 4KBytes and is naturally 4K-aligned. Typically, most systems use only 16-bit addressing for I/Otransactions, so the upper base and limit registers remain 0.
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4.4.4 Check Devices Downstream From Bridge
5 Schematics
Schematics www.ti.com
•Memory base and memory limit registers – PCI offsets 0 ×20 and 0 ×22 : Similar to the I/O base andlimit registers, the bridge must be programmed with a memory address window containing thenonprefetchable memory resources of all downstream PCI devices requiring nonprefetchable memory.Memory windows have a minimum size of 1 MByte and are naturally 1M-aligned. The bridge does notclaim either a memory transaction initiated from upstream that does not fall within its memory windownor memory transactions initiated downstream that do fall within its memory window.•Prefetchable memory base, prefetchable memory limit, prefetchable base upper 32-bit, andprefetchable limit upper 32-bit registers – PCI offsets 0x24, 0x26, 0x28, and 0 ×2C: Identical to thememory base and limit registers but for prefetchable memory resources. The prefetchable base upper32-bit, and prefetchable limit upper 32-bit registers are only used if 64-bit addressing is in use and inmost systems both of these registers will remain all zeroes. If 64-bit addressing is desired and thememory window for devices behind the XIO2001 resides all or in part in 64-bit memory space then theprefetchable base upper 32-bit register will combine with the prefetchable base register and theprefetchable limit upper 32-bit register will combine with the prefetchable limit register to create 64-bitbase and limit registers. All memory addresses between the two addresses will be considered to belocated behind the bridge.•For all base and limit registers any case in which the limit register contains a lower address than thebase register will be considered invalid. In this situation the bridge will react as if all resources of thattype resided upstream of the bridge. The bridge will respond to all downstream transactions of thattype with Unsupported Request and will claim and forward upstream any transactions of that type thatinitiate on the PCI bus.
Depending on desired functionality, other PCI registers on the XIO2001 may have to be configured.Consult the XIO2001 Data Manual for a description of the previous registers or for any other XIO2001registers.
Once the bridge is communicating and is properly configured, check if devices downstream from thebridge have been configured as required. Check the Windows Device Manager to determine if the devicedrivers have been loaded or if other problems exist with the device. Once you have performed thesechecks, you can perform PCI transactions on the bus and examine them with any standard PCI analyzer.
Schematics for the XIO2001 EVM are shown on the following pages.
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PCI_AD 1
PCI_AD 0
PCI_AD 4
PCI_AD 3
PCI_AD 2
PCI_AD 5
PCI_AD 7
PCI_AD 6
PCI_AD 9
PCI_AD 11
PCI_AD 10
PCI_AD 8
PCI_AD 15
PCI_AD 14
PCI_AD 12
PCI_I NTD# 4
PCI_I NTC# 4
PCI_AD 18
PCI_AD 16
PCI_AD 13
PCI_AD 20
PCI_AD 17
PCI_AD 19
PCI_AD 21
PCI_AD 23
PCI_AD 22
PCI_AD 25
PCI_AD 27
PCI_AD 26
PCI_AD 24
PCI_AD 31
PCI_AD 30
PCI_AD 28
PCI_C /BE#0
PCI_C /BE#2
PCI_AD 29
PCI_C /BE#1
PCI_C /BE#3
PCI_F BCLK
C17
0.001uF
cc0805
ECH-U 1H102JB5
PCI_PC LK0
PCI_PC LK1
PCI_PC LK2
PCI_F BCLK
PCI_R EQ#1
PCI_R EQ#2
PCI_R EQ#0
PCI_GN T#2
PCI_GN T#0
PCI_GN T#1
PCI_R EQ#4
PCI_R EQ#5
R19
10K
RR0 805
3. 3V
1. 5V Anal o g
1. 5V 3. 3V Mi sc
POWER
PCI
CL OCKS/ ARBI TER
GND
PCI E
Mi sc
GPI O
JT AG
U6
VDD_15_C OMB N13
VDD_33_C OMBIO K11
VDD_33_C OMB K12
VDD_33_1 E5 VDD_33_2 F6 VDD_33_3 F7 VDD_33_4 F8 VDD_33_5 G6 VDD_33_6 G7 VDD_33_7 H6 VDD_33_8 H7 VDD_33_9 J 11 VDD_15_1 G8 VDD_15_2 H8 VDD_15_3 J 7 VDD_15_4 J 8 VDD_15_5 K13
VDDA_15_1 E12 VDDA_15_2 H12
VDDA_33 C12
VCCP_1 D3 VCCP_2 J 3
VDDPLL_15 F11
VDD_33_AUX J12
AD0 B4
AD1 C5
AD2 C4
AD3 A3
AD4 A2
AD5 C3
AD6 B3
AD7 A1
AD8 B1
AD9 D2
AD10 C1
AD11 D1
AD12 E2
AD13 E1
AD14 E3
AD15 F2
AD16 L1
AD17 K3
AD18 M1
AD19 K2
AD20 L2
AD21 N1
AD22 M2
AD23 L3
AD24 N2
AD25 M4
AD26 L4
AD27 N3
AD28 N4
AD29 M5
AD30 L5
AD31 N5
C/BE#0 C 2
C/BE#1 F 3
C/BE#2 K1
C/BE#3 M3
CLK F1
FRAME# J1
IRD Y # H3
TRDY # J2
DEVSEL# H2
STOP# H1
PAR G1
PERR# G3
SERR# G2
PRST# L7
M66EN M6
LOCK# N8
INTA# N6
INTB# L6
INTC# M7
INTD# N 7
CLKOUT0 B5
CLKOUT1 B6
CLKOUT2 B7
CLKOUT3 A7
CLKOUT4 A8
CLKOUT5 A10
CLKOUT6 C10
REQ0# A4
REQ1# C6
REQ2# C7
REQ3# C8
REQ4# A9
REQ5# C9
GNT0# A5
GNT1# A6
GNT2# B8
GNT3# B9
GNT4# B10
GNT5# B11
VSS1
B12
VSS2
D12
VSS3
E6
VSS4
E7
VSS5
E8
VSS6
E9
VSS7
F5
VSS8
F9
VSS9
F12
VSS10
F13
VSS11
G5
VSS12
G9
VSS13
G12
VSSA_1
H5
VSSA_2
H9
VSSA_3
J5
VSSA_4
J6
VSSA_5
J9
VSSA_6
J13
PERST#
H11
WAKE#
L12
REF0_PC IE
M13
REF1_PC IE
L13
REFC LK-
B13
REFC LK+
C13
RXN
D13
RXP
E13
TXN
G13
TXP
H13
PME#
M12
GRST#
M11
SERIR Q
M8
CLKRU N_EN
C11
EXT_ARB_EN
A12
REFC LK125_SEL
A13
GPIO0_CLKRUN#
N9
GPIO1_PWR _OVER
M9
GPIO2
N10
GPIO3_SDA
L8
GPIO4_SCL
M10
JTAG_TCK
N12
JTAG_TDI
L10
JTAG_TDO
N11
JTAG_TMS
L11
JTAG_TRST#
L9
CLKREQ# D 11
PCLK66_SEL
A11
VREG_PD33 E11
VDD_15_PCIE G11
PERST#
JTAG_TCK
R32 14.3K RR0805
R33 232 RR0805
R20
10K
RR 0805
PCI_AD [31.. 0] 4
PCI_C /BE#[3..0] 4
R6
746_SERIES
R1
1
R2
2
R3
3
R4
4
R5 6
R6 7
R7 8
R8 9
COM1
5
COM2 10
PCI_PC LK[2.. 0] 4
GPIO0
GPIO3
GPIO4
GPIO2
GPIO1
PCLK66_SEL
DVcc _3.3V
R62
10.0K
VREG_PD33
R11
10.0K
DNA
R7
746_SERIES
R1
1
R2
2
R3
3
R4
4
R5 6
R6 7
R7 8
R8 9
COM1
5
COM2 10
PCI_I RD Y# 4
PCI_F RAME# 4
PCI_PAR 4
PCI_STOP# 4
PCI_D EVSEL# 4
PCI_TRD Y# 4
PCI_PR ST# 4
PCI_SER R# 4
PCI_PER R# 4
PCI_R EQ#[2.. 0] 4
PCI_M66EN 4
C39
0.1uF
PCI_GN T#[2..0] 4
PCI_I NTB# 4
PCI_I NTA# 4
C13
1uF
GRM155R61A105JE15D
cc0402
C10
1uF
cc 0402
GRM155R61A105JE15D
DVCC _1.5V
C6
0.1uF
cc0402
ECJ-0EB1A104K
C5
0.001uF
cc0805
ECH-U 1H102JB5
R8
746_SERIES
R1
1
R2
2
R3
3
R4
4
R5 6
R6 7
R7 8
R8 9
COM1
5
COM2 10
R2
10K
RR0805
PCI_F RAME#
PCI_I NTA#
REFC LK_SEL
PCI_R EQ#3
PCI_SER R#
PCI_I NTC#
PCI_R EQ#2
WP
PCI_DE VSEL#
PCI_PER R#
PCI_R EQ#0
PCI_R EQ#1
PCI_I NTB#
PCI_STOP#
PCI_TRD Y#
PCI_I RD Y#
DVcc _3.3V
PCI_I NTD#
Bridge Power
Filtering/Decoupling
XIO2001
Pullups/Pulldowns
C33
0.1uF
C32
0.1uF
PCI_VI O
DVcc _3.3V
JTAG_TMS
CLKREQ#
SERIR Q
PCI_LOC K#
PCI_LOC K# 4
SERIR Q
R21
10K
RR0805
PCLK66_SEL
C15
1000pF
ECJ-0EB1H 102K
cc0402
C12
1000pF
ECJ-0EB1H 102K
cc0402
C3
1000pF
cc0402
ECJ-0EB1H1 02K
VDDA_3. 3V
DVCC _3.3V
C18
0.1uF
WP
WAKE#3
TXp
EXTARB_EN
CLKRU N_EN
DVCC _3.3V
PCI_R EQ#3
R22
10K
RR0805
PCI_PR ST#
P1_REQ64#4
PCI_R EQ#4
PCI_R EQ#5
PCI_M66EN
R3
10K
RR0805
C16
0.1uF
cc0805
ECJ-2VB1C 104K
PCI_VIO 4
VDDA_1. 5V
R42
10K
RR0805
C34
0.1uF
C36
0.1uF
C35
0.1uF
R43
10K
RR0805
R4
10K
RR0805
C21
0.1uF
C24
0.1uF
C26
0.1uF
C23
0.1uF
C27
0.1uF
C22
0.1uF
C25
0.1uF
GPIO3
GPIO0
GPIO2 GPIO1
GPIO4
Vaux
DVCC _3.3V
DVCC _1.5V
C4
0.1uF
cc0805
ECJ -2VB1C104K
L1
BLM21B
R5
10K
RR0805
JP1
Conn 2x5 s hroud
2510-6002UB
1 2
3 4
5 6
7 8
9 10
Vaux
PCI_PME#
C29
0.1uF
GRST#
GRST#
DVCC _3.3V
P2_REQ64#4
P3_REQ64#4
C30
0.1uF
J1
Head 2x6
1
3
5
7
9
2
4
6
8
10
11 12
Vaux
C31
0.1uF
R26
49.9
RR0402
PCI_PME#3,4
TXp3
C37
0.1uF
TXn3
PERST#3
DVcc _1.5V
Clk +3
Clk -3
RXp3
DVcc _3.3V
RXn3
JTAG_TDO
PCI_VI O 4
C20
0.1uF
Vaux
C14
10nF
ECJ0EB1C 103K
cc0402
R10
10.0K
DNA
RR0603
R39
10K
RR0805
VDDA_1. 5V
GPIO0
PCI_AC K64#4
R24
10.0K
R23
10.0K
C7
0.1uF
C2
10nF
cc0402ECJ0EB1C 103K
R25
10K
RR0805
C8
0.1uF
GPIO2
GPIO1
GPIO3
GPIO4
RXn
TXn
RXp
C9
0.1uF
CLKREQ#
C11
10nF
ECJ0EB1C 103K cc0402
R63
10.0K
DNA
CLKREQ#
R12
10.0K
Vaux
L2
BLM21B
JTAG_TRSTN
VREG_PD33
VDDA_3. 3V
EXTARB_EN
CLKRU N_EN
REFC LK_SEL
PCI_PME#
C1
1uF
GRM155R61A105JE15D
cc 0402
R61
10K
RR0805
PM3705 Connector
JTAG_TRSTN
R40
0
RR 0805
C19
0.1uF
R41
10K
RR0805
JTAG_TMS
JTAG_TDO
TRSTN
TDO
TDI
TMS
TCK
JTAG_TCK
JTAG_TDI
PCI_3. 3V
PCI_VI O
PCLK66_SEL
PCLK66_SEL
R13
10.0K
DVcc _3.3V
R29 0 RR0402
R28
0
RR0402
R1
746_SERIES
R1
1
R2
2
R3
3
R4
4
R5 6
R6 7
R7 8
R8 9
COM1
5
COM2 10
GPIO4
GPIO3
C38
1000pF
cc0402
ECJ-0EB1H 102K
U2
24LC08B
A0
1
A1
2
A2
3
VSS
4SDA 5
SCL 6
WP 7
VCC 8
JTAG_TDI
www.ti.com Schematics
SCPU031 – February 2009 XIO2001 Evaluation Module (EVM) 11Submit Documentation Feedback

EVM_12V 4
DVCC_3.3V
R35
49.9
RR0402
DVCC_1.5V
C50
10uF
Power
C106
0.22uF
L3
10 uH
UP4B-100-R
1 2
DVCC_5.0V
C101
4.7nF
F3
Poly Switch Fus es
1
2
R37
1.00K
RR0402
F1
Poly Switch Fus es
1
2
C102
0.1UF
cc 0603
C103
0.1UF
cc 0603
F2
Poly Swi tch Fus es
1
2
U5
TPS63700
VIN
3
EN
4
PS_GND
7
IN
5
GND
2
VREF 10
FB 9
OUT 8
SW 6
COMP 1
PWR_PAD
11
LEDs
PCI_PME# 2,4
DVCC_3.3V
DVCC_3.3V
DVCC_3.3V
WAKE# 2
LED2
eprt-leds-00003-0000
Red
LED0805
SML-LXT0805IW-TR
Clk+ 2
LED4
eprt-leds-00003-0000
Red
LED0805
SML-LXT0805IW-TR
Clk- 2
TXn
lms _f olly
DVCC_3.3V
WAKE#2 PERST# 2
670- 0203 ( SML_LX0805SRC) ???
LED5
eprt-leds-00001-0000
Green
LED0805
SML-LXT0805GW-TR
L4
10 uH
1
2
TXp 2
TXn 2
RXp2
RXn2
DVCC_3.3V
D1
MBRD835L
1
3
4
2
R68
121K
U3
TPS72615DCQ
ENABLE
1
IN
2
GND
3
OUT
4
RESET
5
GND 6
R64
332
R69
1.2M
+
C45
22uF
cc 6032
TAJC226K016R
1
2
R70
100K
R34
332
RR0402
+
C48
22uF
cc 6032
TAJC226K016R
1
2
D2SL03
12
PERST#
+
C49
22uF
cc6032
TAJC226K016R
1
2
C100
4x4. 7uF
C104
0.1UF
cc0603
PRESENT#
PRESENT#
PCI_12V
R67
10.0
CTXp
CTXn
R36
332
RR0402
PCI_3.3VVaux
-12V_in 4
C99
10uF
R65
332
R66
332
LED6
eprt-leds-00002-0000
Yellow
LED0805
SML-LXT0805YW-TR
DVcc_5.0V
+
C43
100uF
1
2
F5
Poly Switch Fus es
SMD250
1
2
U4
LT1370
VC 1
FB 2
S/S 3
GND1 4
Vsw 5
NFB 6
Vin 7
GND2
8
R45
18.7K
RR0805
R47
6.19K
RR0805
C42
10uF
C46
0.047uF
cc 0603
C47
0.047uF
cc 0603
R49
2K
RR0805
LED3
eprt-leds-00003-0000
Red
LED0805
SML-LXT0805IW-TR
DVCC_1.5V
NEED REPLACE W/ 8. 2 nH 0. 12 ohm ? ? ??
LED7
eprt-leds-00002-0000
Yellow
LED0805
SML-LXT0805YW-TR
C44
10uF
PCI_3.3V
DVCC_5.0V
Side B
Component Side
Sid e A
Sol der
Sid e
Key
P1
Edge PCI Ex press
12V#B1
B1
12V#B2
B2
RSVD#B3
B3
GND#B4
B4
SMCLK
B5
SMDAT
B6
GND#B7
B7
3_3V#B8
B8
J_TRSTZ
B9
3_3VAUX
B10
WAKEZ
B11
RSVD#B12
B12
GND#B13
B13
RXP0
B14
RXN0
B15
GND#B16
B16
PRSNT2Z
B17
GND#B18
B18
PRSNT1Z A1
12V#A2 A2
12V#A3 A3
GND#A4 A4
J_TCK A5
J_TDI A6
J_TDO A7
J_TMS A8
3_3V#A9 A9
3_3V#A10 A10
PWRGD A11
GND#A12 A12
REFC LKP A13
REFCLKN A14
GND#A15 A15
TXP0 A16
TXN 0 A17
RSVD#A18 A18
PCI_12V
EVM_12V 4
LED1
eprt-leds-00003-0000
Red
LED0805
SML-LXT0805IW-TR
R38
10.0K
C105
10pF
Schematics www.ti.com
XIO2001 Evaluation Module (EVM)12 SCPU031 – February 2009Submit Documentation Feedback

www.ti.com Schematics
SCPU031 – February 2009 XIO2001 Evaluation Module (EVM) 13Submit Documentation Feedback

6 Bill of Materials
Bill of Materials www.ti.com
Evaluation board bill of materials as assembled. Unused options (e.g., 3.3-V V
IO
) are not populated andnot listed.
Table 7. Bill of MaterialsITEM QTY REFERENCE VALUE MFR PART NO. PACKAGE
1 3 C1, C10, C13 1 µF Murata GRM155R61A105JE15D cc0402
2 3 C2, C11, C14 10 nF Panasonic ECJ0EB1C103K cc0402
3 4 C3, C12, C15, C38 1000 pF Panasonic ECJ-0EB1H102K cc0402
4 2 C4, C16 0.1 µF Panasonic ECJ-2VB1C104K cc0805
5 2 C5, C17 0.001 µF Panasonic ECH-U1H102JB5 cc0805
C6, C7, C8, C9, C18, C19,C20, C21, C22, C23, C24,C25, C26, C27, C29, C3,C31, C32, C33, C34, C35,C36, C37, C39, C51, C52,C53, C54, C55, C56, C57,C58, C59, C60, C61, C62,6 72 C63, C64, C65, C66, C67, 0.1 µF Panasonic ECJ-0EB1A104K cc0402C68, C69, C70, C71 C72,C73, C74 C75, C76, C77,C78, C79, C80 C81, C82,C83, C84, C85, C86, C87,C88, C89, C90 C91, C92,C93, C94 C95, C96, C97,C98
C42, C44, C50, C99, C100, 10 µF Panasonic ECJ-2FB1A106K cc08057 6
C101
8 1 C43 100 µF Panasonic ECA1EHG101 THCap_2P5MM
9 3 C45, C48, C49 22 µF AVX TAJC226K016R cc6032
10 2 C46, C47 0.047 µF Panasonic ECJ1VB1C473K cc0603
11 3 C102, C103, C104 0.1 µF Kemet C0603C104M4RACTU cc0603
12 1 C105 10 pF TDK C1608C0G1H100DB cc0603
13 1 C106 0.22 µF Panasonic ECJ1VB1A224K cc0603
14 1 D1 MBRD835L Diodes, Inc. MBRD835L DPAK_4
15 1 D2 SL03 Vishay SL03D0-219AB-GS08 sl03_schottky_diode
16 4 F1, F2, F3, F5 Polyswitch fuses Tyco Electronics SMD250 SMD250
17 1 J1 Head 2 ×6 Berg 54102-T32-05 HDR_6X2
18 1 JP1 Conn 2 ×5 shroud 3M 2510-6002UB eprt-conn-00002-0001
19 2 L1, L2 BLM21B MuRata BLM21BB221SN1 cc0805
20 1 L3 10 µH Coiltronics UP4B-100-R IND_UP4B_100_R
21 1 L4 10 µH Sumida CDRH5D18NP-100NC CDRH5D18
22 4 LED1, LED2, LED3, LED4 Red Lumex Lumex SML-LXT0805IW-TR LED0805
23 1 LED5 Green Lumex SML-LXT0805GW-TR LED0805
24 2 LED6, LED7 Yellow Lumex SML-LXT0805YW-TR LED0805
25 1 P1 Edge PCI Express DNA eprt-conn- 00023-0000
26 3 P2, P3, P4 PCI 5 V conn Tyco Electronics 145154-8 Conn_PCI_60_Dual
27 4 R1, R6, R7, R8 746_SERIES CTS 746X101103JCT-ND? 10Pin_8Res
R2, R3, R4, R5, R19, R20, 10K Panasonic ERJ6ENF1002V RR080528 14 R21, R22, R25, R39, R41,R42, R43, R61
R10, R11, R12, R13, R23, 10.0K Panasonic ERJ3EKF1002V RR060329 9
R24, R38, R62, R63
30 2 R26, R35 49.9 Panasonic ERJ2RKF49R9X RR0402
31 2 R28, R29 0 Panasonic ERJ2GE0R00X RR0402
32 1 R32 14.3K Panasonic ERJ6ENF1432V RR0805
33 1 R33 232 Panasonic ERJ6ENF2320V RR0805
34 2 R34,R36 332 Panasonic ERJ2GEJ3320X RR0402
35 1 R37 Conn 2 ×5 shroud Panasonic ERJ2RKF1001V RR0402
14 XIO2001 Evaluation Module (EVM) SCPU031 – February 2009Submit Documentation Feedback

www.ti.com Bill of Materials
Table 7. Bill of Materials (continued)ITEM QTY REFERENCE VALUE MFR PART NO. PACKAGE
R40, R50, R51, R52, R53, 0 Panasonic ERJ6ENF0000V RR080536 7
R54, R55
37 1 R45 18.7K Panasonic ERJ6ENF1872V RR0805
38 1 R47 6.19K Panasonic ERJ6ENF6191V RR0805
39 1 R49 2K Panasonic ERJ6ENF2001V RR0805
40 2 R56, R57 0 Panasonic ERJ3GEY0R00V RR0603
41 3 R58, R59, R60 100 Panasonic ERJ6ENF1000V RR0805
42 3 R64, R65, R66 332 Panasonic ERAV39J3320V RR0603
43 1 R67 10.0 Panasonic ERJ2RKF10R0V RR0402
44 1 R68 121K Panasonic ERJ2RKF1213X RR0402
45 1 R69 1.2M Vishay CRCW0603 RR0603
46 1 R70 100K Panasonic ERJ2RKF1003V RR0402
47 1 U2 24LC08B Microchip 24LC08BIST TSSOP_8_122X177_ 26
48 1 U3 TPS72615DCQ Texas Instruments TPS72615DCQ TO_263_6_DCQ
49 1 U4 LT1370 Linear Technology LT1370CR DDPAK_R_7
50 1 U5 TPS63700 Texas Instruments TPS63700DRCT DRC_S_PVSON_N10
bga144ZAJ_0p5mm_51 1 U6 XIO2001_ZAJ Texas Instruments XIO2001ZAJ
socket
SCPU031 – February 2009 XIO2001 Evaluation Module (EVM) 15Submit Documentation Feedback

EVALUATION BOARD/KIT IMPORTANT NOTICE
Texas Instruments (TI) provides the enclosed product(s) under the following conditions:This evaluation board/kit is intended for use for ENGINEERING DEVELOPMENT, DEMONSTRATION, OR EVALUATION PURPOSESONLY and is not considered by TI to be a finished end-product fit for general consumer use. Persons handling the product(s) must haveelectronics training and observe good engineering practice standards. As such, the goods being provided are not intended to be completein terms of required design-, marketing-, and/or manufacturing-related protective considerations, including product safety and environmentalmeasures typically found in end products that incorporate such semiconductor components or circuit boards. This evaluation board/kit doesnot fall within the scope of the European Union directives regarding electromagnetic compatibility, restricted substances (RoHS), recycling(WEEE), FCC, CE or UL, and therefore may not meet the technical requirements of these directives or other related directives.Should this evaluation board/kit not meet the specifications indicated in the User’s Guide, the board/kit may be returned within 30 days fromthe date of delivery for a full refund. THE FOREGOING WARRANTY IS THE EXCLUSIVE WARRANTY MADE BY SELLER TO BUYERAND IS IN LIEU OF ALL OTHER WARRANTIES, EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING ANY WARRANTY OFMERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE.The user assumes all responsibility and liability for proper and safe handling of the goods. Further, the user indemnifies TI from all claimsarising from the handling or use of the goods. Due to the open construction of the product, it is the user’s responsibility to take any and allappropriate precautions with regard to electrostatic discharge.EXCEPT TO THE EXTENT OF THE INDEMNITY SET FORTH ABOVE, NEITHER PARTY SHALL BE LIABLE TO THE OTHER FOR ANYINDIRECT, SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES.TI currently deals with a variety of customers for products, and therefore our arrangement with the user is not exclusive.
TI assumes no liability for applications assistance, customer product design, software performance, or infringement of patents orservices described herein.
Please read the User’s Guide and, specifically, the Warnings and Restrictions notice in the User’s Guide prior to handling the product. Thisnotice contains important safety information about temperatures and voltages. For additional information on TI’s environmental and/orsafety programs, please contact the TI application engineer or visit www.ti.com/esh .No license is granted under any patent right or other intellectual property right of TI covering or relating to any machine, process, orcombination in which such TI products or services might be or are used.FCC Warning
This evaluation board/kit is intended for use for ENGINEERING DEVELOPMENT, DEMONSTRATION, OR EVALUATION PURPOSESONLY and is not considered by TI to be a finished end-product fit for general consumer use. It generates, uses, and can radiate radiofrequency energy and has not been tested for compliance with the limits of computing devices pursuant to part 15 of FCC rules, which aredesigned to provide reasonable protection against radio frequency interference. Operation of this equipment in other environments maycause interference with radio communications, in which case the user at his own expense will be required to take whatever measures maybe required to correct this interference.
EVM WARNINGS AND RESTRICTIONS
It is important to operate this EVM within the input voltage range of and the output voltage range of .Exceeding the specified input range may cause unexpected operation and/or irreversible damage to the EVM. If there are questionsconcerning the input range, please contact a TI field representative prior to connecting the input power.Applying loads outside of the specified output range may result in unintended operation and/or possible permanent damage to the EVM.Please consult the EVM User's Guide prior to connecting any load to the EVM output. If there is uncertainty as to the load specification,please contact a TI field representative.During normal operation, some circuit components may have case temperatures greater than . The EVM is designed to operate properlywith certain components above as long as the input and output ranges are maintained. These components include but are not limited tolinear regulators, switching transistors, pass transistors, and current sense resistors. These types of devices can be identified using theEVM schematic located in the EVM User's Guide. When placing measurement probes near these devices during operation, please beaware that these devices may be very warm to the touch.
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265Copyright © 2009, Texas Instruments Incorporated

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Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements,and other changes to its products and services at any time and to discontinue any product or service without notice. Customers shouldobtain the latest relevant information before placing orders and should verify that such information is current and complete. All products aresold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment.TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI’s standardwarranty. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. Except wheremandated by government requirements, testing of all parameters of each product is not necessarily performed.TI assumes no liability for applications assistance or customer product design. Customers are responsible for their products andapplications using TI components. To minimize the risks associated with customer products and applications, customers should provideadequate design and operating safeguards.TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right, copyright, mask work right,or other TI intellectual property right relating to any combination, machine, or process in which TI products or services are used. Informationpublished by TI regarding third-party products or services does not constitute a license from TI to use such products or services or awarranty or endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectualproperty of the third party, or a license from TI under the patents or other intellectual property of TI.Reproduction of TI information in TI data books or data sheets is permissible only if reproduction is without alteration and is accompaniedby all associated warranties, conditions, limitations, and notices. Reproduction of this information with alteration is an unfair and deceptivebusiness practice. TI is not responsible or liable for such altered documentation. Information of third parties may be subject to additionalrestrictions.
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