Texas Instruments LMK04832EVM-CVAL User manual

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LMK04832EVM-CVAL User’s Guide
User's Guide
SNAU252–June 2020
LMK04832EVM-CVAL User’s Guide
The LMK04832EVM-CVAL evaluation module (EVM) provides a platform to evaluate the performance and
features of the LMK04832-SP Space Grade Ultra-Low-Noise JESD204B Dual-Loop Clock Jitter Cleaner
from Texas Instruments. The user’s guide describes how to set up and operate the EVM. The LMK04832-
SP device on each EVM is an Engineering Model, intended for engineering evaluation only. The devices
and EVMs are not suitable for qualification, production, radiation testing or flight use.
Contents
1 Evaluation Board Kit Contents............................................................................................. 2
2 Quick Start.................................................................................................................... 3
3 PLL Loop Filters and Loop Parameters................................................................................... 6
4 Default TICS Pro Mode ..................................................................................................... 7
5 Using TICS Pro to Program the LMK04832-SP ......................................................................... 7
6 Evaluation Board Inputs and Outputs ................................................................................... 11
7 Recommended Test Equipment.......................................................................................... 13
8 Length Matching............................................................................................................ 13
9 Schematics.................................................................................................................. 15
10 Bill of Materials ............................................................................................................. 20
Appendix A TICS Pro Usage................................................................................................... 25
List of Figures
1 Quick Start Diagram......................................................................................................... 3
2 Clock Outputs Page Description Diagram................................................................................ 5
3 Selecting a Default Mode for the LMK04832-SP Device............................................................... 7
4 Selecting the LMK04832-SP ............................................................................................... 8
5 Loading the Device.......................................................................................................... 9
6 Setting the Default Configuration for LMK04832-SP.................................................................... 9
7 Setting Digital Delay, Clock Divider, Analog Delay, and Output Format............................................ 10
8 Schematic - Power Supply................................................................................................ 15
9 Schematic - LMK04832-SP ............................................................................................... 16
10 Schematic - Digital ......................................................................................................... 17
11 Schematic - Clock Outputs 1 of 2........................................................................................ 18
12 Schematic - Clock Outputs 2 of 2........................................................................................ 19
13 TICS Pro - Communication Setup Window............................................................................. 25
14 TICS Pro - User Controls Page .......................................................................................... 26
15 TICS Pro - Raw Registers Page ......................................................................................... 27
16 TICS Pro - Set Modes Page.............................................................................................. 28
17 TICS Pro - Holdover Page ................................................................................................ 29
18 TICS Pro - CLKinX Control Page ........................................................................................ 30
19 TICS Pro - PLL1 and 2 Page............................................................................................. 31
20 TICS Pro - SYNC / SYSREF Page ...................................................................................... 32
21 TICS Pro - Clock Outputs Page.......................................................................................... 33
22 TICS Pro - Other Page .................................................................................................... 34

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23 TICS Pro - Current Calculator Page..................................................................................... 35
24 TICS Pro - Burst Page..................................................................................................... 36
List of Tables
1 EVM Contents................................................................................................................ 2
2 PLL1 Loop Filter Parameters for Crystek 122.88-MHz VCXO ........................................................ 6
3 Integrated VCO PLL ........................................................................................................ 6
4 Default TICS Pro Modes for the LMK04832-SP......................................................................... 7
5 Description of Evaluation Board Inputs and Outputs.................................................................. 11
6 Differential Pair Lengths................................................................................................... 14
7 Bill of Materials ............................................................................................................. 20
Trademarks
PLLatinum is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
1 Evaluation Board Kit Contents
Table 1 lists the components found in the evaluation board kit.
Table 1. EVM Contents
HSDC005
Evaluation Board (1) LMK04832EVM-CVAL Evaluation Board with VCXO
Communication Interface (1) USB2ANY

x
x
x
x
x
Laptop or PC
4.5 V
1
3
4
Reference clock from
signal generator or
other external
source.
122.88 MHz
(Default)
2
Power
Reference
LMK04832-SP
CLKout9_N
CLKout9_P
PLL1 Digital Lock Detect LED
PLL2 Digital
Lock Detect LED
USB cable
USB2ANY
USB2ANY
Texas Instruments
HPA665 ÅBSL
Button
CLKout5_P
CLKout5_N
10-Pin Ribbon Cable
FBCLKin_P/CLKin1_P FBCLKin_N/CLKin1_N
CLKout8_N
CLKout8_P
SYNC
CLKout0_N CLKout0_P
CLKout1_N CLKout1_P CLKout3_N CLKout3_P CLKout2_N CLKout2_P
CLKout4_P
CLKout4_N
GND
VCC
Default is
LDO to IC
Program with TICS Pro
%HVXUHWRSUHVVµ&WUO- /¶RU
USB commination ÆWrite All Registers
CLKout10_N
CLKout10_P
CLKout11_N
CLKout11_P
CLKout13_N
CLKout13_P
CLKout12_N
CLKout12_P
Fin0_N Fin0_P
CLKout6_P
CLKout6_N
CLKout7_P
CLKout7_N
OSCin_P OSCin_N
OSCout_P/CLKin2_P OSCout_N/CLKin2_N
CLKin0_P CLKin0_N
OR
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2 Quick Start
Figure 1. Quick Start Diagram

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2.1 Quick Start Description
The LMK04832EVM-CVAL allows full verification of the device functionality and performance
specifications. To quickly set up and operate the board with basic equipment, refer to the quick start
procedure below and test setup shown in Figure 1.
1. Connect a voltage of 4.5 volts to the VCC SMA connector or terminal block. The LMK04832-SP and on-
board VCXO operate at 3.3 V provided by the onboard TPS7A4501-SP LDO.
2. Connect a reference clock to the CLKin1* port from a signal generator or other source. Use 122.88
MHz for default configuration.
3. Connect USB2ANY to a PC and the EVM.
4. Program the device with TICS Pro. TICS Pro is available for download at:
http://www.ti.com/tool/ticspro-sw.
a. Select LMK04832-SP from the Select Device Menu. Click Select Device →Clock Generator/Jitter
Cleaner (Dual Loop).
b. Select USB2ANY mode from the Communication Setup window. To access this, select USB
communications →Interface. Confirm that the PC to USB communication is working by clicking on
Identify. A blinking green LED on the USB2ANY indicates the PC is able to communicate through
the USB2ANY.
c. Select a default mode from the Default configuration Menu. For the quick start use, CLKin1 122.88
MHz, OSCin 122.88 MHz, VCO1 2949.12 MHz.
d. Ctrl+L must be pressed at least once to load all registers. Alternatively, click the USB
communications →Write All Registers menu, the Write All Registers button on toolbar, or the Raw
Registers page shown in Section A.3.
5. Measurements may be made at an active CLKout port through the SMA connector.

1 2 4
20
5 6 7 8 13 14 15 16 17
19
9 11 12
21 22 23 2524 26 2718
3 10
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2.1.1 Clock Outputs Page Description
Clock outputs are grouped in pairs. This description applies for all clock outputs on the Clock Outputs
page of the TICS Pro GUI shown in Section A.9.
Figure 2. Clock Outputs Page Description Diagram
1. SYNC_DISX: Prevent the divider from being reset by SYNC/SYSREF path.
2. DCLKX_Y_DIV: Divide value for the device clock. If set to 1, then DCLKX_Y_DCC (DCC & HS) must =
1.
3. DDLYdX_EN: Enable dynamic digital delay for this divider.
4. DCLKX_Y_HSg_PD: If clear, glitchless half-step adjustments are enabled.
5. DCLKX_Y_HS: Set half step for this divider. DCLKX_Y_DCC (DCC & HS) must = 1.
6. DCLKX_Y_DDLY_PD: If clear, the digital delay value is assured when a SYNC occurs.
7. DCLKX_Y_DDLY: The digital delay value to be used when a SYNC occurs.
8. DCLKX_Y_PD: Power down the device clock divider and path.
9. DCLKX_Y_DCC: Enable duty cycle correct and half-step for this device clock divider.
10. DCLKX_Y_POL: If set, polarity of device clock is inverted.
11. DCLKX_Y_BYP: If set, the device clock divider is bypassed for CLKoutX and #15 must be CML.
12. CLKoutX_SRC_MUX: Select device clock or SYSREF clock path for CLKoutX.
13. CLKoutX_Y_IDL: Increase input drive level to improve noise floor at cost of power (~2 mA).
14. SYSREF_GBL_PD: Set the conditional for SCLKX_Y_DIS_MODE registers.
15. CLKoutX_FMT: Set the clock output format for CLKoutX.
16. CLKoutX_Y_ODL: Increase output drive level to improve noise floor at cost of power (~3 mA). No
effect for CLKoutX in bypass mode.
17. CLKoutX_Y_PD: Power down the entire CLKoutX_Y clock pair.
18. SCLKX_Y_DDLY: The SYSREF clock digital delay setting.
19. SCLKX_Y_HS: Set half step for the SYSREF output.
20. SCLKX_Y_ADLY_EN: Enable analog delay for the SYSREF clock path.
21. SCLKX_Y_ADLY: If enabled, set the analog delay for the SYSREF clock path.
22. SCLKX_Y_PD: Power down the SYSREF clock path.
23. SCLKX_Y_POL: If set, polarity of SYSREF output clock is inverted.
24. CLKoutY_SRC_MUX: Select device clock or SYSREF clock path for CLKoutY.
25. SCLKX_Y_DIS_MODE: Set the output state of output clock drivers for the SYSREF clock. For values

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of 1 and 2 works in conjunction with control on this list #14, SYSREF_GBL_PD.
26. CLKoutY_FMT: Set the clock output format for CLKoutY.
27. Clock output frequency for CLKoutX and CLKoutY.
2.1.2 TICS Pro Tips
Mousing over different controls will display a help prompt with the register address, the data bit location
and length, and a brief register description in the lower-left Context help pane.
Setting a register equal to 0 or un-checking a register’s checkbox performs the same action. Similarly,
setting a register equal to 1 is the same as checking that register’s checkbox.
3 PLL Loop Filters and Loop Parameters
In jitter cleaning applications that use a cascaded or dual PLL architecture, the first PLL’s purpose is to
substitute the phase noise of a low-noise oscillator (VCXO) for the phase noise of a dirty reference clock.
The first PLL is typically configured with a narrow loop bandwidth to minimize the impact of the reference
clock phase noise. The reference clock consequently serves only as a frequency reference rather than a
phase reference.
The loop filters on the LMK04832EVM-CVAL evaluation board are setup using the approach above. The
loop filter for PLL1 has been configured for a narrow loop bandwidth (< 1 kHz). The specific loop
bandwidth values depend on the phase noise performance of the oscillator mounted on the board. Table 2
and Table 3 contain the parameters for PLL1 and PLL2 for each oscillator option.
TI’s PLLatinum™ Sim tool can be used to optimize PLL phase noise/jitter for given specifications. See
http://www.ti.com/tool/pllatinumsim-sw for more information.
3.1 PLL1 Loop Filter
(1) Loop Bandwidth is a function of Kφ, Kvco, N as well as loop components. Changing Kφand N will change the loop bandwidth.
Table 2. PLL1 Loop Filter Parameters for Crystek 122.88-MHz VCXO(1)
122.88-MHz VCXO PLL
Phase Margin 50˚Kφ(Charge Pump) 450 µA
Loop Bandwidth 14 Hz Phase Detector Freq 1.024 MHz
VCO Gain 2.5 kHz/V
Reference Clock Frequency 122.88 MHz Output Frequency 122.88 MHz
(To PLL 2)
Loop Filter Components LF1_C1 (C75) = 100 nF LF1_C2 (C73) = 680 nF LF1_R2 (R64) = 39 kΩ
3.2 PLL2 Loop Filter
(1) PLL Loop Bandwidth is a function of Kφ, Kvco, N as well as loop components. Changing Kφand N will change the loop
bandwidth.
Table 3. Integrated VCO PLL(1)
PARAMETER LMK04832-SP UNIT
VCO0 VCO1
LF2_C1 (C58) 0.047 nF
LF2_C2 (C56) 3.9 nF
C3 (internal) 0.03 nF
C4 (internal) 0.01 nF
LF2_R2 (R41) 0.62 kΩ
R3 (internal) 0.2 kΩ
R4 (internal) 0.2 kΩ
Charge Pump Current, Kφ3.2 mA

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Table 3. Integrated VCO PLL(1) (continued)
PARAMETER LMK04832-SP UNIT
VCO0 VCO1
Phase Detector Frequency 122.88 MHz
Frequency 2457.6 2949.12 MHz
Kvco 13.0 25.0 MHz/V
N20 24
Phase Margin 68 71 degrees
Loop Bandwidth 210 326 kHz
4 Default TICS Pro Mode
TICS Pro saves the state of the selected LMK04832-SP device when exiting the software. To ensure a
common starting point, the following modes listed in Table 4 may be restored by clicking Default
configuration and selecting the appropriate device configuration.
Table 4. Default TICS Pro Modes for the LMK04832-SP
DEFAULT TICS PRO MODE DEVICE MODE CLKin FREQUENCY OSCin FREQUENCY
CLKin1 122.88 MHz, OSCin 122.88 MHz, VCO1
2949.12 MHz Dual PLL, Internal VCO 122.88 MHz 122.88 MHz
Figure 3. Selecting a Default Mode for the LMK04832-SP Device
5 Using TICS Pro to Program the LMK04832-SP
This section will demonstrate how to use TICS Pro. For more information on using TICS Pro, refer to
Appendix A. TICS Pro is available for download at http://www.ti.com/tool/ticspro-sw.
Before proceeding, be sure to follow the instructions in Section 2 to ensure proper hardware connections.
5.1 Start TICS Pro Application
Click Start →Programs →Texas Instruments →TICS Pro.
The TICS Pro program is installed by default to the Texas Instruments application group.
5.2 Select Device
Click Select Device →Clock Generator/Jitter Cleaner (Dual Loop) →LMK04832-SP.
Once started, TICS Pro will load the last used device. A recent history of used devices can be quickly
accessed under the File Menu. To load a new device, click Select Device from the menu bar, select the
subgroup, then select the device to load.

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Figure 4. Selecting the LMK04832-SP
5.3 Program the Device
To program, press Ctrl+L.
Alternatively, click USB communications →Write All Registers from the menu to program the device to the
current state of the register map to the device. Ctrl+L is the accelerator key assigned to the Write All
Registers option and is very convenient.

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Figure 5. Loading the Device
Once the device has been initially loaded, TICS Pro will automatically program changed registers, so it is
not necessary to reload the device upon subsequent changes in the device configuration. It is possible to
disable this functionality by ensuring there is no checkmark by the Options →AutoUpdate.
A default mode will be restored in the next step, therefore this step is not necessary. It is included,
however, to emphasize the importance of pressing Ctrl+L to load the device at least once after starting
TICS Pro, restoring a mode, or restoring a saved setup using the File menu.
See TICS Pro instructions located at http://www.ti.com/tool/ticspro-sw/.
5.4 Restoring a Default Mode
Click Default configuration →CLKin1 122.88 MHz, OSCin 122.88 MHz, VCO1 2949.12 MHz.
Press Ctrl+L to restore the default configuration.
Figure 6. Setting the Default Configuration for LMK04832-SP
For the purpose of this walkthrough, a default mode will be loaded to ensure a common starting point.
This is important because when TICS Pro is closed, it remembers the last settings used for a particular
device. Again, remember to press Ctrl+L as the first step after loading a default mode.
5.5 Visual Confirmation of Frequency Lock
After a default mode is restored and loaded LED D3 and D4 must illuminate when PLL1 and PLL2 are
locked to the reference clock applied to CLKin1. This assumes PLL1_LD_MUX = PLL1_DLD,
PLL2_LD_MUX = PLL2_DLD, and PLLX_LD_TYPE = Output (Push-Pull).
5.6 Enable Clock Outputs
The LMK04832-SP offers programmable clock output buffer formats, the evaluation board is shipped with
pre-configured output terminations. Refer to Table 5 to see a list of the outputs what the output format the
hardware is configured for out of the factory.
To measure Phase noise at one of the clock outputs, for example CLKout0:
1. Click on the Clock Outputs page, Section A.9
2. Uncheck CLKoutX_Y_PD in the Clock Output box to enable the channel,
3. Set the following as needed:

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a. For Device Clock:
• DCLKX_Y_PD = 0 in Clock Mode Select box.
• Set Bypass Div (DCLKX_Y_BYP) or Clock Divider (DCLK0_1_DIV) as desired for device clock
frequency.
– If bypass mode is set, CLKoutX must be set to a CML output format. Bypass mode is not
available on CLKoutY.
– If Clock Divider = 1, then DCLKX_Y_DCC must be set for clock output.
• Phase of the device clock can be adjusted with:
– Static Digital delay (DCLKX_Y_DDLY) after a SYNC. Digital Delay (DCLKX_Y_DDLY_PD)
must be powered up.
– Dynamic Digital delay (DDLYdX_EN), then programming DDLYd_STEP_CNT. Digital Delay
(DCLKX_Y_DDLY_PD) must be powered up. Press the Send button at top right of Clock
Outputs window to program the DDLYd_STEP_CNT field multiple times.
– Half Step bit (DCLKX_Y_HS) if DCC & HS (DCLKX_Y_DCC) is set.
– The Polarity bit (DCLKX_Y_POL)
• Select the Device Clock for CLKoutX or CLKoutY with CLKout#_SRC_MUX = 0 (Device Clock)
as desired.
b. While the phase noise of a SYSREF Clock is typically not of concern, to configure an output for
SYSREF:
• SCLKX_Y_PD = 0 in Clock Mode Select box.
• Phase of the SYSREF clock can be adjusted.
– Local digital delay can be set with SCLKX_Y_DDLY.
– Local analog delay can be set by enabling with ADLY_EN = 1 (SCLKX_Y_ADLY_EN) and
then setting SCLKX_Y_ADLY to the desired time delay.
– Global digital delay can be set with SYSREF_DDLY, but this delay change will take effect
only after a SYNC.
• Globally SYSREF output must be enabled. The necessary bits depend upon the type of
SYSREF to be enabled. For a simple continuous SYSREF (not recommended in final
application due to extra power consumption and crosstalk), set SYSREF_PD = 0,
SYSREF_MUX = 0x03 (Continuous), and SYNC_DISSYSREF = 1.
• Select the SYSREF clock for CLKoutX or CLKoutY with CLKout#_SRC_MUX = 1 (SYSREF)
as desired.
Figure 7. Setting Digital Delay, Clock Divider, Analog Delay, and Output Format
4. Depending on the configured output type, the clock output SMAs can be interfaced to a test instrument
with a single-ended, 50-Ωinput as follows.
a. For LVDS:
i. A balun (like ADT2-1T or high quality Prodyn BIB-100G) is recommended for differential-to-
single-ended conversion.