Texas Instruments TMS320C6000 DSP User manual

TMS320C6000 DSP
Enhanced Direct Memory Access (EDMA) Controller
Reference Guide
Literature Number: SPRU234
July 2003

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iiiRead This FirstSPRU234
Preface
Read This First
About This Manual
This document describes the operation of the enhanced direct memory access
(EDMA) controller in the digital signal processors (DSPs) of the
TMS320C6000DSP family. This document also describes the quick DMA
(QDMA) used for fast data requests by the CPU. For operation and registers
unique to the TMS320C621x/C671x EDMA, see Chapter 2. For operation and
registers unique to the TMS320C64xEDMA, see Chapter 3.
Notational Conventions
This document uses the following conventions.
Hexadecimal numbers are shown with the suffix h. For example, the
following number is 40 hexadecimal (decimal 64): 40h.
Registers in this document are shown in figures and described in tables.
Each register figure shows a rectangle divided into fields that represent
the fields of the register. Each field is labeled with its bit name, its
beginning and ending bit numbers above, and its read/write properties
below. A legend explains the notation used for the properties.
Reserved bits in a register figure designate a bit that is used for future
device expansion.
Related Documentation From Texas Instruments
The following documents describe the C6000devices and related support
tools. Copies of these documents are available on the Internet at www.ti.com.
Tip: Enter the literature number in the search box provided at www.ti.com.
TMS320C6000 CPU and Instruction Set Reference Guide (literature
number SPRU189) describes the TMS320C6000CPU architecture,
instruction set, pipeline, and interrupts for these digital signal processors.
TMS320C6000 Peripherals Reference Guide (literature number SPRU190)
describes the peripherals available on the TMS320C6000DSPs.

Trademarks
iv SPRU234
TMS320C6000 Technical Brief (literature number SPRU197) gives an
introduction to the TMS320C62xand TMS320C67xDSPs, develop-
ment tools, and third-party support.
TMS320C64x Technical Overview (SPRU395) gives an introduction to the
TMS320C64xDSP and discusses the application areas that are
enhanced by the TMS320C64x VelociTI.
TMS320C6000 Programmer’s Guide (literature number SPRU198)
describes ways to optimize C and assembly code for the
TMS320C6000DSPs and includes application program examples.
TMS320C6000 Code Composer Studio Tutorial (literature number
SPRU301) introduces the Code Composer Studiointegrated develop-
ment environment and software tools.
Code Composer Studio Application Programming Interface Reference
Guide (literature number SPRU321) describes the Code Composer
Studioapplication programming interface (API), which allows you to
program custom plug-ins for Code Composer.
TMS320C6x Peripheral Support Library Programmer’s Reference
(literature number SPRU273) describes the contents of the
TMS320C6000peripheral support library of functions and macros. It
lists functions and macros both by header file and alphabetically,
provides a complete description of each, and gives code examples to
show how they are used.
TMS320C6000 Chip Support Library API Reference Guide (literature
number SPRU401) describes a set of application programming interfaces
(APIs) used to configure and control the on-chip peripherals.
Trademarks
Code Composer Studio, C6000, C62x, C64x, C67x, TMS320C6000,
TMS320C62x, TMS320C64x, TMS320C67x, and VelociTI are trademarks of
Texas Instruments.
Related Documentation From Texas Instruments / Trademarks

Contents
vContentsSPRU234
Contents
1 Overview 1-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Provides an overview and describes the common operation of the enhanced direct-memory
access (EDMA) controller in the digital signal processors (DSPs) of the TMS320C6000 DSP
family. Also describes the quick DMA (QDMA) used for fast data requests by the CPU.
1.1 Overview 1-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.2 EDMA Terminology 1-5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.3 Initiating an EDMA Transfer 1-6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.4 Synchronization of EDMA Transfers 1-7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.5 Types of EDMA Transfers 1-10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.5.1 1-Dimensional Transfers 1-10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.5.2 2-Dimensional Transfers 1-13. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.6 Element Size and Alignment 1-16. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.7 Element and Frame/Array Count Updates 1-18. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.8 Source/Destination Address Updates 1-19. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.9 Linking EDMA Transfers 1-22. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.10 Terminating an EDMA Transfer 1-24. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.11 EDMA Interrupt Generation 1-25. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.11.1 EDMA Interrupt Servicing by the CPU 1-27. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.11.2 Alternate Transfer Complete Code Interrupt (C64x DSP only) 1-28. . . . . . . . . . . .
1.12 EDMA Performance 1-29. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.13 Quick DMA (QDMA) 1-30. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.13.1 Initiating a QDMA Transfer 1-30. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.13.2 QDMA Performance 1-31. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.13.3 QDMA Stalls and Priority 1-31. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.14 Emulation Operation 1-32. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.15 Transfer Request Submission 1-32. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.15.1 Request Chain 1-32. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.15.2 Transfer Crossbar 1-35. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.15.3 Address Generation/Transfer Logic 1-35. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.16 Transfer Examples 1-37. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.16.1 Block Move Example 1-37. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.16.2 Subframe Extraction Example 1-39. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.16.3 Data Sorting Example 1-41. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.16.4 Peripheral Servicing Examples 1-43. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Contents
vi SPRU234
2 TMS320C621x/C671x EDMA 2-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Describes the operation and registers of the EDMA controller in the
TMS320C621x/C671x DSP. Also describes the quick DMA (QDMA) registers that the CPU
uses for fast data requests.
2.1 Event Encoder 2-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.2 Parameter RAM (PaRAM) 2-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.3 Chaining EDMA Channels by an Event 2-5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.4 Resource Arbitration and Priority Processing 2-6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.5 Transfer Request Queue Length 2-7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.6 EDMA Control Registers 2-8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.6.1 EDMA Event Selector Registers (ESEL0, 1, 3) 2-8. . . . . . . . . . . . . . . . . . . . . . . . . .
2.6.2 Priority Queue Status Register (PQSR) 2-14. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.6.3 EDMA Channel Interrupt Pending Register (CIPR) 2-15. . . . . . . . . . . . . . . . . . . . . .
2.6.4 EDMA Channel Interrupt Enable Register (CIER) 2-16. . . . . . . . . . . . . . . . . . . . . . .
2.6.5 EDMA Channel Chain Enable Register (CCER) 2-17. . . . . . . . . . . . . . . . . . . . . . . .
2.6.6 EDMA Event Register (ER) 2-18. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.6.7 EDMA Event Enable Register (EER) 2-19. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.6.8 Event Clear Register (ECR) 2-20. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.6.9 EDMA Event Set Register (ESR) 2-21. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.7 EDMA Channel Parameter Entries 2-22. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.7.1 EDMA Channel Options Parameter (OPT) 2-22. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.7.2 EDMA Channel Source Address Parameter (SRC) 2-25. . . . . . . . . . . . . . . . . . . . . .
2.7.3 EDMA Channel Transfer Count Parameter (CNT) 2-26. . . . . . . . . . . . . . . . . . . . . . .
2.7.4 EDMA Channel Destination Address Parameter (DST) 2-27. . . . . . . . . . . . . . . . . .
2.7.5 EDMA Channel Index Parameter (IDX) 2-28. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.7.6 EDMA Channel Count Reload/Link Address Parameter (RLD) 2-29. . . . . . . . . . . .
2.8 QDMA Registers 2-31. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.8.1 QDMA Channel Options Register (QOPT, QSOPT) 2-32. . . . . . . . . . . . . . . . . . . . .
2.8.2 QDMA Channel Source Address Register (QSRC, QSSRC) 2-33. . . . . . . . . . . . .
2.8.3 QDMA Channel Transfer Count Register (QCNT, QSCNT) 2-33. . . . . . . . . . . . . . .
2.8.4 QDMA Channel Destination Address Register (QDST, QSDST) 2-33. . . . . . . . . .
2.8.5 QDMA Channel Index Register (QIDX, QSIDX) 2-33. . . . . . . . . . . . . . . . . . . . . . . . .
3 TMS320C64x EDMA 3-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Describes the operation and registers of the EDMA controller in the TMS320C64x DSP. Also
describes the quick DMA (QDMA) registers that are used for fast data requests by the CPU.
3.1 Event Encoder 3-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.2 Parameter RAM (PaRAM) 3-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.3 Chaining EDMA Channels by an Event 3-5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.3.1 Alternate Transfer Chaining 3-5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.3.2 Alternate Transfer Chaining Examples 3-6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.4 Peripheral Device Transfers 3-10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.5 Resource Arbitration and Priority Processing 3-11. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.6 Transfer Request Queue Length 3-11. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.7 EDMA Access Into L2 Control 3-13. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Contents
viiContentsSPRU234
3.8 EDMA Control Registers 3-14. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.8.1 Priority Queue Status Register (PQSR) 3-15. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.8.2 Priority Queue Allocation Registers (PQAR0−3) 3-16. . . . . . . . . . . . . . . . . . . . . . . .
3.8.3 EDMA Channel Interrupt Pending Registers (CIPRL, CIPRH) 3-17. . . . . . . . . . . .
3.8.4 EDMA Channel Interrupt Enable Registers (CIERL, CIERH) 3-19. . . . . . . . . . . . .
3.8.5 EDMA Channel Chain Enable Registers (CCERL, CCERH) 3-21. . . . . . . . . . . . . .
3.8.6 EDMA Event Registers (ERL, ERH) 3-23. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.8.7 EDMA Event Enable Registers (EERL, EERH) 3-25. . . . . . . . . . . . . . . . . . . . . . . . .
3.8.8 Event Clear Registers (ECRL, ECRH) 3-27. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.8.9 Event Set Registers (ESRL, ESRH) 3-29. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.8.10 Event Polarity Registers (EPRL, EPRH) 3-31. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.9 EDMA Channel Parameter Entries 3-33. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.9.1 EDMA Channel Options Parameter (OPT) 3-33. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.9.2 EDMA Channel Source Address Parameter (SRC) 3-37. . . . . . . . . . . . . . . . . . . . . .
3.9.3 EDMA Channel Transfer Count Parameter (CNT) 3-38. . . . . . . . . . . . . . . . . . . . . . .
3.9.4 EDMA Channel Destination Address Parameter (DST) 3-39. . . . . . . . . . . . . . . . . .
3.9.5 EDMA Channel Index Parameter (IDX) 3-40. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.9.6 EDMA Channel Count Reload/Link Address Parameter (RLD) 3-41. . . . . . . . . . . .
3.10 QDMA Registers 3-43. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.10.1 QDMA Channel Options Register (QOPT, QSOPT) 3-44. . . . . . . . . . . . . . . . . . . . .
3.10.2 QDMA Channel Source Address Register (QSRC, QSSRC) 3-45. . . . . . . . . . . . .
3.10.3 QDMA Channel Transfer Count Register (QCNT, QSCNT) 3-45. . . . . . . . . . . . . . .
3.10.4 QDMA Channel Destination Address Register (QDST, QSDST) 3-45. . . . . . . . . .
3.10.5 QDMA Channel Index Register (QIDX, QSIDX) 3-45. . . . . . . . . . . . . . . . . . . . . . . . .
A EDMA Transfers A-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Describes all of the different types of EDMA transfers.
A.1 Element Synchronized 1D-to-1D Transfers A-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
A.2 Frame Synchronized 1D-to-1D Transfers A-19. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
A.3 Array Synchronized 2D-to-2D Transfers A-36. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
A.4 Block Synchronized 2D-to-2D Transfers A-46. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
A.5 Array Synchronized 1D-to-2D Transfers A-56. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
A.6 Block Synchronized 1D-to-2D Transfers A-66. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
A.7 Array Synchronized 2D-to-1D Transfers A-76. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
A.8 Block Synchronized 2D-to-1D Transfers A-86. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
B Revision History B-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Lists the changes made since the previous version of this document.

Figures
viii SPRU234
Figures
1−1 TMS320C621x/C671x/C64x DSP Block Diagram 1-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1−2 EDMA Controller Block Diagram 1-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1−3 1-Dimensional Transfer Data Frame 1-10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1−4 1D Transfer with Element Synchronization (FS = 0) 1-11. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1−5 1D Transfer With Frame Synchronization (FS = 1) 1-12. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1−6 2-Dimensional Transfer Data Block 1-13. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1−7 2D Transfer with Array Synchronization (FS = 0) 1-14. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1−8 2D Transfer with Block Synchronization (FS = 1) 1-15. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1−9 Linked EDMA Transfer 1-22. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1−10 Terminating EDMA Transfers 1-24. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1−11 EDMA Transfer Request Block Diagram 1-33. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1−12 Address Generation/Transfer Logic Block Diagram 1-35. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1−13 Block Move Example Diagram 1-37. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1−14 Block Move Example QDMA Registers Content 1-38. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1−15 Subframe Extraction Example Diagram 1-39. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1−16 Subframe Extraction Example QDMA Registers Content 1-40. . . . . . . . . . . . . . . . . . . . . . . . . .
1−17 Data Sorting Example Diagram 1-41. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1−18 Data Sorting Example QDMA Registers Content 1-42. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1−19 Servicing Incoming McBSP Data Example Diagram 1-44. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1−20 Servicing Incoming McBSP Data Example EDMA Parameters Content 1-45. . . . . . . . . . . . . .
1−21 Servicing Peripheral Bursts Example Diagram 1-46. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1−22 Servicing Peripheral Bursts Example EDMA Parameters Content 1-47. . . . . . . . . . . . . . . . . . .
1−23 Servicing Continuous McBSP Data Example Diagram 1-48. . . . . . . . . . . . . . . . . . . . . . . . . . . .
1−24 Servicing Continuous McBSP Data Example EDMA Parameters Content 1-49. . . . . . . . . . . .
1−25 Servicing Continuous McBSP Data Example EDMA Reload Parameters Content 1-50. . . . .
1−26 Ping-Pong Buffering for McBSP Data Example Diagram 1-52. . . . . . . . . . . . . . . . . . . . . . . . . . .
1−27 Ping-Pong Buffering Example EDMA Parameters Content 1-53. . . . . . . . . . . . . . . . . . . . . . . . .
1−28 Ping-Pong Buffering Example EDMA Pong Parameters Content 1-54. . . . . . . . . . . . . . . . . . . .
1−29 Ping-Pong Buffering Example EDMA Ping Parameters Content 1-55. . . . . . . . . . . . . . . . . . . .
2−1 EDMA Channel Parameter Entries for Each EDMA Event (C621x/C671x DSP) 2-4. . . . . . . .
2−2 EDMA Event Selector Register 0 (ESEL0) 2-9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2−3 EDMA Event Selector Register 1 (ESEL1) 2-10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2−4 EDMA Event Selector Register 3 (ESEL3) 2-11. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2−5 Priority Queue Status Register (PQSR) 2-14. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2−6 EDMA Channel Interrupt Pending Register (CIPR) 2-15. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2−7 EDMA Channel Interrupt Enable Register (CIER) 2-16. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2−8 EDMA Channel Chain Enable Register (CCER) 2-17. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Figures
ixFiguresSPRU234
2−9 EDMA Event Register (ER) 2-18. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2−10 EDMA Event Enable Register (EER) 2-19. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2−11 EDMA Event Clear Register (ECR) 2-20. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2−12 EDMA Event Set Register (ESR) 2-21. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2−13 EDMA Channel Options Parameter (OPT) 2-22. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2−14 EDMA Channel Source Address Parameter (SRC) 2-25. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2−15 EDMA Channel Transfer Count Parameter (CNT) 2-26. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2−16 EDMA Channel Destination Address Parameter (DST) 2-27. . . . . . . . . . . . . . . . . . . . . . . . . . . .
2−17 EDMA Channel Index Parameter (IDX) 2-28. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2−18 EDMA Channel Count Reload/Link Address Parameter (RLD) 2-30. . . . . . . . . . . . . . . . . . . . .
2−19 QDMA Registers 2-32. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2−20 QDMA Channel Options Register (QOPT) 2-32. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2−21 QDMA Channel Source Address Register (QSRC) 2-33. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2−22 QDMA Channel Transfer Count Register (QCNT) 2-33. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2−23 QDMA Channel Destination Address Register (QDST) 2-33. . . . . . . . . . . . . . . . . . . . . . . . . . . .
2−24 QDMA Channel Index Register (QIDX) 2-33. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3−1 EDMA Channel Parameter Entries for Each EDMA Event (C64x DSP) 3-4. . . . . . . . . . . . . . .
3−2 Alternate Transfer Complete Chaining Example 3-7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3−3 Single Large Block Data Transfer 3-8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3−4 Smaller Packet Data Transfers 3-9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3−5 L2 EDMA Access Control Register (EDMAWEIGHT) 3-13. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3−6 Priority Queue Status Register (PQSR) 3-15. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3−7 Priority Queue Allocation Register (PQAR) 3-16. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3−8 EDMA Channel Interrupt Pending Low Register (CIPRL) 3-17. . . . . . . . . . . . . . . . . . . . . . . . . .
3−9 EDMA Channel Interrupt Pending High Register (CIPRH) 3-18. . . . . . . . . . . . . . . . . . . . . . . . .
3−10 EDMA Channel Interrupt Enable Low Register (CIERL) 3-19. . . . . . . . . . . . . . . . . . . . . . . . . . .
3−11 EDMA Channel Interrupt Enable High Register (CIERH) 3-20. . . . . . . . . . . . . . . . . . . . . . . . . .
3−12 EDMA Channel Chain Enable Low Register (CCERL) 3-21. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3−13 EDMA Channel Chain Enable High Register (CCERH) 3-22. . . . . . . . . . . . . . . . . . . . . . . . . . . .
3−14 EDMA Event Low Register (ERL) 3-23. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3−15 EDMA Event High Register (ERH) 3-24. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3−16 EDMA Event Enable Low Register (EERL) 3-25. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3−17 EDMA Event Enable High Register (EERH) 3-26. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3−18 EDMA Event Clear Low Register (ECRL) 3-27. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3−19 EDMA Event Clear High Register (ECRH) 3-28. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3−20 EDMA Event Set Low Register (ESRL) 3-29. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3−21 EDMA Event Set High Register (ESRH) 3-30. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3−22 EDMA Event Polarity Low Register (EPRL) 3-31. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3−23 EDMA Event Polarity High Register (EPRH) 3-32. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3−24 EDMA Channel Options Parameter (OPT) 3-33. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3−25 EDMA Channel Source Address Parameter (SRC) 3-37. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3−26 EDMA Channel Transfer Count Parameter (CNT) 3-38. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3−27 EDMA Channel Destination Address Parameter (DST) 3-39. . . . . . . . . . . . . . . . . . . . . . . . . . . .
3−28 EDMA Channel Index Parameter (IDX) 3-40. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3−29 EDMA Channel Count Reload/Link Address Parameter (RLD) 3-42. . . . . . . . . . . . . . . . . . . . .

Figures
xSPRU234
3−30 QDMA Registers 3-44. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3−31 QDMA Channel Options Register (QOPT) 3-44. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3−32 QDMA Channel Source Address Register (QSRC) 3-45. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3−33 QDMA Channel Transfer Count Register (QCNT) 3-45. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3−34 QDMA Channel Destination Address Register (QDST) 3-45. . . . . . . . . . . . . . . . . . . . . . . . . . . .
3−35 QDMA Channel Index Register (QIDX) 3-45. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
A−1 Element Synchronized 1D-to-1D Transfer (SUM = 00, DUM = 00) A-3. . . . . . . . . . . . . . . . . . .
A−2 Element Synchronized 1D-to-1D Transfer (SUM = 00, DUM = 01) A-4. . . . . . . . . . . . . . . . . . .
A−3 Element Synchronized 1D-to-1D Transfer (SUM = 00, DUM = 10) A-5. . . . . . . . . . . . . . . . . . .
A−4 Element Synchronized 1D-to-1D Transfer (SUM = 00, DUM = 11) A-6. . . . . . . . . . . . . . . . . . .
A−5 Element Synchronized 1D-to-1D Transfer (SUM = 01, DUM = 00) A-7. . . . . . . . . . . . . . . . . . .
A−6 Element Synchronized 1D-to-1D Transfer (SUM = 01, DUM = 01) A-8. . . . . . . . . . . . . . . . . . .
A−7 Element Synchronized 1D-to-1D Transfer (SUM = 01, DUM = 10) A-9. . . . . . . . . . . . . . . . . . .
A−8 Element Synchronized 1D-to-1D Transfer (SUM = 01, DUM = 11) A-10. . . . . . . . . . . . . . . . . .
A−9 Element Synchronized 1D-to-1D Transfer (SUM = 10, DUM = 00) A-11. . . . . . . . . . . . . . . . . .
A−10 Element Synchronized 1D-to-1D Transfer (SUM = 10, DUM = 01) A-12. . . . . . . . . . . . . . . . . .
A−11 Element Synchronized 1D-to-1D Transfer (SUM = 10, DUM = 10) A-13. . . . . . . . . . . . . . . . . .
A−12 Element Synchronized 1D-to-1D Transfer (SUM = 10, DUM = 11) A-14. . . . . . . . . . . . . . . . . .
A−13 Element Synchronized 1D-to-1D Transfer (SUM = 11, DUM = 00) A-15. . . . . . . . . . . . . . . . . .
A−14 Element Synchronized 1D-to-1D Transfer (SUM = 11, DUM = 01) A-16. . . . . . . . . . . . . . . . . .
A−15 Element Synchronized 1D-to-1D Transfer (SUM = 11, DUM = 10) A-17. . . . . . . . . . . . . . . . . .
A−16 Element Synchronized 1D-to-1D Transfer (SUM = 11, DUM = 11) A-18. . . . . . . . . . . . . . . . . .
A−17 Frame Synchronized 1D-to-1D Transfer (SUM = 00, DUM = 00) A-20. . . . . . . . . . . . . . . . . . . .
A−18 Frame Synchronized 1D-to-1D Transfer (SUM = 00, DUM = 01) A-21. . . . . . . . . . . . . . . . . . . .
A−19 Frame Synchronized 1D-to-1D Transfer (SUM = 00, DUM = 10) A-22. . . . . . . . . . . . . . . . . . . .
A−20 Frame Synchronized 1D-to-1D Transfer (SUM = 00, DUM = 11) A-23. . . . . . . . . . . . . . . . . . . .
A−21 Frame Synchronized 1D-to-1D Transfer (SUM = 01, DUM = 00) A-24. . . . . . . . . . . . . . . . . . . .
A−22 Frame Synchronized 1D-to-1D Transfer (SUM = 01, DUM = 01) A-25. . . . . . . . . . . . . . . . . . . .
A−23 Frame Synchronized 1D-to-1D Transfer (SUM = 01, DUM = 10) A-26. . . . . . . . . . . . . . . . . . . .
A−24 Frame Synchronized 1D-to-1D Transfer (SUM = 01, DUM = 11) A-27. . . . . . . . . . . . . . . . . . . .
A−25 Frame Synchronized 1D-to-1D Transfer (SUM = 10, DUM = 00) A-28. . . . . . . . . . . . . . . . . . . .
A−26 Frame Synchronized 1D-to-1D Transfer (SUM = 10, DUM = 01) A-29. . . . . . . . . . . . . . . . . . . .
A−27 Frame Synchronized 1D-to-1D Transfer (SUM = 10, DUM = 10) A-30. . . . . . . . . . . . . . . . . . . .
A−28 Frame Synchronized 1D-to-1D Transfer (SUM = 10, DUM = 11) A-31. . . . . . . . . . . . . . . . . . . .
A−29 Frame Synchronized 1D-to-1D Transfer (SUM = 11, DUM = 00) A-32. . . . . . . . . . . . . . . . . . . .
A−30 Frame Synchronized 1D-to-1D Transfer (SUM = 11, DUM = 01) A-33. . . . . . . . . . . . . . . . . . . .
A−31 Frame Synchronized 1D-to-1D Transfer (SUM = 11, DUM = 10) A-34. . . . . . . . . . . . . . . . . . . .
A−32 Frame Synchronized 1D-to-1D Transfer (SUM = 11, DUM = 11) A-35. . . . . . . . . . . . . . . . . . . .
A−33 Array Synchronized 2D-to-2D Transfer (SUM = 00, DUM = 00) A-37. . . . . . . . . . . . . . . . . . . . .
A−34 Array Synchronized 2D-to-2D Transfer (SUM = 00, DUM = 01) A-38. . . . . . . . . . . . . . . . . . . . .
A−35 Array Synchronized 2D-to-2D Transfer (SUM = 00, DUM = 10) A-39. . . . . . . . . . . . . . . . . . . . .
A−36 Array Synchronized 2D-to-2D Transfer (SUM = 01, DUM = 00) A-40. . . . . . . . . . . . . . . . . . . . .
A−37 Array Synchronized 2D-to-2D Transfer (SUM = 01, DUM = 01) A-41. . . . . . . . . . . . . . . . . . . . .
A−38 Array Synchronized 2D-to-2D Transfer (SUM = 01, DUM = 10) A-42. . . . . . . . . . . . . . . . . . . . .
A−39 Array Synchronized 2D-to-2D Transfer (SUM = 10, DUM = 00) A-43. . . . . . . . . . . . . . . . . . . . .
A−40 Array Synchronized 2D-to-2D Transfer (SUM = 10, DUM = 01) A-44. . . . . . . . . . . . . . . . . . . . .

Figures
xiFiguresSPRU234
A−41 Array Synchronized 2D-to-2D Transfer (SUM = 10, DUM = 10) A-45. . . . . . . . . . . . . . . . . . . . .
A−42 Block Synchronized 2D-to-2D Transfer (SUM = 00, DUM = 00) A-47. . . . . . . . . . . . . . . . . . . . .
A−43 Block Synchronized 2D-to-2D Transfer (SUM = 00, DUM = 01) A-48. . . . . . . . . . . . . . . . . . . . .
A−44 Block Synchronized 2D-to-2D Transfer (SUM = 00, DUM = 10) A-49. . . . . . . . . . . . . . . . . . . . .
A−45 Block Synchronized 2D-to-2D Transfer (SUM = 01, DUM = 00) A-50. . . . . . . . . . . . . . . . . . . . .
A−46 Block Synchronized 2D-to-2D Transfer (SUM = 01, DUM = 01) A-51. . . . . . . . . . . . . . . . . . . . .
A−47 Block Synchronized 2D-to-2D Transfer (SUM = 01, DUM = 10) A-52. . . . . . . . . . . . . . . . . . . . .
A−48 Block Synchronized 2D-to-2D Transfer (SUM = 10, DUM = 00) A-53. . . . . . . . . . . . . . . . . . . . .
A−49 Block Synchronized 2D-to-2D Transfer (SUM = 10, DUM = 01) A-54. . . . . . . . . . . . . . . . . . . . .
A−50 Block Synchronized 2D-to-2D Transfer (SUM = 10, DUM = 10) A-55. . . . . . . . . . . . . . . . . . . . .
A−51 Array Synchronized 1D-to-2D Transfer (SUM = 00, DUM = 00) A-57. . . . . . . . . . . . . . . . . . . . .
A−52 Array Synchronized 1D-to-2D Transfer (SUM = 00, DUM = 01) A-58. . . . . . . . . . . . . . . . . . . . .
A−53 Array Synchronized 1D-to-2D Transfer (SUM = 00, DUM = 10) A-59. . . . . . . . . . . . . . . . . . . . .
A−54 Array Synchronized 1D-to-2D Transfer (SUM = 01, DUM = 00) A-60. . . . . . . . . . . . . . . . . . . . .
A−55 Array Synchronized 1D-to-2D Transfer (SUM = 01, DUM = 01) A-61. . . . . . . . . . . . . . . . . . . . .
A−56 Array Synchronized 1D-to-2D Transfer (SUM = 01, DUM = 10) A-62. . . . . . . . . . . . . . . . . . . . .
A−57 Array Synchronized 1D-to-2D Transfer (SUM = 10, DUM = 00) A-63. . . . . . . . . . . . . . . . . . . . .
A−58 Array Synchronized 1D-to-2D Transfer (SUM = 10, DUM = 01) A-64. . . . . . . . . . . . . . . . . . . . .
A−59 Array Synchronized 1D-to-2D Transfer (SUM = 10, DUM = 10) A-65. . . . . . . . . . . . . . . . . . . . .
A−60 Block Synchronized 1D-to-2D Transfer (SUM = 00, DUM = 00) A-67. . . . . . . . . . . . . . . . . . . . .
A−61 Block Synchronized 1D-to-2D Transfer (SUM = 00, DUM = 01) A-68. . . . . . . . . . . . . . . . . . . . .
A−62 Block Synchronized 1D-to-2D Transfer (SUM = 00, DUM = 10) A-69. . . . . . . . . . . . . . . . . . . . .
A−63 Block Synchronized 1D-to-2D Transfer (SUM = 01, DUM = 00) A-70. . . . . . . . . . . . . . . . . . . . .
A−64 Block Synchronized 1D-to-2D Transfer (SUM = 01, DUM = 01) A-71. . . . . . . . . . . . . . . . . . . . .
A−65 Block Synchronized 1D-to-2D Transfer (SUM = 01, DUM = 10) A-72. . . . . . . . . . . . . . . . . . . . .
A−66 Block Synchronized 1D-to-2D Transfer (SUM = 10, DUM = 00) A-73. . . . . . . . . . . . . . . . . . . . .
A−67 Block Synchronized 1D-to-2D Transfer (SUM = 10, DUM = 01) A-74. . . . . . . . . . . . . . . . . . . . .
A−68 Block Synchronized 1D-to-2D Transfer (SUM = 10, DUM = 10) A-75. . . . . . . . . . . . . . . . . . . . .
A−69 Array Synchronized 2D-to-1D Transfer (SUM = 00, DUM = 00) A-77. . . . . . . . . . . . . . . . . . . . .
A−70 Array Synchronized 2D-to-1D Transfer (SUM = 00, DUM = 01) A-78. . . . . . . . . . . . . . . . . . . . .
A−71 Array Synchronized 2D-to-1D Transfer (SUM = 00, DUM = 10) A-79. . . . . . . . . . . . . . . . . . . . .
A−72 Array Synchronized 2D-to-1D Transfer (SUM = 01, DUM = 00) A-80. . . . . . . . . . . . . . . . . . . . .
A−73 Array Synchronized 2D-to-1D Transfer (SUM = 01, DUM = 01) A-81. . . . . . . . . . . . . . . . . . . . .
A−74 Array Synchronized 2D-to-1D Transfer (SUM = 01, DUM = 10) A-82. . . . . . . . . . . . . . . . . . . . .
A−75 Array Synchronized 2D-to-1D Transfer (SUM = 10, DUM = 00) A-83. . . . . . . . . . . . . . . . . . . . .
A−76 Array Synchronized 2D-to-1D Transfer (SUM = 10, DUM = 01) A-84. . . . . . . . . . . . . . . . . . . . .
A−77 Array Synchronized 2D-to-1D Transfer (SUM = 10, DUM = 10) A-85. . . . . . . . . . . . . . . . . . . . .
A−78 Block Synchronized 2D-to-1D Transfer (SUM = 00, DUM = 00) A-87. . . . . . . . . . . . . . . . . . . . .
A−79 Block Synchronized 2D-to-1D Transfer (SUM = 00, DUM = 01) A-88. . . . . . . . . . . . . . . . . . . . .
A−80 Block Synchronized 2D-to-1D Transfer (SUM = 00, DUM = 10) A-89. . . . . . . . . . . . . . . . . . . . .
A−81 Block Synchronized 2D-to-1D Transfer (SUM = 01, DUM = 00) A-90. . . . . . . . . . . . . . . . . . . . .
A−82 Block Synchronized 2D-to-1D Transfer (SUM = 01, DUM = 01) A-91. . . . . . . . . . . . . . . . . . . . .
A−83 Block Synchronized 2D-to-1D Transfer (SUM = 01, DUM = 10) A-92. . . . . . . . . . . . . . . . . . . . .
A−84 Block Synchronized 2D-to-1D Transfer (SUM = 10, DUM = 00) A-93. . . . . . . . . . . . . . . . . . . . .
A−85 Block Synchronized 2D-to-1D Transfer (SUM = 10, DUM = 01) A-94. . . . . . . . . . . . . . . . . . . . .
A−86 Block Synchronized 2D-to-1D Transfer (SUM = 10, DUM = 10) A-95. . . . . . . . . . . . . . . . . . . . .

Tables
xii SPRU234
Tables
1−1 Differences Between the C621x/C671x and C64x EDMA 1-4. . . . . . . . . . . . . . . . . . . . . . . . . . .
1−2 EDMA Channel Synchronization Events—C621x/C671x DSP 1-7. . . . . . . . . . . . . . . . . . . . . . .
1−3 EDMA Channel Synchronization Events—C64x DSP 1-8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1−4 EDMA Element and Frame/Array Count Updates 1-18. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1−5 Source/Destination Address Update Modes 1-19. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1−6 EDMA Source Address Parameter Updates 1-20. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1−7 EDMA Destination Address Parameter Updates 1-21. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1−8 Channel Completion Conditions 1-23. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1−9 Transfer Complete Code (TCC) to EDMA Interrupt Mapping (C621x/C671x DSP) 1-26. . . .
1−10 Transfer Complete Code (TCC) to EDMA Interrupt Mapping (C64x DSP) 1-26. . . . . . . . . . . .
1−11 QDMA Transfer Length 1-30. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1−12 Cache Controller Data Transfers (C621x/C671x DSP) 1-34. . . . . . . . . . . . . . . . . . . . . . . . . . . .
2−1 EDMA Parameter RAM Contents (C621x/C671x DSP) 2-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2−2 EDMA Channel Parameter Descriptions (C621x/C671x DSP) 2-4. . . . . . . . . . . . . . . . . . . . . . .
2−3 Programmable Priority Levels for Data Requests (C621x/C671x DSP) 2-6. . . . . . . . . . . . . . .
2−4 Transfer Request Queues (C621x/C671x DSP) 2-7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2−5 EDMA Control Registers (C621x/C671x DSP) 2-8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2−6 EDMA Event Selector Register 0 (ESEL0) Field Descriptions 2-9. . . . . . . . . . . . . . . . . . . . . . .
2−7 EDMA Event Selector Register 0 (ESEL1) Field Descriptions 2-10. . . . . . . . . . . . . . . . . . . . . .
2−8 EDMA Event Selector Register 0 (ESEL3) Field Descriptions 2-11. . . . . . . . . . . . . . . . . . . . . .
2−9 Default EDMA Event for EDMA Channel 2-12. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2−10 EDMA Event for EDMA Event Selector Value 2-12. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2−11 Priority Queue Status Register (PQSR) Field Descriptions 2-14. . . . . . . . . . . . . . . . . . . . . . . . .
2−12 EDMA Channel Interrupt Pending Register (CIPR) Field Descriptions 2-15. . . . . . . . . . . . . . .
2−13 EDMA Channel Interrupt Enable Register (CIER) Field Descriptions 2-16. . . . . . . . . . . . . . . .
2−14 EDMA Channel Chain Enable Register (CCER) Field Descriptions 2-17. . . . . . . . . . . . . . . . .
2−15 EDMA Event Register (ER) Field Descriptions 2-18. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2−16 EDMA Event Enable Register (EER) Field Descriptions 2-19. . . . . . . . . . . . . . . . . . . . . . . . . . .
2−17 EDMA Event Clear Register (ECR) Field Descriptions 2-20. . . . . . . . . . . . . . . . . . . . . . . . . . . .
2−18 EDMA Event Set Register (ESR) Field Descriptions 2-21. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2−19 EDMA Parameter Entries (C621x/C671x DSP) 2-22. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2−20 EDMA Channel Options Parameter (OPT) Field Descriptions 2-23. . . . . . . . . . . . . . . . . . . . . .
2−21 EDMA Channel Source Address Parameter (SRC) Field Descriptions 2-25. . . . . . . . . . . . . . .
2−22 EDMA Channel Transfer Count Parameter (CNT) Field Descriptions 2-26. . . . . . . . . . . . . . . .
2−23 EDMA Channel Destination Address Parameter (DST) Field Descriptions 2-27. . . . . . . . . . .
2−24 EDMA Channel Index Parameter (IDX) Field Descriptions 2-28. . . . . . . . . . . . . . . . . . . . . . . . .
2−25 EDMA Channel Count Reload/Link Address Parameter (RLD) Field Descriptions 2-30. . . . .

Tables
xiiiTablesSPRU234
3−1 EDMA Parameter RAM Contents (C64x DSP) 3-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3−2 EDMA Channel Parameter Descriptions (C64x DSP) 3-4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3−3 Programmable Priority Levels for Data Requests (C64x DSP) 3-11. . . . . . . . . . . . . . . . . . . . . .
3−4 Transfer Request Queues (C64x DSP) 3-12. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3−5 L2 EDMA Access Control Register (EDMAWEIGHT) Field Descriptions 3-13. . . . . . . . . . . . .
3−6 EDMA Control Registers (C64x DSP) 3-14. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3−7 Priority Queue Status Register (PQSR) Field Descriptions 3-15. . . . . . . . . . . . . . . . . . . . . . . . .
3−8 Priority Queue Allocation Register (PQAR) Field Descriptions 3-16. . . . . . . . . . . . . . . . . . . . . .
3−9 EDMA Channel Interrupt Pending Low Register (CIPRL) Field Descriptions 3-17. . . . . . . . . .
3−10 EDMA Channel Interrupt Pending High Register (CIPRH) Field Descriptions 3-18. . . . . . . . .
3−11 EDMA Channel Interrupt Enable Low Register (CIERL) Field Descriptions 3-19. . . . . . . . . . .
3−12 EDMA Channel Interrupt Enable High Register (CIERH) Field Descriptions 3-20. . . . . . . . . .
3−13 EDMA Channel Chain Enable Low Register (CCERL) Field Descriptions 3-21. . . . . . . . . . . .
3−14 EDMA Channel Chain Enable High Register (CCERH) Field Descriptions 3-22. . . . . . . . . . .
3−15 EDMA Event Low Register (ERL) Field Descriptions 3-23. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3−16 EDMA Event High Register (ERH) Field Descriptions 3-24. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3−17 EDMA Event Enable Low Register (EERL) Field Descriptions 3-25. . . . . . . . . . . . . . . . . . . . . .
3−18 EDMA Event Enable High Register (EERH) Field Descriptions 3-26. . . . . . . . . . . . . . . . . . . . .
3−19 EDMA Event Clear Low Register (ECRL) Field Descriptions 3-27. . . . . . . . . . . . . . . . . . . . . . .
3−20 EDMA Event Clear High Register (ECRH) Field Descriptions 3-28. . . . . . . . . . . . . . . . . . . . . .
3−21 EDMA Event Set Low Register (ESRL) Field Descriptions 3-29. . . . . . . . . . . . . . . . . . . . . . . . .
3−22 EDMA Event Set High Register (ESRH) Field Descriptions 3-30. . . . . . . . . . . . . . . . . . . . . . . .
3−23 EDMA Event Polarity Low Register (EPRL) Field Descriptions 3-31. . . . . . . . . . . . . . . . . . . . .
3−24 EDMA Event Polarity High Register (EPRH) Field Descriptions 3-32. . . . . . . . . . . . . . . . . . . . .
3−25 EDMA Parameter Entries (C64x DSP) 3-33. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3−26 EDMA Channel Options Parameter (OPT) Field Descriptions 3-34. . . . . . . . . . . . . . . . . . . . . .
3−27 EDMA Channel Source Address Parameter (SRC) Field Descriptions 3-37. . . . . . . . . . . . . . .
3−28 EDMA Channel Transfer Count Parameter (CNT) Field Descriptions 3-38. . . . . . . . . . . . . . . .
3−29 EDMA Channel Destination Address Parameter (DST) Field Descriptions 3-39. . . . . . . . . . .
3−30 EDMA Channel Index Parameter (IDX) Field Descriptions 3-40. . . . . . . . . . . . . . . . . . . . . . . . .
3−31 EDMA Channel Count Reload/Link Address Parameter (RLD) Field Descriptions 3-42. . . . .
A−1 Element Synchronized (FS = 0) 1D-to-1D Transfers A-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
A−2 Frame Synchronized (FS = 1) 1D-to-1D Transfers A-19. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
A−3 Array Synchronized (FS = 0) 2D-to-2D Transfers A-36. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
A−4 Block Synchronized (FS = 1) 2D-to-2D Transfers A-46. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
A−5 Array Synchronized (FS = 0) 1D-to-2D Transfers A-56. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
A−6 Block Synchronized (FS = 1) 1D-to-2D Transfers A-66. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
A−7 Array Synchronized (FS = 0) 2D-to-1D Transfers A-76. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
A−8 Block Synchronized (FS = 1) 2D-to-1D Transfers A-86. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
B−1 Document Revision History B-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1-1OverviewSPRU234
Overview
This chapter provides an overview and describes the common operation of the
enhanced direct memory access (EDMA) controller in the digital signal
processors (DSPs) of the TMS320C6000DSP family. This chapter also
describes the quick DMA (QDMA) used for fast data requests by the CPU. For
operation and registers unique to the TMS320C621x/C671x EDMA, see
Chapter 2. For operation and registers unique to the TMS320C64xEDMA,
see Chapter 3.
Topic Page
1.1 Overview 1-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.2 EDMA Terminology 1-5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.3 Initiating an EDMA Transfer 1-6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.4 Synchronization of EDMA Transfers 1-7. . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.5 Types of EDMA Transfers 1-10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.6 Element Size and Alignment 1-16. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.7 Element and Frame/Array Count Updates 1-18. . . . . . . . . . . . . . . . . . . . . .
1.8 Source/Destination Address Updates 1-19. . . . . . . . . . . . . . . . . . . . . . . . . .
1.9 Linking EDMA Transfers 1-22. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.10 Terminating an EDMA Transfer 1-24. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.11 EDMA Interrupt Generation 1-25. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.12 EDMA Performance 1-29. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.13 Quick DMA (QDMA) 1-30. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.14 Emulation Operation 1-32. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.15 Transfer Request Submission 1-32. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.16 Transfer Examples 1-37. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Chapter 1

Overview
Overview1-2 SPRU234
1.1 Overview
The enhanced direct memory access (EDMA) controller handles all data
transfers between the level-two (L2) cache/memory controller and the device
peripherals on the C621x/C671x/C64x DSP, as shown in Figure 1−1. These
data transfers include cache servicing, non-cacheable memory accesses,
user-programmed data transfers, and host accesses.
The EDMA controller in the C621x/C671x/C64x DSP has a different
architecture from the previous DMA controller in the C620x/C670x devices.
The EDMA includes several enhancements to the DMA, such as 64 channels
for the C64x DSP or 16 channels for the C621x/C671x DSP, with
programmable priority, and the ability to link and chain data transfers. The
EDMA allows movement of data to/from any addressable memory spaces,
including internal memory (L2 SRAM), peripherals, and external memory.
Figure 1−1. TMS320C621x/C671x/C64x DSP Block Diagram
Data path 2
External
memory
interface
(EMIF)
Other
Peripherals
Power down logic
Enhanced
DMA
controller
(EDMA)
Timers
L1P cache direct mapped
L1 S1 M1 D1 D2 M2 S2 L2
A register file
Data path 1
B register file
Interrupt control
CPU core
Instruction fetch
Instruction dispatch
Instruction decode In-circuit emulation
Control registers
L2 memory
4 banks
L1D
controller
L1D cache
2-way set
associative
L1P
controller

Overview
1-3OverviewSPRU234
Figure 1−2 shows a block diagram of the EDMA controller. The EDMA controller
comprises:
Event and interrupt processing registers
Event encoder
Parameter RAM
Address generation hardware
The event register captures EDMA events. An event is a synchronization signal
that triggers an EDMA channel to start a transfer. If events occur
simultaneously, the event encoder resolves them. The transfer parameters
corresponding to this event are stored in the EDMA parameter RAM, and are
passed onto the address generation hardware, which address the EMIF
and/or peripherals to perform the necessary read and write transactions.
Figure 1−2. EDMA Controller Block Diagram
encoder
Event
to EMIF/peripherals
FSM
Address
generation
(scratch area)
Unused
parameters
Reload channel N
parameters
Reload channel 1
parameters
Reload channel 0
Channel N parameters
Channel 1 parameters
Channel 0 parameters
Events (serial ports, FIFO
AFE, external devices)
EDMA parameter RAM
/internal memory

Overview
Overview1-4 SPRU234
The EDMA has the capability of performing fast and efficient transfers by
accepting a quick DMA (QDMA) request from the CPU. A QDMA transfer is
best suited for applications that require quick data transfers, such as data re-
quests in a tight loop algorithm. See section 1.13 for more details. Table 1−1
summarizes the difference between the C6000 EDMAs.
Table 1−1. Differences Between the C621x/C671x and C64x EDMA
Features C621x/C671x EDMA C64x EDMA
Alternate transfer complete
chaining and interrupt
Does not apply. Supported
CIPR, CIER, CCER, ER, EER,
ECR, ESR
Each of these registers supports
16 channels.
Each of these registers supports
64 channels and is expanded into
two registers (low and high).
EDMA clock rate EDMA clock rate equals
CPU clock rate.
EDMA clock rate equals one half of
CPU clock rate (CPU/2).
EDMA transfers possible on all
priority queues
EDMA cannot transfer on Q0. EDMA transfers possible on all
priority queues.
Event polarity selection Does not apply. Supported.
L2 controller transfers possible
on all priority queues
L2 controller transfers on Q0 only. L2 controller transfers possible on all
priority queues.
Number of channels 6 channels. 64 channels.
PQAR0−3, EPRL, EPRH Does not apply. Supported.
Programmable priority queue
allocation
Does not apply. Supported.
Supports peripheral device
transfers
Does not apply. Supported.
Transfer chaining on channels Only channels 8 to 11 can be
chained.
All channels can be chained.

EDMA Terminology
1-5OverviewSPRU234
1.2 EDMA Terminology
The following definitions help in understanding some of the terms used in this
document:
Element transfer: The transfer of a single data element from source to
destination. Each element can be transferred based on a synchronization
event if required. Element transfer is used in context with 1-dimensional
(1D) transfer.
Frame: A group of elements comprise a frame. A frame can have stag-
gered or contiguous elements. A frame can be transferred with or without
a synchronizing event. Frame is used in context with 1-dimensional (1D)
transfer.
Array: A group of contiguous elements comprise an array. The elements
in an array cannot be spaced by an element index. Array is used in context
with 2-dimensional (2D) transfer.
Block: A group of arrays or frames form a block. For 1-dimensional (1D)
transfers, a group of frames form a block. For 2-dimensional (2D) trans-
fers, a group of arrays form a block.
1-dimensional (1D) transfer: A group of frames comprise a 1D block.
The number of frames (FRMCNT) in a block can range from 1 to 65536.
The number of elements (ELECNT) per frame can range from 1 to 65535.
Either elements or full frames can be transferred at a time.
2-dimensional (2D) transfer: A group of arrays comprise a 2D block. The
first dimension is the number of contiguous elements in an array, and the
second dimension is the number of such arrays. The number of arrays
(FRMCNT) in a block can range from 1 to 65536. Either arrays or the entire
block can be transferred at a time.

Initiating an EDMA Transfer
Overview1-6 SPRU234
1.3 Initiating an EDMA Transfer
There are two ways to initiate data transfer using the EDMA:
CPU-initiated EDMA
Event-triggered EDMA (this is a more typical usage of the EDMA)
Event-triggered EDMA transfer allows the submission of transfer requests to
occur automatically based on system events, without any intervention by the
CPU. The design includes CPU-initiated transfer for added control and robust-
ness. Quick-DMA (QDMA) transfers, discussed in section 1.13, are the
preferred method of issuing CPU-synchronized data transfers. Each EDMA
channel can be started independently. The CPU can also disable an EDMA
channel by disabling the event associated with that channel.
CPU-initiated EDMA or unsynchronized EDMA: The CPU can write to
the event set register (ESR) to start an EDMA transfer. Writing a 1 to the
corresponding event in ESR triggers an EDMA event. Just as with a normal
event, the transfer parameters in the EDMA parameter RAM corresponding
to this event are passed to the address generation hardware, which
performs the requested access of the EMIF, L2 memory or peripherals, as
appropriate. CPU-initiated EDMA transfers are unsynchronized data
transfers. The event’s enable bit does not have to be set in the event
enable register (EER) for CPU-initiated EDMA transfers, because a CPU
write to ESR is treated as a real-time event.
Event-triggered EDMA: An event that is latched in the event register (ER)
via the event encoder causes its transfer parameters to be passed on to
the address generation hardware, which performs the requested
accesses. Although the event causes this transfer, it is very important that
the event itself be enabled by the CPU. Writing a 1 to the corresponding
bit in the event enable register (EER) enables an event. Alternatively, an
event is still latched in ER even if its corresponding enable bit in EER is
0 (disabled). The EDMA transfer related to this event occurs as soon as
it is enabled in EER. In addition to event enable using EER, the completion
of a transfer can also trigger another EDMA transfer through chaining and
the channel chain enable register (CCER). See section 2.3 or section 3.3
for chaining details.

Synchronization of EDMA Transfers
1-7OverviewSPRU234
1.4 Synchronization of EDMA Transfers
All EDMA channels are tied to a specific synchronization event.
Synchronization allows EDMA transfers to be triggered by events from
peripherals, interrupts from external hardware, or an EDMA transfer
completion event. A channel only requests a data transfer when it receives its
event or when the CPU manually synchronizes it (by writing to ESR). The
amount of data to be transferred depends on the channel’s configuration.
A channel can submit an entire frame/block when frame/block-synchronized,
or a subset of a frame (element or array, depending on dimension) when
element/array-synchronized.
Table 1−2 and Table 1−3 list the synchronization events associated with each
of the programmable EDMA channels for the C621x/C671x DSP and
C64x DSP, respectively.
The association of an event to a channel is fixed. Unlike the existing
C6201-type DMA, each of the EDMA channels has one specific event associ-
ated with it. For example, if bit 4 (event 4) in EER is set, then an external inter-
rupt on EXT_INT4 pin initiates a transfer on EDMA channel 4.
Events originate from a peripheral such as the McBSP (R/XEVT) or an external
device in the form of an external interrupt (EXT_INTn). The event is specific
to a channel, the priority of each event can be specified independently in the
transfer parameters stored in the EDMA parameter RAM.
Table 1−2. EDMA Channel Synchronization Events—C621x/C671x DSP†
EDMA Channel
Number‡Event Acronym Event Description
0 DSPINT Host port to DSP interrupt
1 TINT0 Timer 0 interrupt
2 TINT1 Timer 1 interrupt
3 SD_INT EMIF SDRAM timer interrupt
4 EXT_INT4 External interrupt pin 4
5 EXT_INT5 External interrupt pin 5
6 EXT_INT6 External interrupt pin 6
7 EXT_INT7 External interrupt pin 7
8 EDMA_TCC8 EDMA transfer complete code 1000b interrupt
9 EDMA_TCC9 EDMA transfer complete code 1001b interrupt
†For C6713/C6712C/C6711C DSP, the mapping of EDMA events to the EDMA channels is programmable (see section 2.6.1).
‡EDMA channels 8 to 11 are used for transfer chaining only. See section 2.3, Chaining EDMA Channels by an Event.