Texas Instruments TMS320DM646x User manual

TMS320DM646x DMSoCDDR2 Memory Controller
User's Guide
Literature Number: SPRUEQ4C
February 2009

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Contents
Preface ........................................................................................................................................ 61 Introduction ......................................................................................................................... 71.1 Purpose of the Peripheral ................................................................................................ 71.2 Features .................................................................................................................... 71.3 Functional Block Diagram ................................................................................................ 71.4 Supported Use Case Statement ........................................................................................ 81.5 Industry Standard(s) Compliance Statement .......................................................................... 82 Architecture ........................................................................................................................ 82.1 Clock Control .............................................................................................................. 82.2 Memory Map ............................................................................................................. 102.3 Signal Descriptions ...................................................................................................... 102.4 Protocol Description(s) .................................................................................................. 112.5 Memory Width and Byte Alignment ................................................................................... 192.6 Address Mapping ........................................................................................................ 202.7 DDR2 Memory Controller Interface ................................................................................... 232.8 Refresh Scheduling ..................................................................................................... 262.9 Self-Refresh Mode....................................................................................................... 262.10 Reset Considerations ................................................................................................... 272.11 VTP IO Buffer Calibration .............................................................................................. 282.12 Auto-Initialization Sequence ............................................................................................ 282.13 Interrupt Support ......................................................................................................... 302.14 DMA Event Support ..................................................................................................... 312.15 Power Management ..................................................................................................... 312.16 Emulation Considerations .............................................................................................. 323 Use Cases ......................................................................................................................... 333.1 Connecting the DDR2 Memory Controller to DDR2 Memory ...................................................... 333.2 Configuring Memory-Mapped Registers to Meet DDR2-667 Specification ...................................... 334 Registers ........................................................................................................................... 394.1 SDRAM Status Register (SDRSTAT) ................................................................................. 394.2 SDRAM Bank Configuration Register (SDBCR) ..................................................................... 404.3 SDRAM Refresh Control Register (SDRCR)......................................................................... 424.4 SDRAM Timing Register (SDTIMR) ................................................................................... 434.5 SDRAM Timing Register 2 (SDTIMR2) ............................................................................... 444.6 Peripheral Bus Burst Priority Register (PBBPR) .................................................................... 454.7 Interrupt Raw Register (IRR) ........................................................................................... 464.8 Interrupt Masked Register (IMR) ...................................................................................... 474.9 Interrupt Mask Set Register (IMSR) ................................................................................... 484.10 Interrupt Mask Clear Register (IMCR) ................................................................................ 494.11 DDR PHY Control Register (DDRPHYCR) ........................................................................... 504.12 DDR VTP IO Control Register (VTPIOCR) ........................................................................... 51Appendix A Revision History ...................................................................................................... 52
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List of Figures
1 Data Paths to DDR2 Memory Controller .................................................................................. 82 DDR2 Memory Controller Clock Block Diagram ......................................................................... 93 DDR2 Memory Controller Signals ........................................................................................ 104 Refresh Command ......................................................................................................... 135 DCAB Command ........................................................................................................... 146 DEAC Command ........................................................................................................... 157 ACTV Command ........................................................................................................... 168 DDR2 READ Command ................................................................................................... 179 DDR2 WRT Command .................................................................................................... 1810 DDR2 MRS and EMRS Command ...................................................................................... 1911 Byte Alignment .............................................................................................................. 2012 Logical Address-to-DDR2 SDRAM Address Map ...................................................................... 2213 DDR2 SDRAM Column, Row, and Bank Access ...................................................................... 2314 DDR2 Memory Controller FIFO Block Diagram ........................................................................ 2415 DDR2 Memory Controller Reset Block Diagram ....................................................................... 2716 DDR2 Memory Controller Power and Sleep Controller Diagram .................................................... 3117 Connecting DDR2 Memory Controller for 32-Bit Connection ......................................................... 3418 Connecting DDR2 Memory Controller for 16-Bit Connection ......................................................... 3519 SDRAM Status Register (SDRSTAT).................................................................................... 3920 SDRAM Bank Configuration Register (SDBCR) ....................................................................... 4021 SDRAM Refresh Control Register (SDRCR) ........................................................................... 4222 SDRAM Timing Register (SDTIMR) ..................................................................................... 4323 SDRAM Timing Register 2 (SDTIMR2).................................................................................. 4424 Peripheral Bus Burst Priority Register (PBBPR) ....................................................................... 4525 Interrupt Raw Register (IRR) ............................................................................................. 4626 Interrupt Masked Register (IMR) ......................................................................................... 4727 Interrupt Mask Set Register (IMSR) ..................................................................................... 4828 Interrupt Mask Clear Register (IMCR) ................................................................................... 4929 DDR PHY Control Register (DDRPHYCR) ............................................................................. 5030 DDR VTP IO Control Register (VTPIOCR) ............................................................................. 51
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List of Tables
1 PLLC2 Configuration ........................................................................................................ 92 DDR2 Memory Controller Signal Descriptions ......................................................................... 113 DDR2 SDRAM Commands ............................................................................................... 114 Truth Table for DDR2 SDRAM Commands ............................................................................ 125 Addressable Memory Ranges ............................................................................................ 196 Bank Configuration Register Fields for Address Mapping ............................................................ 207 Logical Address-to-DDR2 SDRAM Address Map for 32-Bit SDRAM ............................................... 218 Logical Address-to-DDR2 SDRAM Address Map for 16-Bit SDRAM ............................................... 219 DDR2 Memory Controller FIFO Description ............................................................................ 2310 Refresh Urgency Levels ................................................................................................... 2611 Reset Sources .............................................................................................................. 2712 DDR2 SDRAM Configuration by MRS Command ..................................................................... 2913 DDR2 SDRAM Configuration by EMRS(1) Command ................................................................ 2914 SDBCR Configuration ..................................................................................................... 3315 DDR2 Memory Refresh Specification ................................................................................... 3616 SDRCR Configuration ..................................................................................................... 3617 SDTIMR Configuration ..................................................................................................... 3718 SDTIMR2 Configuration ................................................................................................... 3719 DDRPHYCR Configuration ................................................................................................ 3820 DDR2 Memory Controller Registers ..................................................................................... 3921 SDRAM Status Register (SDRSTAT) Field Descriptions ............................................................. 3922 SDRAM Bank Configuration Register (SDBCR) Field Descriptions ................................................. 4023 SDRAM Refresh Control Register (SDRCR) Field Descriptions ..................................................... 4224 SDRAM Timing Register (SDTIMR) Field Descriptions ............................................................... 4325 SDRAM Timing Register 2 (SDTIMR2) Field Descriptions ........................................................... 4426 Peripheral Bus Burst Priority Register (PBBPR) Field Descriptions ................................................. 4527 Interrupt Raw Register (IRR) Field Descriptions ....................................................................... 4628 Interrupt Masked Register (IMR) Field Descriptions ................................................................... 4729 Interrupt Mask Set Register (IMSR) Field Descriptions ............................................................... 4830 Interrupt Mask Clear Register (IMCR) Field Descriptions ............................................................. 4931 DDR PHY Control Register (DDRPHYCR) Field Descriptions ....................................................... 5032 DDR VTP IO Control Register (VTPIOCR) Field Descriptions ....................................................... 51A-1 Document Revision History ............................................................................................... 52
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PrefaceSPRUEQ4C – February 2009
Read This First
About This Manual
This document describes the DDR2 memory controller in the TMS320DM646x Digital MediaSystem-on-Chip (DMSoC).
Notational Conventions
This document uses the following conventions.•Hexadecimal numbers are shown with the suffix h. For example, the following number is 40hexadecimal (decimal 64): 40h.•Registers in this document are shown in figures and described in tables.– Each register figure shows a rectangle divided into fields that represent the fields of the register.Each field is labeled with its bit name, its beginning and ending bit numbers above, and itsread/write properties below. A legend explains the notation used for the properties.– Reserved bits in a register figure designate a bit that is used for future device expansion.
Related Documentation From Texas InstrumentsThe following documents describe the TMS320DM646x Digital Media System-on-Chip (DMSoC). Copiesof these documents are available on the Internet at www.ti.com .Tip: Enter the literature number in thesearch box provided at www.ti.com.
The current documentation that describes the DM646x DMSoC, related peripherals, and other technicalcollateral, is available in the C6000 DSP product folder at: www.ti.com/c6000 .
SPRUEP8 —TMS320DM646x DMSoC DSP Subsystem Reference Guide. Describes the digital signalprocessor (DSP) subsystem in the TMS320DM646x Digital Media System-on-Chip (DMSoC).
SPRUEP9 —TMS320DM646x DMSoC ARM Subsystem Reference Guide. Describes the ARMsubsystem in the TMS320DM646x Digital Media System-on-Chip (DMSoC). The ARM subsystem isdesigned to give the ARM926EJ-S (ARM9) master control of the device. In general, the ARM isresponsible for configuration and control of the device; including the DSP subsystem and a majorityof the peripherals and external memories.
SPRUEQ0 —TMS320DM646x DMSoC Peripherals Overview Reference Guide. Provides an overviewand briefly describes the peripherals available on the TMS320DM646x Digital MediaSystem-on-Chip (DMSoC).
SPRAA84 —TMS320C64x to TMS320C64x+ CPU Migration Guide. Describes migrating from theTexas Instruments TMS320C64x digital signal processor (DSP) to the TMS320C64x+ DSP. Theobjective of this document is to indicate differences between the two cores. Functionality in thedevices that is identical is not included.
SPRU732 —TMS320C64x/C64x+ DSP CPU and Instruction Set Reference Guide. Describes the CPUarchitecture, pipeline, instruction set, and interrupts for the TMS320C64x and TMS320C64x+ digitalsignal processors (DSPs) of the TMS320C6000 DSP family. The C64x/C64x+ DSP generationcomprises fixed-point devices in the C6000 DSP platform. The C64x+ DSP is an enhancement ofthe C64x DSP with added functionality and an expanded instruction set.
SPRU871 —TMS320C64x+ DSP Megamodule Reference Guide. Describes the TMS320C64x+ digitalsignal processor (DSP) megamodule. Included is a discussion on the internal direct memory access(IDMA) controller, the interrupt controller, the power-down controller, memory protection, bandwidthmanagement, and the memory and cache.
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1 Introduction
1.1 Purpose of the Peripheral
1.2 Features
1.3 Functional Block Diagram
User's GuideSPRUEQ4C – February 2009
DDR2 Memory Controller
This document describes the DDR2 memory controller in the TMS320DM646x Digital MediaSystem-on-Chip (DMSoC).
The DDR2 memory controller is used to interface with JESD79D-2A standard compliant DDR2 SDRAMdevices. Memories types such as DDR1 SDRAM, SDR SDRAM, SBSRAM, and asynchronous memoriesare not supported. The DDR2 memory controller is the major memory location for program and datastorage.
The DDR2 memory controller supports the following features:•JESD79D-2A standard compliant DDR2 SDRAM•256 MBbyte memory space•Data bus width of 32 or 16 bits•CAS latencies: 2, 3, 4, and 5•Internal banks: 1, 2, 4, and 8•Burst length: 8•Burst type: sequential•1 CS signal•Page sizes: 256, 512, 1024, and 2048•SDRAM autoinitialization
•Self-refresh mode•Prioritized refresh•Programmable refresh rate and backlog counter•Programmable timing parameters•Little endian
The DDR2 memory controller is the main interface to external DDR2 memory. Figure 1 displays thegeneral data paths to on-chip peripherals and external DDR2 SDRAM.
Master peripherals, EDMA, the ARM processor, and DSP can access the DDR2 memory controllerthrough the switched central resource (SCR).
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SCR DDR2
memory
controller
BUS BUS External
DDR2 SDRAM
ARM
DSP
Master
peripherals
EDMA
VPSS
1.4 Supported Use Case Statement
1.5 Industry Standard(s) Compliance Statement
2 Architecture
2.1 Clock Control
2.1.1 Clock Source
Architecture www.ti.com
Figure 1. Data Paths to DDR2 Memory Controller
The DDR2 memory controller supports JESD79D-2A DDR2-667 SDRAM memories utilizing either 32-bitor 16-bit of the DDR2 memory controller data bus. See Section 3 for more details.
•The DDR2 memory controller does not support the On Die Termination (ODT) function.•The DDR2 memory controller supports differential DQS signals.
This section describes the architecture of the DDR2 memory controller as well as how it is structured andhow it works within the context of the system-on-a-chip. The DDR2 memory controller can gluelesslyinterface to most standard DDR2 SDRAM devices and supports such features as self-refresh mode andprioritized refresh. In addition, it provides flexibility through programmable parameters such as the refreshrate, CAS latency, and many SDRAM timing parameters. The following sections include details on how tointerface and properly configure the DDR2 memory controller to perform read and write operations toexternally-connected DDR2 SDRAM devices. Also, Section 3 provides a detailed example of interfacingthe DDR2 memory controller to a common DDR2 SDRAM device.
The DDR2 memory controller receives two input clocks from internal clock sources, SYSCLK2 andPLL2_SYSCLK1 (Figure 2 ). SYSCLK2 is a divided-down version of the DSP clock. PLL2_SYSCLK1should be configured to clock at the frequency of the desired data rate, or stated similarly, it shouldoperate at twice the frequency of the desired DDR2 memory clock. DDR_CLK and DDR_CLK are the twooutput clocks of the DDR2 memory controller providing the interface clock to the DDR2 SDRAM memory.These two clocks operate at a frequency of PLL2_SYSCLK1/2.
SYSCLK2 and PLL2_SYSCLK1 are sourced from two independent PLLs (Figure 2 ). SYSCLK2 is sourcedfrom PLL controller 1 (PLLC1) and PLL2_SYSCLK1 is sourced from PLL controller 2 (PLLC2).
SYSCLK2 is clocked at a fixed divider ratio of 2 in PLL1, meaning SYSCLK2 is clocked at a frequency ofPLL1/2. Once inside the DDR2 memory controller, this signal is called VCLK.
PLLC2 has a programmable divider that is used to divide-down the output clock of PLL2. This dividershould be configured such that PLLC2 supplies the PLL2_SYSCLK1 at the desired frequency. Forexample, if a 310.5-MHZ DDR2 interface clock (DDR_CLK) is desired, then PLLC2 must be configured togenerate a 621-MHZ clock on PLL2_SYSCLK1. Once inside the DDR2 memory controller,PLL2_SYSCLK1 is called X2_CLK.
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DDR2
memory
controller
/1
PLLC2
/2
PLLC1
X2_CLK
VCLK
DDR_CLK DDR_CLK
PLL2_SYSCLK1
PLL1_SYSCLK2
2.1.2 Clock Configuration
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Figure 2. DDR2 Memory Controller Clock Block Diagram
The frequency of PLL2_SYSCLK1 is configured by selecting the appropriate PLL multiplier and dividerratio. The PLL multiplier and divider ratio are selected by programming registers within PLLC2. Table 1shows a list of PLL multiplier and divider settings to achieve certain DDR2 frequencies. The data inTable 1 is derived by assuming a 27-MHZ reference clock. See the TMS320DM646x DMSoC ARMSubsystem Reference Guide (SPRUEP9 ) for information on the PLL controller.
Note: PLLC2 should be configured and a stable clock present on PLL2_SYSCLK1 before releasingthe DDR2 memory controller from reset.
Table 1. PLLC2 Configuration
PLL PLL PLL2_SYSCLK1 DDR2 ClockMultiplier Frequency (MHZ) Divider Ratio Frequency (MHZ) Frequency (MHZ)
13 351 1 351 175.514 378 1 378 18915 405 1 405 202.516 432 1 432 21617 459 1 459 229.518 486 1 486 24319 513 1 513 256.520 540 1 540 27021 567 1 567 283.522 594 1 594 29723
(1)
621 1 621 310.5(1)
Applies only to 729 MHZ devices.
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2.1.3 DR2 Memory Controller Internal Clock Domains
2.2 Memory Map
2.3 Signal Descriptions
DDR_D[31:0]
DDR2
memory
controller
DDR_CLK
DDR_CLK
DDR_CS
DDR_CKE
DDR_RAS
DDR_WE
DDR_BA[2:0]
DDR_CAS
DDR_DQGATE[3:0]
DDR_DQS[3:0]
DDR_ZN
DDR_ZP
50 Ω
50 Ω
DDR_A[14:0]
DDR_DQS[3:0]
DDR_DQM[3:0]
DDR_ODT0
DDR_VREF
NC
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There are two clock domains within the DDR2 memory controller. The two clock domains are driven byVCLK and a divided-down by 2 version of PLL2_SYSCLK1 called MCLK. The command FIFO, write FIFO,and read FIFO described in Section 2.7 are all on the VCLK domain. From this, you can see that VCLKdrives the interface to the peripheral bus.
The MCLK domain consists of the DDR2 memory controller state machine and memory-mapped registers.This clock domain is clocked at the rate of the external DDR2 memory, PLL2_SYSCLK1/2.
To conserve power within the DDR2 memory controller, VCLK, MCLK, and PLL2_SYSCLK1 may bestopped. See Section 2.15 for proper clock stop procedures.
See the device-specific data manual for information describing the device memory-map.
The DDR2 memory controller signals are shown in Figure 3 and described in Table 2 . The followingfeatures are included:
•The maximum data bus is 32-bits wide.•The address bus is 15-bits wide with an additional 3 bank address pins.•Two differential output clocks driven by internal clock sources.•Command signals: Row and column address strobe, write enable strobe, data strobe, and data mask.•One chip select signal and one clock enable signal.
Figure 3. DDR2 Memory Controller Signals
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2.4 Protocol Description(s)
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Table 2. DDR2 Memory Controller Signal Descriptions
Pin Type Description
DDR_CLK O/Z Clock: Clock output.DDR_CLK O/Z Clock: Differential clock output.DDR_CKE O/Z Clock enable: Active high.DDR_CS O/Z Chip select: Active low.DDR_WE O/Z Write enable: Active low, command output.DDR_RAS O/Z Row access strobe: Active low, command output.DDR_CAS O/Z Column access strobe: Active low, command output.DDR_DQM[3:0] O/Z Data mask: Output mask signal for write data.DDR_DQS[3:0] I/O/Z Data strobe: Data strobe, bi-directional signals. Output with write data, input withread data.DDR_DQS[3:0] I/O/Z Data strobe: Differential data strobe, bi-directional signals. Output with write data,input with read data.DDR_ODT0 O/Z ODT control: Not used (not connected).DDR_BA[2:0] O/Z Bank address: Output, defining which bank a given command is applied.DDR_A[14:0] O/Z Address: Address bus.DDR_D[31:0] I/O/Z Data: Bi-directional data bus. Input for read data, output for write data.DDR_DQGATE[3:0] I/O/Z Data strobe gate: Used as a timing reference during memory reads. TheDDR_DQGATE0 and DDR_DQGATE2 pins should be routed out and connected tothe DDR_DQGATE1 and DDR_DQGATE3 pins, respectively. For more routingrequirements on these pins, see the device-specific data manual.DDR_VREF I Reference voltage: Reference voltage.DDR_ZN, O Output impedance control: Required to set the DDR2 output impedance.DDR_ZP
The DDR2 memory controller supports the DDR2 SDRAM commands listed in Table 3 .Table 4 shows thesignal truth table for the DDR2 SDRAM commands.
Table 3. DDR2 SDRAM Commands
Command Function
ACTV Activates the selected bank and row.DCAB Precharge all command. Deactivates (precharges) all banks.DEAC Precharge single command. Deactivates (precharges) a single bank.DESEL Device DeselectEMRS Extended Mode Register set. Allows altering the contents of the mode register.MRS Mode register set. Allows altering the contents of the mode register.NOP No operationPower Down Power-down modeREAD Inputs the starting column address and begins the read operation.READ with Inputs the starting column address and begins the read operation. The read operation is followed by aautoprecharge precharge.REFR Auto-refresh cycleSLFREFR Self-refresh modeWRT Inputs the starting column address and begins the write operation.WRT with Inputs the starting column address and begins the write operation. The write operation is followed by aautoprecharge precharge.
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Table 4. Truth Table for DDR2 SDRAM CommandsDDR2
SDRAM: CKE CS RAS CAS WE BA[2:0] A[14:11, 9:0] A10
DDR2
memory
controller: DDR_CKE DDR_CS DDR_RAS DDR_CAS DDR_WE DDR_BA[2:0] DDR_A[14:11, 9:0] DDR_A[10]
Previous
Cycles Current Cycle
ACTV H H L L H H Bank Row Address
DCAB H H L L H L X X L
DEAC H H L L H L Bank X L
MRS H H L L L L BA OP Code
EMRS H H L L L L BA OP Code
READ H H L H L H BA Column Address L
READ with H H L H L H BA Column Address Hprecharge
WRT H H L H L L BA Column Address L
WRT with H H L H L L BA Column Address Lprecharge
REFR H H L L L H X X X
SLFREFR H L L L L H X X Xentry
SLFREFR L H H X X X X X Xexit
L H H H X X X
NOP H X L H H H X X X
DESEL H X H X X X X X X
Power Down H L H X X X X X Xentry
L H H H X X X
Power Down L H H X X X X X Xexit
L H H H X X X
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2.4.1 Refresh Mode
DDR_CLK
DDR_CKE
DDR_CS
DDR_RAS
DDR_CAS
DDR_WE
DDR_A[14:0]
DDR_BA[2:0]
DDR_DQM[3:0]
RFR
DDR_CLK
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The DDR2 memory controller issues refresh commands to the DDR2 SDRAM memory (Figure 4 ). REFRis automatically preceded by a DCAB command, ensuring the deactivation of all CE spaces and banksselected. Following the DCAB command, the DDR2 memory controller begins performing refreshes at arate defined by the refresh rate (RR) bit in the SDRAM refresh control register (SDRCR). Page informationis always invalid before and after a REFR command; thus, a refresh cycle always forces a page miss. Thistype of refresh cycle is often called autorefresh. Autorefresh commands may not be disabled within theDDR2 memory controller. See Section 2.8 for more details on REFR command scheduling.
Figure 4. Refresh Command
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2.4.2 Deactivation (DCAB and DEAC)
DDR_CLK
DDR_CKE
DDR_CS
DDR_RAS
DDR_WE
DDR_A[14:11, 9:0]
DDR_BA[2:0]
DDR_DQM[3:0]
DCAB
DDR_A[10]
DDR_CAS
DDR_CLK
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The precharge all banks command (DCAB) is performed after a reset to the DDR2 memory controller orfollowing the initialization sequence. DDR2 SDRAMs also require this cycle prior to a refresh (REFR) andmode set register commands (MRS and EMRS). During a DCAB command, DDR_A[10] is driven high toensure the deactivation of all banks. Figure 5 shows the timing diagram for a DCAB command.
Figure 5. DCAB Command
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DDR_CLK
DDR_CKE
DDR_CS
DDR_RAS
DDR_WE
DDR_A[14:11, 9:0]
DDR_BA[2:0]
DDR_DQM[3:0]
DEAC
DDR_A[10]
DDR_CAS
DDR_CLK
Bank
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The DEAC command closes a single bank of memory specified by the bank select signals. Figure 6 showsthe timings diagram for a DEAC command.
Figure 6. DEAC Command
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2.4.3 Activation (ACTV)
DDR_CLK
DDR_CKE
DDR_CS
DDR_RAS
DDR_WE
DDR_BA[2:0]
DDR_DQM[3:0]
ACTV
DDR_A[14:0]
DDR_CAS
BANK
ROW
DDR_CLK
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The DDR2 memory controller automatically issues the activate (ACTV) command before a read or write toa closed row of memory. The ACTV command opens a row of memory, allowing future accesses (reads orwrites) with minimum latency. The value of DDR_BA[2:0] selects the bank and the value of A[12:0] selectsthe row. When the DDR2 memory controller issues an ACTV command, a delay of t
RCD
is incurred beforea read or write command is issued. Figure 7 shows an example of an ACTV command. Reads or writes tothe currently active row and bank of memory can achieve much higher throughput than reads or writes torandom areas because every time a new row is accessed, the ACTV command must be issued and adelay of t
RCD
incurred.
Figure 7. ACTV Command
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2.4.4 READ Command
DDR_CLK
DDR_CKE
DDR_CS
DDR_WE
DDR_CAS
DDR_DQM[3:0]
DDR_D[31:0]
DDR_A[14:0]
DDR_RAS
DDR_DQS[3:0]
COL
BANK
DDR_A[10]
DDR_BA[2:0]
CAS Latency
D0 D1 D2 D3 D4 D5 D6 D7
DDR_CLK
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Figure 8 shows the DDR2 memory controller performing a read burst from DDR2 SDRAM. The READcommand initiates a burst read operation to an active row. During the READ command, DDR_CAS driveslow, DDR_WE and DDR_RAS remain high, the column address is driven on DDR_A[12:0], and the bankaddress is driven on DDR_BA[2:0].
The DDR2 memory controller uses a burst length of 8, and has a programmable CAS latency of 2, 3, 4, or5. The CAS latency is three cycles in Figure 8 . Read latency is equal to CAS latency plus additive latency.The DDR2 memory controller always configures the memory to have an additive latency of 0, so readlatency equals CAS latency. Since the default burst size is 8, the DDR2 memory controller returns 8pieces of data for every read command. If additional accesses are not pending to the DDR2 memorycontroller, the read burst completes and the unneeded data is disregarded. If additional accesses arepending, depending on the scheduling result, the DDR2 memory controller can terminate the read burstand start a new read burst. Furthermore, the DDR2 memory controller does not issue a DAB/DEACcommand until page information becomes invalid.
Figure 8. DDR2 READ Command
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2.4.5 Write (WRT) Command
DDR_CLK
DDR_CKE
DDR_CS
DDR_WE
DDR_CAS
DDR_DQM[3:0]
DDR_D[31:0]
DDR_A[14:0]
DDR_RAS
DDR_DQS[3:0]
COL
BANK
DDR_A[10]
DDR_BA[2:0]
DQM6
Sample
D0 D1 D2 D3 D4 D5 D6 D7
DQM0 DQM1 DQM2 DQM3 DQM4 DQM5 DQM7
Write Latency
DDR_CLK
Architecture www.ti.com
Prior to a WRT command, the desired bank and row are activated by the ACTV command. Following theWRT command, a write latency is incurred. Write latency is equal to CAS latency minus 1. All writes havea burst length of 8. The use of the DDR_DQM outputs allows byte and halfword writes to be executed.Figure 9 shows the timing for a write on the DDR2 memory controller.
If the transfer request is for less than 8 words, depending on the scheduling result and the pendingcommands, the DDR2 memory controller can:•Mask out the additional data using DDR_DQM outputs•Terminate the write burst and start a new write burst
The DDR2 memory controller does not perform the DEAC command until page information becomesinvalid.
Figure 9. DDR2 WRT Command
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2.4.6 Mode Register Set (MRS and EMRS)
DDR_CLK
DDR_CKE
DDR_CS
DDR_RAS
DDR_WE
DDR_BA[2:0]
COL
MRS/EMRS
DDR_A[14:0]
DDR_CAS
BANK
DDR_CLK
2.5 Memory Width and Byte Alignment
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DDR2 SDRAM contains mode and extended mode registers that configure the DDR2 memory foroperation. These registers control burst type, burst length, CAS latency, DLL enable/disable (on DDR2device), single-ended strobe, etc.
The DDR2 memory controller programs the mode and extended mode registers of the DDR2 memory byissuing MRS and EMRS commands. When the MRS or EMRS command is executed, the value onDDR_BA[1:0] selects the mode register to be written and the data on DDR_A[12:0] is loaded into theregister. Figure 10 shows the timing for an MRS and EMRS command.
The DDR2 memory controller only issues MRS and EMRS commands during the DDR2 memory controllerinitialization sequence. See Section 2.12 for more information.
Figure 10. DDR2 MRS and EMRS Command
The DDR2 memory controller supports memory widths of 16 bits and 32 bits. Table 5 summarizes theaddressable memory ranges on the DDR2 memory controller. Only little-endian format is supported.
Figure 11 shows the byte lanes used on the DDR2 memory controller. The external memory is alwaysright aligned on the data bus.
Table 5. Addressable Memory Ranges
Memory Width Maximum addressable bytes per CS space Description
×16 256 Mbytes Halfword address×32 256 Mbytes Word address
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DDR2 memory controller data bus
DDR_D[31:24] DDR_D[23:16] DDR_D[15:8] DDR_D[7:0]
32-bit memory device
16-bit memory device
2.6 Address Mapping
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Figure 11. Byte Alignment
The DDR2 memory controller views external DDR2 SDRAM as one continuous block of memory. Thisstatement is true regardless of the number of external physical devices mapped to a given chip selectspace. The DDR2 memory controller receives DDR2 memory access requests along with a 32-bit logicaladdress from the rest of the system. In turn, the DDR2 memory controller uses the logical address togenerate a row/page, column, and bank address for the DDR2 SDRAM. The number of column and bankaddress bits used is determined by the IBANK and PAGESIZE fields in the SDRAM bank configurationregister (SDBCR) (see Table 6 ).
Table 6. Bank Configuration Register Fields for Address Mapping
Bit Field Bit Value Bit Description
IBANK Defines the number of internal banks on the external DDR2 memory.0 1 bank1h 2 banks2h 4 banks3h 8 banksPAGESIZE Defines the page size of each page of the external DDR2 memory.0 256 words (requires 8 column address bits)1h 512 words (requires 9 column address bits)2h 1024 words (requires 10 column address bits)3h 2048 words (requires 11 column address bits)
As stated in Table 6 , the IBANK and PAGESIZE fields of SDBCR control the mapping of the logical,source address of the DDR2 memory controller to the DDR2 SDRAM row, column, and bank address bits.The DDR2 memory controller logical address always contains 13 row address bits, whereas the number ofcolumn and bank bits are determined by the IBANK and PAGESIZE fields. Table 7 and Table 8 show howthe logical address bits map to the DDR2 SDRAM row, column, and bank bits for combinations of IBANKand PAGESIZE values. The same DDR2 memory controller pins provide the row and column address tothe DDR2 SDRAM, thus the DDR2 memory controller appropriately shifts the address during row andcolumn address selection.
Figure 12 shows how this address-mapping scheme organizes the DDR2 SDRAM rows, columns, andbanks into the device memory map. Note that during a linear access, the DDR2 memory controllerincrements the column address as the logical address increments. When the DDR2 memory controllerreaches a page/row boundary, it moves onto the same page/row in the next bank. This movementcontinues until the same page has been accessed in all banks. To the DDR2 SDRAM, this process looksas shown in Figure 13 .
20 DDR2 Memory Controller SPRUEQ4C – February 2009Submit Documentation Feedback