Texas Instruments TMS320DM357 User manual

TMS320DM357 DMSoC Universal Serial Bus(USB) Controller
User's Guide
Literature Number: SPRUGH3November 2008

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Contents
Preface ....................................................................................................................................... 111 Introduction ....................................................................................................................... 141.1 Purpose of the Peripheral .............................................................................................. 141.2 Features .................................................................................................................. 141.3 Features Not Supported ................................................................................................ 141.4 Functional Block Diagram .............................................................................................. 151.5 Supported Use Case Examples ....................................................................................... 161.6 Industry Standard(s) Compliance Statement ........................................................................ 222 Peripheral Architecture ....................................................................................................... 232.1 Clock Control ............................................................................................................. 232.2 Signal Descriptions ...................................................................................................... 232.3 Indexed and Non-Indexed Registers .................................................................................. 232.4 USB PHY Initialization .................................................................................................. 242.5 Dynamic FIFO Sizing ................................................................................................... 243 USB Controller Host and Peripheral Modes Operation ............................................................ 243.1 USB Controller Peripheral Mode Operation .......................................................................... 263.2 USB Controller Host Mode Operation ................................................................................ 443.3 DMA Operation .......................................................................................................... 573.4 Interrupt Handling ........................................................................................................ 683.5 Test Modes ............................................................................................................... 703.6 Reset Considerations ................................................................................................... 743.7 Interrupt Support ......................................................................................................... 743.8 EDMA Event Support ................................................................................................... 743.9 Power Management ..................................................................................................... 744 Registers ........................................................................................................................... 754.1 Control Register (CTRLR) .............................................................................................. 824.2 Status Register (STATR) ............................................................................................... 834.3 RNDIS Register (RNDISR) ............................................................................................. 834.4 Auto Request Register (AUTOREQ) .................................................................................. 844.5 USB Interrupt Source Register (INTSRCR) .......................................................................... 854.6 USB Interrupt Source Set Register (INTSETR) ..................................................................... 864.7 USB Interrupt Source Clear Register (INTCLRR) ................................................................... 874.8 USB Interrupt Mask Register (INTMSKR) ............................................................................ 884.9 USB Interrupt Mask Set Register (INTMSKSETR) .................................................................. 894.10 USB Interrupt Mask Clear Register (INTMSKCLRR) ............................................................... 904.11 USB Interrupt Source Masked Register (INTMASKEDR) .......................................................... 914.12 USB End of Interrupt Register (EOIR) ................................................................................ 924.13 USB Interrupt Vector Register (INTVECTR) ......................................................................... 924.14 Transmit CPPI Control Register (TCPPICR) ......................................................................... 934.15 Transmit CPPI Teardown Register (TCPPITDR) .................................................................... 934.16 CPPI DMA End of Interrupt Register (CPPIEOIR) .................................................................. 94
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4.17 Transmit CPPI Masked Status Register (TCPPIMSKSR) .......................................................... 954.18 Transmit CPPI Raw Status Register (TCPPIRAWSR) ............................................................. 954.19 Transmit CPPI Interrupt Enable Set Register (TCPPIIENSETR) ................................................. 964.20 Transmit CPPI Interrupt Enable Clear Register (TCPPIIENCLRR) ............................................... 964.21 Receive CPPI Control Register (RCPPICR) ......................................................................... 974.22 Receive CPPI Masked Status Register (RCPPIMSKSR) .......................................................... 974.23 Receive CPPI Raw Status Register (RCPPIRAWSR) .............................................................. 984.24 Receive CPPI Interrupt Enable Set Register (RCPPIENSETR) ................................................... 984.25 Receive CPPI Interrupt Enable Clear Register (RCPPIIENCLRR) ............................................... 994.26 Receive Buffer Count 0 Register (RBUFCNT0) ..................................................................... 994.27 Receive Buffer Count 1 Register (RBUFCNT1) .................................................................... 1004.28 Receive Buffer Count 2 Register (RBUFCNT2) .................................................................... 1004.29 Receive Buffer Count 3 Register (RBUFCNT3) .................................................................... 1014.30 Transmit CPPI DMA State Word 0 (TCPPIDMASTATEW0) ..................................................... 1014.31 Transmit CPPI DMA State Word 1 (TCPPIDMASTATEW1) ..................................................... 1024.32 Transmit CPPI DMA State Word 2 (TCPPIDMASTATEW2) ..................................................... 1024.33 Transmit CPPI DMA State Word 3 (TCPPIDMASTATEW3) ..................................................... 1034.34 Transmit CPPI DMA State Word 4 (TCPPIDMASTATEW4) ..................................................... 1034.35 Transmit CPPI DMA State Word 5 (TCPPIDMASTATEW5) ..................................................... 1044.36 Transmit CPPI Completion Pointer (TCPPICOMPPTR) .......................................................... 1044.37 Receive CPPI DMA State Word 0 (RCPPIDMASTATEW0) ...................................................... 1054.38 Receive CPPI DMA State Word 1 (RCPPIDMASTATEW1) ...................................................... 1054.39 Receive CPPI DMA State Word 2 (RCPPIDMASTATEW2) ...................................................... 1074.40 Receive CPPI DMA State Word 3 (RCPPIDMASTATEW3) ...................................................... 1074.41 Receive CPPI DMA State Word 4 (RCPPIDMASTATEW4) ...................................................... 1094.42 Receive CPPI DMA State Word 5 (RCPPIDMASTATEW5) ...................................................... 1094.43 Receive CPPI DMA State Word 6 (RCPPIDMASTATEW6) ...................................................... 1104.44 Receive CPPI Completion Pointer (RCPPICOMPPTR) ........................................................... 1104.45 Function Address Register (FADDR) ................................................................................ 1114.46 Power Management Register (POWER) ............................................................................ 1114.47 Interrupt Register for Endpoint 0 Plus Transmit Endpoints 1 to 4 (INTRTX) ................................... 1124.48 Interrupt Register for Receive Endpoints 1 to 4 (INTRRX) ....................................................... 1124.49 Interrupt Enable Register for INTRTX (INTRTXE) ................................................................. 1134.50 Interrupt Enable Register for INTRRX (INTRRXE) ................................................................ 1134.51 Interrupt Register for Common USB Interrupts (INTRUSB) ...................................................... 1154.52 Interrupt Enable Register for INTRUSB (INTRUSBE) ............................................................. 1164.53 Frame Number Register (FRAME) .................................................................................. 1174.54 Index Register for Selecting the Endpoint Status and Control Registers (INDEX) ............................ 1174.55 Register to Enable the USB 2.0 Test Modes (TESTMODE) ..................................................... 1184.56 Maximum Packet Size for Peripheral/Host Transmit Endpoint (TXMAXP) ..................................... 1194.57 Control Status Register for Endpoint 0 in Peripheral Mode (PERI_CSR0) ..................................... 1204.58 Control Status Register for Endpoint 0 in Host Mode (HOST_CSR0) ......................................... 1214.59 Control Status Register for Peripheral Transmit Endpoint (PERI_TXCSR) .................................... 1224.60 Control Status Register for Host Transmit Endpoint (HOST_TXCSR) ......................................... 1234.61 Maximum Packet Size for Peripheral Host Receive Endpoint (RXMAXP) ..................................... 1244.62 Control Status Register for Peripheral Receive Endpoint (PERI_RXCSR) ..................................... 1254.63 Control Status Register for Host Receive Endpoint (HOST_RXCSR) ......................................... 1264.64 Count 0 Register (COUNT0).......................................................................................... 1284.65 Receive Count Register (RXCOUNT) ............................................................................... 128
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4.66 Type Register (Host mode only) (HOST_TYPE0) ................................................................ 1294.67 Transmit Type Register (Host mode only) (HOST_TXTYPE) ................................................... 1294.68 NAKLimit0 Register (Host mode only) (HOST_NAKLIMIT0) .................................................... 1304.69 Transmit Interval Register (Host mode only) (HOST_TXINTERVAL) .......................................... 1304.70 Receive Type Register (Host mode only) (HOST_RXTYPE) ................................................... 1314.71 Receive Interval Register (Host mode only) (HOST_RXINTERVAL) .......................................... 1314.72 Configuration Data Register (CONFIGDATA) ...................................................................... 1324.73 Transmit and Receive FIFO Register for Endpoint 0 (FIFO0) ................................................... 1344.74 Transmit and Receive FIFO Register for Endpoint 1 (FIFO1) ................................................... 1354.75 Transmit and Receive FIFO Register for Endpoint 2 (FIFO2) ................................................... 1354.76 Transmit and Receive FIFO Register for Endpoint 3 (FIFO3) ................................................... 1364.77 Transmit and Receive FIFO Register for Endpoint 4 (FIFO4) ................................................... 1364.78 OTG Device Control Register (DEVCTL) ........................................................................... 1374.79 Transmit Endpoint FIFO Size (TXFIFOSZ) ......................................................................... 1384.80 Receive Endpoint FIFO Size (RXFIFOSZ) ......................................................................... 1384.81 Transmit Endpoint FIFO Address (TXFIFOADDR) ................................................................ 1394.82 Receive Endpoint FIFO Address (RXFIFOADDR) ................................................................. 1394.83 Transmit Function Address (TXFUNCADDR) ...................................................................... 1404.84 Transmit Hub Address (TXHUBADDR) ............................................................................. 1404.85 Transmit Hub Port (TXHUBPORT) .................................................................................. 1404.86 Receive Function Address (RXFUNCADDR) ...................................................................... 1414.87 Receive Hub Address (RXHUBADDR) .............................................................................. 1414.88 Receive Hub Port (RXHUBPORT) ................................................................................... 141Appendix A Revision History ..................................................................................................... 143
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List of Figures
1 Functional Block Diagram ................................................................................................. 152 Interrupt Service Routine Flow Chart .................................................................................... 253 CPU Actions at Transfer Phases ......................................................................................... 294 Sequence of Transfer ...................................................................................................... 305 Service Endpoint 0 Flow Chart ........................................................................................... 326 IDLE Mode Flow Chart .................................................................................................... 337 TX Mode Flow Chart ....................................................................................................... 348 RX Mode Flow Chart ....................................................................................................... 359 Setup Phase of a Control Transaction Flow Chart ..................................................................... 4510 IN Data Phase Flow Chart ................................................................................................ 4711 OUT Data Phase Flow Chart ............................................................................................. 4812 Completion of SETUP or OUT Data Phase Flow Chart ............................................................... 4913 Completion of IN Data Phase Flow Chart ............................................................................... 5114 Tx Queue Flow Chart ...................................................................................................... 6015 Rx Queue Flow Chart ...................................................................................................... 6516 Control Register (CTRLR) ................................................................................................. 8217 Status Register (STATR) .................................................................................................. 8318 RNDIS Register (RNDISR) ................................................................................................ 8319 Auto Request Register (AUTOREQ) ..................................................................................... 8420 USB Interrupt Source Register (INTSRCR) ............................................................................. 8521 USB Interrupt Source Set Register (INTSETR) ........................................................................ 8622 USB Interrupt Source Clear Register (INTCLRR) ...................................................................... 8723 USB Interrupt Mask Register (INTMSKR)............................................................................... 8824 USB Interrupt Mask Set Register (INTMSKSETR) .................................................................... 8925 USB Interrupt Mask Clear Register (INTMSKCLRR) .................................................................. 9026 USB Interrupt Source Masked Register (INTMASKEDR) ............................................................. 9127 USB End of Interrupt Register (EOIR) ................................................................................... 9228 USB Interrupt Vector Register (INTVECTR) ............................................................................ 9229 Transmit CPPI Control Register (TCPPICR) ........................................................................... 9330 Transmit CPPI Teardown Register (TCPPITDR) ...................................................................... 9331 CPPI DMA End of Interrupt Register (CPPIEOIR) ..................................................................... 9432 Transmit CPPI Masked Status Register (TCPPIMSKSR) ............................................................ 9533 Transmit CPPI Raw Status Register (TCPPIRAWSR) ................................................................ 9534 Transmit CPPI Interrupt Enable Set Register (TCPPIIENSETR) .................................................... 9635 Transmit CPPI Interrupt Enable Clear Register (TCPPIIENCLRR) .................................................. 9636 Receive CPPI Control Register (RCPPICR) ............................................................................ 9737 Receive CPPI Masked Status Register (RCPPIMSKSR) ............................................................. 9738 Receive CPPI Raw Status Register (RCPPIRAWSR)................................................................. 9839 Receive CPPI Interrupt Enable Set Register (RCPPIENSETR) ..................................................... 9840 Receive CPPI Interrupt Enable Clear Register (RCPPIIENCLRR) .................................................. 9941 Receive Buffer Count 0 Register (RBUFCNT0) ........................................................................ 9942 Receive Buffer Count 1 Register (RBUFCNT1) ...................................................................... 10043 Receive Buffer Count 2 Register (RBUFCNT2) ...................................................................... 10044 Receive Buffer Count 3 Register (RBUFCNT3) ...................................................................... 10145 Transmit CPPI DMA State Word 0 (TCPPIDMASTATEW0) ........................................................ 10146 Transmit CPPI DMA State Word 1 (TCPPIDMASTATEW1) ........................................................ 10247 Transmit CPPI DMA State Word 2 (TCPPIDMASTATEW2) ........................................................ 10248 Transmit CPPI DMA State Word 3 (TCPPIDMASTATEW3) ........................................................ 10349 Transmit CPPI DMA State Word 4 (TCPPIDMASTATEW4) ........................................................ 10350 Transmit CPPI DMA State Word 5 (TCPPIDMASTATEW5) ........................................................ 10451 Transmit CPPI Completion Pointer (TCPPICOMPPTR) ............................................................. 10452 Receive CPPI DMA State Word 0 (RCPPIDMASTATEW0) ........................................................ 105
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53 Receive CPPI DMA State Word 1 (RCPPIDMASTATEW1) ........................................................ 10654 Receive CPPI DMA State Word 2 (RCPPIDMASTATEW2) ........................................................ 10755 Receive CPPI DMA State Word 3 (RCPPIDMASTATEW3) ........................................................ 10756 Receive CPPI DMA State Word 4 (RCPPIDMASTATEW4) ........................................................ 10957 Receive CPPI DMA State Word 5 (RCPPIDMASTATEW5) ........................................................ 10958 Receive CPPI DMA State Word 6 (RCPPIDMASTATEW6) ........................................................ 11059 Receive CPPI Completion Pointer (RCPPICOMPPTR) ............................................................. 11060 Function Address Register (FADDR) .................................................................................. 11161 Power Management Register (POWER) .............................................................................. 11162 Interrupt Register for Endpoint 0 Plus Tx Endpoints 1 to 4 (INTRTX) ............................................. 11263 Interrupt Register for Receive Endpoints 1 to 4 (INTRRX) .......................................................... 11364 Interrupt Enable Register for INTRTX (INTRTXE).................................................................... 11365 Interrupt Enable Register for INTRRX (INTRRXE) ................................................................... 11466 Interrupt Register for Common USB Interrupts (INTRUSB) ......................................................... 11567 Interrupt Enable Register for INTRUSB (INTRUSBE) ............................................................... 11668 Frame Number Register (FRAME) ..................................................................................... 11769 Index Register for Selecting the Endpoint Status and Control Registers (INDEX) ............................... 11770 Register to Enable the USB 2.0 Test Modes (TESTMODE) ........................................................ 11871 Maximum Packet Size for Peripheral/Host Transmit Endpoint (TXMAXP) ........................................ 11972 Control Status Register for Endpoint 0 in Peripheral Mode (PERI_CSR0) ....................................... 12073 Control Status Register for Endpoint 0 in Host Mode (HOST_CSR0) ............................................. 12174 Control Status Register for Peripheral Transmit Endpoint (PERI_TXCSR) ....................................... 12275 Control Status Register for Host Transmit Endpoint (HOST_TXCSR) ............................................ 12376 Maximum Packet Size for Peripheral Host Receive Endpoint (RXMAXP) ........................................ 12477 Control Status Register for Peripheral Receive Endpoint (PERI_RXCSR) ....................................... 12578 Control Status Register for Host Receive Endpoint (HOST_RXCSR) ............................................. 12679 Count 0 Register (COUNT0) ............................................................................................ 12880 Receive Count Register (RXCOUNT) .................................................................................. 12881 Type Register (Host mode only) (HOST_TYPE0) .................................................................... 12982 Transmit Type Register (Host mode only) (HOST_TXTYPE) ....................................................... 12983 NAKLimit0 Register (Host mode only) (HOST_NAKLIMIT0) ........................................................ 13084 Transmit Interval Register (Host mode only) (HOST_TXINTERVAL) .............................................. 13085 Receive Type Register (Host mode only) (HOST_RXTYPE) ....................................................... 13186 Receive Interval Register (Host mode only) (HOST_RXINTERVAL) .............................................. 13187 Configuration Data Register (CONFIGDATA) ......................................................................... 13288 Transmit and Receive FIFO Register for Endpoint 0 (FIFO0) ...................................................... 13489 Transmit and Receive FIFO Register for Endpoint 1 (FIFO1) ...................................................... 13590 Transmit and Receive FIFO Register for Endpoint 2 (FIFO2) ...................................................... 13591 Transmit and Receive FIFO Register for Endpoint 3 (FIFO3) ...................................................... 13692 Transmit and Receive FIFO Register for Endpoint 4 (FIFO4) ...................................................... 13693 OTG Device Control Register (DEVCTL) .............................................................................. 13794 Transmit Endpoint FIFO Size (TXFIFOSZ) ............................................................................ 13895 Receive Endpoint FIFO Size (RXFIFOSZ) ............................................................................ 13896 Transmit Endpoint FIFO Address (TXFIFOADDR) ................................................................... 13997 Receive Endpoint FIFO Address (RXFIFOADDR) ................................................................... 13998 Transmit Function Address (TXFUNCADDR) ......................................................................... 14099 Transmit Hub Address (TXHUBADDR) ................................................................................ 140100 Transmit Hub Port (TXHUBPORT) ..................................................................................... 140101 Receive Function Address (RXFUNCADDR) ......................................................................... 141102 Receive Hub Address (RXHUBADDR) ................................................................................ 141103 Receive Hub Port (RXHUBPORT) ..................................................................................... 141
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List of Tables
1 USB Pins .................................................................................................................... 232 PERI_TXCSR Register Bit Configuration for Bulk IN Transactions ................................................. 373 PERI_RXCSR Register Bit Configuration for Bulk OUT Transactions .............................................. 394 PERI_TXCSR Register Bit Configuration for Isochronous IN Transactions ........................................ 415 PERI_RXCSR Register Bit Configuration for Isochronous OUT Transactions ..................................... 436 Transmit Buffer Descriptor Word 0 ....................................................................................... 587 Transmit Buffer Descriptor Word 1 ....................................................................................... 588 Transmit Buffer Descriptor Word 2 ....................................................................................... 589 Transmit Buffer Descriptor Word 3 ....................................................................................... 5810 Receive Buffer Descriptor Word 0 ....................................................................................... 6311 Receive Buffer Descriptor Word 1 ....................................................................................... 6312 Receive Buffer Descriptor Word 2 ....................................................................................... 6313 Receive Buffer Descriptor Word 3 ....................................................................................... 6414 Interrupts Generated by the USB Controller ............................................................................ 6815 USB Interrupt Conditions .................................................................................................. 6816 Universal Serial Bus (USB) Registers ................................................................................... 7517 Control Register (CTRLR) Field Descriptions .......................................................................... 8218 Status Register (STATR) Field Descriptions............................................................................ 8319 RNDIS Register (RNDISR) Field Descriptions ......................................................................... 8320 Auto Request Register (AUTOREQ) Field Descriptions .............................................................. 8421 USB Interrupt Source Register (INTSRCR) Field Descriptions ...................................................... 8522 USB Interrupt Source Set Register (INTSETR) Field Descriptions .................................................. 8623 USB Interrupt Source Clear Register (INTCLRR) Field Descriptions ............................................... 8724 USB Interrupt Mask Register (INTMSKR) Field Descriptions ........................................................ 8825 USB Interrupt Mask Set Register (INTMSKSETR) Field Descriptions .............................................. 8926 USB Interrupt Mask Clear Register (INTMSKCLRR) Field Descriptions ............................................ 9027 USB Interrupt Source Masked Register (INTMASKEDR) Field Descriptions ...................................... 9128 USB End of Interrupt Register (EOIR) Field Descriptions ............................................................ 9229 USB Interrupt Vector Register (INTVECTR) Field Descriptions...................................................... 9230 Transmit CPPI Control Register (TCPPICR) Field Descriptions ..................................................... 9331 Transmit CPPI Teardown Register (TCPPITDR) Field Descriptions ................................................ 9332 CPPI DMA End of Interrupt Register (CPPIEOIR) Field Descriptions .............................................. 9433 Transmit CPPI Masked Status Register (TCPPIMSKSR) Field Descriptions ...................................... 9534 Transmit CPPI Raw Status Register (TCPPIRAWSR) Field Descriptions .......................................... 9535 Transmit CPPI Interrupt Enable Set Register (TCPPIIENSETR) Field Descriptions .............................. 9636 Transmit CPPI Interrupt Enable Clear Register (TCPPIIENCLRR) Field Descriptions ........................... 9637 Receive CPPI Control Register (RCPPICR) Field Descriptions...................................................... 9738 Receive CPPI Masked Status Register (RCPPIMSKSR) Field Descriptions ....................................... 9739 Receive CPPI Raw Status Register (RCPPIRAWSR) Field Descriptions .......................................... 9840 Receive CPPI Interrupt Enable Set Register (RCPPIENSETR) Field Descriptions ............................... 9841 Receive CPPI Interrupt Enable Clear Register (RCPPIIENCLRR) Field Descriptions ............................ 9942 Receive Buffer Count 0 Register (RBUFCNT0) Field Descriptions .................................................. 9943 Receive Buffer Count 1 Register (RBUFCNT1) Field Descriptions ................................................ 10044 Receive Buffer Count 2 Register (RBUFCNT2) Field Descriptions ................................................ 10045 Receive Buffer Count 3 Register (RBUFCNT3) Field Descriptions ................................................ 10146 Transmit CPPI DMA State Word 0 (TCPPIDMASTATEW0) Field Descriptions .................................. 10147 Transmit CPPI DMA State Word 1 (TCPPIDMASTATEW1) Field Descriptions .................................. 10248 Transmit CPPI DMA State Word 2 (TCPPIDMASTATEW2) Field Descriptions .................................. 10249 Transmit CPPI DMA State Word 3 (TCPPIDMASTATEW3) Field Descriptions .................................. 103
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50 Transmit CPPI DMA State Word 4 (TCPPIDMASTATEW4) Field Descriptions .................................. 10351 Transmit CPPI DMA State Word 5 (TCPPIDMASTATEW5) Field Descriptions .................................. 10452 Transmit CPPI Completion Pointer (TCPPICOMPPTR) Field Descriptions....................................... 10553 Receive CPPI DMA State Word 0 (RCPPIDMASTATEW0) Field Descriptions .................................. 10554 Receive CPPI DMA State Word 1 (RCPPIDMASTATEW1) Field Descriptions .................................. 10655 Receive CPPI DMA State Word 2 (RCPPIDMASTATEW2) Field Descriptions .................................. 10756 Receive CPPI DMA State Word 3 (RCPPIDMASTATEW3) Field Descriptions .................................. 10757 Receive CPPI DMA State Word 4 (RCPPIDMASTATEW4) Field Descriptions .................................. 10958 Receive CPPI DMA State Word 5 (RCPPIDMASTATEW5) Field Descriptions .................................. 10959 Receive CPPI DMA State Word 6 (RCPPIDMASTATEW6) Field Descriptions .................................. 11060 Receive CPPI Completion Pointer (RCPPICOMPPTR) Field Descriptions ....................................... 11061 Function Address Register (FADDR) Field Descriptions ............................................................ 11162 Power Management Register (POWER) Field Descriptions ........................................................ 11163 Interrupt Register for Endpoint 0 Plus Transmit Endpoints 1 to 4 (INTRTX) Field Descriptions ............... 11264 Interrupt Register for Receive Endpoints 1 to 4 (INTRRX) Field Descriptions ................................... 11365 Interrupt Enable Register for INTRTX (INTRTXE) Field Descriptions ............................................. 11366 Interrupt Enable Register for INTRRX (INTRRXE) Field Descriptions ............................................. 11467 Interrupt Register for Common USB Interrupts (INTRUSB) Field Descriptions .................................. 11568 Interrupt Enable Register for INTRUSB (INTRUSBE) Field Descriptions ......................................... 11669 Frame Number Register (FRAME) Field Descriptions ............................................................... 11770 Index Register for Selecting the Endpoint Status and Control Registers (INDEX) Field Descriptions ........ 11771 Register to Enable the USB 2.0 Test Modes (TESTMODE) Field Descriptions .................................. 11872 Maximum Packet Size for Peripheral/Host Transmit Endpoint (TXMAXP) Field Descriptions ................. 11973 Control Status Register for Endpoint 0 in Peripheral Mode (PERI_CSR0) Field Descriptions ................. 12074 Control Status Register for Endpoint 0 in Host Mode (HOST_CSR0) Field Descriptions ....................... 12175 Control Status Register for Peripheral Transmit Endpoint (PERI_TXCSR) Field Descriptions ................. 12276 Control Status Register for Host Transmit Endpoint (HOST_TXCSR) Field Descriptions ...................... 12377 Maximum Packet Size for Peripheral Host Receive Endpoint (RXMAXP) Field Descriptions .................. 12478 Control Status Register for Peripheral Receive Endpoint (PERI_RXCSR) Field Descriptions ................. 12579 Control Status Register for Host Receive Endpoint (HOST_RXCSR) Field Descriptions ....................... 12680 Count 0 Register (COUNT0) Field Descriptions ...................................................................... 12881 Receive Count Register (RXCOUNT) Field Descriptions ........................................................... 12882 Type Register (Host mode only) (HOST_TYPE0) Field Descriptions ............................................. 12983 Transmit Type Register (Host mode only) (HOST_TXTYPE) Field Descriptions ................................ 12984 NAKLimit0 Register (Host mode only) (HOST_NAKLIMIT0) Field Descriptions ................................. 13085 Transmit Interval Register (Host mode only) (HOST_TXINTERVAL) Field Descriptions ....................... 13086 Receive Type Register (Host mode only) (HOST_RXTYPE) Field Descriptions ................................. 13187 Receive Interval Register (Host mode only) (HOST_RXINTERVAL) Field Descriptions ........................ 13288 Configuration Data Register (CONFIGDATA) Field Descriptions .................................................. 13289 Transmit and Receive FIFO Register for Endpoint 0 (FIFO0) Field Descriptions ................................ 13490 Transmit and Receive FIFO Register for Endpoint 1 (FIFO1) Field Descriptions ................................ 13591 Transmit and Receive FIFO Register for Endpoint 2 (FIFO2) Field Descriptions ................................ 13592 Transmit and Receive FIFO Register for Endpoint 3 (FIFO3) Field Descriptions ................................ 13693 Transmit and Receive FIFO Register for Endpoint 4 (FIFO4) Field Descriptions ................................ 13694 OTG Device Control Register (DEVCTL) Field Descriptions ....................................................... 13795 Transmit Endpoint FIFO Size (TXFIFOSZ) Field Descriptions ..................................................... 13896 Receive Endpoint FIFO Size (RXFIFOSZ) Field Descriptions ...................................................... 13897 Transmit Endpoint FIFO Address (TXFIFOADDR) Field Descriptions............................................. 13998 Receive Endpoint FIFO Address (RXFIFOADDR) Field Descriptions ............................................. 13999 Transmit Function Address (TXFUNCADDR) Field Descriptions .................................................. 140100 Transmit Hub Address (TXHUBADDR) Field Descriptions .......................................................... 140
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101 Transmit Hub Port (TXHUBPORT) Field Descriptions ............................................................... 140102 Receive Function Address (RXFUNCADDR) Field Descriptions ................................................... 141103 Receive Hub Address (RXHUBADDR) Field Descriptions .......................................................... 141104 Receive Hub Port (RXHUBPORT) Field Descriptions ............................................................... 141A-1 Document Revision History .............................................................................................. 143
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PrefaceSPRUGH3 – November 2008
Read This First
About This Manual
This document describes the universal serial bus (USB) controller in the TMS320DM357 Digital MediaSystem-on-Chip (DMSoC).
Notational Conventions
This document uses the following conventions.•Hexadecimal numbers are shown with the suffix h. For example, the following number is 40hexadecimal (decimal 64): 40h.•Registers in this document are shown in figures and described in tables.– Each register figure shows a rectangle divided into fields that represent the fields of the register.Each field is labeled with its bit name, its beginning and ending bit numbers above, and itsread/write properties below. A legend explains the notation used for the properties.– Reserved bits in a register figure designate a bit that is used for future device expansion.
Related Documentation From Texas InstrumentsThe following documents describe the TMS320DM357 Digital Media System-on-Chip (DMSoC). Copies ofthese documents are available on the Internet at www.ti.com .Tip: Enter the literature number in thesearch box provided at www.ti.com.
SPRUG06 —TMS320DM357 DMSoC Video Processing Back End (VPBE) User's Guide. Describesthe video processing back end (VPBE) in the TMS320DM357 Digital Media System-on-Chip(DMSoC) video processing subsystem. Included in the VPBE is the video encoder, on-screendisplay, and digital LCD controller.
SPRUG25 —TMS320DM357 DMSoC ARM Subsystem Reference Guide. Describes the ARMsubsystem in the TMS320DM357 Digital Media System-on-Chip (DMSoC). The ARM subsystem isdesigned to give the ARM926EJ-S (ARM9) master control of the device. In general, the ARM isresponsible for configuration and control of the device; including the video processing subsystem,and a majority of the peripherals and external memories.
SPRUG26 —TMS320DM357 DMSoC Universal Asynchronous Receiver/Transmitter (UART) User'sGuide. This document describes the universal asynchronous receiver/transmitter (UART) peripheralin the TMS320DM357 Digital Media System-on-Chip (DMSoC). The UART peripheral performsserial-to-parallel conversion on data received from a peripheral device, and parallel-to-serialconversion on data received from the CPU.
SPRUG27 —TMS320DM357 DMSoC Inter-Integrated Circuit (I2C) Peripheral User's Guide.Describes the inter-integrated circuit (I2C) peripheral in the TMS320DM357 Digital MediaSystem-on-Chip (DMSoC). The I2C peripheral provides an interface between the DMSoC and otherdevices compliant with the I2C-bus specification and connected by way of an I2C-bus. Externalcomponents attached to this 2-wire serial bus can transmit and receive up to 8-bit wide data to andfrom the DMSoC through the I2C peripheral. This document assumes the reader is familiar with theI2C-bus specification.
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SPRUG28 —TMS320DM357 DMSoC 64-Bit Timer User's Guide. Describes the operation of thesoftware-programmable 64-bit timer in the TMS320DM357 Digital Media System-on-Chip (DMSoC).Timer 0 and Timer 1 are used as general-purpose (GP) timers and can be programmed in 64-bitmode, dual 32-bit unchained mode, or dual 32-bit chained mode; Timer 2 is used only as awatchdog timer. The GP timer modes can be used to generate periodic interrupts or enhanceddirect memory access (EDMA) synchronization events. The watchdog timer mode is used toprovide a recovery mechanism for the device in the event of a fault condition, such as a non-exitingcode loop.
SPRUG29 —TMS320DM357 DMSoC Serial Peripheral Interface (SPI) User's Guide. Describes theserial peripheral interface (SPI) in the TMS320DM357 Digital Media System-on-Chip (DMSoC). TheSPI is a high-speed synchronous serial input/output port that allows a serial bit stream ofprogrammed length (1 to 16 bits) to be shifted into and out of the device at a programmedbit-transfer rate. The SPI is normally used for communication between the DMSoC and externalperipherals. Typical applications include an interface to external I/O or peripheral expansion viadevices such as shift registers, display drivers, SPI EPROMs and analog-to-digital converters.
SPRUG30 —TMS320DM357 DMSoC Host Port Interface (HPI) Reference Guide. This documentdescribes the host port interface in the TMS320DM357 Digital Media System-on-Chip (DMSoC).The HPI provides a parallel port interface through which an external host processor can directlyaccess the TMS320DM357 DMSoC processor's resources (configuration and program/datamemories).
SPRUG31 —TMS320DM357 DMSoC General-Purpose Input/Output (GPIO) User's Guide. Describesthe general-purpose input/output (GPIO) peripheral in the TMS320DM357 Digital MediaSystem-on-Chip (DMSoC). The GPIO peripheral provides dedicated general-purpose pins that canbe configured as either inputs or outputs. When configured as an input, you can detect the state ofthe input by reading the state of an internal register. When configured as an output, you can writeto an internal register to control the state driven on the output pin.
SPRUG32 —TMS320DM357 DMSoC Multimedia Card (MMC)/Secure Digital (SD) Card ControllerUser's Guide. Describes the multimedia card (MMC)/secure digital (SD) card controller in theTMS320DM357 Digital Media System-on-Chip (DMSoC). The MMC/SD card is used in a number ofapplications to provide removable data storage. The MMC/SD controller provides an interface toexternal MMC and SD cards. The communication between the MMC/SD controller and MMC/SDcard(s) is performed by the MMC/SD protocol.
SPRUG33 —TMS320DM357 DMSoC Asynchronous External Memory Interface (EMIF) User'sGuide. Describes the asynchronous external memory interface (EMIF) in the TMS320DM357Digital Media System-on-Chip (DMSoC). The EMIF supports a glueless interface to a variety ofexternal devices.
SPRUG34 —TMS320DM357 DMSoC Enhanced Direct Memory Access (EDMA) Controller User'sGuide. Describes the operation of the enhanced direct memory access (EDMA3) controller in theTMS320DM357 Digital Media System-on-Chip (DMSoC). The EDMA3 controller’s primary purposeis to service user-programmed data transfers between two memory-mapped slave endpoints on theDMSoC.
SPRUG35 —TMS320DM357 DMSoC Audio Serial Port (ASP) User's Guide. Describes the operationof the audio serial port (ASP) audio interface in the TMS320DM357 Digital Media System-on-Chip(DMSoC). The primary audio modes that are supported by the ASP are the AC97 and IIS modes. Inaddition to the primary audio modes, the ASP supports general serial port receive and transmitoperation, but is not intended to be used as a high-speed interface.
SPRUG36 —TMS320DM357 DMSoC Ethernet Media Access Controller (EMAC)/Management DataInput/Output (MDIO) Module User's Guide. Discusses the ethernet media access controller(EMAC) and physical layer (PHY) device management data input/output (MDIO) module in theTMS320DM357 Digital Media System-on-Chip (DMSoC). The EMAC controls the flow of packetdata from the DMSoC to the PHY. The MDIO module controls PHY configuration and statusmonitoring.
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www.ti.com Notational Conventions
SPRUG37 —TMS320DM357 DMSoC Pulse-Width Modulator (PWM) Peripheral User's Guide.Describes the pulse-width modulator (PWM) peripheral in the TMS320DM357 Digital MediaSystem-on-Chip (DMSoC).
SPRUG38 —TMS320DM357 DMSoC DDR2 Memory Controller User's Guide. Describes the DDR2memory controller in the TMS320DM357 Digital Media System-on-Chip (DMSoC). The DDR2memory controller is used to interface with JESD79D-2A standard compliant DDR2 SDRAMdevices.
SPRUG39 —TMS320DM357 DMSoC Video Processing Front End (VPFE) User's Guide. Describesthe video processing front end (VPFE) in the TMS320DM357 Digital Media System-on-Chip(DMSoC) video processing subsystem. Included in the VPFE is the preview engine, CCD controller,resizer, histogram, and hardware 3A (H3A) statistic generator.
SPRUGH2 —TMS320DM357 DMSoC Peripherals Overview Reference Guide. This document providesan overview of the peripherals in the TMS320DM357 Digital Media System-on-Chip (DMSoC).
SPRUGH3 —TMS320DM357 DMSoC Universal Serial Bus Controller User's Guide. This documentdescribes the universal serial bus (USB) controller in the TMS320DM357 Digital MediaSystem-on-Chip (DMSoC). The USB controller supports data throughput rates up to 480 Mbps. Itprovides a mechanism for data transfer between USB devices and also supports host negotiation.
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1 Introduction
1.1 Purpose of the Peripheral
1.2 Features
1.3 Features Not Supported
User's GuideSPRUGH3 – November 2008
Universal Serial Bus (USB) Controller
This document describes the universal serial bus (USB) controller in the TMS320DM357 Digital MediaSystem-on-Chip (DMSoC). The controller supports high-speed USB peripheral mode and high-speedlimited host-mode operations. The USB controller can be operated by ARM through the memory-mappedregisters.
Note: The High-Speed USB OTG Controller is an instantiation of the MUSBMHDRC from MentorGraphics Corporation.
This document contains materials that are ©2003-2007 Mentor Graphics Corporation.
Mentor Graphics is a registered trademark of Mentor Graphics Corporation or its affiliatedcompanies in the United States and other countries.
The USB controller supports data throughput rates up to 480 Mbps. It provides a mechanism for datatransfer between USB devices and also supports host negotiation.
The USB has the following features:•Supports USB 2.0 peripheral at High Speed (480 Mbps) and Full Speed (12 Mbps)•Supports USB 2.0 host at High Speed (480 Mbps), Full Speed (12 Mbps), and Low Speed (1.5 Mbps)•Supports USB 2.0 OTG•Supports four simultaneous RX and TX endpoints, more can be supported by dynamically switching•Each endpoint can support all transfer types (control, bulk, interrupt, and isochronous)•Supports USB extensions for Session Request (SRP) and Host Negotiation (HNP)•Includes a 4K endpoint FIFO RAM, and supports programmable FIFO sizes•External 5V power supply for VBUS can be controlled through I2C•Includes a DMA controller that supports four TX and four RX DMA channels•Includes RNDIS mode of DMA for accelerating RNDIS type protocols using short packet terminationover USB
The following features are not supported:•High Bandwidth Isochronous Transfer.•High Bandwidth Interrupt Transfer.•Automatic Amalgamation of Bulk Packets (CPPI DMA will indirectly handle this feature and is notsupported at the core level).•Automatic Splitting of Bulk Packets (CPPI DMA will indirectly handle this feature and is not supportedat the core level).
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1.4 Functional Block Diagram
Internal
bus
CPPI
DMA
engine FIFO encode/ decode
Packet USB
PHY
2.0 USB
24 MHz
oscillator
crystal
Registers, interrupts, endpoint control,
and packet scheduling
www.ti.com Introduction
The USB functional block diagram is shown in Figure 1 .
Figure 1. Functional Block Diagram
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1.5 Supported Use Case Examples
Introduction www.ti.com
The USB supports the following user cases:
Detailed information about the architecture and operation of the USB controller follows in Section 2 .Programming examples are also provided for each of the operational modes of the controller.
User Case 1: An example of how to initialize the USB controller
Example 1. Initializing the USB Controller
// Routine to initialize USB controllervoid usb_init()
{
// local loop variableint I;
// VBUS must be controlled externally. The following routine// should perform whatever actions are required (if any) to// turn off VBUS in the system.vbus_off();
// Reset the USB controllerusbRegs->CTRLR = 0x00000001;
// Power on PHY and oscillator by clearing bits 2, 1, and 0 of USBPHY_CTLsysRegs->USB_PHY_CTRL = 0x000000D0;
//Clear all pending interruptsusbRegs->INTCLRR = usbRegs->INTSRCR;
// Initialize CPPI DMAusbRegs->RCPPICR = 0; //Disable the RX DMAusbRegs->TCPPICR = 0; //Disable the TX DMA
// Initialize CPPI DMA statefor(I = 0; i < 4; I++) {usbRegs->CHANNEL[i].TCPPIDMASTATEW0 = 0;usbRegs->CHANNEL[i].TCPPIDMASTATEW1 = 0;usbRegs->CHANNEL[i].TCPPIDMASTATEW2 = 0;usbRegs->CHANNEL[i].TCPPIDMASTATEW3 = 0;usbRegs->CHANNEL[i].TCPPIDMASTATEW4 = 0;usbRegs->CHANNEL[i].TCPPIDMASTATEW5 = 0;usbRegs->CHANNEL[i].RCPPIDMASTATEW0 = 0;usbRegs->CHANNEL[i].RCPPIDMASTATEW1 = 0;usbRegs->CHANNEL[i].RCPPIDMASTATEW2 = 0;usbRegs->CHANNEL[i].RCPPIDMASTATEW3 = 0;usbRegs->CHANNEL[i].RCPPIDMASTATEW4 = 0;usbRegs->CHANNEL[i].RCPPIDMASTATEW5 = 0;usbRegs->CHANNEL[i].RCPPIDMASTATEW6 = 0;}}
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www.ti.com Introduction
User Case 2: An example of how to program the USB Endpoints in peripheral mode
Example 2. Programming the USB Endpoints in Peripheral Mode
// DMA channel number. Valid values are 0, 1, 2, or 3.int CHAN_NUM = 0;
// Fifo sizes: uncomment the desired size.// This example uses 64-byte fifo.// int fifosize = 0; // 8 bytes// int fifosize = 1; // 16 bytes// int fifosize = 2; // 32 bytesint fifosize = 3; // 64 bytes// int fifosize = 4; // 128 bytes// int fifosize = 5; // 256 bytes// int fifosize = 6; // 512 bytes// int fifosize = 7; // 1024 bytes// int fifosize = 8; // 2048 bytes// int fifosize = 9; // 4096 bytes
// FIFO address. Leave 64-bytes for endpoint 0.int fifo_start_address = 8;
// Uncomment the desired buffering. If double-buffer is selected, actual// FIFO space will be twice the value listed above for fifosize.// This example uses single buffer.int double_buffer = 0; // Single-buffer// int double_buffer = 1; // Double-buffer
// For maximum packet size this formula will usually work, but it can also be// set to another value if needed. If non power of 2 value is needed (such as// 1023) set it explicitly.#define FIFO_MAXP 8*(1 < < fifosize);
// Set the following variable to the device address.int device_address = 0;
// The following code should be run after receiving a USB reset from the host.
// Initialize the endpoint FIFO. RX and TX will be allocated the same sizes.usbRegs->INDEX = CHAN_NUM+1;usbRegs->RXFIFOSZ = fifosize | ((double_buffer & 1) < < 4);usbRegs->RXFIFOADDR = fifo_start_address;usbRegs->TXFIFOSZ = fifosize | ((double_buffer & 1) < < 4);usbRegs->TXFIFOADDR = fifo_start_address + (1 < < (fifosize+double_buffer));usbRegs->RXMAXP = FIFO_MAXP;usbRegs->TXMAXP = FIFO_MAXP;
// Force Data Toggle is optional for interrupt traffic. Uncomment if needed.// CSL_FINS(usbRegs->PERI_TXCSR,USB_PERI_TXCSR_FRCDATATOG,1);
// Uncomment below to configure the endpoint for ISO and not respond with a// handshake packet.// CSL_FINS(usbRegs->PERI_RXCSR,USB_PERI_RXCSR_ISO,1);
// CSL_FINS(usbRegs->PERI_TXCSR,USB_PERI_TXCSR_ISO,1);
// After receiving a successful set-address command, set the following register// to the specified address immediately following the status stage.usbRegs->FADDR = device_address;
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Introduction www.ti.com
User Case 3: An example of how to program the USB endpoints in host mode
Example 3. Programming the USB Endpoints in Host Mode
// DMA channel number. Valid values are 0, 1, 2, or 3.int CHAN_NUM = 0;
// Fifo sizes: uncomment the desired size.// This example uses 64-byte fifo.// int fifosize = 0; // 8 bytes// int fifosize = 1; // 16 bytes// int fifosize = 2; // 32 bytesint fifosize = 3; // 64 bytes// int fifosize = 4; // 128 bytes// int fifosize = 5; // 256 bytes// int fifosize = 6; // 512 bytes// int fifosize = 7; // 1024 bytes// int fifosize = 8; // 2048 bytes// int fifosize = 9; // 4096 bytes
// FIFO address. Leave 64-bytes for endpoint 0.int fifo_start_address = 8;
// Uncomment the desired buffering. If double-buffer is selected, actual// FIFO space will be twice the value listed above for fifosize.// This example uses single buffer.int double_buffer = 0; // Single-buffer// int double_buffer = 1; // Double-buffer
// Set the following variable to the device endpoint type: CONTROL ISO BULK or INint device_protocol = BULK;//int device_protocol = ISO;//int device_protocol = INT;
// USB speeds#define LOW_SPEED 0#define FULL_SPEED 1#define HIGH_SPEED 2
// TXTYPE protocol#define CONTROL 0#define ISO 1#define BULK 2#define INT 3
// For maximum packet size this formula will usually work, but it can also be// set to another value if needed. If non power of 2 value is needed (such as// 1023) set it explicitly.#define FIFO_MAXP 8*(1 < < fifosize);
// Set the following variable to the device address.int device_address = 1;
// Set the following variable to the device endpoint number.int device_ep = 1;
// Variable used for endpoint configurationUint8 type = 0;
// Variable to keep track of errorsint error = 0;
// The following code should be run after resetting the attached device
// Initialize the endpoint FIFO. RX and TX will be allocated the same sizes.usbRegs->INDEX = CHAN_NUM+1;usbRegs->RXFIFOSZ = fifosize | ((double_buffer & 1) < < 4);usbRegs->RXFIFOADDR = fifo_start_address;
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www.ti.com Introduction
Example 3. Programming the USB Endpoints in Host Mode (continued)
usbRegs->TXFIFOSZ = fifosize | ((double_buffer & 1) < < 4);usbRegs->TXFIFOADDR = fifo_start_address + (1 < < (fifosize+double_buffer));usbRegs->RXMAXP = FIFO_MAXP;usbRegs->TXMAXP = FIFO_MAXP;
//Configure the endpointswitch (device_speed) {case LOW_SPEED : type = (3 < < 6) | ((device_protocol & 3) < < 4) | (device_ep & 0xf); break;case FULL_SPEED: type = (2 < < 6) | ((device_protocol & 3) < < 4) | (device_ep & 0xf); break;case HIGH_SPEED: type = (1 < < 6) | ((device_protocol & 3) < < 4) | (device_ep & 0xf); break;default:error++;
}
usbRegs->EPCSR[CHAN_NUM+1].HOST_TYPE0 = type; // TXTYPEusbRegs->EPCSR[CHAN_NUM+1].HOST_RXTYPE = type;
// Set NAK limit / Polling interval (Interrupt & Iso protocols)if ((device_protocol == INT) || (device_protocol == ISO)) {usbRegs->EPCSR[CHAN_NUM+1].HOST_NAKLIMIT0 = TXINTERVAL; // TX Polling intervalusbRegs->EPCSR[CHAN_NUM+1].HOST_RXINTERVAL = RXINTERVAL; // RX Polling interval} else {usbRegs->EPCSR[CHAN_NUM+1].HOST_NAKLIMIT0 = 2; // Frames to timeout from NAKsusbRegs->EPCSR[CHAN_NUM+1].HOST_RXINTERVAL = 2; // Frames to timeout from NAKs}
//Set the address for transactions after SET ADDRESS successfully completedusbRegs->EPTRG[CHAN_NUM+1].TXFUNCADDR = device_address;usbRegs->EPTRG[CHAN_NUM+1].RXFUNCADDR = device_address;
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Introduction www.ti.com
User Case 4: An example of how to do host negotiation to support USB
If the HOSTREQ bit in the DEVCTL register is set, host negotiation is performed by the hardware whenthe device enters suspend mode. The bit is cleared when host negotiation is complete.
User Case 5: An example of how to program the USB DMA controller
Example 4. Programming the USB DMA Controller
// Number of DMA channels#define NUM_CHANNEL 4
// Number of DMA buffers to allocate#define RX_BUFFERS 32#define TX_BUFFERS 32
// Memory region to place DMA buffers and descriptors#define MEMORY_TARGET ".DDREMIF_0_BUF"
// DMA defines#define SOP (Uint32) (1 < < 31)#define EOP (Uint32) (1 < < 30)#define OWNER (Uint32) (1 < < 29)#define EOQ (Uint32) (1 < < 28)#define ZERO_BYTE (Uint32) (1 < < 23)#define RX_ABORT (Uint32) (1 < < 19)
// DMA channel configuration#define CH0 0#define CH1 1#define CH2 2#define CH3 3
// Loop variableint I;
// Variable to keep track of errorsint error = 0;
// Variable to keep track of the number of descriptors builtint tx_desc[NUM_CHANNEL]; // Current TX Buffer descriptor[channel number]int rx_desc[NUM_CHANNEL]; // Current RX Buffer descriptor[channel number]
// Separate data section for bufferDesc. NOTE: CPPI buffers MUST be aligned to 16-byteboundaries.
#pragma DATA_SECTION(rx_bufferDesc, MEMORY_TARGET)Uint32 rx_bufferDesc[NUM_CHANNEL][RX_BUFFERS];
#pragma DATA_SECTION(tx_bufferDesc, MEMORY_TARGET)Uint32 tx_bufferDesc[NUM_CHANNEL][TX_BUFFERS];
// Initialize CPPI DMA. This code is also included in the controller initialization.usbRegs->RCPPICR = 0; //Disable the RX DMAusbRegs->TCPPICR = 0; //Disable the TX DMAfor(I = 0; i < NUM_CHANNEL;i++) { // Initialize CPPI DMA stateusbRegs->CHANNEL[i].TCPPIDMASTATEW0 = 0;usbRegs->CHANNEL[i].TCPPIDMASTATEW1 = 0;usbRegs->CHANNEL[i].TCPPIDMASTATEW2 = 0;usbRegs->CHANNEL[i].TCPPIDMASTATEW3 = 0;usbRegs->CHANNEL[i].TCPPIDMASTATEW4 = 0;usbRegs->CHANNEL[i].TCPPIDMASTATEW5 = 0;
usbRegs->CHANNEL[i].RCPPIDMASTATEW0 = 0;usbRegs->CHANNEL[i].RCPPIDMASTATEW1 = 0;usbRegs->CHANNEL[i].RCPPIDMASTATEW2 = 0;usbRegs->CHANNEL[i].RCPPIDMASTATEW3 = 0;usbRegs->CHANNEL[i].RCPPIDMASTATEW4 = 0;usbRegs->CHANNEL[i].RCPPIDMASTATEW5 = 0;
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