Texas Instruments TMS320DM646 Series User manual

TMS320DM646x DMSoCATA Controller
User's Guide
Literature Number: SPRUEQ3December 2007

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Contents
Preface ............................................................................................................................... 51 Introduction ................................................................................................................ 71.1 Purpose of the Peripheral ....................................................................................... 71.2 Features ........................................................................................................... 71.3 Functional Block Diagram ....................................................................................... 81.4 Supported Use Cases ........................................................................................... 81.5 Industry Standard(s) Compliance .............................................................................. 91.6 Terminology Used in This Document .......................................................................... 92 Architecture ............................................................................................................... 92.1 Clock Control ..................................................................................................... 92.2 Signal Descriptions ............................................................................................. 102.3 Pin Multiplexing ................................................................................................. 122.4 Protocol Description(s) ......................................................................................... 122.5 General Architecture ........................................................................................... 132.6 DMA and PIO Data Transaction Overview .................................................................. 182.7 Attached Device Reset Considerations ...................................................................... 222.8 Initialization ...................................................................................................... 232.9 Interrupt Support ................................................................................................ 262.10 EDMA Event Support .......................................................................................... 292.11 Power Management ............................................................................................ 302.12 Emulation Considerations ..................................................................................... 303 Use Cases ................................................................................................................ 303.1 Interfacing to a Standard ATA/ATAPI Device ............................................................... 303.2 Interfacing to a Standard ATA/ATAPI Device Through a Level-Shifter .................................. 313.3 Interfacing to Compact Flash ................................................................................. 324 Registers .................................................................................................................. 344.1 Primary IDE Channel DMA Control Register (BMICP) .................................................... 354.2 Primary IDE Channel DMA Status Register (BMISP)...................................................... 364.3 Primary IDE Channel DMA Descriptor Table Pointer Register (BMIDTP) .............................. 374.4 Primary IDE Channel Timing Register (IDETIMP) ......................................................... 384.5 IDE Controller Status Register (IDESTAT) .................................................................. 394.6 Ultra-DMA Control Register (UDMACTL) ................................................................... 404.7 Miscellaneous Control Register (MISCCTL) ................................................................ 414.8 Task File Register Strobe Timing Register (REGSTB) .................................................... 424.9 Task File Register Recovery Timing Register (REGRCVR) .............................................. 434.10 Data Register Access PIO Strobe Timing Register (DATSTB) ........................................... 444.11 Data Register Access PIO Recovery Timing Register (DATRCVR) ..................................... 454.12 Multiword DMA Strobe Timing Register (DMASTB) ....................................................... 464.13 Multiword DMA Recovery Timing Register (DMARCVR).................................................. 474.14 Ultra-DMA Strobe Timing Register (UDMASTB) ........................................................... 484.15 Ultra-DMA Ready-to-Pause Timing Register (UDMATRP) ............................................... 494.16 Ultra-DMA Timing Envelope Register (UDMATENV) ...................................................... 504.17 Primary IO Ready Timer Configuration Register (IORDYTMP) .......................................... 51
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List of Figures
1 ATA Controller Block Diagram ............................................................................................. 82 Physical Region Descriptor (PRD) Table Entry ........................................................................ 193 Primary IDE Channel DMA Control Register (BMICP) ................................................................ 354 Primary IDE Channel DMA Status Register (BMISP) ................................................................. 365 Primary IDE Channel DMA Descriptor Table Pointer Register (BMIDTP) .......................................... 376 Primary IDE Channel Timing Register (IDETIMP) ..................................................................... 387 IDE Controller Status Register (IDESTAT) ............................................................................. 398 Ultra-DMA Control Register (UDMACTL) ............................................................................... 409 Miscellaneous Control Register (MISCCTL) ............................................................................ 4110 Task File Register Strobe Timing Register (REGSTB) ............................................................... 4211 Task File Register Recovery Timing Register (REGRCVR) .......................................................... 4312 Data Register Access PIO Strobe Timing Register (DATSTB) ...................................................... 4413 Data Register Access PIO Recovery Timing Register (DATRCVR) ................................................. 4514 Multiword DMA Strobe Timing Register (DMASTB) ................................................................... 4615 Multiword DMA Recovery Timing Register (DMARCVR) ............................................................. 4716 Ultra-DMA Strobe Timing Register (UDMASTB) ....................................................................... 4817 Ultra-DMA Ready-to-Pause Timing Register (UDMATRP) ........................................................... 4918 Ultra-DMA Timing Envelope Register (UDMATENV) .................................................................. 5019 Primary IO Ready Timer Configuration Register (IORDYTMP) ...................................................... 51
List of Tables
1 Supported ATA Controller Signals ....................................................................................... 102 Unsupported ATA Controller Signals .................................................................................... 123 Description of Single Physical Region Descriptor (PRD) Table Entry ............................................... 194 ATA Controller Interrupt ................................................................................................... 265 Identifying the ATA Controller Interrupt Sources ....................................................................... 276 DMA Driven Interrupt Conditions ......................................................................................... 297 ATA/ATAPI Device Interface Connections for a Standard ATA/ATAPI Device .................................... 308 ATA/ATAPI Device Interface Connections for a Standard ATA/ATAPI Device Through a Level-Shifter ....... 329 ATA/ATAPI Device Interface Connections for a Compact Flash Device ........................................... 3310 ATA Host Controller Registers ........................................................................................... 3411 ATA Controller Registers in the Attached Device ...................................................................... 3412 Primary IDE Channel DMA Control Register (BMICP) Field Descriptions .......................................... 3513 Primary IDE Channel DMA Status Register (BMISP) Field Descriptions ........................................... 3614 Primary IDE Channel DMA Descriptor Table Pointer Register (BMIDTP) Field Descriptions .................... 3715 Primary IDE Channel Timing Register (IDETIMP) Field Descriptions ............................................... 3816 IDE Controller Status Register (IDESTAT) Field Descriptions ....................................................... 3917 Ultra-DMA Control Register (UDMACTL) Field Descriptions ......................................................... 4018 Miscellaneous Control Register (MISCCTL) Field Descriptions ...................................................... 4119 Task File Register Strobe Timing Register (REGSTB) Field Descriptions ......................................... 4220 Task File Register Recovery Timing Register (REGRCVR) Field Descriptions .................................... 4321 Data Register Access PIO Strobe Timing Register (DATSTB) Field Descriptions ................................ 4422 Data Register Access PIO Recovery Timing Register (DATRCVR) Field Descriptions .......................... 4523 Multiword DMA Strobe Timing Register (DMASTB) Field Descriptions ............................................. 4624 Multiword DMA Recovery Timing Register (DMARCVR) Field Descriptions ....................................... 4725 Ultra-DMA Strobe Timing Register (UDMASTB) Field Descriptions ................................................. 4826 Ultra-DMA Ready-to-Pause Timing Register (UDMATRP) Field Descriptions ..................................... 4927 Ultra-DMA Timing Envelope Register (UDMATENV) Field Descriptions ........................................... 5028 Primary IO Ready Timer Configuration Register (IORDYTMP) Field Descriptions ................................ 51
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PrefaceSPRUEQ3 – December 2007
Read This First
About This Manual
The AT attachment/ATA packet interface (ATA/ATAPI), also known as IDE controller, is the traditionalchoice of the communication medium between a portable computer (PC) and a hard-disk drive. Ever sinceits adoption by the industry, it has been the choice of interface between a PC and a common storagemedium. This standard interface provides a common attachment interface for system manufacturers,system integrators, software suppliers, and suppliers of intelligent storage devices.
Notational Conventions
This document uses the following conventions.•Hexadecimal numbers are shown with the suffix h. For example, the following number is 40hexadecimal (decimal 64): 40h.•Registers in this document are shown in figures and described in tables.– Each register figure shows a rectangle divided into fields that represent the fields of the register.Each field is labeled with its bit name, its beginning and ending bit numbers above, and itsread/write properties below. A legend explains the notation used for the properties.– Reserved bits in a register figure designate a bit that is used for future device expansion.
Related Documentation From Texas InstrumentsThe following documents describe the TMS320DM646x Digital Media System-on-Chip (DMSoC). Copiesof these documents are available on the Internet at www.ti.com .Tip: Enter the literature number in thesearch box provided at www.ti.com.
The current documentation that describes the DM646x DMSoC, related peripherals, and other technicalcollateral, is available in the C6000 DSP product folder at: www.ti.com/c6000 .
SPRUEP8 —TMS320DM646x DMSoC DSP Subsystem Reference Guide. Describes the digital signalprocessor (DSP) subsystem in the TMS320DM646x Digital Media System-on-Chip (DMSoC).
SPRUEP9 —TMS320DM646x DMSoC ARM Subsystem Reference Guide. Describes the ARMsubsystem in the TMS320DM646x Digital Media System-on-Chip (DMSoC). The ARM subsystem isdesigned to give the ARM926EJ-S (ARM9) master control of the device. In general, the ARM isresponsible for configuration and control of the device; including the DSP subsystem and a majorityof the peripherals and external memories.
SPRUEQ0 —TMS320DM646x DMSoC Peripherals Overview Reference Guide. Provides an overviewand briefly describes the peripherals available on the TMS320DM646x Digital MediaSystem-on-Chip (DMSoC).
SPRAA84 —TMS320C64x to TMS320C64x+ CPU Migration Guide. Describes migrating from theTexas Instruments TMS320C64x digital signal processor (DSP) to the TMS320C64x+ DSP. Theobjective of this document is to indicate differences between the two cores. Functionality in thedevices that is identical is not included.
SPRU732 —TMS320C64x/C64x+ DSP CPU and Instruction Set Reference Guide. Describes the CPUarchitecture, pipeline, instruction set, and interrupts for the TMS320C64x and TMS320C64x+ digitalsignal processors (DSPs) of the TMS320C6000 DSP family. The C64x/C64x+ DSP generationcomprises fixed-point devices in the C6000 DSP platform. The C64x+ DSP is an enhancement ofthe C64x DSP with added functionality and an expanded instruction set.
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Related Documentation From Texas Instruments
SPRU871 —TMS320C64x+ DSP Megamodule Reference Guide. Describes the TMS320C64x+ digitalsignal processor (DSP) megamodule. Included is a discussion on the internal direct memory access(IDMA) controller, the interrupt controller, the power-down controller, memory protection, bandwidthmanagement, and the memory and cache.
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1 Introduction
1.1 Purpose of the Peripheral
1.2 Features
User's GuideSPRUEQ3 – December 2007
ATA Controller
The AT attachment/ATA packet interface (ATA/ATAPI), also known as IDE controller, is the traditionalchoice of the communication medium between a portable computer (PC) and a hard-disk drive. Ever sinceits adoption by the industry, it has been the choice of interface between a PC and a common storagemedium. This standard interface provides a common attachment interface for system manufacturers,system integrators, software suppliers, and suppliers of intelligent storage devices.
This document describes the ATA controller on the TMS320DM646x Digital Media System-on-Chip(DMSoC). The ATA controller provides a glueless interface to storage media to be used by video andaudio applications for video and audio data storage.
The AT attachment/ATA packet interface (ATA/ATAPI) is an interface that is most commonly used by PCsand portable devices to interface a host processor with data storage or audio devices. The ATA interfacedebuted in the mid 1980s as an interface between a hard-disk drive and a PC by way of a ribbon cable.Ever since then, other devices, mostly storage, including compact Flash and compact disks have widelyadopted the ATA/ATAPI interface, leveraging from its proven capability as the means for connecting to ahost processor. These allowed device manufacturers to avoid developing and supporting a proprietaryinterface that would significantly limit the use of their devices. The ATA/ATAPI interface is popular due toits simplicity, low cost, reliability, compatibility, as well as its wide acceptance and long history of usewithin the PC industry market.
The DM646x DMSoC supports an onboard ATA/ATAPI host controller module (IDE controller) allowing itto exploit access to a vast majority of available data storage and audio devices. The onboard IDE hostcontroller performs PIO, multiword, and ultra-DMA transactions with ATA and ATAPI compliant devices.Hard-disk drive, compact disk (CD), compact Flash (CF), and DVD are members of ATA/ATAPI-compliantdevices that the IDE host controller is destined to interface with. This allows applications like streamingmedia and digital still cameras the means for easy access to commonly used external storage devices.
The content described here assumes the knowledge of ATA/ATAPI-6 and compact Flash v2.0specifications and should be used in conjunction with these documents.
The IDE host controller logic supports PIO, multiword DMA and ultra-DMA (ultra-ATA) modes. The ATAcontroller has the following features:•Single channel capable for connecting up to two ATA/ATAPI devices•Supports interface to compact Flash (CF) configured in True-IDE mode•Supports PIO modes 0, 1, 2, 3, and 4•Supports multiword DMA modes 0, 1, and 2•Supports ultra-DMA modes 0, 1, 2, 3, 4, and 5•Full scatter gather DMA capability•Programmable timing parameters provide support of any multiple ATA timing options mode at anyprocessor clock frequency
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1.3 Functional Block Diagram
Peripheral
Interface
ATA_INTRQ
IDE Controller
Register File
Interrupt
DMA
Engine
DMA Read
FIFO
DMA Read
FIFO
ARM CPU
ARM
Interrupt
Controller
System
Memory
IDE Timing
Control
IDE Host
Interface
ATA_IORDY
ATA_DMARQ
ATA CS0
ATA_DMACK
ATA CS1
ATA_HA0
ATA_HIOR
ATA_D[15:0]
ATA_HIOW
ATA_DDIR
ATA_HA1
ATA_HA2
1.4 Supported Use Cases
Introduction
The ATA controller is shown in Figure 1 .
Figure 1. ATA Controller Block Diagram
The IDE controller is commonly used to interface to ATA and ATAPI devices. Devices like hard disk drivesare ATA devices. Devices like CDs, compact flash, and DVDs are ATAPI devices. Both ATA and ATAPIdevices use the same identical interface and differ partly in protocol (specifically the way command isdelivered to the attached device). This difference is transparent to the IDE host controller and meaningfulto the driver/firmware that is running on the host supporting the attached device. For ATA devices, allcommands and commands parameters are register-driven while ATAPI devices make use of bothregister-driven and packet-driven commands. Consult the ATA/ATAPI-6 specification for more information.
For information on how to interface to a standard ATA/ATAPI device, see Section 3.1 .
For information on how to interface to a standard ATA/ATAPI device with a higher I/O voltage requirementusing a level-shifter, see Section 3.2 .
For information on how to interface to a compact Flash (CF) device, see Section 3.3 .
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1.5 Industry Standard(s) Compliance
1.6 Terminology Used in This Document
2 Architecture
2.1 Clock Control
Architecture
The IDE controller supports the ATA/ATAPI-6 and compact Flash v2.0 specifications. The specific modesof operations (PIO, multiword, and ultra-DMA) depend on the frequency at which the IDE controlleroperates. For this reason, not all modes supported by the specification and device may be exercised if theclocking frequency to the IDE controller is low. The actual mode supported (subset of the ATA/ATAPIstandard) by the device is directly tied to the IDE controller clock sourcing. For more information on theclocking provided to the peripheral, see Section 2.1 . In addition to possible reduction of mode support dueto low frequency clocking, the processor does not pin out all the signals available in the ATA/ATAPIspecification. Additional signals (necessary to support wide range of devices) that are not present withinthe ATA/ATAPI standard specification are also available. See Section 2.2 for more information on thesignals supported on this peripheral.
The following is a brief explanation of some terms used in this document:
Term MeaningATA/ATAPI AT attachment/ATA packet interfaceATA controller ATA/ATAPI controller peripheralCF Compact Flashdevice External ATA/ATAPI device attached to the IDE controllerDMA DMA within the ATA controller, not the processor EDMA systemhost Processor IDE controller (this peripheral), unless otherwise specifiedIDE controller Synonymous with ATA controllerprocessor DM646x Digital Media Processor
This section discusses the architecture of the ATA controller.
The IDE controller uses a single programmable clock for its operation. This clock needs to be reconfiguredprior to enabling access to the attached ATA/ATAPI device. The maximum clock frequency supplied to theATA controller is dependent upon the clock frequency of the processor. See the device specific datamanual for more information on the processor voltage and speed characteristics.
SYSCLK4 (PLL0 output frequency divided by 6) is the source of the clock to the ATA peripheral. Toensure proper operation, the operating frequency of the ATA controller clock should be chosen in such away that it is at least twice as fast as the ATA data strobe frequency in order to achieve expectedthroughput.
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2.2 Signal Descriptions
2.2.1 ATA/ATAPI Interface Signals Supported by the ATA Controller
Architecture
Table 1 describes the signals supported by the IDE controller interface.
Table 1. Supported ATA Controller Signals
Direction fromTerminal Name IDE Controller Description
ATA_CS0 Output Chip Select Signals 0 and 1ATA_CS1
These are the chip select signals from the host used to select the Command Block orControl Block registers. ATA_CS0 is asserted during Command Block registeraccesses. ATA_CS1 is asserted during Control Block register accesses. WhenATA_DMACK is asserted, ATA_CS0 and ATA_CS1 are both asserted and transferswill be 16 bits wide.ATA_HA0 Output Device Address Bits[2:0]ATA_HA1
This is a 3-bit binary coded address asserted by the host to access a register or dataATA_HA2
port in the attached device.ATA_D[15:0] Input/Output Host Read/Write Data BusThis is a 16-bit bi-directional data interface between the host and the device. Datatransfers are 16-bits wide except for CF devices that implement 8-bit data transfers. Inthis case, ATA_D[7:0] will be used for 8-bit register transfers.ATA_DMARQ Input Device DMA RequestThe device will assert this signal, used for DMA data transfers between host anddevice, when the device is ready to transfer data to or from the host in any of the DMAmodes. For multiword transfers, the direction of data transfer is controlled byATA_HIOR and ATA_HIOW. This signal is used in a handshake manner withATA_DMACK, that is, the device will wait until the host asserts ATA_DMACK beforenegating ATA_DMARQ, and re-asserting ATA_DMARQ if there is more data totransfer. For multiword DMA transfers, the ATA_DMARQ/ ATA_DMACK handshake isused to provide flow control during the transfer. For ultra-DMA, theATA_DMARQ/ ATA_DMACK handshake is used to indicate when the function ofinterface signals changes.This signal will be released when the device is not selected.ATA_DMACK Output Host DMA Acknowledge
This signal is used by the host in response to ATA_DMARQ to initiate DMA transfers.For multiword DMA transfers, the ATA_DMARQ/ ATA_DMACK handshake is used toprovide flow control during the transfer. For ultra-DMA, theATA_DMARQ/ ATA_DMACK handshake is used to indicate when the function ofinterface signals changes.When ATA_DMACK is asserted, ATA_CS0 and ATA_CS1 is not asserted andtransfers are 16 bits wide.ATA_IORDY Input Device I/O ready during PIO transactionDMA ready during ultra-DMA writeDMA strobe during ultra-DMA readATA_IORDY is negated to extend the host transfer cycle of any host register access(PIO 8-bit) or PIO data access when the device is not ready to respond to a transferrequest. If the device requires that the host transfer cycle time be extended, the devicewill assert the ATA_IORDY signal. Devices that support PIO modes 3 and above arerequired by the ATA/ATAPI specification to support ATA_IORDY.For ultra-DMA data-write transaction, this signal is a flow control signal for data-outbursts. This signal is asserted by the device to indicate to the host that the device isready to receive Ultra DMA data-out bursts. The device may negate ATA_IORDY topause an Ultra DMA data-out burst.For ultra-DMA data-read transaction, this signal is a data-in strobe signal from thedevice for data-in burst. Both the rising and falling edges of ATA_IORDY latch thedata from ATA_D[15:0] into the host. The device may stop generating ATA_IORDYedges to pause an ultra DMA data-in burst.This signal is released when the device is not selected.
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Architecture
Table 1. Supported ATA Controller Signals (continued)
Direction fromTerminal Name IDE Controller Description
ATA_HIOR Output PIO Read Transaction IndicatorDMA Ready during Ultra-DMA ReadDMA Data Strobe during Ultra-DMA WriteATA_HIOR is the strobe signal used by the host to read device registers or data. Datais transferred on the negation of this signal.When performing ultra-DMA data read transaction, this signal is used by the host forflow control during data-in bursts. This signal is asserted by the host to indicate to thedevice that the host is ready to receive ultra-DMA data-in bursts. The host may negateATA_HIOR to pause an ultra DMA data-in burst.When performing ultra-DMA data write transaction, the host uses the ATA_HIOR tostrobe the ultra-DMA data-out burst.Both the rising and falling edges of ATA_HIOR latch the data from ATA_D[15:0] intothe device. The host may stop generating ATA_HIOR edges to pause an ultra DMAdata-out burst.ATA_HIOW Output PIO Write Transaction IndicatorStop Ultra-DMA Data Read/Write BurstsATA_HIOW is the strobe signal used by the host to write device registers (PIO 8-bit)or data (PIO 16-bit). Data is transferred on the negation of this signal.The host will negate ATA_HIOW prior to initiation of an ultra DMA burst. The host willnegate ATA_HIOW before data is transferred in an ultra-DMA burst. Assertion ofATA_HIOW by the host during an ultra-DMA burst signals the termination of the ultraDMA burst.ATA_INTRQ Input Attached Device Interrupt RequestThis signal is used by the selected device to interrupt the host system when interruptpending is set. When the nIEN bit is cleared to zero and the device is selected, INTRQis enabled. When the nIEN bit is set to one or the device is not selected, the INTRQsignal is disabled.When asserted, this signal should be negated by the device within 400 ns of thenegation of ATA_HIOR that reads the Status register to clear interrupt pending. Whenasserted, this signal should be negated by the device within 400 ns of the negation ofATA_HIOW that writes the Command register to clear interrupt pending.When the device is selected by writing to the Device register while interrupt pending isset, ATA_INTRQ should be asserted within 400 ns of the negation of ATA_HIOW thatwrites the device register. When the device is deselected by writing to the deviceregister while interrupt pending is set, ATA_INTRQ should be released within 400 nsof the negation of ATA_HIOW that writes the device register.This signal shares a function with an EMIF signal. For simplicity, in the remainder ofthis document this signal will be referred to as INTRQ.ATA_DDIR Output External Level Shifter Direction IndicatorThis signal is used when a 3.3 V or 5.0 V tolerant ATA/ATAPI devices are used tointerface with the IDE controller. This signal indicates the direction of the current datatransfer.
Although this signal provides direction control, it is the responsibility of the user toenable the shifter properly. The processor does not provide an enable control for thelevel shifter.
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2.2.2 ATA/ATAPI/Compact Flash Specification Signals Not Supported by This Peripheral
2.3 Pin Multiplexing
2.4 Protocol Description(s)
Architecture
The processor supports all the signals needed to realize the supported modes of operation. Table 2 listssome of the signals that are present within the ATA/ATAPI specification that are not available. In addition,the processor supports additional signals to interface to devices that are 3.3 V and 5.0 V tolerant devices.
Table 2. Unsupported ATA Controller Signals
Name Description
RESET This signal is used by the IDE controller to perform a hardware reset on the attached ATA/ATAPI device.A GPIO signal can be used for this purpose due to lack of a dedicated ATA reset signal on theprocessor.Cable Select (CSEL) The processor host IDE controller requires the use of the proper type cable based on the maximummode of operation in which the external device is intended to operate. Specifically, if the external devicesupports UDMA mode greater than mode2, then it is expected that an 80-conductor ribbon cable beused to connect the IDE controller with the ATA device. The use of a 40-conductor ribbon cable withhigher UDMA mode of operation would result in reduced throughput due to the introduction of error fromsignals propagating on adjacent conductors. This signal is not necessary because an 80-conductor cablemust be used with the DM646x.Cable ID (CBLID) The Cable ID signal is used by attached devices in order to configure themselves as master or slavewithout the need for a jumper configuration setting. The host does not need to have a dedicated signal todrive this signal. This task is achieved by tying the appropriate pin (on the header on the processor side)low external to the processor.True IDE Mode Selector This signal needs to be driven low prior to power-up in order to configure a Compact Flash in True IDE(ATA_SEL) mode. Since any Compact Flash mounted to work with the processor is only useful in True IDE mode,the state of this signal is tied to ground by the header. Note that CF devices use a 50 pin header that isdifferent from the standard ATA/ATAPI header.
On the DM646x DMSoC, extensive pin multiplexing is used to accommodate the largest number ofperipheral functions in the smallest possible package. Pin multiplexing is controlled using a combination ofhardware configuration at device reset and software programmable register settings. Refer to thedevice-specific data manual to determine how pin multiplexing affects the ATA.
The IDE controller supports the protocols defined in the ATA/ATAPI-6 and compact Flash 2.0specifications.
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2.5 General Architecture
2.5.1 Programmable Timing Registers
Architecture
The IDE controller implements several programmable timing registers that allow users to reprogram thekey IDE interface signal timings for the four transfer types: 8-bit task file registers accesses, 16-bit PIOdata accesses, multiword DMA transfers, and ultra-DMA transfers. This allows the host controller toeffectively be reconfigured to support a wide range of input clock frequencies and any target interface forall transfer types.
The default state for the programmable timing registers logic is disabled; that is, the TIMORIDE bit in themiscellaneous control register (MISCCTL) is 0. The programmable timing registers should be enabled bysetting the TIMORIDE bit to 1 for proper operation. The IDE controller may not be able to operate correctlyif the programmable timing registers are not enabled.
Four sets of programming timing registers exist to support the four types of IDE transfers. In addition, theMISCCTL upper bits allow for a common control over the write data hold time for three of the fourtransfers: task file writes, PIO writes, and multiword DMA writes. The write data hold time in MISCCTLmust satisfy the worst case requirement of these three modes.•The task file register strobe timing register (REGSTB) and the task file register recovery timing register(REGRCVR) control the timing parameters for 8-bit accesses of the task file registers.•The data register PIO strobe timing register (DATSTB) and the data register PIO recovery timingregister (DATRCVR) control the timing parameters for PIO data accesses.•The DMA strobe timing register (DMASTB) and the DMA recovery timing register (DMARCVR) controltimings for multiword DMA accesses.•The ultra DMA strobe timing register (UDMASTB), the ultra DMA ready-to-stop timing register(UDMATRP), and the ultra DMA timing envelope register (UDMATENV) control the timing of ultra DMAaccesses.
The timing override registers are programmed with a value indicating the number of clock cycles (minus1 cycle) that the IDE controller will wait to meet a particular timing parameter. You identify the minimum ormaximum value for a timing parameter from the IDE specification, determine the IDE clock frequency, andthen calculate the number of clock cycles necessary to meet that timing parameter. For example, if therequired IDE controller clock frequency is 99 MHZ (10.10 ns period), then to meet a minimum IDEinterface timing requirement of 25 ns, 3 clock cycles are required (3 cycles נ10.10 ns = 30.3 ns). Thismeans that the corresponding timing register that controls the parameter would be programmed with a 2(3 clock cycles minus 1 cycle). If the IDE controller clock frequency is 50 MHZ (20 ns) and a minimumtiming requirement of 55 ns is to be met, this would require at least 3 clock cycles (3 cycles נ20 ns =60 ns); therefore, the timing register should be programmed with a value of 2.
Note that programming the HWNHLD nP bits in MISCCTL controls the write data hold times used for taskfile registers writes, PIO data writes, and multiword DMA data writes. Since a single timing programmableparameter is used for all three types of write transfers, the value programmed here will be the largestamong the three transfers: PIO-8 bit, PIO-16-bit, and multiword DMA.
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2.5.1.1 Programming 8-bit Task File Timing Registers
Architecture
The REGSTB, REGRCVR, and MISCCTL are used in reprogramming the timings for 8-bit task file registeraccesses. The required IDE timing parameters for 8-bit task file register accesses are defined in theATA/ATAPI-6 specification.
The REGSTB and REGRCVR can be programmed to match the parameters t
0
(cycle time), t
2
(strobetime), and t
2i
(recovery time). The HWNHLD bits in MISCCTL are used to program the hold time for thewrite data (t
4
parameter).
The REGSTB directly controls the number of clock cycles that the ATA_HIOR and ATA_HIOW strobes willbe asserted during 8-bit task file accesses. This corresponds to the strobe width timing parameter, t
2
.
The REGRCVR defines the number of clock cycles for the recovery time between task file accesses. Thiscorresponds to recovery timing parameter, t
2i
.
The sum of both parameters (t
2
+ t
2i
) must be equal or greater than the cycle time, t
0
. The HWNHLD nPbits in MISCCTL allow control over the number of clock cycles for the write data hold time during task filewrites. With knowledge of the IDE controller clock frequency, you can program the appropriate number ofclock cycles to match the timing requirements. Note that the timing registers must be programmed with avalue one less than the desired number of cycles, so a value of 0 specifies 1 clock cycle, a value of 1specifies 2 clock cycles, etc.
Example 1 and Example 2 illustrate how the 8-bit task file timing registers can be programmed.
Example 1. 8-Bit Task File Timing Registers Programming for Mode 0
Programming task file accesses for mode 0 operation using an IDE controller clock frequency of66 MHZ (15 ns period).
For mode 0 operation, t
2
requires a minimum of 290 ns, this translates to a minimum of 20 clock cycles(20 cycles נ15 ns = 300 ns). There is no requirement for t
2i
in mode 0 operation, but t
0
requires aminimum of 600 ns, or 40 clock cycles. This means REGSTB and REGRCVR can be programmed toany combination equaling 40 (or more) clock cycles, with REGSTB specifying at least 20 clock cycles.
Sample programming values are REGSTB = 13h (20 clock cycles) and REGRCVR = 13h (20 clockcycles), or REGSTB = 1Fh (32 clock cycles) and REGRCVR = 7h (8 clock cycles). In addition, theminimum write data hold time specified is 30 ns, so the HWNHLD nP bits in MISCCTL should beprogrammed to a value of at least 2 clock cycles. A sample value is HWNHLD nP = 2h (3 clock cycles)providing enough hold time and margin.
Example 2. 8-Bit Task File Timing Registers Programming for Mode 4
Programming task file accesses for mode 4 operation using an IDE controller clock frequency of99 MHZ (10.10 ns period).
For mode 4 operation, t
2
requires a minimum of 70 ns, this translates to a minimum of 7 clock cycles (7cycles נ10.10 ns = 70.70 ns). t
2i
is defined to be at least 25 ns, this translates to a minimum of 3 clockcycles (3 cycles נ10.10 ns = 30.30 ns). The minimum cycle time t
0
is 120 ns, or 12 clock cycles. Thismeans REGSTB and REGRCVR can be programmed to any combination equaling 12 (or more) clockcycles, with REGSTB specifying at least 7 cycles and REGRCVR specifying at least 3 cycles.
Sample programming values are REGSTB = 7h (8 clock cycles) and REGRCVR = 3h (4 clock cycles),or REGSTB = 8h (9 clock cycles) and REGRCVR = 2h (3 clock cycles). In addition, the minimum writedata hold time specified is 10 ns, so the HWNHLD nP bits in MISCCTL should be programmed to avalue of at least 1 clock cycle. A sample value is HWNHLD nP = 1h (2 clock cycles) providing enoughhold time and margin.
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2.5.1.2 Programming Data Register Timing Register Access
Architecture
The DATSTB and DATRCVR are used in reprogramming the timings for 16-bit PIO data accesses. Therequired IDE timing parameters for 8-bit task file register accesses are defined in the ATA/ATAPI-6specification.
The DATSTB and DATRCVR can be programmed to match the parameters t
0
(cycle time), t
2
(strobetime), and t
2i
(recovery time). The HWNHLD nP bits in MISCCTL are used to program the hold time for thewrite data (t
4
parameter).
The DATSTB directly controls the number of clock cycles that the ATA_HIOR and ATA_HIOW strobes willbe asserted during the PIO data access. This corresponds to the strobe width timing parameter, t
2
.
The DATRCVR defines the number of clock cycles for the recovery (de-assert) time for the PIO dataaccess. This corresponds to recovery timing parameter, t
2i
.
The sum of both parameters (t
2
+ t
2i
) must be equal or greater than the cycle time, t
0
. The HWNHLD nPbits in MISCCTL allow control over the number of clock cycles for the write data hold time during PIO datawrites. With knowledge of the IDE controller clock frequency, you can program the appropriate number ofclock cycles to match the timing requirements. Note that the timing registers must be programmed with avalue one less than the desired number of cycles, so a value of 0 specifies 1 clock cycle, a value of 1specifies 2 clock cycles, etc.
Example 3 and Example 4 illustrate how the data register access timing registers can be programmed.
Example 3. Data Register Timing Registers Programming for Mode 2
Programming PIO data accesses for mode 2 operation using an IDE controller clock frequency of33 MHZ (30 ns period).
For mode 2 operation, t
2
requires a minimum of 100 ns, this translates to a minimum of 4 clock cycles(4 cycles נ30 ns = 120 ns). There is no requirement for t
2i
in mode 2 operation, but the minimumrequirement for t
0
is 240 ns, or 8 clock cycles. This means DATSTB and DATRCVR can beprogrammed to any combination equaling 8 (or more) clock cycles, with DATSTB specifying at least4 clock cycles.
Sample programming values are DATSTB = 3h (4 clock cycles) and DATRCVR = 3h (4 clock cycles),or REGSTB = 5h (6 clock cycles) and DATRCVR = 1h (2 clock cycles). In addition, the minimum writedata hold time specified is 15 ns, so the HWNHLD nP bits in MISCCTL should be programmed to avalue of at least 1 clock cycle. A sample value is HWNHLD nP = 0h (0 clock cycles) providing enoughhold time and margin.
Example 4. Data Register Timing Registers Programming for Mode 3
Programming PIO data accesses for mode 3 operation using an IDE controller clock frequency of99 MHZ (10.10 ns period).
For mode 3 operation, t
2
requires a minimum of 80 ns, this translates to a minimum of 8 clock cycles(8 cycles נ10.10 ns = 80.80 ns). The minimum requirement on t
2i
is defined to be 70 ns, this translatesto a minimum of 7 clock cycles (7 cycles נ10.10 ns = 70.70 ns). The minimum cycle time t
0
is 180 ns,or 18 clock cycles. This means that DATSTB and DATRCVR can be programmed to any combinationequaling 18 (or more) clock cycles, with DATSTB specifying at least 8 cycles and DATRCVR specifyingat least 7 cycles.
Sample programming values are DATSTB = 9h (10 clock cycles) and DATRCVR = 7h (8 clock cycles),or DATSTB = Ah (11 clock cycles) and DATRCVR = 6h (7 clock cycles). In addition, the minimum writedata hold time specified is 10 ns, so the HWNHLD nP bits in MISCCTL should be programmed to avalue of at least 1 clock cycle. A sample value is HWNHLD nP = 0h (1 clock cycle) providing enoughhold time and margin.
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2.5.1.3 Programming Multiword DMA Register Accesses
Architecture
The DMASTB and DMARCVR are used in reprogramming the timings for multiword DMA transfers. Therequired IDE timing parameters for multiword DMA transfers are defined in the ATA/ATAPI-6 specification.
The DMASTB and DMARCVR can be programmed to match the parameters t
0
(cycle time), t
D
(strobetime), and t
KW
(recovery time for DMA write). The HWNHLD nP bits in MISCCTL are used to program thehold time for the write data (t
H
parameter).
The DMASTB directly controls the number of clock cycles that the ATA_HIOR and ATA_HIOW strobes willbe asserted during multiword DMA transfers. This corresponds to the strobe width timing parameter, t
D
.
The DMARCVR defines the number of clock cycles for the recovery time for multiword DMA transfers.This corresponds to recovery timing parameters, t
KR
and t
KW
.
The sum of both parameters must be equal or greater than the cycle time, t
0
. The HWNHLD nP bits inMISCCTL allow control over the number of clock cycles for the write data hold time during multiword DMAdata writes. With knowledge of the system clock frequency, you can program the appropriate number ofclock cycles to match the timing requirements. Note that the timing registers must be programmed with avalue one less than the desired number of cycles, so a value of 0 specifies 1 clock cycle, a value of 1specifies 2 clock cycles, etc.
Example 5 and Example 6 illustrate how the timing of the multiword DMA registers can be programmed.
Example 5. Multiword DMA Register Access Programming for Mode 0
Programming multiword DMA transfers for mode 0 operation using an IDE controller clock frequency of66 MHZ (15 ns period).
For mode 0 operation, t
D
requires a minimum of 215 ns, this translates to a minimum of 15 clock cycles(15 cycles נ15 ns = 225 ns). The minimum requirement on t
KW
is 215 ns (for writes), this translates to aminimum of 15 clock cycles (15 cycles נ15 ns = 225 ns). The minimum requirement for t
0
is 480 ns, or32 clock cycles. This means DMASTB and DMARCVR can be programmed to any combinationequaling 32 (or more) clock cycles, with both DMASTB and DMARCVR specifying at least 15 clockcycles.
Sample programming values are DMASTB = Fh (16 clock cycles) and DMARCVR = Fh (16 clockcycles), or DMASTB = 10h (17 clock cycles) and DMARCVR = Eh (15 clock cycles). In addition, theminimum write data hold time specified is 20 ns, so the HWNHLD nP bits in MISCCTL should beprogrammed to a value of at least 2 clock cycles. A sample value is HWNHLD nP = 2h (3 clock cycles)providing enough hold time and margin and also covering the PIO and task file mode 0 timings.
Example 6. Multiword DMA Register Access Programming for Mode 2
Programming multiword DMA transfers for mode 2 operation using an IDE controller clock frequency of99 MHZ (10.10 ns period).
For mode 2 operation, t
D
requires a minimum of 70 ns, this translates to a minimum of 7 clock cycles (7cycles נ10.10 ns = 70.70 ns). The minimum requirement on t
KW
is 25 ns, this translates to a minimum of3 clock cycles (3 cycles נ10.10 ns = 30.30 ns). The minimum cycle time t
0
is 120 ns, or 12 clock cycles.This means that DMASTB and DMARCVR can be programmed to any combination equaling 12 (ormore) clock cycles, with DMASTB specifying at least 7 cycles and DMARCVR specifying at least3 cycles.
Sample programming values are DMASTB = 7h (8 clock cycles) and DMARCVR = 3h (4 clock cycles),or DMASTB = 8h (9 clock cycles) and DMARCVR = 2h (3 clock cycles). In addition, the minimum writedata hold time specified is 10 ns, so the HWNHLD nP bits in MISCCTL should be programmed to avalue of at least 1 clock cycle. A sample value is HWNHLD nP = 2h (3 clock cycles) providing enoughhold time and margin and also covering the PIO and task file mode 2 timings.
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2.5.1.4 Programming Ultra-DMA Register Accesses
Architecture
The UDMASTB, UDMATRP, and UDMATENV are used in reprogramming the timings for ultra-DMAtransfers. The required IDE timings parameters for ultra-DMA transfers are defined in the ATA/ATAPI-6specification.
The UDMASTB, UDMATRP, and UDMATENV can be programmed to match the parameters t
CYC
(cycletime), t
2CYCTYP
(two cycle time), t
RP
(ready-to-pause), and t
ENV
(time envelope).
The UDMASTB directly controls the number of clock cycles for the ultra-DMA strobe during ultra-DMAtransfers. This corresponds to the strobe width timing parameter, t
CYC
, which is (t
2CYCTYP
).
The UDMATRP defines the number of clock cycles for the ready-to-pause timing parameter, t
RP
.
The UDMATENV indicates the number of clock cycles for the timing envelope timing parameter, t
ENV
.
With knowledge of the IDE controller clock frequency, you can program the appropriate number of clockcycles to match the timing requirements. Note that the timing registers must be programmed with a valueone less than the desired number of clock cycles, so a value of 0 specifies 1 clock cycle, a value of 1specifies 2 clock cycles, etc.
Example 7 and Example 8 illustrate how the timing of the ultra-DMA registers can be programmed.
Example 7. Ultra-DMA Register Access Programming for Mode 5
Programming ultra-DMA transfers for mode 5 operation using an IDE controller clock frequency of99 MHZ (10.10 ns period).
For mode 5 operation, t
2CYC
is 40 ns (t
CYC
= 20 ns), this translates to a minimum of 2 clock cycles(2 cycles נ10.10 ns = 20.20 ns) per UDMA cycle. The requirement on t
RP
is 85 ns, this translates to aminimum of 9 clock cycles (9 cycles נ10 ns = 90.90 ns). t
ENV
has a minimum value of 20 ns and amaximum value of 50 ns, so this needs to be 2 to 5 clock cycles (2 נ10 ns = 20.20 ns to5צnbsp;10 ns = 50.50 ns).
Sample programming values are UDMASTB = 1h (2 clock cycles), UDMATRP = 8h (9 clock cycles),and UDMATENV = 2h (3 clock cycles).
Example 8. Ultra-DMA Register Access Programming for Mode 4
Programming ultra-DMA transfers for mode 4 operation using an IDE controller clock frequency of66 MHZ (15 ns period).
For mode 4 operation, t
2CYC
is 60 ns (t
CYC
= 30 ns), this translates to a minimum of 2 clock cycles(2 cycles נ15 ns = 30 ns) per UDMA cycle. The requirement on t
RP
is 100 ns, this translates to aminimum of 7 clock cycles (7 cycles נ15 ns = 105 ns). t
ENV
has a minimum value of 20 ns and amaximum value of 55 ns, so this needs to be 2 to 4 clock cycles (2 cycles נ15 ns = 30 ns to4 cycles צnbsp;15 ns = 60 ns).
Sample programming values are UDMASTB = 1h (2 clock cycles), UDMATRP = 6h (7 clock cycles),and UDMATENV = 2h (3 clock cycles).
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2.6 DMA and PIO Data Transaction Overview
2.6.1 DMA Controller and FIFO Operation
2.6.1.1 Physical Region Descriptors (PRDs)
Architecture
The IDE controller supports a dedicated DMA controller in order to handle DMA transfers between hostmemory and attached ATA/ATAPI device. This occurs for both multiword and ultra-DMA transfers duringDMA writes to and reads from the device. The DMA controller includes logic to manage the physicalregion descriptors (PRDs) that describe the DMA transfers, and controls a set of 32-bit wide FIFOs(256-byte read FIFO and 256-byte write FIFO resident within the IDE controller) to temporarily store datafor DMA transfers.
When pre-fetching and post-writing is enabled, the dedicated DMA controller also controls PIO sectorwrites and reads even though this is a PIO transaction. The internal FIFO is reused for these PIOtransfers to store the pre-fetch/post-write data. During PIO reads, the sector data is pre-fetched into theFIFO and then read out of the FIFO by firmware. During PIO write, the PIO write sector data is stored inthe FIFO and then eventually written out through the IDE interface to the device.
The DMA controller is the primary initiator for DMA transfers for both multiword and ultra-DMA read andwrite transfers. For any ATA DMA writes to the device, the DMA controller will initiate a read transfer fromhost memory to fill up its internal FIFO and then transfer the data out of the FIFO to the ATA device. ForATA DMA read transfers from the device to host/system memory, the DMA controller will initiate a readtransfer and read data from the ATA device into the internal FIFO and then transfer the data from theFIFO into host memory. The DMA controller makes use of the physical region descriptors to identify bufferlocations and sizes of data (in bytes) to be transferred for its data transaction.
The difference between multiword DMA and ultra-DMA transfers is mostly on the signaling part of thetransaction. For multiword DMA transactions, the host IDE controller is responsible for strobing data. Inaddition, a single word is transferred per strobe cycle. For ultra-DMA data transactions, data strobing ishandled by the entity that is sending the data. If the data transaction is a write to a disk, then the host IDEcontroller is responsible for strobing the data. However, if the data transaction is a read from a disk, thenthe attached device is responsible for strobing the data. In addition, during ultra-DMA transactions, oneword (2 bytes/word) is transferred for every edge of the strobe within a single strobe cycle increasing thethroughput.
The physical region descriptors (PRDs) define the physical memory regions that data is transferred from(when moving data from host memory to the ATA device) or transferred to (when moving data from theATA device to host memory). The DMA controller contains the logic and control for handling the physicalregion descriptors. When a DMA transfer is started, the DMA controller will issue a two-word burst to readthe first descriptor from memory. It then decodes and stores the byte transfer count and the source ortarget memory address, and then starts the DMA operation using the descriptor information. Once a PRDhas been completely processed by the DMA controller and the entire DMA transfer has completed, thenext PRD in the table will be fetched and processed. If all PRD entries have been processed, an interruptis generated.
The DMA interface is used to control data transfers to and from host memory and the FIFO internal to theIDE controller block. The DMA engine contains the bus master IDE control registers. These registers arethe primary IDE channel DMA control register (BMICP), the primary IDE channel DMA status register(BMISP), and the primary IDE channel DMA descriptor pointer register (BMIDTP).
The DMA engine interfaces to the DMA interface to the processor on one end and the IDE controllerinterface on the other. The IDE controller block strobes data into and out of the FIFO in the DMA engineblock, based on the setting of the read/write direction bit (DMADIR bit in BMICP).
The BMIDTP is the pointer to a physical region descriptor table in system memory. This descriptor tablecontains physical region descriptors, which describe areas of memory that are involved in the datatransfer. The descriptor table must be aligned on a 4-byte boundary and the table cannot cross a 64 KBboundary in memory.
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Memory Region Physical Base Address
PRDx word
byte 3
EOT
PRDx word
byte 2 byte 1 byte 0
0
0reserved Byte Count
Memory
Region
Architecture
The physical memory region to be transferred is described by a physical region descriptor (PRD). EachPRD entry is 8 bytes in length (Figure 2 and Table 3 ). The first 4 bytes specify the byte address of aphysical memory region; the next two bytes specify the count of the region in bytes (64K byte limit perregion). A value of zero in these two bytes indicates 64K. Bit 7 of the last byte indicates the end of thetable (EOT) when set to 1.
Figure 2. Physical Region Descriptor (PRD) Table Entry
Table 3. Description of Single Physical Region Descriptor (PRD) Table Entry
PRDx Word Bit Description
0 31-0 Memory region physical base address for PRDx (Must be 2-bytes aligned, even).1 31 End of descriptor table marker (last PRD marker).1 30-16 Reserved1 15-0 Byte count (must be even). A value of 0 implies 64 Kbytes size.
DMA activity is started when the host software sets the DMA start/stop bit (DMASTART bit in BMICP). TheDMA engine state machine starts fetching the first entry in the PRD table. Once the PRD is fetched, theDMA engine state machine starts moving data between system memory and the FIFO. If the end of table(EOT) bit is 0, a new PRD table entry is fetched when the current physical region data transfer iscomplete. Data transfer continues until the last block of data is moved and the EOT bit is set to 1.
By linking multiple PRDs where each PRD identifies a buffer within the reach of the dedicated ATA DMA,the IDE controller can perform a single transaction where data is read from (or written to) multiple (PRDentries) buffers allowing the realization of the scatter gather capability.
When all data transfers for the DMA command submitted to the device are complete, the ATA/ATAPIdevice asserts INTRQ (if enabled). The DMA channel waits until the last data words have been movedto/from system memory before setting the interrupt bit (and passing the interrupt to the host interrupthandler) and clearing the bus master IDE active bit (IDEACT bit in BMISP).
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2.6.1.2 DMA Driven Disk Write Transfer Operation
2.6.1.3 DMA Driven Disk Read Transfer Operation
Architecture
To perform an ATA DMA write operation to an attached ATA/ATAPI device, a physical descriptor region isprogrammed by firmware indicating a system memory address to transfer data from and the number ofbytes to transfer. The BMIDTP register is initialized with the start address of the first physical regiondescriptor. The DMA write command is then issued to the drive, and the DMA transfer starts whenfirmware programs the DMASTART bit in the primary IDE channel DMA control register (BMICP). Whenthe DMASTART bit is set, the DMA controller issues a two-word (8 bytes) request to read the first physicalregion descriptor (PRD) entry from memory. This information is stored and processed by the DMAcontroller to indicate where in memory to start reading data from and also the size of data (in bytes) totransfer to the device. The DMA controller will then read out the data from host/system memory in burstsstarting at the specified transfer address. Data read from the system memory is stored in the FIFO. TheDMA controller will issue consecutive read bursts until it fills the FIFO. The transfer will start up againwhen the IDE controller starts emptying out the FIFO and space is available in the FIFO. When the DMAfinishes processing the current PRD, based on the state of the EOT field of the current PRD, it will eitherfetch the next PRD or wait until the FIFO is fully empty to generate an interrupt (and also set theINTRSTAT bit in the primary IDE channel DMA status register, BMISP) and also clear the IDEACT bit inBMISP indicating the end of the transfer. The total data size entered within the PRD tables for a givenDMA transaction should be equal to the data size value entered via command. The combination of statusbit settings by the DMA controller and the attached device will allow you to identify the user entrycondition.
To perform an ATA DMA read operation from an attached ATA/ATAPI device, a physical descriptor regionis programmed by firmware indicating a system memory address to transfer the disk data to and thenumber of bytes to transfer. The BMIDTP register is initialized with the start address of the first physicalregion descriptor. The DMA read command is then issued to the drive, and the DMA transfer is startedwhen firmware programs the DMASTART bit in the primary IDE channel DMA control register (BMICP).When the DMASTART bit is set, the DMA controller first issues a two-word (8 bytes) request to read thefirst physical region descriptor (PRD) entry from memory. This information is stored and processed by theDMA controller to indicate where in memory to store the data read from the disk and also the size (inbytes) of data transfer. The IDE controller will facilitate the reception of data from the attached device andstore read data within the read FIFO. This occurs for both multiword and ultra-DMA writes. The IDEinterface control logic continues reading words from the ATA device and storing them into the FIFO. TheDMA controller routes read data to the system/host memory based on the PRD entries. This continuesuntil the size entered in the PRD is exhausted or the FIFO becomes empty. When enough data to fill allthe sizes noted within the PRD entries has been stored at the host/system memory, the DMA generatesan interrupt (also sets the INTRSTAT bit in the primary IDE channel DMA status register, BMISP) and alsoclears the IDEACT bit in BMISP indicating the end of the transfer. The total data size entered within thePRD tables for a given DMA transaction should be equal to the data size value entered via command. hecombination of status bit settings by the DMA controller and the attached device will allow you to identifythe user entry condition.
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