Texas Instruments TMS320DM646 Series User manual

TMS320DM646x DMSoCATA Controller
User's Guide
Literature Number: SPRUEQ3December 2007

2 SPRUEQ3 – December 2007Submit Documentation Feedback

Contents
Preface ............................................................................................................................... 51 Introduction ................................................................................................................ 71.1 Purpose of the Peripheral ....................................................................................... 71.2 Features ........................................................................................................... 71.3 Functional Block Diagram ....................................................................................... 81.4 Supported Use Cases ........................................................................................... 81.5 Industry Standard(s) Compliance .............................................................................. 91.6 Terminology Used in This Document .......................................................................... 92 Architecture ............................................................................................................... 92.1 Clock Control ..................................................................................................... 92.2 Signal Descriptions ............................................................................................. 102.3 Pin Multiplexing ................................................................................................. 122.4 Protocol Description(s) ......................................................................................... 122.5 General Architecture ........................................................................................... 132.6 DMA and PIO Data Transaction Overview .................................................................. 182.7 Attached Device Reset Considerations ...................................................................... 222.8 Initialization ...................................................................................................... 232.9 Interrupt Support ................................................................................................ 262.10 EDMA Event Support .......................................................................................... 292.11 Power Management ............................................................................................ 302.12 Emulation Considerations ..................................................................................... 303 Use Cases ................................................................................................................ 303.1 Interfacing to a Standard ATA/ATAPI Device ............................................................... 303.2 Interfacing to a Standard ATA/ATAPI Device Through a Level-Shifter .................................. 313.3 Interfacing to Compact Flash ................................................................................. 324 Registers .................................................................................................................. 344.1 Primary IDE Channel DMA Control Register (BMICP) .................................................... 354.2 Primary IDE Channel DMA Status Register (BMISP)...................................................... 364.3 Primary IDE Channel DMA Descriptor Table Pointer Register (BMIDTP) .............................. 374.4 Primary IDE Channel Timing Register (IDETIMP) ......................................................... 384.5 IDE Controller Status Register (IDESTAT) .................................................................. 394.6 Ultra-DMA Control Register (UDMACTL) ................................................................... 404.7 Miscellaneous Control Register (MISCCTL) ................................................................ 414.8 Task File Register Strobe Timing Register (REGSTB) .................................................... 424.9 Task File Register Recovery Timing Register (REGRCVR) .............................................. 434.10 Data Register Access PIO Strobe Timing Register (DATSTB) ........................................... 444.11 Data Register Access PIO Recovery Timing Register (DATRCVR) ..................................... 454.12 Multiword DMA Strobe Timing Register (DMASTB) ....................................................... 464.13 Multiword DMA Recovery Timing Register (DMARCVR).................................................. 474.14 Ultra-DMA Strobe Timing Register (UDMASTB) ........................................................... 484.15 Ultra-DMA Ready-to-Pause Timing Register (UDMATRP) ............................................... 494.16 Ultra-DMA Timing Envelope Register (UDMATENV) ...................................................... 504.17 Primary IO Ready Timer Configuration Register (IORDYTMP) .......................................... 51
SPRUEQ3 – December 2007 Table of Contents 3Submit Documentation Feedback

List of Figures
1 ATA Controller Block Diagram ............................................................................................. 82 Physical Region Descriptor (PRD) Table Entry ........................................................................ 193 Primary IDE Channel DMA Control Register (BMICP) ................................................................ 354 Primary IDE Channel DMA Status Register (BMISP) ................................................................. 365 Primary IDE Channel DMA Descriptor Table Pointer Register (BMIDTP) .......................................... 376 Primary IDE Channel Timing Register (IDETIMP) ..................................................................... 387 IDE Controller Status Register (IDESTAT) ............................................................................. 398 Ultra-DMA Control Register (UDMACTL) ............................................................................... 409 Miscellaneous Control Register (MISCCTL) ............................................................................ 4110 Task File Register Strobe Timing Register (REGSTB) ............................................................... 4211 Task File Register Recovery Timing Register (REGRCVR) .......................................................... 4312 Data Register Access PIO Strobe Timing Register (DATSTB) ...................................................... 4413 Data Register Access PIO Recovery Timing Register (DATRCVR) ................................................. 4514 Multiword DMA Strobe Timing Register (DMASTB) ................................................................... 4615 Multiword DMA Recovery Timing Register (DMARCVR) ............................................................. 4716 Ultra-DMA Strobe Timing Register (UDMASTB) ....................................................................... 4817 Ultra-DMA Ready-to-Pause Timing Register (UDMATRP) ........................................................... 4918 Ultra-DMA Timing Envelope Register (UDMATENV) .................................................................. 5019 Primary IO Ready Timer Configuration Register (IORDYTMP) ...................................................... 51
List of Tables
1 Supported ATA Controller Signals ....................................................................................... 102 Unsupported ATA Controller Signals .................................................................................... 123 Description of Single Physical Region Descriptor (PRD) Table Entry ............................................... 194 ATA Controller Interrupt ................................................................................................... 265 Identifying the ATA Controller Interrupt Sources ....................................................................... 276 DMA Driven Interrupt Conditions ......................................................................................... 297 ATA/ATAPI Device Interface Connections for a Standard ATA/ATAPI Device .................................... 308 ATA/ATAPI Device Interface Connections for a Standard ATA/ATAPI Device Through a Level-Shifter ....... 329 ATA/ATAPI Device Interface Connections for a Compact Flash Device ........................................... 3310 ATA Host Controller Registers ........................................................................................... 3411 ATA Controller Registers in the Attached Device ...................................................................... 3412 Primary IDE Channel DMA Control Register (BMICP) Field Descriptions .......................................... 3513 Primary IDE Channel DMA Status Register (BMISP) Field Descriptions ........................................... 3614 Primary IDE Channel DMA Descriptor Table Pointer Register (BMIDTP) Field Descriptions .................... 3715 Primary IDE Channel Timing Register (IDETIMP) Field Descriptions ............................................... 3816 IDE Controller Status Register (IDESTAT) Field Descriptions ....................................................... 3917 Ultra-DMA Control Register (UDMACTL) Field Descriptions ......................................................... 4018 Miscellaneous Control Register (MISCCTL) Field Descriptions ...................................................... 4119 Task File Register Strobe Timing Register (REGSTB) Field Descriptions ......................................... 4220 Task File Register Recovery Timing Register (REGRCVR) Field Descriptions .................................... 4321 Data Register Access PIO Strobe Timing Register (DATSTB) Field Descriptions ................................ 4422 Data Register Access PIO Recovery Timing Register (DATRCVR) Field Descriptions .......................... 4523 Multiword DMA Strobe Timing Register (DMASTB) Field Descriptions ............................................. 4624 Multiword DMA Recovery Timing Register (DMARCVR) Field Descriptions ....................................... 4725 Ultra-DMA Strobe Timing Register (UDMASTB) Field Descriptions ................................................. 4826 Ultra-DMA Ready-to-Pause Timing Register (UDMATRP) Field Descriptions ..................................... 4927 Ultra-DMA Timing Envelope Register (UDMATENV) Field Descriptions ........................................... 5028 Primary IO Ready Timer Configuration Register (IORDYTMP) Field Descriptions ................................ 51
4List of Figures SPRUEQ3 – December 2007Submit Documentation Feedback

PrefaceSPRUEQ3 – December 2007
Read This First
About This Manual
The AT attachment/ATA packet interface (ATA/ATAPI), also known as IDE controller, is the traditionalchoice of the communication medium between a portable computer (PC) and a hard-disk drive. Ever sinceits adoption by the industry, it has been the choice of interface between a PC and a common storagemedium. This standard interface provides a common attachment interface for system manufacturers,system integrators, software suppliers, and suppliers of intelligent storage devices.
Notational Conventions
This document uses the following conventions.•Hexadecimal numbers are shown with the suffix h. For example, the following number is 40hexadecimal (decimal 64): 40h.•Registers in this document are shown in figures and described in tables.– Each register figure shows a rectangle divided into fields that represent the fields of the register.Each field is labeled with its bit name, its beginning and ending bit numbers above, and itsread/write properties below. A legend explains the notation used for the properties.– Reserved bits in a register figure designate a bit that is used for future device expansion.
Related Documentation From Texas InstrumentsThe following documents describe the TMS320DM646x Digital Media System-on-Chip (DMSoC). Copiesof these documents are available on the Internet at www.ti.com .Tip: Enter the literature number in thesearch box provided at www.ti.com.
The current documentation that describes the DM646x DMSoC, related peripherals, and other technicalcollateral, is available in the C6000 DSP product folder at: www.ti.com/c6000 .
SPRUEP8 —TMS320DM646x DMSoC DSP Subsystem Reference Guide. Describes the digital signalprocessor (DSP) subsystem in the TMS320DM646x Digital Media System-on-Chip (DMSoC).
SPRUEP9 —TMS320DM646x DMSoC ARM Subsystem Reference Guide. Describes the ARMsubsystem in the TMS320DM646x Digital Media System-on-Chip (DMSoC). The ARM subsystem isdesigned to give the ARM926EJ-S (ARM9) master control of the device. In general, the ARM isresponsible for configuration and control of the device; including the DSP subsystem and a majorityof the peripherals and external memories.
SPRUEQ0 —TMS320DM646x DMSoC Peripherals Overview Reference Guide. Provides an overviewand briefly describes the peripherals available on the TMS320DM646x Digital MediaSystem-on-Chip (DMSoC).
SPRAA84 —TMS320C64x to TMS320C64x+ CPU Migration Guide. Describes migrating from theTexas Instruments TMS320C64x digital signal processor (DSP) to the TMS320C64x+ DSP. Theobjective of this document is to indicate differences between the two cores. Functionality in thedevices that is identical is not included.
SPRU732 —TMS320C64x/C64x+ DSP CPU and Instruction Set Reference Guide. Describes the CPUarchitecture, pipeline, instruction set, and interrupts for the TMS320C64x and TMS320C64x+ digitalsignal processors (DSPs) of the TMS320C6000 DSP family. The C64x/C64x+ DSP generationcomprises fixed-point devices in the C6000 DSP platform. The C64x+ DSP is an enhancement ofthe C64x DSP with added functionality and an expanded instruction set.
SPRUEQ3 – December 2007 Preface 5Submit Documentation Feedback

www.ti.com
Related Documentation From Texas Instruments
SPRU871 —TMS320C64x+ DSP Megamodule Reference Guide. Describes the TMS320C64x+ digitalsignal processor (DSP) megamodule. Included is a discussion on the internal direct memory access(IDMA) controller, the interrupt controller, the power-down controller, memory protection, bandwidthmanagement, and the memory and cache.
6Read This First SPRUEQ3 – December 2007Submit Documentation Feedback

1 Introduction
1.1 Purpose of the Peripheral
1.2 Features
User's GuideSPRUEQ3 – December 2007
ATA Controller
The AT attachment/ATA packet interface (ATA/ATAPI), also known as IDE controller, is the traditionalchoice of the communication medium between a portable computer (PC) and a hard-disk drive. Ever sinceits adoption by the industry, it has been the choice of interface between a PC and a common storagemedium. This standard interface provides a common attachment interface for system manufacturers,system integrators, software suppliers, and suppliers of intelligent storage devices.
This document describes the ATA controller on the TMS320DM646x Digital Media System-on-Chip(DMSoC). The ATA controller provides a glueless interface to storage media to be used by video andaudio applications for video and audio data storage.
The AT attachment/ATA packet interface (ATA/ATAPI) is an interface that is most commonly used by PCsand portable devices to interface a host processor with data storage or audio devices. The ATA interfacedebuted in the mid 1980s as an interface between a hard-disk drive and a PC by way of a ribbon cable.Ever since then, other devices, mostly storage, including compact Flash and compact disks have widelyadopted the ATA/ATAPI interface, leveraging from its proven capability as the means for connecting to ahost processor. These allowed device manufacturers to avoid developing and supporting a proprietaryinterface that would significantly limit the use of their devices. The ATA/ATAPI interface is popular due toits simplicity, low cost, reliability, compatibility, as well as its wide acceptance and long history of usewithin the PC industry market.
The DM646x DMSoC supports an onboard ATA/ATAPI host controller module (IDE controller) allowing itto exploit access to a vast majority of available data storage and audio devices. The onboard IDE hostcontroller performs PIO, multiword, and ultra-DMA transactions with ATA and ATAPI compliant devices.Hard-disk drive, compact disk (CD), compact Flash (CF), and DVD are members of ATA/ATAPI-compliantdevices that the IDE host controller is destined to interface with. This allows applications like streamingmedia and digital still cameras the means for easy access to commonly used external storage devices.
The content described here assumes the knowledge of ATA/ATAPI-6 and compact Flash v2.0specifications and should be used in conjunction with these documents.
The IDE host controller logic supports PIO, multiword DMA and ultra-DMA (ultra-ATA) modes. The ATAcontroller has the following features:•Single channel capable for connecting up to two ATA/ATAPI devices•Supports interface to compact Flash (CF) configured in True-IDE mode•Supports PIO modes 0, 1, 2, 3, and 4•Supports multiword DMA modes 0, 1, and 2•Supports ultra-DMA modes 0, 1, 2, 3, 4, and 5•Full scatter gather DMA capability•Programmable timing parameters provide support of any multiple ATA timing options mode at anyprocessor clock frequency
SPRUEQ3 – December 2007 ATA Controller 7Submit Documentation Feedback

www.ti.com
1.3 Functional Block Diagram
Peripheral
Interface
ATA_INTRQ
IDE Controller
Register File
Interrupt
DMA
Engine
DMA Read
FIFO
DMA Read
FIFO
ARM CPU
ARM
Interrupt
Controller
System
Memory
IDE Timing
Control
IDE Host
Interface
ATA_IORDY
ATA_DMARQ
ATA CS0
ATA_DMACK
ATA CS1
ATA_HA0
ATA_HIOR
ATA_D[15:0]
ATA_HIOW
ATA_DDIR
ATA_HA1
ATA_HA2
1.4 Supported Use Cases
Introduction
The ATA controller is shown in Figure 1 .
Figure 1. ATA Controller Block Diagram
The IDE controller is commonly used to interface to ATA and ATAPI devices. Devices like hard disk drivesare ATA devices. Devices like CDs, compact flash, and DVDs are ATAPI devices. Both ATA and ATAPIdevices use the same identical interface and differ partly in protocol (specifically the way command isdelivered to the attached device). This difference is transparent to the IDE host controller and meaningfulto the driver/firmware that is running on the host supporting the attached device. For ATA devices, allcommands and commands parameters are register-driven while ATAPI devices make use of bothregister-driven and packet-driven commands. Consult the ATA/ATAPI-6 specification for more information.
For information on how to interface to a standard ATA/ATAPI device, see Section 3.1 .
For information on how to interface to a standard ATA/ATAPI device with a higher I/O voltage requirementusing a level-shifter, see Section 3.2 .
For information on how to interface to a compact Flash (CF) device, see Section 3.3 .
ATA Controller8 SPRUEQ3 – December 2007Submit Documentation Feedback

www.ti.com
1.5 Industry Standard(s) Compliance
1.6 Terminology Used in This Document
2 Architecture
2.1 Clock Control
Architecture
The IDE controller supports the ATA/ATAPI-6 and compact Flash v2.0 specifications. The specific modesof operations (PIO, multiword, and ultra-DMA) depend on the frequency at which the IDE controlleroperates. For this reason, not all modes supported by the specification and device may be exercised if theclocking frequency to the IDE controller is low. The actual mode supported (subset of the ATA/ATAPIstandard) by the device is directly tied to the IDE controller clock sourcing. For more information on theclocking provided to the peripheral, see Section 2.1 . In addition to possible reduction of mode support dueto low frequency clocking, the processor does not pin out all the signals available in the ATA/ATAPIspecification. Additional signals (necessary to support wide range of devices) that are not present withinthe ATA/ATAPI standard specification are also available. See Section 2.2 for more information on thesignals supported on this peripheral.
The following is a brief explanation of some terms used in this document:
Term MeaningATA/ATAPI AT attachment/ATA packet interfaceATA controller ATA/ATAPI controller peripheralCF Compact Flashdevice External ATA/ATAPI device attached to the IDE controllerDMA DMA within the ATA controller, not the processor EDMA systemhost Processor IDE controller (this peripheral), unless otherwise specifiedIDE controller Synonymous with ATA controllerprocessor DM646x Digital Media Processor
This section discusses the architecture of the ATA controller.
The IDE controller uses a single programmable clock for its operation. This clock needs to be reconfiguredprior to enabling access to the attached ATA/ATAPI device. The maximum clock frequency supplied to theATA controller is dependent upon the clock frequency of the processor. See the device specific datamanual for more information on the processor voltage and speed characteristics.
SYSCLK4 (PLL0 output frequency divided by 6) is the source of the clock to the ATA peripheral. Toensure proper operation, the operating frequency of the ATA controller clock should be chosen in such away that it is at least twice as fast as the ATA data strobe frequency in order to achieve expectedthroughput.
SPRUEQ3 – December 2007 ATA Controller 9Submit Documentation Feedback

www.ti.com
2.2 Signal Descriptions
2.2.1 ATA/ATAPI Interface Signals Supported by the ATA Controller
Architecture
Table 1 describes the signals supported by the IDE controller interface.
Table 1. Supported ATA Controller Signals
Direction fromTerminal Name IDE Controller Description
ATA_CS0 Output Chip Select Signals 0 and 1ATA_CS1
These are the chip select signals from the host used to select the Command Block orControl Block registers. ATA_CS0 is asserted during Command Block registeraccesses. ATA_CS1 is asserted during Control Block register accesses. WhenATA_DMACK is asserted, ATA_CS0 and ATA_CS1 are both asserted and transferswill be 16 bits wide.ATA_HA0 Output Device Address Bits[2:0]ATA_HA1
This is a 3-bit binary coded address asserted by the host to access a register or dataATA_HA2
port in the attached device.ATA_D[15:0] Input/Output Host Read/Write Data BusThis is a 16-bit bi-directional data interface between the host and the device. Datatransfers are 16-bits wide except for CF devices that implement 8-bit data transfers. Inthis case, ATA_D[7:0] will be used for 8-bit register transfers.ATA_DMARQ Input Device DMA RequestThe device will assert this signal, used for DMA data transfers between host anddevice, when the device is ready to transfer data to or from the host in any of the DMAmodes. For multiword transfers, the direction of data transfer is controlled byATA_HIOR and ATA_HIOW. This signal is used in a handshake manner withATA_DMACK, that is, the device will wait until the host asserts ATA_DMACK beforenegating ATA_DMARQ, and re-asserting ATA_DMARQ if there is more data totransfer. For multiword DMA transfers, the ATA_DMARQ/ ATA_DMACK handshake isused to provide flow control during the transfer. For ultra-DMA, theATA_DMARQ/ ATA_DMACK handshake is used to indicate when the function ofinterface signals changes.This signal will be released when the device is not selected.ATA_DMACK Output Host DMA Acknowledge
This signal is used by the host in response to ATA_DMARQ to initiate DMA transfers.For multiword DMA transfers, the ATA_DMARQ/ ATA_DMACK handshake is used toprovide flow control during the transfer. For ultra-DMA, theATA_DMARQ/ ATA_DMACK handshake is used to indicate when the function ofinterface signals changes.When ATA_DMACK is asserted, ATA_CS0 and ATA_CS1 is not asserted andtransfers are 16 bits wide.ATA_IORDY Input Device I/O ready during PIO transactionDMA ready during ultra-DMA writeDMA strobe during ultra-DMA readATA_IORDY is negated to extend the host transfer cycle of any host register access(PIO 8-bit) or PIO data access when the device is not ready to respond to a transferrequest. If the device requires that the host transfer cycle time be extended, the devicewill assert the ATA_IORDY signal. Devices that support PIO modes 3 and above arerequired by the ATA/ATAPI specification to support ATA_IORDY.For ultra-DMA data-write transaction, this signal is a flow control signal for data-outbursts. This signal is asserted by the device to indicate to the host that the device isready to receive Ultra DMA data-out bursts. The device may negate ATA_IORDY topause an Ultra DMA data-out burst.For ultra-DMA data-read transaction, this signal is a data-in strobe signal from thedevice for data-in burst. Both the rising and falling edges of ATA_IORDY latch thedata from ATA_D[15:0] into the host. The device may stop generating ATA_IORDYedges to pause an ultra DMA data-in burst.This signal is released when the device is not selected.
ATA Controller10 SPRUEQ3 – December 2007Submit Documentation Feedback