Texas Instruments TPS59640EVM-751 User manual

User's Guide
SLUU796–January 2012
Using the TPS59640EVM-751 IMVP-7, 3-Phase
CPU/1-Phase GPU SVID Power System
The TPS59640EVM-751 evaluation module (EVM) is a complete solution for the Intel™IMVP-7 Serial VID
(SVID) Power System from a 9-V to 20-V input bus. This EVM uses the TPS59640 for IMVP-7 3-Phase
CPU and 1-Phase GPU Vcore, TPS51219 for 1.05VCCIO, TPS51916 for DDR3L/DDR4 memory rail
(1.2VDDQ, 0.6VTT, and 0.6VTTREF). The TPS59640EVM-751 also uses the 5-mm x 6-mm TI power
block MOSFET (CSD87350Q5D) for high-power density and superior thermal performance.
Contents
1 Description ................................................................................................................... 4
1.1 Typical Applications ................................................................................................ 4
1.2 Features ............................................................................................................. 4
2 TPS59640EVM-751 Power System Block Diagram .................................................................... 5
3 Electrical Performance Specifications .................................................................................... 6
4 Schematic .................................................................................................................... 8
5 Test Setup .................................................................................................................. 21
5.1 Test Equipment ................................................................................................... 21
5.2 Recommended Wire Gage ...................................................................................... 22
5.3 Recommended Test Setup ...................................................................................... 22
5.4 USB Cable Connections ......................................................................................... 23
5.5 Input Connections ................................................................................................ 23
5.6 Output Connections .............................................................................................. 24
6 Configuration ............................................................................................................... 24
6.1 CPU and GPU Configuration ................................................................................... 24
6.2 1.2VDDQ, 0.6V VTT and 0.6V VTTREF Configuration ...................................................... 27
6.3 1.05V VCCIO Configuration ..................................................................................... 27
7 Test Procedure ............................................................................................................ 28
7.1 Line/Load Regulation and Efficiency Measurement Procedure ............................................ 28
7.2 Equipment Shutdown ............................................................................................ 31
8 Performance Data and Typical Characteristic Curves ................................................................ 32
8.1 CPU3-Phase Operation .......................................................................................... 32
8.2 CPU 2-Phase Operation ......................................................................................... 36
8.3 CPU 1-Phase Operation ......................................................................................... 40
8.4 GPU Operation ................................................................................................... 44
8.5 1.05V VCCIO ...................................................................................................... 48
8.6 1.2 VDDQ .......................................................................................................... 51
9 EVM Assembly Drawings and PCB layout ............................................................................. 53
10 Bill of Materials ............................................................................................................. 59
List of Figures
1 TPS59640EVM-751 Power System Block Diagram.................................................................... 5
2 TPS59640EVM-751 EVM Illustration..................................................................................... 6
3 TPS59640EVM-751 Schematic (1 of 13)................................................................................ 8
4 TPS59640EVM-751 Schematic (2 of 13)................................................................................ 9
Intel is a trademark of Intel Corporation.
Windows is a trademark of Microsoft Corporation.
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5 TPS59640EVM-751 Schematic (3 of 13)............................................................................... 10
6 TPS59640EVM-751 Schematic (4 of 13)............................................................................... 11
7 TPS59640EVM-751 Schematic (5 of 13)............................................................................... 12
8 TPS59640EVM-751 Schematic (6 of 13)............................................................................... 13
9 TPS59640EVM-751 Schematic (7 of 13)............................................................................... 14
10 TPS59640EVM-751 Schematic (8 of 13)............................................................................... 15
11 TPS59640EVM-751 Schematic (9 of 13)............................................................................... 16
12 TPS59640EVM-751 Schematic (10 of 13) ............................................................................. 17
13 TPS59640EVM-751 Schematic (11 of 13) ............................................................................. 18
14 TPS59640EVM-751 Schematic (12 of 13) ............................................................................. 19
15 TPS59640EVM-751 Schematic (13 of 13) ............................................................................. 20
16 USB Cable.................................................................................................................. 21
17 TPS59640EVM-751 Recommended Test Setup...................................................................... 23
18 TPS59640EVM-751 CPU GUI Setup Window......................................................................... 29
19 TPS59640EVM-751 GPU GUI Setup Window ........................................................................ 30
20 CPU3 Efficiency ........................................................................................................... 32
21 CPU3 Load Regulation ................................................................................................... 32
22 CPU3 Enable Turnon ..................................................................................................... 32
23 CPU3 Enable Turnoff ..................................................................................................... 32
24 CPU3 Switching Node (Ripple) ......................................................................................... 32
25 CPU3 Dynamic VID: SetVID-Slow/Slow................................................................................ 32
26 CPU3 Dynamic VID:SetVID-Fast/Fast ................................................................................. 33
27 CPU3 Dynamic VID:SetVID-Decay/Fast ............................................................................... 33
28 CPU3 Output Load Insertion With OSR/USR20k (Min) ............................................................. 33
29 CPU3 Output Load Release With OSR/USR 20k (Min).............................................................. 33
30 CPU3 Bode Plot at 12Vin, 1.05 V/60 A................................................................................. 34
31 CPU3 MOSFET ........................................................................................................... 34
32 CPU3 IC .................................................................................................................... 34
33 CPU2 Efficiency ........................................................................................................... 36
34 CPU2 Load Regulation ................................................................................................... 36
35 CPU2 Enable Turnon .................................................................................................... 36
36 CPU2 Enable Turnoff .................................................................................................... 36
37 CPU2 Switching Node (Ripple) ......................................................................................... 36
38 CPU2 Dynamic VID: SetVID-Slow/Slow................................................................................ 36
39 CPU2 Dynamic VID: SetVID-Fast/Fast ................................................................................ 37
40 CPU2 Dynamic VID: SetVID-Decay/Fast .............................................................................. 37
41 CPU2 Output Load Insertion With OSR/USR 20k (Min) ............................................................. 37
42 CPU2 Output Load Release With OSR/USR 20k (Min) ............................................................. 37
43 CPU2 Bode Plot at 12Vin, 1.05 V/55 A................................................................................. 38
44 CPU2 MOSFET ........................................................................................................... 38
45 CPU2 IC .................................................................................................................... 38
46 CPU1 Efficiency ........................................................................................................... 40
47 CPU1 Load Regulation ................................................................................................... 40
48 CPU1 Enable Turnon .................................................................................................... 40
49 CPU1 Enable Turnoff .................................................................................................... 40
50 CPU1 Switching Node ................................................................................................... 40
51 CPU1 Switching Node and Ripple ...................................................................................... 40
52 CPU1 Dynamic VID: SetVID-Slow/Slow ............................................................................... 41
53 CPU1 Dynamic VID: SetVID-Fast/Fast ................................................................................ 41
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54 CPU1 Dynamic VID: SetVID-Decay/Fast .............................................................................. 41
55 CPU1 Output Load Insertion With OSR/USR 20k (Min) ............................................................. 41
56 CPU1 Output Load Release With OSR/USR 20k (Min) ............................................................. 42
57 CPU1 Bode Plot at 12Vin, 1.05 V/33 A................................................................................. 43
58 CPU1 MOSFET ........................................................................................................... 43
59 CPU1 IC .................................................................................................................... 43
60 GPU Efficiency ............................................................................................................ 44
61 GPU Load Regulation..................................................................................................... 44
62 GPU Enable Turnon ...................................................................................................... 44
63 GPU Enable Turnoff ...................................................................................................... 44
64 GPU Switching Node ..................................................................................................... 44
65 GPU Switching Node and Ripple........................................................................................ 44
66 GPU Dynamic VID: SetVID-Slow/Slow ................................................................................ 45
67 GPU Dynamic VID: SetVID-Fast/Fast ................................................................................. 45
68 GPU Dynamic VID: SetVID-Decay/Fast ............................................................................... 45
69 GPU Output Load Insertion With OSR/USR 20k (Min) .............................................................. 45
70 GPU Output Load Release With OSR/USR 20k (Min) .............................................................. 46
71 GPU Bode Plot at 12Vin, 1.23 V/33 A.................................................................................. 47
72 GPU MOSFET ............................................................................................................ 47
73 GPU IC...................................................................................................................... 47
74 1.05-V Efficiency .......................................................................................................... 48
75 1.05-V Load Regulation .................................................................................................. 48
76 1.05-V Enable Turnon .................................................................................................... 48
77 1.05-V Enable Turnoff .................................................................................................... 48
78 1.05-V Switching Node ................................................................................................... 48
79 1.05-V Ripple............................................................................................................... 48
80 1.05-V Transient DCM to CCM ......................................................................................... 49
81 1.05-V Transient CCM to DCM.......................................................................................... 49
82 TPS51219 Thermal........................................................................................................ 49
83 1.2-V Efficiency ........................................................................................................... 51
84 1.2-V Load Regulation.................................................................................................... 51
85 1.2-V Enable Turnon ..................................................................................................... 51
86 1.2-V Enable Turnoff ..................................................................................................... 51
87 1.2-V Switching Node .................................................................................................... 51
88 1.2-V Ripple................................................................................................................ 51
89 1.2-V Transient DCM to CCM ........................................................................................... 52
90 1.2-V Transient CCM to DCM ........................................................................................... 52
91 TPS51916 Thermal........................................................................................................ 52
92 TPS59640EVM-751 Top Layer Assembly Drawing (Top View)..................................................... 53
93 TPS59640EVM-751 Bottom Assembly Drawing (Bottom View)..................................................... 54
94 TPS59640EVM-751 Top Copper ....................................................................................... 54
95 TPS59640EVM-751 Bottom Copper ................................................................................... 55
96 TPS59640EVM-751 Internal Layer 2 .................................................................................. 55
97 TPS59640EVM-751 Internal Layer 3 .................................................................................. 56
98 TPS59640EVM-751 Internal Layer 4 .................................................................................. 56
99 TPS59640EVM-751 Internal Layer 5 ................................................................................... 57
100 TPS59640EVM-751 Internal Layer 6 ................................................................................... 57
101 TPS59640EVM-751 Internal Layer 7 ................................................................................... 58
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Description www.ti.com
List of Tables
1 TPS59640EVM-751 Electrical Performance Specifications........................................................... 6
2 Current Limit Trip Selection.............................................................................................. 24
3 CPU Frequency Selection................................................................................................ 25
4 GPU Frequency Selection................................................................................................ 25
5 GPU Overshoot/Undershoot Reduction Selection .................................................................... 25
6 GPU Overshoot/Undershoot Reduction Selection .................................................................... 26
7 F2806 DSP Program Mode Selection .................................................................................. 26
8 F2806 DSP Program Mode Selection .................................................................................. 26
9 Onboard Dynamic Load Selection ...................................................................................... 26
10 VR_ON Enable Selection................................................................................................. 27
11 VDDQ S3, S5 Enable Selection ........................................................................................ 27
12 VCCIO Output Voltage Selection ....................................................................................... 27
13 Bill of Materials............................................................................................................. 59
1 Description
The TPS59640EVM-751 evaluation module is designed to use a 9-V to 20-V input bus to produce six
regulated outputs for the IMVP-7 SVID CPU/GPU Power System. The TPS59640EVM-751 is specially
designed to demonstrate the TPS59640 full IMVP-7 mobile feature while providing a GUI communication
program and a number of test points to evaluate the static and dynamic performance of the TPS59640.
1.1 Typical Applications
•IMVP-7 Vcore applications for adapter, battery, NVDC, or 3-V/5-V/12-V rails
1.2 Features
The TPS59640EVM-751 features:
•Complete solution for 9-V to 20-V input Intel IMVP-7 SVID Power System
•GUI communication to demonstrate full IMVP-7 mobile feature
•Three-phase CPU Vcore can support up to 94-A output current
•One-Phase GPU Vcore can support up to 33-A output current
•Eight selectable switching frequencies for CPU and GPU power
•Eight levels selectable current limit for CPU and GPU power
•Eight levels selectable output overshoot/undershoot reduction (OSR/USR™) for CPU and GPU power
•Switches or jumpers for each output enable
•Onboard dynamic load for CPU, GPU Vcore and VCCIO output
•High efficiency and high density by using TI power block MOSFET
•Convenient test points for probing critical waveforms
•Eight-layer PCB with 2-oz copper
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9-20VBAT CPU Core
(94A)
GPU Core
(33A)
Power Block
IMVP7
TPS59640
48 Pin
6x6 QFN
TPS51219
16 Pin
3x3 QFN VCCIO: 1.05V/15A
TPS70102PWP
20 Pin
PWP
TPS51916
20 Pin
3x3 QFN
TMS320F2806PZS
TUSB3410RHB
VCCIO: 0A-10A
VDDQ: 1.2V/15A
VTT: 0.6V/2A,
VTTREF: 0.6V/10mA
1.8V/500mA
GPU: 0A-19A
On Board Dynamic
Load for CPU, GPU
and VCCIO
CPU: 0A-32A
SVID
5Vin 3.3V/250mA
Host Computer
B
USB Cable
A
GUI communication
DDR3L/DDR4 Memory Rail
www.ti.com TPS59640EVM-751 Power System Block Diagram
2 TPS59640EVM-751 Power System Block Diagram
Figure 1. TPS59640EVM-751 Power System Block Diagram
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IMVP7 TPS59640 + TPS51219 + TPS51916 POWER EVM with
CSD87350Q5D Powerblocks
CPU Core
GPU CORE
TPS51219
VCCIO
TPS59640
Sandy Bridge
CPU socket (not
populated)
OCL, FSW,
OSR selection
TPS51916
DDR3L/DDR4
Memory Rail
Intel SVID GUI
from USB
CPU/GPU
VR_ON
Connections
for electronic
loads CSD87350Q5D
Electrical Performance Specifications www.ti.com
Figure 2. TPS59640EVM-751 EVM Illustration
3 Electrical Performance Specifications
Table 1. TPS59640EVM-751 Electrical Performance Specifications
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
INPUT CHARACTERISTICS
12VBAT input voltage range VBAT 9 12 20 V
Maximum input current VBAT = 12 V, all full load (3-Phase CPU/1-Phase GPU) 16.2 A
No-load input current VBAT=12 V, all no load(3-Phase CPU/1-Phase GPU) 0.1 A
5VIN input voltage range Vin = 5 V 4.5 5 5.5 V
Maximum input current VBAT =12 V, all full load 0.3 A
No-load input current VBAT=12 V, all no load 0.1 A
OUTPUT CHARACTERISTICS
CPU (TPS59640)
Output voltage Vcore SVID: address:00 CPU, payload: 1.05 V 1.05 V
Line regulation 0.1%
Output voltage regulation Load regulation(droop) load line –1.9 mΩ
Output voltage ripple VBAT=12 V, 1.05 V/90 A (3-Phase) at 300 kHz 25 mVpp
Output load current CPU 3-Phase operation 0 94 A
Output over current Selectable per phase 37 A
Switching frequency Selectable 250 300 600 kHz
Full load efficiency VBAT=12 V, 1.05 V/94 A at 300 kHz 80.05%
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www.ti.com Electrical Performance Specifications
Table 1. TPS59640EVM-751 Electrical Performance Specifications (continued)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
GPU (TPS59640)
Output voltage Vcore SVID: address:01 GPU, payload: 1.23 V 1.23 V
Line regulation 0.1%
Output voltage regulation Load regulation (droop) load line –3.9 mΩ
Output voltage ripple VBAT = 12 V, 1.23 V/35 A at 385 kHz 30 mVpp
Output load current CPU 3-Phase operation 0 35 A
Output over current Selectable per phase 37 A
Switching frequency Selectable 275 385 660 kHz
Full load efficiency VBAT = 12 V, 1.23 V/35 A at 385 kHz 81.99%
1.05-V VCCIO (TPS51219)
Output voltage 1.05 V
Output voltage regulation Line regulation 0.1%
Load regulation 0.1%
Output voltage ripple VBAT =12 V, 1.05 V/15 A 30 mVpp
Output load current 0 15 A
Output over current 24 A
Switching frequency Selectable 500 kHz
Full load efficiency VBAT = 12 V, 1.05 V/15 A 89.27%
DDR3L/DDR4 MEMORY RAIL (TPS51916)
Output voltage 1.2 V
Line regulation 0.1%
Output voltage regulation Load regulation 0.1%
Output voltage ripple VBAT = 12 V, 1.2 V/15 A 30 mVpp
Output load current 0 15 A
Output over current 24 A
Switching frequency Selectable 500 kHz
Full-load efficiency VBAT = 12 V, 1.2 V/15 A 90.62%
Operating temperature 25 °C
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5
9
8
7
6
5 4
3
2
1
1
1
1
7
6
8 9
1
1
1
1
2
3
1
Notused
TP19
C28
220nF
R21
200k
TP17
C16
0.33uF
R7
42.2k
R4
130
R5
TP7
C14
100pF
54.9
R3
1
C27
TP18
R25
4
TP5
TP8
C15
2.21
R15
2.21
R11
R2
10
R19
2.21
C17
1uF
TP6
R13
0
TP12
C25
R10
+C18
470uF
+
470uF
C21
TP10
C26
100pF
8.45k
R6
TP1
R1
71.5k
15.4k
R8
TP2
C3
4.7uF
R9
2.21
TP13
C4
10uF
R12
0
TP15
C6
10uF
TP11
R18
10uF
C7
C22
10uF
C9
10uF
C11C13
1nF
R24
309kR26
0
RT2
100k
15.4k
R23
4.12k
R22
169k
R14
C23
1uF
C1
220nF
TP16
C24
1uF
100k
RT1
2.2uF
C2
0.36uH
L2
TP4
TP3
TP14
+C20
470uF
TP9
150k
R16R17
10.0k
R20
10uF
C5
10uF
C8
10uF
C10
0.36uH
L1
C12
1nF
GPUOSR/USRselection:Seesheet5
CPUOSR/USRselection:Seesheet5
GPUOCPselection:Sees
heet5
CPUOCPselection:Seesheet5
GPUSwitchingfrequencyselection:Sees
heet5
CPUSwitc
hingfrequencyselection:Seesheet5
CPUthridphase:Seesheet2
GPUphase:Seesheet3
+C19
470uF
CPUandGPUControl,1stand2ndPhaseCPUVCORE
TPS59640RSL
Schematic www.ti.com
Note: Jumpers set to default locations; see Section 6 of this user’s guide.
4 Schematic
Figure 3. TPS59640EVM-751 Schematic (1 of 13)
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11
1
1
1
1
1
1 11
TP24
22uF
C39
C54
22uF
C41
22uF
C55
22uF
22uF
C42
22uF
C57
C38
2.2uF
22uF
C44
22uF
C58 22uF
C45
10uF
C60
R30
0
22uF
C47
10uF
C61 10uF
C48
10uF
C63 1
C50
10uF
C64
1
TP22
22uF
C51
10uF
C66
1
22uF
C52
10uF
C29 C30
10uF
C34
1uF
10uF
C32 C33
1nF
+
C35
+
C36
C40
22uF
22uF
C53
22uF
C56
TP25
TP21
TP20
Not
used
C43
22uF 10uF
C46
1
0uF
C59
10uF
C62
TP26
C49
10uF
C65
C37
0.36 u
H
L3
C31
10uF
R27
2.21 2.21
R28
TP23
CPU 3 rd Phase
VCORE
R29
www.ti.com Schematic
Figure 4. TPS59640EVM-751 Schematic (2 of 13)
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1
11
1
1
1
1
11
1
1
TP33
1
C77
TP28
C78
1
C80
2.2uF
C76
22uF
C81
TP30
C82
22uF
TP35
Notused
C83
22uF
TP31
0.36uH
L4
C67
10uF
22uF
C89
C68
10uF
C90
22uF
10uF
C70
C91
1nF
C71
R31
2.21
C94
R34
0
22uF
C95
22uF
C96
C75 R32
C79
1uF
C73
R33
2.21
TP34 TP29
22uF
C84
GPUVCORE
GND_PWR
22uF
C85
22uF
C86
TP36
+
330uF
C72
+
330uF
C74
TP32
22uF
C87
22uF
C88
C69
10uF
C92C93
Schematic www.ti.com
Figure 5. TPS59640EVM-751 Schematic (3 of 13)
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1
11
1
1
1
1
1
1
1
11
1
1
1
1
1
10
10
1
1 1
1
1
1
Tocontroller
R65
17.8k
R62
162k
R50
162k
17.8k
R35
R38
162k
C106
33nF
33nF
C102
R70
0
R66
0
1
1
R36
0
1
C109
1
1
TP45
TP43
TP41
TP39
R58
R46
R37
Notused
R59
10
R53
10
R57
0R60
0
R54
R42
0
R68
162k
17.8k
R44
R55
17.8k
C110
33nF
C98
33nF
1
C107
C111
C99
C103
TP44
TP40
TP42
TP38
R40
10
R47
10
R43
0R48
RT6
100k
RT5
100k
RT4
100k
0
R41
100k
RT3
R67
C105
C101
C97
R61
Toprocessor
J13Tocontroller
J14
R63 28.7kR64
0
R69
28.7k
R39
28.7k
R45
0
28.7k
R51
R52
0
R56
0
C108 C112
C100
C104
ToprocessorJ15
R49
J16
CPUandGPUVCORE:
CurrentSenseFeedbackandDifferentialVoltageFeedback
AphasecanbedisabledbypullingthecorrespondingxCSPxpinto3.3V.
DefaultsettingforCPU:3phaseoperation
DafaultsettingforGPU:1phaseoperation
Phasedisablecanbedoneinreverseorder.Phase3,then2,then1.
1.CPU3Phaseoperation:R37,R46,R58open
2.CPU2Phaseoperation:R58used0ohm
3.CPU1Phaseoperation:R46used0ohmandConnectedCSP3toGND
4.DisableGPU,R67used0ohm
www.ti.com Schematic
Figure 6. TPS59640EVM-751 Schematic (4 of 13)
11
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11
13 12
11
12 13
TP46
TP47
R117
20.0k
R108
39.2k
R99
100k R98
100k
R89
24.3k
R80
56.2k
R71
150k
R102
75.0k
R105
56.2k
R111
30.1k
R114
24.3k
R96
150k
R93
20.0k
R75
100k
R78
75.0k
R81
56.2k
R84
39.2k
R87
30.1k
Over-Shoot /Under-Shoot Reduction Selection:
1. CPU OSR/USR Default Setting: Jumper shorts on pin1 and pin2 to set Max
2. GPU OSR/USR Default Setting: Jumper shorts on pin1 and pin2 to set Max
R101
75.0k
R104
56.2k
R107
39.2k
R110
30.1k
R113
24.3k
R95
150k
R92
20.0k
R74
100k
R77
75.0k
R83
39.2k
R86
30.1k
R72
150k
R90
24.3k
R116
20.0k
Level 8 (MAX)
Level 7
Level 6
Level 5
Level 4
Level 3
Level 2
Level 1 (MIN)
Level 8 (MAX OS)
Level 7
Level 6
Level 5
Level 4
Level 3
Level 2
Level 1 (MIN OS)
Level 8 (MAX)
Level 7
Level 6
Level 5
Level 4
Level 3
Level 2
Level 1 (MIN)
Level 8 (MAX OS)
Level 7
Level 6
Level 5
Level 4
Level 3
Level 2
Level 1 (MIN OS)
R112
30.1k
R103
75.0k
R88
30.1k
R79
75.0k
Switching Frequency Selection:
1. CPU Switching Frequency Default Setting: Jumper shorts on pin13 and pin14 to set 300kHz
2. GPU Switching Frequency Default Setting: Jumper shorts on pin 11 and pin12 to set 385kHz
R118
20.0k
R100
100k
R106
56.2k
R109
39.2k
R91
24.3k
R94
20.0k
R73
150k
R76
100k
R82
56.2k
R85
39.2k
SWITCHING FREQUENCY SELECTION OVER-CURRENT PROTECTION SELECTION OVER-SHOOT/UNDER-SHOOT REDUCTION
Over Current Protection Selection:
1. CPU O ver Current Protection Per Phase Default Setting: Jumper shorts on pin 7 and pin 8 to set 40A
2. GPU Over Current Protection Default Setting: Jumper short s on pin7 and pin8 to set 40A
Frequenc y, OCP, OSR/USR SELECTIONS
R115
24.3k
600kHz (MAX)
550kHz
500kHz
450kHz
400kHz
350kHz
300kHz
250kHz (MIN)
R97
150k
660kHz (MAX)
605kHz
550kHz
495kHz
440kHz
385kHz
330kHz
275kHz (MIN)
Schematic www.ti.com
Figure 7. TPS59640EVM-751 Schematic (5 of 13)
12 Using the TPS59640EVM-751 IMVP-7, 3-Phase CPU/1-Phase GPU SVID SLUU796–January 2012
Power System Submit Documentation Feedback
Copyright ©2012, Texas Instruments Incorporated

15
1
14
1
15
111
11
1
1
11
14
1
1
Not used
R135
10
10
R132
TP53
R123
1.00k
C125
0.01uF
TP51
TP48
1
C148
2.2uF
C127
C150
1
TP56
2.21
R125
1
C126
TP50
R128
10.5k
0.1uF
C119
C124
1nF
TP49
J25
C120
0. 1uF
C128
22uF
22uF
C146
C115
10uF
C130
C144
22uF
C131 C118
1nF
C142
22uF
C134
R127
C139
TP55
+
C123
+C121
330uF
S1: VCCIO Enable Pin
To processor
0
R134
R122
10.0k
R119
180 R120
180
C147 C149
To controller
0
R131
R124
2.21
TP52
R121
1.00k
C113
1nF
VCCIO Power Supply
R129
0
0.56uH
L5
R133
0
D2
GREEN
Q5
BSS123 Q6
BSS123
R126
C129
C143
22uF
R130
37.4k
10uF
C114 C116
10uF
C132
22uF
C133
22uF
C135
22uF
C137
22uF
C138
22uF
C141
22uF
C145
TP57
C117
10uF
TP54
C136
C140
22uF
+
330uF
C122
VCCIO Output Selection:
1. Jumper shorts on pin1 and pin2 of J23 to set VCCIO: 1.05V(Default)
2. Jumper shorts on pin2 and pin3 of J23 to set VCCIO: 1.00V
D1
GREEN
www.ti.com Schematic
Figure 8. TPS59640EVM-751 Schematic (6 of 13)
13
SLUU796–January 2012 Using the TPS59640EVM-751 IMVP-7, 3-Phase CPU/1-Phase GPU SVID
Power System
Submit Documentation Feedback Copyright ©2012, Texas Instruments Incorporated

11
1
1
1
1
11
R 148
0
R 150
0
R136
180
TP60
16
R149
20.0k
R147
10.0k
C176
1nF
C156
0.1uF
R138
10.0k
16
C 162
2.2uF
TP61
T P67
R 143
2.21
T P59 T P58
C161
TP63
1
10uF
C157
R137
10.0k
TP70
37.4k
R141
2.21
R142
C174
C166
10uF
C151
10uF
C171 C153
10uF
C169
C155
1nF
R144
TP68
+
330uF
C158 +C159
To controller
J29
C164
0.1uF
0. 22uF
C163
D3
GREEN
Not used
S3/S5 Enable Control, See datasheet for detail
R139
10.0k
VDDQ Power Supply
R145
0
L6
0.56uH
TP62
C160
2.2uF
Q8
BSS123
R146
0
R140
1. 00k
C165
10uF 10uF
C167 C168
10uF
10uF
C170 C172
10uF
C173
C175
C152
10uF
C154
10uF
CSD87350Q5D
Q9
Schematic www.ti.com
Figure 9. TPS59640EVM-751 Schematic (7 of 13)
14 Using the TPS59640EVM-751 IMVP-7, 3-Phase CPU/1-Phase GPU SVID SLUU796–January 2012
Power System Submit Documentation Feedback
Copyright ©2012, Texas Instruments Incorporated

1
17
1
1
17
R170
8. 06k
C192
0.1uF
10.0k
R171
TP73
TP82
TP75 TP72
D8
RED
R152
100k
1uF
C190
TP86
3.3V LDO
R175
0.005
0.05
R168
R155
30.1k
R151
15.0k
R169
0.05
C177
10uF
TP84
0.1uF
C182
R172
0. 005
R162
0.01
100k
R173
TP77
+C179
1
R159
TP78
10.0k
R174
TP74
TP79
C181
10uF
330
R176
RED
D5
R178
330
R179
330
2.2uF
C184
0.05
R166
30.1k
R154
0.01
R167
TP71
R164
0.05
10.0k
R165
Q10
CSD16407Q5
1.8V LDO
C189
0.01uF C191
0.1uF
5V Bias Voltage Input
VBAT Voltage Input:
9V- 20V
U8:C
U8:B C188
1uF
Not used
D4
RED
CSD16407Q5
Q12
CSD16407Q5
Q13
C183
10uF R157
1
C187
1uF
TP83
0.01
R161
C193
0.1uF
D6
BAT54
+C178
1
R158
1
R160
TP80
D7
RED
330
R177
U8:D
U8:A
CD74HCT08D
UCC27324D
U9
UCC27324D
U10
C194
1uF
VCCIO, GPU and CPU Dynamic Load:
1. Switch to "ON" position to enable the Dynamic Load
2. Switch to "OFF" position to disable the Dynamic Load (Default )
C180
0. 1uF
C185
0.1uF
TP85
C186
0.01uF
R156
51.1k TP76
TP81
R153
2. 00k
0.05
R163
VCCIO_DL
GPU_DL
CPU_DL1
CPU_DL2
Q11
CSD16407Q5
150mA LDO
LDOs and Dynamic Loads
1.2V LDO
S2
5
OUT
4
NR/FB
1IN 3EN 2GND
U7
TPS71712DCK
S3
3VIN1 2VIN1
7SEQUENCE 8GND 9VIN2
10 VIN2
1NC
11
NC
12
VOU T2
13
VOU T2
14
VSENSE2
16
PG D_1
17
VSENSE1
18
VOU T1
19
VOU T1
20
N C
Pw rPad
4MR2 5MR1 6ENA BLE 1 5
RESET
TPS70102PWP
U6
www.ti.com Schematic
Figure 10. TPS59640EVM-751 Schematic (8 of 13)
15
SLUU796–January 2012 Using the TPS59640EVM-751 IMVP-7, 3-Phase CPU/1-Phase GPU SVID
Power System
Submit Documentation Feedback Copyright ©2012, Texas Instruments Incorporated

1
18
1
1
1
111
VR_ON
1
1
R203
180
TP87
R204
180
TP90 TP89
18
R207
1. 00k
1
C200
1uF
1
D9
GREEN
Q15
BSS123
C195
1nF
R186
100
3. 01k
R193
J33
R187
10.0k
10pF
C198
R201
10.0k
TP88
G_PGOOD
1M
R195
R191 0
R188 1M R182 1M
C_PGOOD
R206
10.0k
TPS59640 Default Trim
R117=not used, R116 = 1.00k J35
Not used
VR_HOT
R205
180
J45, J46 are not used and they are for internal I2C connection
C196
0.1uF
Jumper to enter
I2C Mode
Support and Pull-ups
R199
330
R200
1. 00k
1M
R196
0
R197
0
R198
10.0k
R194
1M
R189
0
R190
R180 1M 10.0k
R181
D10
GREEN
Q16
BSS123
R185
D11
RED
D12
GREEN
Q14
BSS83P
Q17
BSS123
10.0k
R202
R208
10.0k
R209
180
C197
10pF
3.01k
R192
0.1uF
C199
1M
R183
1M
R184
To I2C Terminal
Logic Signal and Status LED's
LED is ON when the logic signal is in the ACTIVE state
J 32 , J34 are Labview co nn ectors for E VM t est ing
S4: I MVP-7 VR Enable:
1. Switch to "O N" position to E nable TPS59640 controller
2. Switch to "OFF" position to Disable TPS59640 controller(Default )
Schematic www.ti.com
Figure 11. TPS59640EVM-751 Schematic (9 of 13)
16 Using the TPS59640EVM-751 IMVP-7, 3-Phase CPU/1-Phase GPU SVID SLUU796–January 2012
Power System Submit Documentation Feedback
Copyright ©2012, Texas Instruments Incorporated

1
1Not used
R211
75.0
1
R210 R212
130
uC Socket Main
R213 43.2
www.ti.com Schematic
Figure 12. TPS59640EVM-751 Schematic (10 of 13)
17
SLUU796–January 2012 Using the TPS59640EVM-751 IMVP-7, 3-Phase CPU/1-Phase GPU SVID
Power System
Submit Documentation Feedback Copyright ©2012, Texas Instruments Incorporated

1
1Not used
uC Socket Others
Schematic www.ti.com
Figure 13. TPS59640EVM-751 Schematic (11 of 13)
18 Using the TPS59640EVM-751 IMVP-7, 3-Phase CPU/1-Phase GPU SVID SLUU796–January 2012
Power System Submit Documentation Feedback
Copyright ©2012, Texas Instruments Incorporated

1
19
1
11
20 20
R221
475
D13
GREEN
19
TP91 TP92
Not used
C206
22pF
TP94
0.01uF
C207
J41
1.50k
R214
TP93
2
1
Y1
For Internal software developmenet
USB Connector
33.2
R216
C208
0.01uF
C205
22pF
0
R219
R217
10.0k
C203 C204
J43
R222
2.21k
FB1
NC
V+
DP
DM
V-
J42
33.2
R215
C201
0.1uF
C202
0.1uF
R218
10.0k
USB to DSP
R220
0
5V Bias option:
1. Jumper shorts on J41, 5V Bias used from USB. If USB 5V is used, external 5V supply from J31 should not be used.
2. No Jumper shorts on J41, 5V Bias used from external J31 (Default)
TUSB3410RHB
U14
www.ti.com Schematic
Figure 14. TPS59640EVM-751 Schematic (12 of 13)
19
SLUU796–January 2012 Using the TPS59640EVM-751 IMVP-7, 3-Phase CPU/1-Phase GPU SVID
Power System
Submit Documentation Feedback Copyright ©2012, Texas Instruments Incorporated

1
23
22
1
21
1
23
23
C211
0.1uF
C212
0.1uF
C213
0.1uF0.1uF
C214C215
0.1uF
C209
0.1uF
21
R227
2.74k
1
X1
R224
2.00k
C216
0.1uF
Notused
22
0.1uF
C218
0.1uF
C219
TP96
C221
0.1uF
TP97
C226
1uF
SPISOMI
C222
0.1uF
23
J44
C224
R226
475
TP95
0.1uF
C223
J45
R223
2.00k
C210
0.1uF
R225
2.00k
0.1uF
C217
DSPtoSVID
J47
34
U18:B
C225
1uF
D14
GREEN34
U16:B
C220
0.1uF
60GPIO8 53GPIO5
45GPIO2
56GPIO6 58GPIO7
47GPIO0 44GPIO1 48GPIO3
51GPIO4
8GPIO14
70GPIO11
57
GPIO19
71
GPIO22
91
GPIO25
92
GPIO28
7
GPIO31
43
GPIO34
1GPIO12
95GPIO13
9GPIO15
61GPIO9
54
GPIO18
63
GPIO20
67
GPIO21
83
GPIO24
99
GPIO26
79
GPIO27
6
GPIO30
100
GPIO32
5
GPIO33
64GPIO10 50GPIO1652
GPIO17
72
GPIO23
4
GPIO29
TMS320F2806PZS
U15:A
39VSS2AGND 12VDD1A18 14VSSA2 13VSS1AGND 40VDD2A18 10VDD 15VDDA2 26VDDAIO 25VSSAIO
65VDDIO 93VDD
59VDD
82
VDDIO
41
VSS
62
VSS
87
VSS
84
TRST
73
TDI
68VDD 85VDD
3VDDIO
46VDDIO
42VDD
2
VSS
11
VSS
49
VSS
55
VSS
69
VSS
77
VSS
89
VSS
94
VSS
75
TCK
74
TMS
76
TDO
TMS320F2806PZS
U15:B
C227
J46
J48
16
5
2
U18:A
5B1 2OE 1DIR2 3GND 4B26
VCCB
9
A2
7
VCCA
8
A1
10
DIR1
SN74AVC2T245RSW
U17
19ADCINA4 16ADCINA7 88X1 98TEST2 81EMU1
22
ADCINA1
33
ADCINB6
30
ADCINB3
27
ADCINB0
35
ADCREFIN
17ADCINA6 18ADCINA5 20ADCINA3 66XCLKOUT 90XCLKIN 86X2 80EMU0 96VDD3VFL
21
ADCINA2
23
ADCINA0
34
ADCINB7
31
ADCINB4
29
ADCINB2
28
ADCINB1
38
ADCRESEXT
37
ADCREFP
36
ADCREFM
78XRS 97TEST1
32
ADCINB5
24
ADCLO
TMS320F2806PZS
U15:C
DifferentialProbeTestPoint
LevelShiftingTranceiverndOpenDrainBuffersforDSPtoSVIDTranslation
J46:F2806DSPProgramModeSelection:
1.JumpershortsforF2806DSPProgramMode
2.NoJumpershortsfornormaloperation(Default)
GUIandIntelVRTTToolSelection:
1.JumpershortstouseIntelVRTTTool(Notused)
2.NoJumpershortstouserGUI(Default)
16
5
2
U16:A
SN74LVC2G07DCK
Schematic www.ti.com
Figure 15. TPS59640EVM-751 Schematic (13 of 13)
20 Using the TPS59640EVM-751 IMVP-7, 3-Phase CPU/1-Phase GPU SVID SLUU796–January 2012
Power System Submit Documentation Feedback
Copyright ©2012, Texas Instruments Incorporated