Texas Instruments TMS320C6457 User manual

TMS320C6457 DSPPower/Sleep Controller (PSC)
User's Guide
Literature Number: SPRUGL4March 2009

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Contents
Preface ........................................................................................................................................ 51 Introduction/Feature Overview ............................................................................................... 61.1 Purpose of the Peripheral ................................................................................................ 61.2 Features .................................................................................................................... 61.3 Terms and Abbreviations ................................................................................................ 62 Power/Sleep Controller ......................................................................................................... 72.1 Power and Reset Domains .............................................................................................. 72.2 Power Domain and Module States Defined ........................................................................... 82.2.1 Power Domain States ........................................................................................ 82.2.2 Module States ................................................................................................. 92.2.3 Local Reset .................................................................................................... 92.3 Executing State Transitions .............................................................................................. 92.3.1 Power Domain State Transitions ........................................................................... 92.3.2 Module State Transitions................................................................................... 102.3.3 Concurrent Power Domain/Module State Transitions .................................................. 102.3.4 Recommendations for Power Domain/Module Sequencing ........................................... 112.4 Emulation Support in the PSC ......................................................................................... 113 PSC Registers .................................................................................................................... 123.1 Power and Sleep Controller (PSC) Register Map ................................................................... 123.2 Register Descriptions ................................................................................................... 133.2.1 Peripheral Identification Register (PID) ................................................................. 133.2.2 Power Domain Transition Command Register (PTCMD) .............................................. 143.2.3 Power Domain Transition Status Register (PTSTAT) .................................................. 153.2.4 Power Domain Status Register 0-4 (PDSTATx) ........................................................ 153.2.5 Power Domain Control Register 0-4 (PDCTLx) ......................................................... 163.2.6 Module Status Register 0-10 (MDSTATy) ............................................................... 173.2.7 Module Control Register 0-10 (MDCTLy) ................................................................ 18
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List of Figures
1 Power and Clock Domains ................................................................................................. 72 Peripheral Identification Register (PID) .................................................................................. 133 Power Domain Transition Command Register (PTCMD) ............................................................. 144 Power Domain Transition Status Register (PTSTAT) ................................................................. 155 Power Domain Status Register 0-4 (PDSTATx) ....................................................................... 156 Power Domain Control Register 0-4 (PDCTLx) ........................................................................ 167 Module Status Register 0-10 (MDSTATy) .............................................................................. 178 Module Control Register 0-10 (MDCTLy) ............................................................................... 18
List of Tables
1 C6457 Power Domains ..................................................................................................... 82 C6457 Clock Domains ...................................................................................................... 83 Module States ................................................................................................................ 94 PSC Register Memory Map ............................................................................................... 125 Peripheral Identification Register (PID) Field Descriptions ........................................................... 136 Power Domain Transition Command Register (PTCMD) Field Descriptions ....................................... 147 Power Domain Transition Status Register (PTSTAT) Field Descriptions ........................................... 158 Power Domain Status Register 0-4 (PDSTATx) Field Descriptions ................................................. 159 Power Domain Control Register 0-4 (PDCTLx) Field Descriptions .................................................. 1610 Module Status Register 0-10 (MDSTATy) Field Descriptions ........................................................ 1711 Module Control Register 0-10 (MDCTLy) Field Descriptions ......................................................... 18
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PrefaceSPRUGL4 – March 2009
Read This First
About This Manual
The TMS320C6457 device is single-core DSP platform architected primarily for the communicationsinfrastructure market. This document covers the usage of the Power/Sleep Controller (PSC) inTMS320C6457 device.
Notational Conventions
This document uses the following conventions.•Hexadecimal numbers are shown with the suffix h. For example, the following number is 40hexadecimal (decimal 64): 40h.•Registers in this document are shown in figures and described in tables.– Each register figure shows a rectangle divided into fields that represent the fields of the register.Each field is labeled with its bit name, its beginning and ending bit numbers above, and itsread/write properties below. A legend explains the notation used for the properties.– Reserved bits in a register figure designate a bit that is used for future device expansion.
Related Documentation From Texas InstrumentsThe following documents describe the TMS320C6457 DSP. Copies of these documents are available onthe Internet at www.ti.com .Tip: Enter the literature number in the search box provided at www.ti.com.
SPRU189 —TMS320C6000 DSP CPU and Instruction Set Reference Guide. Describes the CPUarchitecture, pipeline, instruction set, and interrupts for the TMS320C6000 digital signal processors(DSPs).
SPRU198 —TMS320C6000 Programmer's Guide. Describes ways to optimize C and assembly code forthe TMS320C6000™ DSPs and includes application program examples.
SPRU301 —TMS320C6000 Code Composer Studio Tutorial. Introduces the Code Composer Studio™integrated development environment and software tools.
SPRU321 —Code Composer Studio Application Programming Interface Reference Guide.Describes the Code Composer Studio™ application programming interface (API), which allows youto program custom plug-ins for Code Composer.
SPRU871 —TMS320C64x+ Megamodule Reference Guide. Describes the TMS320C64x+ digital signalprocessor (DSP) megamodule. Included is a discussion on the internal direct memory access(IDMA) controller, the interrupt controller, the power-down controller, memory protection, bandwidthmanagement, and the memory and cache.Trademarks
TMS320C6000, Code Composer Studio are trademarks of Texas Instruments.
All other trademarks are the property of their respective owners.
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1 Introduction/Feature Overview
1.1 Purpose of the Peripheral
1.2 Features
1.3 Terms and Abbreviations
User's GuideSPRUGL4 – March 2009
TMS320C6457 DSP Power/Sleep Controller (PSC)
The TMS320C6457 device is single-core DSP platform architected primarily for the communicationsinfrastructure market. This document covers the usage of the Power/Sleep Controller (PSC) in theTMS320C6457 device. The intent is not to keep this document as a user's guide, but to actually add thisto the TMS320C6457 data manual, once it is available.
The purpose of the PSC is to reduce power when a module is not being utilized. In the TMS320C6457system, the PSC is responsible for managing transitions of clock on/off and memory sleep on/off. ThePSC provides the user with an interface to control several important power and clock operations. Theseoperations are the focus of this document.
The PSC includes the following features:•Provides software interface to:– Control module memory sleep on/off.– Control module clock on/off.– Control CPU local resets.•Supports emulation features: power, clock, and reset.
3GPP — Third-Generation Partnership Project
CPU — Central Processing Unit of the C64x+ Core
DSP — Digital Signal Processor
GPSC — Global Power/Sleep Controller; manages the LPSCs.
LPSC — Local Power/Sleep Controller; one per module.
PSC — Power/Sleep Controller, including one GPSC and multiple LPSCs
RAC — Receive Accelerator, including GCCP cores, FEI, and BEI
TCP — Turbo Coprocessor
VCP — Viterbi Coprocessor
WCDMA — Wideband Code Division Multiple Access
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2 Power/Sleep Controller
2.1 Power and Reset Domains
Clock Domain 1
C64x+
AlwaysOn
Power Domain 0
Clock Domain 6
(Never Gated)
Proxied
Power Domain 1
SRIO
Clock Domain 0
Reserved
DDR.PLLC
Main.PLLC
LPSC0
sysclk1_po
sysclk2_po
sysclk3_po
bpsysclk_po
Global PSC
sysclkn_pi
chip_0_early_rst_pi_n
por_pi_n
Chip
Configuration
Module
rail_gnt_A
iso_ctl_A
rail_gnt_B
iso_ctl_B
rail_gnt_C
iso_ctl_C
rail_gnt_D
iso_ctl_D Proxied
Power Domain 2
TCP2_0
Proxied
Power Domain 3
TCP2_1
Proxied
Power Domain 4
VCP2
sysclk1_po
sysclk2_po
sysclkn_po
chip_1_rst_po_n
chip_0_rst_po_n
chip_0_early_rst_po_n
chip_1_rst_po_n
chip_0_rst_po_n
chip_0_early_rst_po_n
sysclkn
LPSC1
LPSC2
LPSC3
LPSC4
LPSC5
(Shared LPSC)
LPSC6
LPSC7
LPSC8
LPSC9
LPSC10
DDR
EMIF EMAC
McBSP1
Timer1
I2C
McBSP0
Timer0
GPIO
SCRs, bridges and
other non-power
managed modules
Clock Domain 3
HPI
Clock Domain 2
EMIF64
Clock Domain 6
DEBUGSS
Clock Domain 4
UTOPIA
Clock Domain 8
TCP2_0
Clock Domain 7
SRIO
Clock Domain 10
VCP2
Clock Domain 9
TCP2_1
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The C6457 device comprises several power domains to enable minimizing power dissipation for unusedlogic on the device. The GPSC is used to control sleep for memories within each power domain.
Additionally, clock gating to each of the logic blocks is managed by the LPSCs of each module. Formodules with a dedicated clock or multiple clocks, the LPSC communicates with the PLL controller toenable and disable that module's clock(s) at the source. For modules that share a clock with othermodules, the LPSC controls the clock gating.
Figure 1 shows the PSC components and the power and clock domains they control. Many modulesreside in the AlwaysOn domain, that always has power and clocks provided. These consist primarily of theinfrastructure components that are responsible for the clock and reset control (PLL Controller, PSC), theswitch fabric that connects all of the modules, and small modules that do not need dynamic enable/disablebecause they do not consume a significant amount of power.
Figure 1. Power and Clock Domains
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2.2 Power Domain and Module States Defined
2.2.1 Power Domain States
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Table 1 summarizes the C6457 power domains.
Table 1. C6457 Power Domains
Domain Block(s) Note Power Connection
AlwaysOn Core, L1/L2 RAMs L2 RAMs can sleep , contents Software power-down from the CPUmaintainedAlwaysOn Most peripheral logic Cannot be disabled Always onAlwaysOn I/O: All 1.8-/3.3-V LVCMOS I/O, Cannot be disabled Always onmost peripheralsA RapidIO RAMs can sleep , contents Software controlmaintainedB TCP2_0 RAMs can sleep , contents Software controlmaintainedC TCP2_1 RAMs can sleep , contents Software controlmaintainedD VCP2 RAMs can sleep , contents Software controlmaintained
Table 2 summarizes the C6457 clock domains. These may also be referred to later in the document asmodules.
Table 2. C6457 Clock Domains
LPSC Number Module(s) Notes
0 Reserved1 CPU Cannot be controlled; always on2 EMIF64 Software control3 HPI Software control4 UTOPIA Software control5 Shared LPSC for all modules other than those Cannot be controlled; always onlisted in this table.6 DEBUGSS Software control7 SRIO Software control8 TCP2_0 Software control9 TCP2_1 Software control10 VCP2 Software controlNo LPSC Bootcfg, PSC, Main PLLCTL, Efuse, and DFT. These modules do not use LPSC.
The PSC module organizes modules into different power domains and into different modules (clockdomains). Note that there is no relationship between a power domain and a module. These are completelyseparate entities and may be controlled separately.
A power domain can only be in one of two states: ON or OFF, defined as follows:•ON: Power to the power domain is on. Memories are awake.•OFF: Power to the power domain is off. Memories are asleep (low-leakage standby mode).
In the C6457 device, the AlwaysOn power domain is always in the ON state, when the chip is powered on.The other power domains, however, can be in either the ON or OFF state; i.e., the memory for a specificmodule can remain powered down if it is not used.
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2.2.2 Module States
2.2.3 Local Reset
2.3 Executing State Transitions
2.3.1 Power Domain State Transitions
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A module can be in one of two states: Enable or SwRstDisable. As shown in Table 3 , these two statescorrespond to combinations of module reset asserted or de-asserted and module clock on or off. Note thatmodule reset is defined to completely reset a given module, such that all hardware is put back into itsdefault state. For more information on module reset, see Curie Chip Architecture (XXXX-SYS-FS-001)Revision XXXX.
Table 3. Module States
Module State Module Reset Module Clock
Enable De-asserted ONSwRstDisable Asserted OFF
The module states are defined as follows:•Enable: A module in the Enable state has its module reset de-asserted and its clock on. This is thenormal run-time state for a given module.•SwRstDisable: A module in the SwResetDisable state has its module reset asserted and its clockOFF. This state is not expected to be initiated by software.
In addition to module reset described in the previous section, the C64x+ CPU can be reset using a speciallocal reset. When local reset is asserted, the internal memories (L1P, L1D, and L2) for the core are stillaccessible. The local reset only resets the corresponding C64x+ core, not the rest of the chip. Local resetis intended to be used by the watchdog timers to reset the C64x+ core in the event of an error. Theprocedures for asserting and de-asserting local reset are as follows (Y denotes the module domainnumber):
•Set MDCTL[Y].LRSTZ to 0x0 to assert local reset.•Set MDCTL[Y].LRSTZ to 0x1 to de-assert local reset. The 64x+ core immediately executes programinstructions after reset is de-asserted. Note that the boot sequence does not re-occur unless there is achip-level reset. Execution of code previously in L2 begins execution.
This section describes how to execute state transitions for power domains and modules. Examples showhow to enable only power domains, only modules, or a combination. Although you have complete controlof the sequencing, for TI recommendations, see Section 2.3.4 .
This section describes the basic procedure for transitioning the state of a power domain which, in the caseof the C6457 device is limited to the memories located in a particular domain. The majority of the moduleson the chip are always in the ON state. The PSC handles all required internal operations to wakememories for the controlled power domains.
Note: As mentioned previously, in the C6457 device there are multiple power domains. TheAlwaysOn power domain is always in the ON state when the chip is powered-on, andtherefore it is not possible to transition this domain to the OFF state. Conversely, the otherdomains are in the OFF states when the chip is powered-on. Transitions from ON to OFF arenever allowed.
The procedure for power domain state transitions follows (X denotes the power domain number, Ydenotes the module domain number):•Wait for PTSTAT.GOSTAT[X] to clear to 0x0. Wait for any previously initiated transitions to finishbefore initiating a new transition.
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2.3.2 Module State Transitions
2.3.3 Concurrent Power Domain/Module State Transitions
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•Set PDCTL[X].NEXT for an ON (0x1) transition. Note: When PTCMD.GO[X] is set to 0x1 in the nextstep, the PDCTL[X].NEXT field of this power domain and the MDCTL[Y].NEXT field of the module inthis power domain are evaluated. Therefore, you may set the MDCTL[Y].NEXT field for multiplemodules before executing this step. Note that, if enabling other modules, ensure that if they are not inthe AlwaysOn domain, the memories for that module are not asleep.•Set PTCMD.GO[X] to 0x1 to initiate the state transition(s). The PSC awakens the memory for thatparticular domain.•Wait for PTSTAT.GOSTAT[X] to clear to 0x0. The domain is safely in the new state only afterPTSTAT.GOSTAT[X] is cleared to 0x0.
This section describes the procedure for transitioning the module state.
Note: In the C6457 device, the following procedure is directly applicable for all LPSC-controlledmodules, except the C64x+ core domains. To transition the module state, you must be awareof several system considerations. Transitions from Enable to any other state are not allowed.Also, before transitioning a module to Enable, if the memories are not in the AlwaysOnpower domain, they must be turned on before or in parallel with the transition. SeeSection 2.3.1 .
The procedure for module state transitions follows (X denotes the power domain number, Y denotes themodule domain number):•Wait for PTSTAT.GOSTAT[X] to clear to 0x0. Wait for any previously initiated transitions to finishbefore initiating a new transition.•Set MDCTL[Y].NEXT to Enable (0x3). Note that you may set transitions in multiple MDCTL[Y].NEXTfields in this step as long as the corresponding power domain is on.•Set PTCMD.GO[X] to 0x1 to initiate the transition(s).•Wait for PTSTAT.GOSTAT[X] to clear to 0x0. The module is safely in the new state only afterPTSTAT.GOSTAT[X] clears to 0x0.
This section describes the basic procedure for transitioning the state of a power domain and moduledomain for modules which are not in the AlwaysOn domain. You may do these separately as described inthe sections above, if desired.
The procedure for concurrent power domain/module state transitions follows (X denotes the power domainnumber, Y denotes the module domain number):•Wait for PTSTAT.GOSTAT[X] to clear to 0x0. Wait for any previously initiated transitions to finishbefore initiating a new transition.•Set PDCTL[X].NEXT for an ON (0x1) transition.•Set MDCTL[Y].NEXT to Enable (0x3). Note that you may set transitions in multiple MDCTL.NEXTfields in this step as long as the corresponding power domain is on.•Set PTCMD.GO[X] 0x1 to initiate the state transition(s). The PSC awakens the memory for thatparticular domain, starts the module clock, then de-asserts the module reset.•Wait for PTSTAT.GOSTAT[X] to clear to 0x0. The domain is safely in the new state only afterPTSTAT.GOSTAT[X] is cleared to 0x0.
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2.3.4 Recommendations for Power Domain/Module Sequencing
2.4 Emulation Support in the PSC
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As noted in Section 2.2 and Section 2.3 , a particular peripheral's power domain must be enabled beforethe module is enabled.
Unless there is a system level reason to perform both functions separate from each other, therecommendation is to use the sequence listed in Section 2.3.3 rather than individual sequencing. Eventhough a single write to the appropriate GO bit starts the power domain and module transition, it is stillsequenced such that the memory is guaranteed to awaken before the module is enabled. Thus, there isno ill effect in performing these together.
It is important to know that when a power domain is enabled that all memories for that module areimmediately moved from a low-leakage sleep state to an active awake state. This means that there will bea spike in power consumption for that particular time, in other words di/dt will be affected. To minimize theeffect on di/dt of enabling power domains, it is recommended to power up modules one at a time. It is alsorecommended that all modules be initialized early in the application to avoid a large spike in di/dt duringnormal operation where the application may already be drawing a fair amount of current from the supply.
The PSC supports commands that allow emulation tools to have some control over the state of powerdomains and modules.
In particular, the PSC supports the following emulation commands:•Power on and enable features:–Force Power: Allows emulation to force the power domain into and ON state.–Force Active: Allows emulation to force the power domain into and ON state and force the moduleinto the Enable state.•Reset features:
–Assert Reset: Allows emulation to assert the module's local reset.–Wait Reset: Allows emulation to keep local reset asserted for an extended period of time aftersoftware initiates local reset de-assert.–Block Reset: Allows emulation to block software initiated local and module resets.
Local reset applies only to the C64x+ core domains; module reset applies to all other domains.
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3 PSC Registers
3.1 Power and Sleep Controller (PSC) Register Map
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This section includes the PSC memory map and bit registers.
This section includes the PSC memory map and bit registers. Table 4 provides the PSC register memorymap.
Table 4. PSC Register Memory Map
Offset Register Description See
0x0 PID Peripheral Revision and Class Information Section 3.2.10x014 - Reserved0x120 PTCMD Power Domain Transition Command Register Section 3.2.20x128 PTSTAT Power Domain Transition Status Register Section 3.2.30x200 PDSTATx Power Domain Status Register 0-5 Section 3.2.40x300 PDCTL0 Power Domain Control Register 0 (AlwaysOn) Section 3.2.50x304 PDCTL1 Power Domain Control Register 1 (Serial RapidIO) Section 3.2.50x308 PDCTL2 Power Domain Control Register 2 (TCP2_0) Section 3.2.50x30C PDCTL3 Power Domain Control Register 3 (TCP2_1) Section 3.2.50x310 PDCTL4 Power Domain Control Register 4 (VCP2) Section 3.2.50x800 MDSTAT0 Module Status Register 0 ( Reserved) Section 3.2.60x804 MDSTAT1 Module Status Register 1 (C64x+ Core) Section 3.2.60x808 MDSTAT2 Module Status Register 2 (EMIF64) Section 3.2.60x80C MDSTAT3 Module Status Register 3 (HPI) Section 3.2.60x810 MDSTAT4 Module Status Register 4 (UTOPIA) Section 3.2.60x814 MDSTAT5 Module Status Register 5 (Never Gated) Section 3.2.60x818 MDSTAT6 Module Status Register 6 (DEBUGSS) Section 3.2.60x81C MDSTAT7 Module Status Register 7 (Serial RapidIO) Section 3.2.60x820 MDSTAT8 Module Status Register 8 (TCP2_0) Section 3.2.60x824 MDSTAT9 Module Status Register 9 (TCP2_1) Section 3.2.60x828 MDSTAT10 Module Status Register 10 (VCP2) Section 3.2.60xA00 MDCTL0 Module Control Register 0 ( Reserved) Section 3.2.70xA04 MDCTL1 Module Control Register 1 (C64x+ Core) Section 3.2.70xA08 MDCTL2 Module Control Register 2 (EMIF64) Section 3.2.70xA0C MDCTL3 Module Control Register 3 (HPI) Section 3.2.70xA10 MDCTL4 Module Control Register 4 (UTOPIA) Section 3.2.70xA14 MDCTL5 Module Control Register 5 (Never Gated) Section 3.2.70xA18 MDCTL6 Module Control Register 6 (DEBUGSS) Section 3.2.70xA1C MDCTL7 Module Control Register 7 (Serial RapidIO) Section 3.2.70xA20 MDCTL8 Module Control Register 8 (TCP2_0) Section 3.2.70xA24 MDCTL9 Module Control Register 9 (TCP2_1) Section 3.2.70xA28 MDCTL10 Module Control Register 10 (VCP2) Section 3.2.7
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3.2 Register Descriptions
3.2.1 Peripheral Identification Register (PID)
www.ti.com PSC Registers
This section describes, in detail, the module registers with a register figure and a description table foreach. Each register figure identifies the bit field, the register name, read/write capability, and the default.
The peripheral identification register is shown in Figure 2 and described in Table 5 . The PID offset is 0.
Figure 2. Peripheral Identification Register (PID)
31 0PIDR-0x44823A00
LEGEND:R = Read only; - n= value after reset
Table 5. Peripheral Identification Register (PID) Field Descriptions
Bit Field Value Description
31-0 PID Peripheral ID used to differentiate different modules in the system
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3.2.2 Power Domain Transition Command Register (PTCMD)
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The power domain transition command register is shown in Figure 3 and described in Table 6 .
Figure 3. Power Domain Transition Command Register (PTCMD)
31 5 4 0Reserved GO[X]R-0 W-0
LEGEND: R = Read only; W = Write only; - n= value after reset
Table 6. Power Domain Transition Command Register (PTCMD) Field Descriptions
Bit Field Value Description
31-5 Reserved Reserved4-0 GO[X] Power domain GO transition command (X denotes power domain number).1 Write 1 to cause the state transition interrupt generation block to evaluate the new PTNEXT andMDCTL.NEXT states as the application desired states.
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3.2.3 Power Domain Transition Status Register (PTSTAT)
3.2.4 Power Domain Status Register 0-4 (PDSTATx)
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The power domain transition status register is shown in Figure 4 and described in Table 7 . PSTST offsetis 0x128.
Figure 4. Power Domain Transition Status Register (PTSTAT)
31 5 4 0Reserved GOSTAT[X]R-0 R-0
LEGEND: R = Read only; - n= value after reset
Table 7. Power Domain Transition Status Register (PTSTAT) Field Descriptions
Bit Field Value Description
31-5 Reserved Reserved4-0 GOSTAT[X] Power domain transition status (X denotes power domain number).0 No transition in progress.1 Power domain is transitioning (i.e., either the power domain is transitioning or modules in this powerdomain are transitioning).
The power domain status register 0-4 is shown in Figure 5 and described in Table 8 . PDSTAT[X] offset is0x200.
Figure 5. Power Domain Status Register 0-4 (PDSTATx)
31 16Reserved
R-0
15 10 9 8 7 2 1 0
Reserved Rsvd Reserved STATER-0 R-1 R-0 R
(A)
LEGEND: R = Read only; - n= value after resetA. Default value after reset: AlwaysOn domain -1; other domains -0.
Table 8. Power Domain Status Register 0-4 (PDSTATx) Field Descriptions
Bit Field Value Description
31-2 Reserved Reserved1-0 STATE Power domain status0 Power Domain is in the OFF state.1 ower Domain is in the ON state.
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3.2.5 Power Domain Control Register 0-4 (PDCTLx)
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The power domain control register 0-4 is shown in Figure 6 and described in Table 9 . PDSTAT[X] offset is0x300 - 0x310.
Figure 6. Power Domain Control Register 0-4 (PDCTLx)
31 30 29 28 27 24 23 16Rsvd Rsvd Reserved Reserved ReservedR/W-0 R-0 R/W-0 R-0 R/W
(A)
15 12 11 10 9 8 7 1 0
Reserved Reserved Reserved Reserved NEXTR/W
(B)
R-0 RW-0 R-0 R/W
(C)
LEGEND: R/W = Read/Write; R = Read only; - n= value after resetA. Default value after reset: AlwaysOn domain -0x01; other domains -0x33.B. Default value after reset: AlwaysOn domain -0xB; other domains -0x8.C. Default value after reset: AlwaysOn domain -1; other domains -0.
Table 9. Power Domain Control Register 0-4 (PDCTLx) Field Descriptions
Bit Field Value Description
31-1 Reserved Reserved0 NEXT Power domain next state0 Power domain off.1 Power domain on.Others Indicates transition.
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3.2.6 Module Status Register 0-10 (MDSTATy)
www.ti.com PSC Registers
The module status register 0-10 is shown in Figure 7 and described in Table 10 . MDSTAT[Y] offset is0x800 - 0x828.
Figure 7. Module Status Register 0-10 (MDSTATy)
31 16Reserved
R-0
15 13 12 11 10 9 8
Reserved MCKOUT MRSTDON MRST LRSTDONE LRSTR-0 R
(A)
R-1 R
(A)
R
(B)
R
(A)
7 6 5 0
Reserved STATER-0 R
(C)
LEGEND: R = Read only; - n= value after resetA. Default value after reset: C64x+ domain and Never-Gated domain -1; other domains -0.B. Default value after reset: C64x+ domain -0; other domains -1.C. Default value after reset: C64x+ domain and Never-Gated domain -0x3; other domains -0.
Table 10. Module Status Register 0-10 (MDSTATy) Field Descriptions
Bit Field Value Description
31-13 Reserved Reserved12 MCKOUT Module clock output status. Shows status of module clock; on/off.0 Module clock is off.1 Module clock is on.11 MRSTDONE Module reset done. Software is responsible for checking that mode reset is done before accessingthe module.0 Module reset is not done.1 Module reset is done.10 MRST Module reset status. Reflects actual state of module reset.0 Module reset is asserted.1 Module reset is de-asserted.9 LRSTDONE Local reset done. Software is responsible for checking that local reset is done before accessing thismodule.
0 Local reset is not done.1 Local reset is done.8 LRST Module local reset status. (This bit applies to C64x+ domains only.)0 Local reset is asserted.1 Local reset is de-asserted.7-6 Reserved Reserved5-0 STATE Module state status. Indicates current module status.0 SwRstDisable state.0x3 Enable state.Others Reserved.
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3.2.7 Module Control Register 0-10 (MDCTLy)
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The module control register 0-10 is shown in Figure 8 and described in Table 11 . MDCTL[Y] offset is0xA00 - 0xA28.
Figure 8. Module Control Register 0-10 (MDCTLy)
31 30 16Rsvd ReservedR/W-0 R-0
15 13 12 9 8 7 5 4 0
Reserved Reserved LRST Reserved NEXTR-0 R/W-0 R/W-1 R-0 R/W
(A)
LEGEND: R/W = Read/Write; R = Read only; - n= value after resetA. Default value after reset: C64x+ domain and Never-Gated domain -0x3; other domains -0.
Table 11. Module Control Register 0-10 (MDCTLy) Field Descriptions
Bit Field Value Description
31-9 Reserved Reserved8 LRST Module local reset control. (This bit applies to C64x+ modules only.)0 Assert local reset.1 De-assert local reset.7-5 Reserved Reserved4-0 NEXT Module next state.0 SwRstDisable state.0x3 Enable state.Others Reserved.
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IMPORTANT NOTICE
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