Texas Instruments TUSB3210 Installation and user guide

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
February 2001 MSDS Bus Solutions
Data Manual
SLLS466
Designing with this device may require extensive support. Before incorporating this device into
a design, customers should contact TI or an Authorized TI Distributor.
NOTE

IMPORTANT NOTICE
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Customers are responsible for their applications using TI components.
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Copyright 2001, Texas Instruments Incorporated

iii
Contents
Section Title Page
1 Introduction 1–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.1 Features 1–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.2 Functional Block Diagram 1–2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.3 Terminal Assignments 1–3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.4 Ordering Information 1–3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.5 Terminal Functions 1–4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2 Functional Description 2–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.1 MCU Memory Map 2–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.2 Miscellaneous Registers 2–2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.2.1 TUSB3210 Boot Operation 2–2. . . . . . . . . . . . . . . . . . . . . . . . . . .
2.2.2 MCNFG: MCU Configuration Register 2–3. . . . . . . . . . . . . . . . .
2.2.3 PUR_n: GPIO Pullup Register for Port n (n = 0 to 3) 2–3. . . . .
2.2.4 INTCFG: Interrupt Configuration 2–3. . . . . . . . . . . . . . . . . . . . . .
2.2.5 WDCSR: Watchdog Timer, Control, and Status Register 2–4.
2.2.6 PCON: Power Control Register (at SFR 87h) 2–4. . . . . . . . . . .
2.3 Buffers + I/O RAM Map 2–4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.4 Endpoint Descriptor Block (EDB-1 to EDB-3) 2–7. . . . . . . . . . . . . . . . . . . .
2.4.1 OEPCNF_n: Output Endpoint Configuration 2–7. . . . . . . . . . .
2.4.2 OEPBBAX_n: Output Endpoint X-Buffer Base-Address 2–8. .
2.4.3 OEPBCTX_n: Output Endpoint X Byte Count 2–8. . . . . . . . . .
2.4.4 OEPBBAY_n: Output Endpoint Y-Buffer Base-Address 2–8. .
2.4.5 OEPBCTY_n: Output Endpoint Y Byte Count 2–8. . . . . . . . . . .
2.4.6 OEPSIZXY_n: Output Endpoint X/Y Byte Count 2–9. . . . . . . .
2.4.7 IEPCNF_n: Input Endpoint Configuration 2–9. . . . . . . . . . . . . .
2.4.8 IEPBBAX_n: Input Endpoint X-Buffer Base-Address 2–9. . . . .
2.4.9 IEPBCTX_n: Input Endpoint X-Byte Base-Address 2–10. . . . . .
2.4.10 IEPBBAY_n: Input Endpoint Y-Buffer Base-Address 2–10. . . . .
2.4.11 IEPBCTY_n: Input Endpoint Y Byte Count 2–10. . . . . . . . . . . . .
2.4.12 IEPSIZXY_n: Input Endpoint X/Y-Buffer Size 2–11. . . . . . . . . . .
2.5 Endpoint-0 Descriptor Registers 2–11. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.5.1 IEPCNFG_0: Input Endpoint-0 Configuration Register 2–11. . .
2.5.2 IEPBCNT_0: Input Endpoint-0 Byte Count Register 2–12. . . . .
2.5.3 OEPCNFG_0: Output Endpoint-0 Configuration
Register 2–12. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.5.4 OEPBCNT_0: Output Endpoint-0 Byte Count Register 2–13. . .
2.6 USB Registers 2–13. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.6.1 FUNADR: Function Address Register 2–13. . . . . . . . . . . . . . . . .

iv
2.6.2 USBSTA: USB Status Register 2–14. . . . . . . . . . . . . . . . . . . . . . .
2.6.3 USBMSK: USB Interrupt Mask Register 2–15. . . . . . . . . . . . . . .
2.6.4 USBCTL: USB Control Register 2–16. . . . . . . . . . . . . . . . . . . . . .
2.6.5 VIDSTA: VID/PID Status Register 2–16. . . . . . . . . . . . . . . . . . . . .
2.7 Function Reset and Power-Up Reset Interconnect 2–17. . . . . . . . . . . . . . .
2.8 Pullup Resistor Connect/Disconnect 2–18. . . . . . . . . . . . . . . . . . . . . . . . . . .
2.9 8052 Interrupt and Status Registers 2–18. . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.9.1 8052 Standard Interrupt Enable Register 2–19. . . . . . . . . . . . . . .
2.9.2 Additional Interrupt Sources 2–19. . . . . . . . . . . . . . . . . . . . . . . . . .
2.9.3 VECINT: Vector Interrupt Register 2–20. . . . . . . . . . . . . . . . . . . . .
2.9.4 Logical Interrupt Connection Diagram (INT0)2–21. . . . . . . . . . .
2.9.5 P2[7:0] Interrupt (INT1)2–21. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.10 I2C Registers 2–22. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.10.1 I2CSTA: I2C Status and Control Register 2–22. . . . . . . . . . . . . .
2.10.2 I2CADR: I2C Address Register 2–23. . . . . . . . . . . . . . . . . . . . . . .
2.10.3 I2CDAI: I2C Data-Input Register 2–23. . . . . . . . . . . . . . . . . . . . . .
2.10.4 I2CDAO: I2C Data-Output Register 2–23. . . . . . . . . . . . . . . . . . .
2.11 Read/Write Operations 2–23. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.11.1 Read Operation (Serial EEPROM) 2–23. . . . . . . . . . . . . . . . . . . .
2.11.2 Current Address Read Operation 2–24. . . . . . . . . . . . . . . . . . . . .
2.11.3 Sequential Read Operation 2–24. . . . . . . . . . . . . . . . . . . . . . . . . .
2.11.4 Write Operation (Serial EEPROM) 2–25. . . . . . . . . . . . . . . . . . . .
2.11.5 Page Write Operation 2–26. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3 Electrical Specifications 3–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.1 Absolute Maximum Ratings Over Operating Free-air Temperature 3–1.
3.2 Commercial Operating Condition 3–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.3 Electrical Characteristics, TA= 25°C, VCC = 3.3 V ±0.3 V,
GND = 0 V 3–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4 Application 4–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.1 Examples 4–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.2 Reset Timing 4–2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5 Mechanical Data 5–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

v
List of Illustrations
Figure Title Page
1–1 TUSB3210 Block Diagram 1–2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2–1 MCU Memory Map (TUSB3210) 2–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2–2 MCU Memory Map (ROM Version) 2–2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2–3 Reset Diagram 2–17. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2–4 Pullup Resistor Connect/Disconnect Circuit 2–18. . . . . . . . . . . . . . . . . . . . . . . . . .
2–5 Internal Vector Interrupt (EX0) 2–21. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2–6 P2[7:0] Input Port Interrupt Generation 2–21. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4–1 Example LED Connection 4–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4–2 Partial Connection Bus Power Mode 4–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4–3 Upstream Connection (a) Non-switching Power Mode (b) Switching
Power Mode 4–2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4–4 Downstream Connection–(Only One Port Shown) 4–2. . . . . . . . . . . . . . . . . . . . .
4–5 Reset Timing 4–2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
List of Tables
Table Title Page
2–1 XDATA Space 2–5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2–2 Memory Mapped Registers Summary (XDATA Range = FF80 →FFFF) 2–5. .
2–3 EDB and Buffer Allocations in XDATA 2–6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2–4 EDB Entries in RAM (n = 1 to 3) 2–7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2–5 Input/Output EDB-0 Registers 2–11. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2–6 External Pins Mapping to S[3:0] in VIDSTA Register 2–17. . . . . . . . . . . . . . . . . . .
2–7 8052 Interrupt Location Map 2–18. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2–8 Vector Interrupt Values 2–20. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

vi

1–1
1 Introduction
The TUSB3210 has 8k ×8 RAM space for application development. A ROM based version of the TUSB3210 has 8k
×8 ROM space for predeveloped customer specific production applications. In addition, the programmability of the
TUSB3210 makes it flexible enough to use for various other general USB I/O applications. Unique vendor
identification and product identification (VID/PID) may be selected without the use of an external EEPROM. Using
a 12 MHz crystal, the onboard oscillator generates the internal system clocks. The device may be programmed via
an inter-IC (I2C) serial interface at power on from an EEPROM, or optionally, the application firmware may be
downloaded from a host PC via USB. The popular 8052-based microprocessor allows several third party standard
toolstobeusedforapplicationdevelopment.Inaddition,thevastamountsofapplicationcodeavailableinthegeneral
market may also be utilized (this may or may not require some code modification due to hardware variations).
1.1 Features
•Multiproduct support with one code and one chip (up to 16 products with one chip)
•Fully compliant with the USB release 1.1 specification
•Supports USB suspend/resume and remote wake-up operation
•Integrated 8052 Microcontroller with:
–256 ×8 RAM for internal data
–8k ×8 RAM code space available for downloadable firmware from host or I2C port. [1]
–512 ×8 shared RAM used for data buffers and endpoint descriptor blocks (EDB) [2]
–Four 8052 GPIO ports, Port 0,1, 2 and 3
–Master I2C controller for external slave device access
–Watchdog timer
•Operates from a 12 MHz crystal
•On-chip PLL generates 48/12 MHz
•Supports a total of 4 input and 4 output endpoints
•Power-down mode
•Single 3.3 V operation [3]
•64-pin TQFP package
•Applications include keyboard, bar code reader, flash memory reader, general-purpose controller
[1] The TUSB3210 has 8K x 8 RAM for development.
[2] This is the buffer space for USB packet transactions.
[3] 1.8 V required only to support suspend mode.

1–2
1.2 Functional Block Diagram
RSTI
8052
Core
8
6K x 8
ROM
8K x 8
RAM[1]
512 x 8
SRAM
CPU –I/F
Suspend/
Resume
UBM
USB Buffer
Manager
TDM
Control
Logic
USB
SIE
USB
TxR
8
8
8
88
USB-0
PLL
and
Dividers
Clock
Oscillator
12 MHz
82 x 16-Bit
Timers
I2C
Controller
8
8
Reset,
Interrupt
and WDT
8 P0.[7:0]
8 P1.[7:0]
8 P2.[7:0]
8 P3.[7:0]
I2C Bus
Port-0
Port-1
Port-2
Port-3
Logic
[1] The TUSB3210 has 8K x 8 RAM for development. 8k x 8 ROM version available. Contact TI Marketing
Figure 1–1. TUSB3210 Block Diagram

1–3
1.3 Terminal Assignments
12 3
P1.1
P1.0
P2.7
P2.6
P2.5
P2.4
P2.3
P2.2
GND
P2.1
P2.0
SELF/BUS
TEST2
DM
DP
PUR
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
4
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
P0.6
P0.7
P3.7
P3.6
P3.5
P3.4
P3.3
P3.2
P3.1/S1
P3.0/S0
GND
X2
X1
VCC
NC
NC 5678
P1.3 VREN
47 46 45 44 4348 42
P0.3 P0.2 P0.1 P0.0 GND P1.7 P1.6
VCC
SDA
SCL
RST
NC
GND
RSV
NC NC
S2 S3
40 39 3841
910111213
37 36
RSV
VDDOUT P1.5
35 34 33
14 15 16
TEST0 TEST1
SUSP
P1.4 VCC P1.2 P0.5 P0.4
NC
PM PACKAGE
(TOP VIEW)
1.4 Ordering Information
PACKAGE
TAPLASTIC QUAD FLATPACK
(PM)
0°C to 70°C TUSB3210PM

1–4
1.5 Terminal Functions
TERMINAL
I/O
DESCRIPTION
NAME NO. I/O DESCRIPTION
DM 19 I/O Differential data minus USB
DP 18 I/O Differential data plus USB
GND 5,24,42,5
9IPower supply ground
NC 2, 3, 6,
7, 63, 64 No connection
P0.0 43 I/O General-purpose I/O port 0 bit 0, Schmitt-trigger input 100 µA active pullup, open drain output
P0.1 44 I/O General-purpose I/O port 0 bit 1, Schmitt-trigger input 100 µA active pullup, open drain output
P0.2 45 I/O General-purpose I/O port 0 bit 2, Schmitt-trigger input 100 µA active pullup, open drain output
P0.3 46 I/O General-purpose I/O port 0 bit 3, Schmitt-trigger input 100 µA active pullup, open drain output
P0.4 47 I/O General-purpose I/O port 0 bit 4, Schmitt-trigger input 100 µA active pullup, open drain output
P0.5 48 I/O General-purpose I/O port 0 bit 5, Schmitt-trigger input 100 µA active pullup, open drain output
P0.6 49 I/O General-purpose I/O port 0 bit 6, Schmitt-trigger input 100 µA active pullup, open drain output
P0.7 50 I/O General-purpose I/O port 0 bit 7, Schmitt-trigger input 100 µA active pullup, open drain output
P1.0 31 I/O General-purpose I/O port 1 bit 0, Schmitt-trigger input 100 µA active pullup, open drain output
P1.1 32 I/O General-purpose I/O port 1 bit 1, Schmitt-trigger input 100 µA active pullup, open drain output
P1.2 33 I/O General-purpose I/O port 1 bit 2, Schmitt-trigger input 100 µA active pullup, open drain output
P1.3 34 I/O General-purpose I/O port 1 bit 3, Schmitt-trigger input 100 µA active pullup, open drain output
P1.4 35 I/O General-purpose I/O port 1 bit 4, Schmitt-trigger input 100 µA active pullup, open drain output
P1.5 36 I/O General-purpose I/O port 1 bit 5, Schmitt-trigger input 100 µA active pullup, open drain output
P1.6 40 I/O General-purpose I/O port 1 bit 6, Schmitt-trigger input 100 µA active pullup, open drain output
P1.7 41 I/O General-purpose I/O port 1 bit 7, Schmitt-trigger input 100 µA active pullup, open drain output
P2.0 22 I/O General-purpose I/O port 2 bit 0, Schmitt-trigger input 100 µA active pullup, open drain output
P2.1 23 I/O General-purpose I/O port 2 bit 1, Schmitt-trigger input 100 µA active pullup, open drain output
P2.2 25 I/O General-purpose I/O port 2 bit 2, Schmitt-trigger input 100 µA active pullup, open drain output
P2.3 26 I/O General-purpose I/O port 2 bit 3, Schmitt-trigger input 100 µA active pullup, open drain output
P2.4 27 I/O General-purpose I/O port 2 bit 4, Schmitt-trigger input 100 µA active pullup, open drain output
P2.5 28 I/O General-purpose I/O port 2 bit 5, Schmitt-trigger input 100 µA active pullup, open drain output
P2.6 29 I/O General-purpose I/O port 2 bit 6, Schmitt-trigger input 100 µA active pullup, open drain output
P2.7 30 I/O General-purpose I/O port 2 bit 7, Schmitt-trigger input 100 µA active pullup, open drain output
P3.0/S0 58 I/O General-purpose I/O port 3 bit 0, Schmitt-trigger input 100 µA active pullup, open drain output
P3.1/S1 57 I/O General-purpose I/O port 3 bit 1, Schmitt-trigger input 100 µA active pullup, open drain output
P3.2 56 I/O General-purpose I/O port 3 bit 2
P3.3 55 I/O General-purpose I/O port 3 bit 3, Schmitt-trigger input 100 µA active pullup, open drain output;
will not support INT1 input
P3.4 54 I/O General-purpose I/O port 3 bit 4, Schmitt-trigger input 100 µA active pullup, open drain output
P3.5 53 I/O General-purpose I/O port 3 bit 5, Schmitt-trigger input 100 µA active pullup, open drain output
P3.6 52 I/O General-purpose I/O port 3 bit 6, Schmitt-trigger input 100 µA active pullup, open drain output
P3.7 51 I/O General-purpose I/O port 3 bit 7, Schmitt-trigger input 100 µA active pullup, open drain output
PUR 17 O Pullup resistor connection pin (3-state) push-pull CMOS output (±8 mA)
RST 13 I Controller master reset signal, Schmitt-trigger input 100 µA active pullup
RSV 1, 4 Reserved (Do not connect these pins)
S2 8 I VID/PID selection pin
S3 9 I VID/PID selection pin

1–5
1.5 Terminal Functions (Continued)
TERMINAL
I/O
DESCRIPTION
NAME NO. I/O DESCRIPTION
SCL 12 O Serial clock I2C; open drain output
SDA 11 I/O Serial data I2C; open drain output
SELF/BUS 21 I USB power MODE select: self-powered (HIGH), bus-powered (LOW)
SUSP 16 O Suspend status signal: suspended (HIGH); unsuspended (LOW)
TEST0 14 I Test input0, Schmitt-trigger input 100 µA active pullup
TEST1 15 I Test input1, Schmitt-trigger input 100 µA active pullup
TEST2 20 I Test input2, Schmitt-trigger input 100 µA active pullup
VCC 10,39,62 I Power supply input 3.3 V typical
VDDOUT 37 O Power supply regulator output 1.8 V (May be used as an input when VREN is low)
VREN 38 I Voltage regulator enable: enable active LOW; disable active HIGH
X1 61 I 12-MHz crystal input
X2 60 O 12-MHz crystal output

1–6

2–1
2 Functional Description
2.1 MCU Memory Map
Figure 2–1 illustrates the MCU memory map under boot and normal operation. It must be noted that the internal 256
bytes of IDATA are not shown since it is assumed to be in the standard 8052 location (0000 to 00FF). The shaded
areas represent the internal ROM/RAM.
When SDW bit = 0 (Boot mode): The 6k-ROM is mapped to address (0000–17FF) and is duplicated in location
(8000–97FF) in code space. The internal 8k-RAM is mapped to address range (0000–1FFF) in data space. Buffers,
MMR and I/O are mapped to address range (FD80–FFFF) in data space.
When SDW bit = 1 (Normal mode): The 6k-ROM is mapped to (8000–97FF) in code space. The internal 8k-RAM
is mapped to address range (0000–1FFF) code space. Buffers, MMR and I/O are mapped to address range
(FD80–FFFF) in data space.
Boot Mode (SDW = 0) Normal Mode (SDW = 1)
CODE XDATA CODE XDATA
0000
6k Boot ROM
6k Boot ROM
8k
8k
17FF
8k
RAM
8k
Code RAM
RAM
Read/Write
Code
RAM
Read Only
1FFF
8000
6k Boot ROM 6k Boot ROM
6k
Boot
ROM
6k
Boot
ROM
97FF
FD80 512 B
y
tes 512 B
y
tes
512
Bytes
RAM
512
Bytes
RAM
FF80
MMR
MMR
FFFF MMR MMR
Figure 2–1. MCU Memory Map (TUSB3210)

2–2
CODE XDATA
0000
8k ROM
1FFF
FD80 512 Bytes
RAM
FF80 MMR
FFFF
Figure 2–2. MCU Memory Map (ROM Version)
2.2 Miscellaneous Registers
2.2.1 TUSB3210 Boot Operation
Since the code-space is in RAM (with the exception of the boot ROM), the TUSB3210 firmware must be loaded from
an external source. Two options for booting are available: an external serial EEPROM source connected to the I2C
bus, or the host may be used via the USB. On device reset, the SDW bit (in ROM register) and CONT bit in USB
Control Register (USBCTL) will be cleared. This will configure the memory space to boot mode (see memory map)
and will keep the device disconnected from the host.
Thefirstinstructionwillbefetchedfromlocation0000(whichisinthe6k-ROM).The8k-RAMwillbemappedtoXDATA
space (location 0000h). MCU will execute a read from an external EEPROM and test to see if it contains the code
(test for boot signature). If it contains the code, MCU will read from EEPROM and write to the 8k-RAM in XDATA
space. If not, MCU will proceed to boot from USB.
Oncethecodeisloaded,theMCUwillsetSDWto1.Thiswillswitchthememorymaptonormalmode,i.e.the8k-RAM
will be mapped to code space, and the MCU will start executing from location 0000h. Once the switch is done, the
MCU will set CONT to 1 (in USBCTL register) This will connect the device to the USB bus, resulting in the normal
USB device enumeration.

2–3
2.2.2 MCNFG: MCU Configuration Register
This register is used to control the MCU clock rate.
76 5 43210
12/48 XINT RSV R3 R2 R1 R0 SDW
R/W R/W R/O R/O R/O R/O R/O R/W
BIT NAME RESET FUNCTION
0 SDW 0 This bit enables/disables boot ROM. In the ROM version of the controller, this bit has no effect.
SDW = 0 When clear, MCU executes from the 6k boot ROM space. The boot ROM appears in two
locations: 0000 and 8000h. The 8k RAM is mapped to XDATA space; therefore, Read/Write
operation is possible. This bit is set by MCU after the RAM load is completed. MCU cannot
clear this bit. It is cleared on power-up-reset or function reset.
SDW = 1 When set by MCU, the 6k boot ROM maps to location 8000h, and the 8k RAM is mapped to
code-space, starting at location 0000h. At this point, MCU executes from RAM, and write
operation is disabled (No write operation is possible in code space).
4–1 R[3:0] No affect These bits reflect the device revision number
5 RSV 0 Reserved
6 XINT 0 INT1 source control bit.
XINT = 0 INT1 is connected to P3.3-pin and operates as a standard INT1 interrupt
XINT = 1 INT1 is connected to the OR of Port–2 inputs.
7 12/48 0 This bit selects 12 or 48MHz clock for MCU
12/48 = 0 12 MHz
12/48 = 1 48 MHz
2.2.3 PUR_n: GPIO Pullup Register for Port n (n = 0 to 3)
76 5 43210
Pin7 Pin6 Pin5 Pin4 Pin3 Pin2 Pin1 Pin0
R/W R/W R/W R/W R/W R/W R/W R/W
BIT NAME RESET FUNCTION
0–7 PinN
(N = 0 to 7) 0TheMCU may writeto this register. If the MCU setsthis bit to1, the pullupresistor is disconnected from the pin. If the MCU clears this bit to 0, the pullup resistor is connected to the pin. The pullup resistor is
connected to VCC power supply.
2.2.4 INTCFG: Interrupt Configuration
76 5 43210
RSV RSV RSV RSV I3 I2 I1 I0
R/O R/O R/O R/O R/W R/W R/W R/W
BIT NAME RESET FUNCTION
0–3 I[3:0] 0010 TheMCUmay write tothisregisterto set theinterruptdelaytime for Port2onthe MCU. Thevalueofthe
lower nibble represents the delay in ms. Default after reset is 2 ms.
4–7 RSV 0 Reserved

2–4
2.2.5 WDCSR: Watchdog Timer, Control, and Status Register
A watchdog timer (WDT) with 1ms clock is provided. If this register is not accessed for a period of 32ms, the WDT
counter will reset the MCU. (See Figure 2–3, Reset Diagram). When the IDL bit in PCON is set, the WDT will be
suspended until an interrupt is detected. At this point, the IDL bit will be cleared and the WDT will resume operation.
76 5 43210
WDE WDR RSV RSV RSV RSV RSV WDT
R/W R/W R/O R/O R/O R/O R/O W/O
BIT NAME RESET FUNCTION
0 WDT 0 MCU must write a 1 to this bit to prevent the WDT from resetting the MCU. If MCU does not write a 1 in a
periodof31ms,theWDTwillresetthedevice.Writinga0hasnoeffectontheWDT.(WDTisa5-bitcounter
using 1ms CLK). This bit is read as 0.
5–1 RSV 0 Reserved = 0
6 WDR 0 Watchdog reset indication bit. This bit indicates if the reset occurred due to power-on reset or watchdog
timer reset.
WDR = 0 A power-up or USB reset occurred.
WDR = 1 Awatchdogtimeoutresetoccurred.Toclearthisbit,theMCUmustwritea1.Writinga0hasno
effect.
7 WDE 0 Watchdog Timer Enable.
WDE = 0 This bit is cleared only on power-up, USB-reset (if enabled) or WDT reset.
WDE = 1 WhenMCUwritesa1tothisbittheWDTwillstartrunning.MCUcannotdisabletheWDT.Only
poweruporUSBreset(ifenabled)canclearit.WhenMCUisinidlestate(IDL=1),theWDTis
suspended.
2.2.6 PCON: Power Control Register (at SFR 87h)
76 5 43210
SMOD RSV RSV RSV GF1 GF0 RSV IDL
R/W R/O R/O R/O R/W R/W R/O R/W
BIT NAME RESET FUNCTION
0 IDL 0 MCU idle mode bit. This bit can be set by MCU and is cleared only by INT1 interrupt.
IDL = 0 MCUisNOTin idle mode.Thisbitis cleared byINT1interruptlogicwhenINT1is assertedfor
at least 400µs.
IDL = 1 MCU is in idle mode and RAM is in low-power mode. The oscillator/APLL is off and the WDT
willbe suspended.When insuspendmode,onlyINT1canbe used toexitfromidlemode and
generate an interrupt. INT1 must be asserted for at least 400µs for the interrupt to be
recognized.
1 RSV 0 Reserved
3–2 GF[1:0] 00 General-purpose bits. MCU can write and read them.
6–4 RSV 0 Reserved
7 SMOD 0 Double baud rate control bit. For more information see UART serial interface in M8052 core specification.
2.3 Buffers + I/O RAM Map
The address range from FD80 to FFFF is reserved for data buffers, setup packet, endpoint descriptor blocks(EDB),
and all I/O. RAM space of 512 bytes [FD80–FF7F] is used for EDB and buffers. The FF80–FFFF range is used for
memory mapped registers (MMR). Table 2–1 represents the internal XDATA space allocation.

2–5
Table 2–1. XDATA Space
DESCRIPTION ADDRESS RANGE
FFFF
I t l MMR
Internal MMR
↑
Internal
MMR
(Memory ma
pp
ed registers)
↑
(Memory
mapped
registers)
FF80
FF7F
EDB
EDB
(End
p
oint descri
p
tor blocks)
↑
(E
n
d
po
i
n
t
d
escr
i
p
t
or
bl
oc
k
s
)
FF08
FF07
Setup packet buffer ↑
Setu
acket
buffer
FF00
FEFF
512 b t
Input endpoint-0 buffer ↑512 byte
RAM
In ut
end oint 0
buffer
FEF8
RAM
FEF7
Output endpoint-0 buffer ↑
Out ut
end oint 0
buffer
FEF0
FEEF
Dt bff
Data buffers
↑
Data
buffers
(367 bytes)
↑
(367
bytes)
FD80
Table 2–2. Memory Mapped Registers Summary (XDATA Range = FF80 →FFFF)
ADDRESS REGISTER DESCRIPTION
FFFF FUNADR FUNADR: Function address register
FFFE USBSTA USBSTA: USB status register
FFFD USBMSK USBMSK: USB interrupt mask register
FFFC USBCTL USBCTL: USB control register
↑RESERVED
FFF6 VIDSTA VIDSTA: VID/PID status register
↑RESERVED
FFF3 I2CADR I2CADR: I2C address register
FFF2 I2CDAI I2CDAI: I2C data-input register
FFF1 I2CDAO I2CDAO: I2C data-output register
FFF0 I2CSTA I2CSTA: I2C status and control register
↑RESERVED
FF97 PUR3 Port 3 pullup resistor register
FF96 PUR2 Port 2 pullup resistor register
FF95 PUR1 Port 1 pullup resistor register
FF94 PUR0 Port 0 pullup resistor register
FF93 WDCSR WDCSR: Watchdog timer, control & status register
FF92 VECINT VECINT: Vector interrupt register

2–6
Table 2–2. Memory Mapped Registers Summary (XDATA Range = FF80 →FFF) (Continued)
ADDRESS REGISTER DESCRIPTION
FF91 RESERVED
FF90 MCNFG MCNFG: MCU configuration register
↑RESERVED
FF84 INTCFG INTCFG: Interrupt delay configuration register
FF83 OEPBCNT_0 OEPBCNT_0: Output endpoint-0 byte count register
FF82 OEPCNFG_0 OEPCNFG_0: Output endpoint-0 configuration register
FF81 IEPBCNT_0 IEPBCNT_0: Input endpoint-0 byte count register
FF80 IEPCNFG_0 IEPCNFG_0: Input endpoint-0 configuration register
Table 2–3. EDB and Buffer Allocations in XDATA
ADDRESS DESCRIPTION
FF7F
↑(32–bytes) RESERVED
(32 bytes)
RESERVED
FF60
FF5F
↑(8–bytes) Input endpoint_3: configuration
FF58
(8 bytes)
In ut
end oint
_
3:
configuration
FF57
↑(8–bytes) Input endpoint_2: configuration
FF50
(8 bytes)
In ut
end oint
_
2:
configuration
FF4F
↑(8–bytes) Input endpoint_1: configuration
FF48
(8 bytes)
In ut
end oint
_
1:
configuration
FF47
↑(40–bytes) RESERVED
FF20
FF1F
↑(8–bytes) Output endpoint_3: configuration
FF18
(8 bytes)
Out ut
end oint
_
3:
configuration
FF17
↑(8–bytes) Output endpoint_2: configuration
FF10
(8 bytes)
Out ut
end oint
_
2:
configuration
FF0F
↑(8–bytes) Output endpoint_1: configuration
FF08
(8 bytes)
Out ut
end oint
_
1:
configuration
FF07
↑(8–bytes) Setup packet block
FF00
(8 bytes)
Setu
acket
block
FEFF
↑(8–bytes) Input endpoint_0 buffer
FEF8
(8 bytes)
In ut
end oint
_
0
buffer

2–7
Table 2–3. EDB and Buffer Allocations in XDATA (Continued)
ADDRESS DESCRIPTION
FEF7
↑(8–bytes) Output endpoint_0 buffer
FEF0
(8 bytes)
Out ut
end oint
_
0
buffer
FEEF TOPBUFF Top of buffer space
↑
Buffers space

FD80 STABUFF Start of buffer space
2.4 Endpoint Descriptor Block (EDB-1 to EDB-3)
Data transfers between USB, MCU and external devices are defined by an endpoint descriptor block (EDB). Four
input and four output EDBs are provided. With the exception of EDB–0 (I/O Endpoint–0), all EDBs are located in
SRAM as shown in Table 2–3. Each EDB contains information describing the X and Y buffers. In addition, it provides
general status information.
Table 2–4 illustrates the EDB entries for EDB–1 to EDB–3. EDB–0 registers will be described separately.
Table 2–4. EDB Entries in RAM (n = 1 to 3)
Offset ENTRY NAME DESCRIPTION
07 EPSIZXY_n I/O endpoint_n: X/Y buffer size
06 EPBCTY_n I/O endpoint_n: Y byte count
05 EPBBAY_n I/O endpoint_n: Y buffer base address
04 SPARE Not used
03 SPARE Not used
02 EPBCTX_n I/O endpoint_n: X byte count
01 EPBBAX_n I/O endpoint_n: X buffer base address
00 EPCNF_n I/O endpoint_n: configuration
2.4.1 OEPCNF_n: Output Endpoint Configuration (n=1 to 3)
76 5 43210
UBME ISO TOGLE DBUF STALL USBIE RSV RSV
R/W R/W R/W R/W R/W R/W R/O R/O
BIT NAME RESET FUNCTION
1–0 RSV 0 Reserved
2 USBIE x USB interrupt enable on transaction completion. Set/clear by MCU.
USBIE = 0 no interrupt
USBIE = 1 interrupt on transaction completion
3 STALL 0 USB stall condition indication. Set/clear by MCU.
STALL = 0 No stall
STALL = 1 USBstallcondition.IfsetbyMCU,aSTALLhandshakeisinitiatedandthebitisclearedbyMCU.
4 DBUF x Double buffer enable. Set/clear by MCU.
DBUF = 0 Primary buffer only (X–buffer only)
DBUF = 1 Toggle bit selects buffer
5 TOGLE x USB Toggle bit. This bit reflects the toggle sequence bit of DATA0, DATA1
6 ISO x ISO = 0 Non-isochronoustransfer.ThisbitmustbeclearedbyMCUsinceonlyNon-isochronoustransfer
is supported.
7 UBME x UBM enable/disable bit. Set/clear by MCU.
UBME = 0 UBM cannot use this endpoint.
UBME = 1 UBM can use this endpoint.

2–8
2.4.2 OEPBBAX_n: Output Endpoint X-Buffer Base-Address (n=1 to 3)
76 5 43210
A10 A9A8A7A6A5A4A3
R/W R/W R/W R/W R/W R/W R/W R/W
BIT NAME RESET FUNCTION
7–0 A[10:3] x A[10:3]of X–bufferbaseaddress(paddedwith3-LSBof zeros for atotal of11-bits).Thisvalueissetbythe
MCU.UBMorDMAusesthisvalueas the start-addressof agiventransaction.Furthermore,UBMorDMA
does not change this value at the end of a transaction.
2.4.3 OEPBCTX_n: Output Endpoint X Byte Count (n=1 to 3)
76 5 43210
NAK C6C5C4C3C2C1C0
R/W R/W R/W R/W R/W R/W R/W R/W
BIT NAME RESET FUNCTION
6–0 C[6:0] x X-Buffer Byte count:
X000.0000b > Count = 0
X000.0001b > Count = 1 byte
:
:
X011.1111b > Count = 63 bytes
X100.0000b > Count = 64 bytes
Any value ≥100.0001b produces unpredictable results.
7 NAK x NAK= 0 No valid data in buffer. Ready for host out
NAK= 1 Buffer contains a valid packet from Host (host-out request is NAK)
2.4.4 OEPBBAY_n: Output Endpoint Y-Buffer Base-Address (n=1 to 3)
76 5 43210
A10 A9A8A7A6A5A4A3
R/W R/W R/W R/W R/W R/W R/W R/W
BIT NAME RESET FUNCTION
7–0 A[10:3] x A[10:3]ofY–bufferbase address(paddedwith 3-LSB ofzerosfor atotalof11bits).Thisvalue issetbythe
MCU.UBMorDMA usesthisvalueasthestart-addressofagiventransaction.Furthermore,UBMorDMA
does not change this value at the end of a transaction.
2.4.5 OEPBCTY_n: Output Endpoint Y Byte Count (n=1 to 3)
76 5 43210
NAK C6C5C4C3C2C1C0
R/W R/W R/W R/W R/W R/W R/W R/W
BIT NAME RESET FUNCTION
6–0 C[6:0] x Y-Byte count:
X000.0000b > Count = 0
X000.0001b > Count = 1 byte
:
:
X011.1111b > Count = 63 bytes
X100.0000b > Count = 64 bytes
Any value ≥100.0001b will result in unpredictable results.
7 NAK x NAK= 0 No valid data in buffer. Ready for host out
NAK= 1 Buffer contains a valid packet from host (host-out request is NAK)