Texas Instruments TMS320F28004 Series User manual

Errata
TMS320F28004x Real-Time MCUs Silicon Errata
Silicon Revisions B, A, 0
ABSTRACT
This document describes the known exceptions to the functional specifications (advisories). This document
may also contain usage notes. Usage notes describe situations where the device's behavior may not match
presumed or documented behavior. This may include behaviors that affect device performance or functional
correctness.
Table of Contents
1 Usage Notes and Advisories Matrices..................................................................................................................................2
1.1 Usage Notes Matrix............................................................................................................................................................2
1.2 Advisories Matrix................................................................................................................................................................2
2 Nomenclature, Package Symbolization, and Revision Identification................................................................................ 4
2.1 Device and Development Support Tool Nomenclature...................................................................................................... 4
2.2 Devices Supported.............................................................................................................................................................4
2.3 Package Symbolization and Revision Identification...........................................................................................................5
3 Silicon Revision B Usage Notes and Advisories.................................................................................................................7
3.1 Silicon Revision B Usage Notes.........................................................................................................................................7
3.2 Silicon Revision B Advisories...........................................................................................................................................10
4 Silicon Revision A Usage Notes and Advisories...............................................................................................................36
4.1 Silicon Revision A Usage Notes.......................................................................................................................................36
4.2 Silicon Revision A Advisories...........................................................................................................................................36
5 Silicon Revision 0 Usage Notes and Advisories............................................................................................................... 40
5.1 Silicon Revision 0 Usage Notes....................................................................................................................................... 40
5.2 Silicon Revision 0 Advisories........................................................................................................................................... 40
6 Documentation Support.......................................................................................................................................................42
7 Trademarks............................................................................................................................................................................42
8 Revision History................................................................................................................................................................... 42
List of Figures
Figure 2-1. Examples of Device Markings for PM and PZ Packages.......................................................................................... 5
Figure 2-2. Example of Device Markings for RSH Package........................................................................................................ 5
Figure 2-3. Example of Device Nomenclature............................................................................................................................. 6
Figure 3-1. Pipeline Diagram of the Issue When There are no Stalls in the Pipeline................................................................ 10
Figure 3-2. Pipeline Diagram of the Issue if There is a Stall in the E3 Slot of the Instruction I1................................................11
Figure 3-3. Pipeline Diagram With Workaround in Place...........................................................................................................12
Figure 3-4. Placement of Series Termination Resistor and Pullup Resistor.............................................................................. 23
Figure 3-5. Undesired Trip Event and Blanking Window Expiration.......................................................................................... 24
Figure 3-6. Resulting Undesired ePWM Outputs Possible........................................................................................................ 24
List of Tables
Table 1-1. Usage Notes Matrix.................................................................................................................................................... 2
Table 1-2. Advisories Matrix.........................................................................................................................................................2
Table 2-1. Determining Silicon Revision From Lot Trace Code................................................................................................... 5
Table 3-1. Memories Impacted by Advisory...............................................................................................................................29
Table 3-2. ADCCTL2 Register................................................................................................................................................... 32
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1 Usage Notes and Advisories Matrices
Table 1-1 lists all usage notes and the applicable silicon revisions. Table 1-2 lists all advisories, modules
affected, and the applicable silicon revisions.
1.1 Usage Notes Matrix
Table 1-1. Usage Notes Matrix
NUMBER TITLE
SILICON REVISIONS
AFFECTED
0 A B
Section 3.1.1 PIE: Spurious Nested Interrupt After Back-to-Back PIEACK Write and Manual CPU
Interrupt Mask Clear
Yes Yes Yes
Section 3.1.2 FPU32 and VCU Back-to-Back Memory Accesses Yes Yes Yes
Section 3.1.3 Caution While Using Nested Interrupts Yes Yes Yes
1.2 Advisories Matrix
Table 1-2. Advisories Matrix
MODULE DESCRIPTION
SILICON REVISIONS
AFFECTED
0 A B
FPU FPU: FPU-to-CPU Register Move Operation Preceded by Any FPU 2p Operation Yes Yes Yes
SDFM SDFM: Dynamically Changing Threshold Settings (LLT, HLT), Filter Type, or COSR
Settings Will Trigger Spurious Comparator Events
Yes Yes Yes
SDFM SDFM: Dynamically Changing Data Filter Settings (Such as Filter Type or DOSR)
Will Trigger Spurious Data Acknowledge Events
Yes Yes Yes
SDFM SDFM: Two Back-to-Back Writes to SDCPARMx Register Bit Fields CEVT1SEL,
CEVT2SEL, and HZEN Within Three SD-Modulator Clock Cycles can Corrupt SDFM
State Machine, Resulting in Spurious Comparator Events
Yes Yes Yes
SDFM SDFM: Manchester Mode (Mode 2) Does Not Produce Correct Filter Results Under
Several Conditions
Yes Yes Yes
eQEP eQEP: Position Counter Incorrectly Reset on Direction Change During Index Yes Yes Yes
eQEP eQEP: eQEP Inputs in GPIO Asynchronous Mode Yes Yes Yes
VDD Supply: VDD Supply: During VDDIO Power Up, VDD May Also Rise Yes Yes Yes
eCAP eCAP: HRFRC is Not EALLOW-Protected Yes Yes Yes
PLL PLL: PLL May Not Lock on the First Lock Attempt Yes Yes Yes
LPM LPM: STANDBY Low-Power Mode is Not Supported Yes Yes Yes
DCC DCC: Single-Shot-Mode Operation May End Prematurely Yes Yes Yes
BOR BOR: VDDIO Between 2.45 V and 3.0 V can Result in Multiple XRSn Pulses Yes Yes Yes
I2C I2C: SDA and SCL Open-Drain Output Buffer Issue Yes Yes Yes
ePWM ePWM: An ePWM Glitch can Occur if a Trip Remains Active at the End of the
Blanking Window
Yes Yes Yes
ePWM ePWM: Trip Events Will Not be Filtered by the Blanking Window for the First 3 Cycles
After the Start of a Blanking Window
Yes Yes Yes
ePWM ePWM: Event Latch (DCxEVTxLAT) of "DC Event-Based CBC Trip" May not Extend
Trigger Pulse as Expected When Asynchronous Path is Selected
Yes – –
INTOSC INTOSC: VDDIO Powered Without VDD Can Cause INTOSC Frequency Drift Yes Yes Yes
FSI FSI: RX FIFO Spurious Overrun Yes Yes Yes
During DCAN FIFO Mode, Received Messages May be Placed Out of Order in the
FIFO Buffer
Yes Yes Yes
Boot ROM Boot ROM: Calling SCI Bootloader from Application Yes Yes Yes
Boot ROM, MPOST Boot-ROM, MPOST: Longer Boot Time With MPOST Enabled Yes Yes Yes
Memory Memory: Prefetching Beyond Valid Memory Yes Yes Yes
SYSTEM SYSTEM: Multiple Successive Writes to CLKSRCCTL1 Can Cause a System Hang Yes Yes Yes
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Table 1-2. Advisories Matrix (continued)
MODULE DESCRIPTION
SILICON REVISIONS
AFFECTED
0 A B
ADC ADC: Interrupts may Stop if INTxCONT (Continue-to-Interrupt Mode) is not Set Yes Yes Yes
ADC ADC: Degraded ADC Performance With ADCCLK Fractional Divider Yes Yes Yes
ADC ADC: DMA Read of Stale Result Yes Yes Yes
CLB CLB: Back-to-Back PUSH or PULL Instructions With More Than One Active High
Level Controller (HLC) Channel is not Supported
Yes Yes Yes
Analog Subsystem Analog Subsystem: Software Configuration for Shared Reference Pins Yes Yes –
Analog Trim of Some TMX Devices Yes Yes –
PGA PGA: Output Filter Path is Not Supported Yes Yes –
ROM ROM: Flash API Library and FPU32 Twiddle Factor RFFT Table Not Present Yes Yes –
REVID REVID: Some TMX Revision A Devices Have an Incorrect REVID Value – Yes –
GPIO GPIO: X2/GPIO18 Pin Pullup Current During Power Up Yes Yes Yes
GPIO GPIO: Open-Drain Configuration May Drive a Short High Pulse Yes Yes Yes
GPIO GPIO: Parasitic Path to VSS When Maximum VIH is Exceeded in Input Mode – Yes –
GPIO GPIO: Pins may Drive High During Power Up Yes – –
GPIO GPIO: Signal Latch-up to VSS Yes – –
LIN LIN: Inconsistent Sync Field Error (ISFE) Flag/Interrupt Not Set When Sync Field is
Erroneous
Yes Yes Yes
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2 Nomenclature, Package Symbolization, and Revision Identification
2.1 Device and Development Support Tool Nomenclature
To designate the stages in the product development cycle, TI assigns prefixes to the part numbers of all TMS320
MCU devices and support tools. Each TMS320™ MCU commercial family member has one of three prefixes:
TMX, TMP, or TMS (for example, TMS320F280049). Texas Instruments recommends two of three possible prefix
designators for its support tools: TMDX and TMDS. These prefixes represent evolutionary stages of product
development from engineering prototypes (with TMX for devices and TMDX for tools) through fully qualified
production devices and tools (with TMS for devices and TMDS for tools).
Device development evolutionary flow:
TMX Experimental device that is not necessarily representative of the final device's electrical specifications and
may not use production assembly flow.
TMP Prototype device that is not necessarily the final silicon die and may not necessarily meet final electrical
specifications.
TMS Production version of the silicon die that is fully qualified.
Support tool development evolutionary flow:
TMDX Development-support product that has not yet completed Texas Instruments internal qualification testing.
TMDS Fully-qualified development-support product.
TMX and TMP devices and TMDX development-support tools are shipped against the following disclaimer:
"Developmental product is intended for internal evaluation purposes."
Production devices and TMDS development-support tools have been characterized fully, and the quality and
reliability of the device have been demonstrated fully. TI's standard warranty applies.
Predictions show that prototype devices (X or P) have a greater failure rate than the standard production
devices. Texas Instruments recommends that these devices not be used in any production system because their
expected end-use failure rate still is undefined. Only qualified production devices are to be used.
TI device nomenclature also includes a suffix with the device family name. This suffix indicates the package type
(for example, PZ) and temperature range (for example, S).
2.2 Devices Supported
This document supports the following devices:
•TMS320F280049
•TMS320F280049-Q1
•TMS320F280049C
•TMS320F280049C-Q1
•TMS320F280048
•TMS320F280048-Q1
•TMS320F280048C
•TMS320F280048C-Q1
•TMS320F280045
•TMS320F280041
•TMS320F280041-Q1
•TMS320F280041C
•TMS320F280041C-Q1
•TMS320F280040
•TMS320F280040-Q1
•TMS320F280040C
•TMS320F280040C-Q1
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2.3 Package Symbolization and Revision Identification
Figure 2-1 and Figure 2-2 provide examples of the F28004x device markings and define each of the markings.
The device revision can be determined by the symbols marked on the top of the package as shown in Figure 2-1
and Figure 2-2. Some prototype devices may have markings different from those illustrated. Figure 2-3 shows
the device nomenclature.
YMLLLLS
YM
LLLL
S
980
$$
#
G4
Lot Trace Code
2-Digit Year/Month Code
Assembly Lot
Assembly Site Code
TI E.I.A. Code
Wafer Fab Code (one or two characters) as applicable
Silicon Revision Code
Green (Low Halogen and RoHS-compliant)
=
=
=
=
=
=
=
=
G4
980
$$#−YMLLLLS
F280049PZS
Package
Pin 1
G4
980
$$#−YMLLLLS
F280049PMS
Package
Pin 1
Figure 2-1. Examples of Device Markings for PM and PZ Packages
YMLLLLS
YM
LLLL
S
$$
#
G4
Lot Trace Code
2-Digit Year/Month Code
Assembly Lot
Assembly Site Code
Wafer Fab Code (one or two characters) as applicable
Silicon Revision Code
Green (Low Halogen and RoHS-compliant)
=
=
=
=
=
=
=
G4
F280049
$$#−YMLLLLS
RSHS
TI
Package
Pin 1
Figure 2-2. Example of Device Markings for RSH Package
Table 2-1. Determining Silicon Revision From Lot Trace Code
SILICON REVISION CODE SILICON REVISION REVID(1)
Address: 0x5D00C COMMENTS(2)
Blank 0 0x0000 0000 This silicon revision is available as TMX.
A A 0x0000 0001 This silicon revision is available as TMX.
B B 0x0000 0002 This silicon revision is available as TMX and
TMS.
(1) Silicon Revision ID
(2) For orderable device numbers, see the PACKAGING INFORMATION table in the TMS320F28004x Real-Time Microcontrollers data
sheet.
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A. Prefix X is used in orderable part numbers.
Figure 2-3. Example of Device Nomenclature
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3 Silicon Revision B Usage Notes and Advisories
This section lists the usage notes and advisories for this silicon revision.
3.1 Silicon Revision B Usage Notes
This section lists all the usage notes that are applicable to silicon revision B [and earlier silicon revisions].
3.1.1 PIE: Spurious Nested Interrupt After Back-to-Back PIEACK Write and Manual CPU Interrupt Mask
Clear
Revisions Affected: 0, A, B
Certain code sequences used for nested interrupts allow the CPU and PIE to enter an inconsistent state that can
trigger an unwanted interrupt. The conditions required to enter this state are:
1. A PIEACK clear is followed immediately by a global interrupt enable (EINT or asm(" CLRC INTM")).
2. A nested interrupt clears one or more PIEIER bits for its group.
Whether the unwanted interrupt is triggered depends on the configuration and timing of the other interrupts in
the system. This is expected to be a rare or nonexistent event in most applications. If it happens, the unwanted
interrupt will be the first one in the nested interrupt's PIE group, and will be triggered after the nested interrupt
re-enables CPU interrupts (EINT or asm(" CLRC INTM")).
Workaround: Add a NOP between the PIEACK write and the CPU interrupt enable. Example code is shown
below.
//Bad interrupt nesting code
PieCtrlRegs.PIEACK.all = 0xFFFF; //Enable nesting in the PIE
EINT; //Enable nesting in the CPU
//Good interrupt nesting code
PieCtrlRegs.PIEACK.all = 0xFFFF; //Enable nesting in the PIE
asm(" NOP"); //Wait for PIEACK to exit the pipeline
EINT; //Enable nesting in the CPU
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3.1.2 FPU32 and VCU Back-to-Back Memory Accesses
Revisions Affected: 0, A, B
This usage note applies when a VCU memory access and an FPU memory access occur back-to-back. There
are three cases:
Case 1. Back-to-back memory reads: one read performed by a VCU instruction (VMOV32) and one read
performed by an FPU32 instruction (MOV32).
If an R1 pipeline phase stall occurs during the first read, then the second read will latch the wrong data. If the
first instruction is not stalled during the R1 pipeline phase, then the second read will occur properly.
The order of the instructions—FPU followed by VCU or VCU followed by FPU—does not matter. The address of
the memory location accessed by either read does not matter.
Case 1 Workaround: Insert one instruction between the two back-to-back read instructions. Any instruction,
except a VCU or FPU memory read, can be used.
Case 1, Example 1:
VMOV32 VR1,mem32 ; VCU memory read
NOP ; Not a FPU/ VCU memory read
MOV32 R0H,mem32 ; FPU memory read
Case 1, Example 2:
VMOV32 VR1,mem32 ; VCU memory read
VMOV32 mem32, VR2 ; VCU memory write
MOV32 R0H,mem32 ; FPU memory read
Case 2. Back-to-back memory writes: one write performed by a VCU instruction (VMOV32) and one write
performed by an FPU instruction (MOV32).
If a pipeline stall occurs during the first write, then the second write can corrupt the data. If the first instruction is
not stalled in the write phase, then no corruption will occur.
The order of the instructions—FPU followed by VCU or VCU followed by FPU—does not matter. The address of
the memory location accessed by either write does not matter.
Case 2 Workaround: Insert two instructions between the back-to-back VCU and FPU writes. Any instructions,
except VCU or FPU memory writes, can be used.
Case 2, Example 1:
VMOV32 mem32,VR0 ; VCU memory write
NOP ; Not a FPU/VCU memory write
NOP ; Not a FPU/VCU memory write
MOV32 mem32,R3H ; FPU memory write
Case 2, Example 2:
VMOV32 mem32,VR0 ; VCU memory write
VMOV32 VR1, mem32 ; VCU memory read
NOP
MOV32 mem32,R3H ; FPU memory write
Case 3. Back-to-back memory writes followed by a read or a memory read followed by a write. In this case,
there is no interaction between the two instructions. No action is required.
Workaround: See Case 1 Workaround and Case 2 Workaround.
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3.1.3 Caution While Using Nested Interrupts
Revisions Affected: 0, A, B
If the user is enabling interrupts using the EINT instruction inside an interrupt service routine (ISR) in order to
use the nesting feature, then the user must disable the interrupts before exiting the ISR. Failing to do so may
cause undefined behavior of CPU execution.
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3.2 Silicon Revision B Advisories
This section lists all the advisories that are applicable to silicon revision B [and earlier silicon revisions].
Advisory FPU: FPU-to-CPU Register Move Operation Preceded by Any FPU 2p Operation
Revisions Affected 0, A, B
Details This advisory applies when a multicycle (2p) FPU instruction is followed by a FPU-to-CPU
register transfer. If the FPU-to-CPU read instruction source register is the same as the 2p
instruction destination, then the read may be of the value of the FPU register before the
2p instruction completes. This occurs because the 2p instructions rely on data-forwarding
of the result during the E3 phase of the pipeline. If a pipeline stall happens to occur in the
E3 phase, the result does not get forwarded in time for the read instruction.
The 2p instructions impacted by this advisory are MPYF32, ADDF32, SUBF32, and
MACF32. The destination of the FPU register read must be a CPU register (ACC, P, T,
XAR0...XAR7). This advisory does not apply if the register read is a FPU-to-FPU register
transfer.
In the example below, the 2p instruction, MPYF32, uses R6H as its destination. The FPU
register read, MOV32, uses the same register, R6H, as its source, and a CPU register as
the destination. If a stall occurs in the E3 pipeline phase, then MOV32 will read the value
of R6H before the MPYF32 instruction completes.
Example of Problem:
MPYF32 R6H, R5H, R0H ; 2p FPU instruction that writes to R6H
|| MOV32 *XAR7++, R4H
F32TOUI16R R3H, R4H ; delay slot
ADDF32 R2H, R2H, R0H
|| MOV32 *--SP, R2H ; alignment cycle
MOV32 @XAR3, R6H ; FPU register read of R6H
Figure 3-1 shows the pipeline diagram of the issue when there are no stalls in the
pipeline.
Instruction F1 F2 D1 D2 R1 R2 E W
R1 R2 E1 E2 E3
MPYF32 R6H, R5H, R0H
|| MOV32 *XAR7++, R4H
I2 F32TOUI16R R3H, R4H I2 I1
ADDF32 R3H, R2H, R0H
|| MOV32 *--SP, R2H
I4 MOV32 @XAR3, R6H I4 I3 I2 I1
I4 I3 I2 I1
I4 I3 I2 I1
I4 I3 I2 I1
I4 I3 I2 I1
I4
I3 I2 I1
I4 samples the result as it enters
the R2 phase. The product
R6H=R5H*R0H (I1) finishes
computing in the E3 phase, but is
forwarded
as an operand to I4.
This makes I4 appear to be a 2p
instruction, but I4 actually takes
3p cycles to compute.
I4 I3 I2
I4 I3
I3
Comments
FPU pipeline--->
I1 I1
I3 I2 I1
Figure 3-1. Pipeline Diagram of the Issue When There are no Stalls in the Pipeline
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Advisory (continued) FPU: FPU-to-CPU Register Move Operation Preceded by Any FPU 2p Operation
Figure 3-2 shows the pipeline diagram of the issue if there is a stall in the E3 slot of the
instruction I1.
Instruction F1 F2 D1 D2 R1 R2 E W
R1 R2 E1 E2 E3
MPYF32 R6H, R5H, R0H
|| MOV32 *XAR7++, R4H
I2 F32TOUI16R R3H, R4H I2 I1
ADDF32 R3H, R2H, R0H
|| MOV32 *--SP, R2H
I4 MOV32 @XAR3, R6H I4 I3 I2 I1
I4 I3 I2 I1
I4 I3 I2 I1
I4 I3 I2 I1
I4 I3 I2 I1
I4
I3 I2
I1
(STALL)
I4 samples the result as it enters
the R2 phase, but I1 is stalled in
E3 and is unable to forward the
product of R5H*R0H to I4 (R6H does
not have the product yet due to a
design bug). So, I4 reads the old
value of R6H.
I4 I3 I2 I1
There is no change in the pipeline
as it was stalled in the previous
cycle. I4 had already sampled the
old value of R6H in the previous
cycle.
I4 I3 I2 Stall over
I3 I3 I2 I1
Comments
FPU pipeline-->
I1 I1
Figure 3-2. Pipeline Diagram of the Issue if There is a Stall in the E3 Slot of the
Instruction I1
Workaround Treat MPYF32, ADDF32, SUBF32, and MACF32 in this scenario as 3p-cycle instructions.
Three NOPs or non-conflicting instructions must be placed in the delay slot of the
instruction.
The C28x Code Generation Tools v.6.2.0 and later will both generate the correct
instruction sequence and detect the error in assembly code. In previous versions, v6.0.5
(for the 6.0.x branch) and v.6.1.2 (for the 6.1.x branch), the compiler will generate the
correct instruction sequence but the assembler will not detect the error in assembly code.
Example of Workaround:
MPYF32 R6H, R5H, R0H
|| MOV32 *XAR7++, R4H ; 3p FPU instruction that writes to R6H
F32TOUI16R R3H, R4H ; delay slot
ADDF32 R2H, R2H, R0H
|| MOV32 *--SP, R2H ; delay slot
NOP ; alignment cycle
MOV32 @XAR3, R6H ; FPU register read of R6H
Figure 3-3 shows the pipeline diagram with the workaround in place.
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Advisory (continued) FPU: FPU-to-CPU Register Move Operation Preceded by Any FPU 2p Operation
Instruction F1 F2 D1 D2 R1 R2 E W
R1 R2 E1 E2 E3
MPYF32 R6H, R5H, R0H
|| MOV32 *XAR7++, R4H
I2 F32TOUI16R R3H, R4H I2 I1
ADDF32 R3H, R2H, R0H
|| MOV32 *--SP, R2H
I4 NOP I4 I3 I2 I1
I5 MOV32 @XAR3, R6H I5 I4 I3 I2 I1
I5 I4 I3 I2 I1
I5 I4 I3 I2 I1
I5 I4 I3 I2 I1
I5 I4 I3 I2 I1
(STALL)
Due to one extra NOP, I5 does not
reach R2 when I1 enters E3; thus,
forwarding is not needed.
I5 I4 I3 I2 I1 There is no change due to the
stall in the previous cycle.
I5 I4 I3 I2
I1 moves out of E3 and I5 moves to
R2. R6H has the result of R5H*R0H
and is read by I5. There is no
need to forward the result in this
case.
I5 I4 I3
I3 I3 I2 I1
Comments
FPU pipeline-->
I1 I1
Figure 3-3. Pipeline Diagram With Workaround in Place
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Advisory SDFM: Dynamically Changing Threshold Settings (LLT, HLT), Filter Type, or COSR
Settings Will Trigger Spurious Comparator Events
Revisions Affected 0, A, B
Details When SDFM comparator settings—such as filter type, lower/upper threshold, or
comparator OSR (COSR) settings—are dynamically changed during run time, spurious
comparator events will be triggered. The spurious comparator event will trigger a
corresponding CPU interrupt, CLA task, ePWM X-BAR events, and GPIO output X-BAR
events if configured appropriately.
Workaround When comparator settings need to be changed dynamically, follow the procedure below to
ensure spurious comparator events do not generate a CPU interrupt, CLA task, or
X-BAR events (ePWM X-BAR/GPIO output X-BAR events):
1. Disable the comparator filter.
2. Delay for at least a latency of the comparator filter + 3 SD-Cx clock cycles.
3. Change comparator filter settings such as filter type, COSR, or lower/upper threshold.
4. Delay for at least a latency of the comparator filter + 5 SD-Cx clock cycles.
5. Enable the comparator filter.
Advisory SDFM: Dynamically Changing Data Filter Settings (Such as Filter Type or DOSR)
Will Trigger Spurious Data Acknowledge Events
Revisions Affected 0, A, B
Details When SDFM data settings—such as filter type or DOSR settings—are dynamically
changed during run time, spurious data-filter-ready events will be triggered. The spurious
data-ready event will trigger a corresponding CPU interrupt, CLA task, and DMA trigger if
configured appropriately.
Workaround When SDFM data filter settings need to be changed dynamically, follow the procedure
below to ensure spurious data-filter-ready events are not generated:
1. Disable the data filter.
2. Delay for at least a latency of the data filter + 3 SD-Cx clock cycles.
3. Change data filter settings such as filter type and DOSR.
4. Delay for at least a latency of the data filter + 5 SD-Cx clock cycles.
5. Enable the data filter.
Advisory SDFM: Two Back-to-Back Writes to SDCPARMx Register Bit Fields CEVT1SEL,
CEVT2SEL, and HZEN Within Three SD-Modulator Clock Cycles can Corrupt SDFM
State Machine, Resulting in Spurious Comparator Events
Revisions Affected 0, A, B
Details Back-to-back writes to SDCPARMx register bit fields CEVT1SEL, CEVT2SEL, and HZEN
within three SD-modulator clock cycles can potentially corrupt the SDFM state machine,
resulting in spurious comparator events, which can potentially trigger CPU interrupts, CLA
tasks, ePWM XBAR events, and GPIO output X-BAR events if configured appropriately.
Workaround Avoid back-to-back writes within three SD-modulator clock cycles or have the SDCPARMx
register bit fields configured in one register write.
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Advisory SDFM: Manchester Mode (Mode 2) Does Not Produce Correct Filter Results Under
Several Conditions
Revisions Affected 0, A, B
Details The Manchester decoding algorithm samples the Manchester bitstream with SYSCLK
in a calibration window of 1024 SDx_Dy signal transitions. The derived clock from the
Manchester bitstream is used to sample for data in the subsequent calibration window
cycle.
There are several scenarios that can cause large errors in the filter results:
• Any single noise event on SDx_Dy can corrupt the decoded Manchester clock and
cause subsequent data to be sampled at an incorrect frequency.
• If the Manchester bitstream clock rate is a near exact integer multiple of SYSCLK,
then an occasional Manchester bit can be skipped when the phases of the Manchester
stream and internal SYSCLK drift past each other in phase before the next 1024
transition calibration window becomes effective. Deviations in duty cycle from 50% of
the Manchester clock also need to be accounted for to ensure the longer Manchester
pulses are not an integer multiple of SYSCLK. This situation can be unavoidable if the
clock sources for either the SD modulator or this device have a wide variation since a
wide range of keep out frequencies become problematic
• If the Manchester edge delay variation between rising and falling (duty cycle of the
bitstream) is greater than one SYSCLK, then the SDFM clock decode algorithm can
incorrectly identify the clock period as shorter than it is.
Workarounds The workarounds available are:
• Avoid using Manchester mode and consider using Mode 0, which provides the best
filter performance under noisy conditions. This is the recommended workaround.
• Avoid any noise on the Manchester bitstream and avoid integer multiples of SYSCLK
for the selected Manchester clock source. A precision clock source for the modulator
and this device must be used.
• Ensure rising and falling edge delays (high and low pulses) are within one SYSCLK of
each other in length.
• Design an application-level algorithm that is robust against occasional incorrect SDFM
results.
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Advisory eQEP: Position Counter Incorrectly Reset on Direction Change During Index
Revisions Affected 0, A, B
Details While using the PCRM = 0 configuration, if the direction change occurs when the index
input is active, the position counter (QPOSCNT) could be reset erroneously, resulting
in an unexpected change in the counter value. This could result in a change of up
to ±4 counts from the expected value of the position counter and lead to unexpected
subsequent setting of the error flags.
While using the PCRM = 0 configuration [that is, Position Counter Reset on Index Event
(QEPCTL[PCRM] = 00)], if the index event occurs during the forward movement, then
the position counter is reset to 0 on the next eQEP clock. If the index event occurs
during the reverse movement, then the position counter is reset to the value in the
QPOSMAX register on the next eQEP clock. The eQEP peripheral records the occurrence
of the first index marker (QEPSTS[FIMF]) and direction on the first index event marker
(QEPSTS[FIDF]) in QEPSTS registers. It also remembers the quadrature edge on the
first index marker so that same relative quadrature transition is used for index event reset
operation.
If the direction change occurs while the index pulse is active, the module would still
continue to look for the relative quadrature transition for performing the position counter
reset. This results in an unexpected change in the position counter value.
The next index event without a simultaneous direction change will reset the counter
properly and work as expected.
Workaround Do not use the PCRM = 0 configuration if the direction change could occur while the
index is active and the resultant change of the position counter value could affect the
application.
Other options for performing position counter reset, if appropriate for the application [such
as Index Event Initialization (IEI)], do not have this issue.
Advisory eQEP: eQEP Inputs in GPIO Asynchronous Mode
Revisions Affected 0, A, B
Details If any of the eQEP input pins are configured for GPIO asynchronous input mode via the
GPxQSELn registers, the eQEP module may not operate properly because the eQEP
peripheral assumes the presence of external synchronization to SYSCLKOUT on inputs to
the module. For example, QPOSCNT may not reset or latch properly, and pulses on the
input pins may be missed.
For proper operation of the eQEP module, input GPIO pins should be configured via the
GPxQSELn registers for synchronous input mode (with or without qualification), which
is the default state of the GPxQSEL registers at reset. All existing eQEP peripheral
examples supplied by TI also configure the GPIO inputs for synchronous input mode.
The asynchronous mode should not be used for eQEP module input pins.
Workaround Configure GPIO inputs configured as eQEP pins for non-asynchronous mode (any
GPxQSELn register option except “11b = Asynchronous”).
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Advisory VDD Supply: During VDDIO Power Up, VDD May Also Rise
Revisions Affected 0, A, B
Details A leakage current from VDDIO to VDD is present when the VDD supply is below
approximately 0.5 V. This causes the VDD voltage to rise to approximately 0.5 V when
VDDIO is powered. This is observed when the device is configured to use either the
internal VREG (VREGENZ tied to VSS) or an external 1.2-V regulator (VREGENZ tied
to VDDIO), and there is a significant delay (about 1 ms) between the power up of VDDIO
and VDD from external regulators or the ramp time of VDDIO is greater than 1 ms when in
internal VREG mode.
This does not impact device functionality once the external 1.2-V or internal 1.2-V supply
begins to ramp. See the TMS320F28004x Real-Time Microcontrollers data sheet for
power sequencing requirements.
Workaround If this early voltage on VDD is a problem for system-level supervisor circuits, then minimize
the delay between ramping the 3.3-V VDDIO and 1.2-V VDD rails. If the internal VREG is
used, decrease the ramp time of the 3.3-V VDDIO supply to 1 ms or less.
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Advisory eCAP: HRFRC is Not EALLOW-Protected
Revisions Affected 0, A, B
Details The HRFRC register is not EALLOW-protected. Issuing the EALLOW and EDIS
instructions to write to this register is not required. To enable software reuse on
other devices where HRFRC is EALLOW-protected, using EALLOW and EDIS is
recommended.
Workaround None
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Advisory PLL: PLL May Not Lock on the First Lock Attempt
Revisions Affected 0, A, B
Details The PLL may not start properly at device power up. The PLLSTS[LOCKS] bit is set, but
the PLL does not produce a clock.
Once the PLL has started properly, the PLL can be disabled and reenabled with no issues
and will stay locked. However, the PLL lock problem could reoccur on a subsequent
power-up cycle.
If the SYSPLL has not started properly and is selected as the CPU clock source, the CPU
will stop executing instructions.
The occurrence rate of this transient issue is low. After an initial occurrence, this
issue may not be subsequently observed in the system again. Implementation of the
workaround reduces the rate of occurrence.
Workaround TI recommends doing lock sequences in succession until the PLL is in locked state when
the PLL is configured for the first time after power up. The lock sequence is: disable the
PLL, start the PLL, wait for the LOCKS bit to set, and validate the PLL frequency using the
Dual Clock Comparator (DCC). After the PLL is observed to be running, it can be selected
as the CPU clock source.
TI recommends using the C2000Ware SysCtl_setClock() function, which also includes
implementation of this workaround, to set the PLL clock.
Details on DCC usage are in the C2000Ware SysCtl_IsPLLValid() function.
The workaround can also be applied at the system level by a supervisor resetting the
device if it is not responding.
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Advisory LPM: STANDBY Low-Power Mode is Not Supported
Revisions Affected 0, A, B
Details The STANDBY low-power mode is not supported.
Workaround The IDLE or HALT low-power modes can be used for power reduction. See the
TMS320F28004x Real-Time Microcontrollers Technical Reference Manual for information
on implementing these modes.
If IDLE is used, additional power reduction can be optionally achieved through software by
one or all of these methods:
• Decrease the SYSCLK frequency:
– Change the SYSCLK source to OSCCLK by configuring SYSPLLCTL1[PLLCLKEN]
= 0.
– Change the SYSCLKDIVSEL register to a higher divider.
• Disable peripheral clocks through the PCLKCRx register.
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Advisory DCC: Single-Shot-Mode Operation May End Prematurely
Revisions Affected 0, A, B
Details In single-shot mode, DCCSTATUS[DONE] or DCCSTATUS[ERROR] may be prematurely
set. When this occurs, DCC results are invalid.
Workaround Any of the following conditions ends DCC operation prematurely. TI recommends
rerunning DCC if any of the below conditions are met.
• DCCSTATUS[DONE] = 1 and (DCCCNT1 > 0 or DCCCNT0 > 0 or DCCVALID0 > 0)
• DCCSTATUS[ERROR] = 1 and DCCCNT1 > 0 and DCCVALID0 > 0
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