Texas Instruments RM48 series Product manual

RM48x 16/32-Bit RISC Flash Microcontroller
Technical Reference Manual
Literature Number: SPNU503C
March 2018

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Contents
Contents
Preface....................................................................................................................................... 87
1 Introduction....................................................................................................................... 89
1.1 Designed for Safety Applications......................................................................................... 90
1.2 Family Description.......................................................................................................... 90
1.3 Endianism Considerations ................................................................................................ 93
1.3.1 RM48x: Little Endian (LE)........................................................................................ 93
2 Architecture....................................................................................................................... 94
2.1 Introduction.................................................................................................................. 95
2.1.1 Architecture Block Diagram...................................................................................... 95
2.1.2 Definitions of Terms............................................................................................... 96
2.1.3 Bus Master / Slave Access Privileges.......................................................................... 98
2.2 Memory Organization...................................................................................................... 99
2.2.1 Memory-Map Overview........................................................................................... 99
2.2.2 Memory-Map Table.............................................................................................. 100
2.2.3 Flash Memory .................................................................................................... 104
2.2.4 On-Chip SRAM................................................................................................... 106
2.3 Exceptions................................................................................................................. 111
2.3.1 Resets............................................................................................................. 111
2.3.2 Aborts ............................................................................................................. 111
2.3.3 System Software Interrupts..................................................................................... 113
2.4 Clocks ...................................................................................................................... 114
2.4.1 Clock Sources.................................................................................................... 114
2.4.2 Clock Domains................................................................................................... 115
2.4.3 Low Power Modes............................................................................................... 117
2.4.4 Clock Test Mode................................................................................................. 119
2.4.5 Embedded Trace Macrocell (ETM-R4)........................................................................ 120
2.4.6 Safety Considerations for Clocks.............................................................................. 121
2.5 System and Peripheral Control Registers ............................................................................. 123
2.5.1 Primary System Control Registers (SYS) .................................................................... 123
2.5.2 Secondary System Control Registers (SYS2) ............................................................... 176
2.5.3 Peripheral Central Resource (PCR) Control Registers .................................................... 185
3 Power Management Module (PMM) ..................................................................................... 200
3.1 Overview................................................................................................................... 201
3.1.1 Main Features of the Power Management Module (PMM)................................................. 201
3.1.2 Block Diagram.................................................................................................... 201
3.2 Power Domains ........................................................................................................... 202
3.3 PMM Operation ........................................................................................................... 204
3.3.1 Power Switch..................................................................................................... 204
3.3.2 Power Domain State ............................................................................................ 204
3.3.3 Default Power Domain State................................................................................... 204
3.3.4 Disabling a Power Domain Permanently ..................................................................... 204
3.3.5 Changing Power Domain State................................................................................ 204
3.3.6 Reset Management.............................................................................................. 205
3.3.7 Diagnostic Power State Controller (PSCON) ................................................................ 205
3.3.8 PSCON Compare Block ........................................................................................ 205

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3.4 PMM Registers............................................................................................................ 207
3.4.1 Logic Power Domain Control Register (LOGICPDPWRCTRL0) .......................................... 208
3.4.2 Memory Power Domain Control Register 0 (MEMPDPWRCTRL0)....................................... 209
3.4.3 Power Domain Clock Disable Register (PDCLKDISREG) ................................................. 210
3.4.4 Power Domain Clock Disable Set Register (PDCLKDISSETREG) ...................................... 211
3.4.5 Power Domain Clock Disable Clear Register (PDCLKDISCLRREG)..................................... 212
3.4.6 Logic Power Domain PD2 Power Status Register (LOGICPDPWRSTAT0)............................. 213
3.4.7 Logic Power Domain PD3 Power Status Register (LOGICPDPWRSTAT1)............................. 214
3.4.8 Logic Power Domain PD4 Power Status Register (LOGICPDPWRSTAT2)............................. 215
3.4.9 Logic Power Domain PD5 Power Status Register (LOGICPDPWRSTAT3)............................. 216
3.4.10 Memory Power Domain RAM_PD1 Power Status Register (MEMPDPWRSTAT0) ................... 217
3.4.11 Memory Power Domain RAM_PD2 Power Status Register (MEMPDPWRSTAT1) ................... 218
3.4.12 Memory Power Domain RAM_PD3 Power Status Register (MEMPDPWRSTAT2) ................... 219
3.4.13 Global Control Register 1 (GLOBALCTRL1)................................................................ 220
3.4.14 Global Status Register (GLOBALSTAT)..................................................................... 221
3.4.15 PSCON Diagnostic Compare Key Register (PRCKEYREG) ............................................. 221
3.4.16 LogicPD PSCON Diagnostic Compare Status Register 1 (LPDDCSTAT1)............................. 222
3.4.17 LogicPD PSCON Diagnostic Compare Status Register 2 (LPDDCSTAT2)............................. 223
3.4.18 Memory PD PSCON Diagnostic Compare Status Register 1 (MPDDCSTAT1)........................ 224
3.4.19 Memory PD PSCON Diagnostic Compare Status Register 2 (MPDDCSTAT2)........................ 225
3.4.20 Isolation Diagnostic Status Register (ISODIAGSTAT)..................................................... 226
4 I/O Multiplexing and Control Module (IOMM) ........................................................................ 227
4.1 Overview .................................................................................................................. 228
4.2 Main Features of I/O Multiplexing Module (IOMM) .................................................................. 228
4.3 Control of Multiplexed Functions ....................................................................................... 228
4.3.1 Control of Multiplexed Outputs ................................................................................ 228
4.3.2 Control of Multiplexed Inputs .................................................................................. 229
4.3.3 Control of Special Multiplexed Options ...................................................................... 231
4.4 Safety Features .......................................................................................................... 232
4.4.1 Locking Mechanism for Memory-Mapped Registers ....................................................... 232
4.4.2 Error Conditions ................................................................................................. 232
4.5 IOMM Registers........................................................................................................... 233
4.5.1 REVISION_REG: Revision Register ......................................................................... 233
4.5.2 ENDIAN_REG: Device Endianness Register ............................................................... 234
4.5.3 KICK_REG0: Kicker Register 0 ............................................................................... 235
4.5.4 KICK_REG1: Kicker Register 1 ............................................................................... 235
4.5.5 ERR_RAW_STATUS_REG: Error Raw Status / Set Register ............................................ 236
4.5.6 ERR_ENABLED_STATUS_REG: Error Enabled Status / Clear Register ............................... 237
4.5.7 ERR_ENABLE_REG: Error Signaling Enable Register .................................................... 238
4.5.8 ERR_ENABLE_CLR_REG: Error Signaling Enable Clear Register ...................................... 239
4.5.9 FAULT_ADDRESS_REG: Fault Address Register.......................................................... 239
4.5.10 FAULT_STATUS_REG: Fault Status Register ............................................................ 240
4.5.11 FAULT_CLEAR_REG: Fault Clear Register ............................................................... 241
4.5.12 PINMMRnn: Pin Multiplexing Control Registers ........................................................... 241
4.6 Signal Multiplexing and Control......................................................................................... 242
5 F021 Flash Module Controller (FMC) ................................................................................... 246
5.1 Overview .................................................................................................................. 247
5.1.1 Features .......................................................................................................... 247
5.1.2 Definition of Terms .............................................................................................. 247
5.1.3 F021 Flash Tools ................................................................................................ 248
5.2 Default Flash Configuration ............................................................................................. 248
5.3 SECDED .................................................................................................................. 249
5.3.1 SECDED Initialization ........................................................................................... 249

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5.3.2 ECC Encoding.................................................................................................... 250
5.3.3 Syndrome Table: Decode to Bit in Error...................................................................... 251
5.3.4 Syndrome Table: An Alternate Method ....................................................................... 252
5.4 Memory Map .............................................................................................................. 253
5.4.1 Location of Flash ECC Bits..................................................................................... 253
5.4.2 OTP Memory ..................................................................................................... 254
5.5 Power On, Power Off, and Reset Considerations ................................................................... 256
5.5.1 Error Checking at Power On ................................................................................... 256
5.5.2 Flash Integrity when Reset while Programming or Erasing................................................ 256
5.5.3 Flash Integrity at Power Off .................................................................................... 257
5.6 Emulation and SIL3 Diagnostic Modes ................................................................................ 257
5.6.1 System Emulation ............................................................................................... 257
5.6.2 Diagnostic Mode ................................................................................................. 257
5.6.3 Diagnostic Mode Summary..................................................................................... 262
5.6.4 Read Margin...................................................................................................... 263
5.7 Control Registers ......................................................................................................... 263
5.7.1 Flash Option Control Register (FRDCNTL) .................................................................. 265
5.7.2 Flash Error Detection and Correction Control Register 1 (FEDACCTRL1) ............................. 266
5.7.3 Flash Error Correction and Correction Control Register 2 (FEDACCTRL2) ............................ 268
5.7.4 Flash Correctable Error Count Register (FCOR_ERR_CNT) ............................................. 268
5.7.5 Flash Correctable Error Address Register (FCOR_ERR_ADD) .......................................... 269
5.7.6 Flash Correctable Error Position Register (FCOR_ERR_POS) .......................................... 270
5.7.7 Flash Error Detection and Correction Status Register (FEDACSTATUS) ............................... 271
5.7.8 Flash Uncorrectable Error Address Register (FUNC_ERR_ADD) ....................................... 274
5.7.9 Flash Error Detection and Correction Sector Disable Register (FEDACSDIS) ......................... 275
5.7.10 Primary Address Tag Register (FPRIM_ADD_TAG) ...................................................... 276
5.7.11 Duplicate Address Tag Register (FDUP_ADD_TAG) ..................................................... 276
5.7.12 Flash Bank Protection Register (FBPROT) ................................................................ 277
5.7.13 Flash Bank Sector Enable Register (FBSE) ................................................................ 277
5.7.14 Flash Bank Busy Register (FBBUSY) ....................................................................... 278
5.7.15 Flash Bank Access Control Register (FBAC) .............................................................. 279
5.7.16 Flash Bank Fallback Power Register (FBFALLBACK) .................................................... 280
5.7.17 Flash Bank/Pump Ready Register (FBPRDY) ............................................................. 281
5.7.18 Flash Pump Access Control Register 1 (FPAC1) ......................................................... 282
5.7.19 Flash Pump Access Control Register 2 (FPAC2) ......................................................... 283
5.7.20 Flash Module Access Control Register (FMAC) ........................................................... 283
5.7.21 Flash Module Status Register (FMSTAT) .................................................................. 284
5.7.22 EEPROM Emulation Data MSW Register (FEMU_DMSW)............................................... 286
5.7.23 EEPROM Emulation Data LSW Register (FEMU_DLSW) ................................................ 286
5.7.24 EEPROM Emulation ECC Register (FEMU_ECC)......................................................... 287
5.7.25 EEPROM Emulation Address Register (FEMU_ADDR)................................................... 288
5.7.26 Diagnostic Control Register (FDIAGCTRL) ................................................................. 289
5.7.27 Uncorrected Raw Data High Register (FRAW_DATAH) .................................................. 291
5.7.28 Uncorrected Raw Data Low Register (FRAW_DATAL) ................................................... 291
5.7.29 Uncorrected Raw ECC Register (FRAW_ECC) ............................................................ 292
5.7.30 Parity Override Register (FPAR_OVR) ...................................................................... 293
5.7.31 Flash Error Detection and Correction Sector Disable Register (FEDACSDIS2) ...................... 294
5.7.32 FSM Register Write Enable (FSM_WR_ENA) ............................................................. 295
5.7.33 FSM Sector Register (FSM_SECTOR) ..................................................................... 295
5.7.34 EEPROM Emulation Configuration Register (EEPROM_CONFIG) ..................................... 296
5.7.35 EEPROM Emulation Error Detection and Correction Control Register 1 (EE_CTRL1) .............. 297
5.7.36 EEPROM Emulation Error Correction and Correction Control Register 2 (EE_CTRL2) ............. 299
5.7.37 EEPROM Emulation Correctable Error Count Register (EE_COR_ERR_CNT) ....................... 299

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5.7.38 EEPROM Emulation Correctable Error Address Register (EE_COR_ERR_ADD) .................... 300
5.7.39 EEPROM Emulation Correctable Error Position Register (EE_COR_ERR_POS) .................... 301
5.7.40 EEPROM Emulation Error Status Register (EE_STATUS) .............................................. 302
5.7.41 EEPROM Emulation Uncorrectable Error Address Register (EE_UNC_ERR_ADD) ................. 303
5.7.42 Flash Bank Configuration Register (FCFG_BANK) ....................................................... 304
6 Tightly-Coupled RAM (TCRAM) Module ............................................................................... 305
6.1 Overview................................................................................................................... 306
6.1.1 B0TCM and B1TCM Connection Diagram ................................................................... 306
6.1.2 Main Features.................................................................................................... 306
6.2 RAM Memory Map........................................................................................................ 307
6.3 Safety Features ........................................................................................................... 308
6.3.1 Support for Cortex-R4F CPU's Single-Error-Correction Double-Error-Detection (SECDED).......... 308
6.3.2 Support for Cortex-R4F CPU's Address and Control Bus Parity Checking.............................. 309
6.3.3 Redundant Address Decode ................................................................................... 309
6.4 TCRAM Auto-Initialization ............................................................................................... 309
6.5 Trace Module Support ................................................................................................... 310
6.6 Emulation / Debug Mode Behavior..................................................................................... 310
6.7 Control and Status Registers............................................................................................ 310
6.7.1 TCRAM Module Control Register (RAMCTRL).............................................................. 311
6.7.2 TCRAM Module Single-Bit Error Correction Threshold Register (RAMTHRESHOLD)................. 312
6.7.3 TCRAM Module Single-Bit Error Occurrences Counter Register (RAMOCCUR)....................... 313
6.7.4 TCRAM Module Interrupt Control Register (RAMINTCTRL)............................................... 313
6.7.5 TCRAM Module Error Status Register (RAMERRSTATUS)............................................... 314
6.7.6 TCRAM Module Single-Bit Error Address Register (RAMSERRADDR).................................. 315
6.7.7 TCRAM Module Uncorrectable Error Address Register (RAMUERRADDR) ............................ 316
6.7.8 TCRAM Module Test Mode Control Register (RAMTEST)................................................. 317
6.7.9 TCRAM Module Test Mode Vector Register (RAMADDRDECVECT).................................... 318
6.7.10 TCRAM Module Parity Error Address Register (RAMPERRADDR) ..................................... 318
6.7.11 Auto-Memory Initialization Enable Register (INIT_DOMAIN)............................................. 319
7 Programmable Built-In Self-Test (PBIST) Module.................................................................. 320
7.1 Overview .................................................................................................................. 321
7.1.1 Features of PBIST .............................................................................................. 321
7.1.2 PBIST vs. Application Software-Based Testing.............................................................. 321
7.1.3 PBIST Block Diagram .......................................................................................... 321
7.2 RAM Grouping and Algorithm .......................................................................................... 322
7.3 PBIST Flow ............................................................................................................... 323
7.3.1 PBIST Sequence ................................................................................................ 324
7.4 Memory Test Algorithms on the On-chip ROM ...................................................................... 325
7.5 PBIST Control Registers ................................................................................................ 327
7.5.1 RAM Configuration Register (RAMT) ......................................................................... 328
7.5.2 Datalogger Register (DLR) ..................................................................................... 329
7.5.3 PBIST Activate/Clock Enable Register (PACT).............................................................. 330
7.5.4 PBIST ID Register ............................................................................................... 331
7.5.5 Override Register (OVER)...................................................................................... 332
7.5.6 Fail Status Fail Register (FSRF0) ............................................................................. 333
7.5.7 Fail Status Count Registers (FSRC0 and FSRC1).......................................................... 334
7.5.8 Fail Status Address Registers (FSRA0 and FSRA1) ....................................................... 335
7.5.9 Fail Status Data Registers (FSRDL0 and FSRDL1) ........................................................ 336
7.5.10 ROM Mask Register (ROM)................................................................................... 337
7.5.11 ROM Algorithm Mask Register (ALGO) ..................................................................... 337
7.5.12 RAM Info Mask Lower Register (RINFOL) .................................................................. 338
7.5.13 RAM Info Mask Upper Register (RINFOU).................................................................. 339
7.6 PBIST Configuration Example .......................................................................................... 340

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7.6.1 Example 1 : Configuration of PBIST Controller to Run Self-Test on RAM Group 3 .................... 340
7.6.2 Example 2 : Configuration of PBIST Controller to Run Self-Test on ALL RAM Groups................ 341
8 CPU Self-Test Controller (STC) Module ............................................................................... 342
8.1 General Description ...................................................................................................... 343
8.1.1 CPU Self-Test Controller Features............................................................................ 343
8.1.2 STC Block Diagram ............................................................................................. 343
8.2 Application Self-Test Flow............................................................................................... 345
8.2.1 STC Module Configuration ..................................................................................... 345
8.2.2 Context Saving................................................................................................... 345
8.2.3 Entering CPU Idle Mode........................................................................................ 345
8.2.4 Self-Test Completion and Error Generation.................................................................. 346
8.3 STC Test Coverage and Duration...................................................................................... 347
8.4 STC Control Registers ................................................................................................... 348
8.4.1 STC Global Control Register 0 (STCGCR0) ................................................................. 349
8.4.2 STC Global Control Register 1 (STCGCR1) ................................................................. 349
8.4.3 Self-Test Run Timeout Counter Preload Register (STCTPR) ............................................. 350
8.4.4 STC Current ROM Address Register (STC_CADDR) ...................................................... 350
8.4.5 STC Current Interval Count Register (STCCICR)........................................................... 351
8.4.6 Self-Test Global Status Register (STCGSTAT).............................................................. 352
8.4.7 Self-Test Fail Status Register (STCFSTAT) ................................................................. 353
8.4.8 CPU1 Current MISR Register (CPU1_CURMISR[3:0])..................................................... 354
8.4.9 CPU2_CURMISR[3:0] (CPU2 Current MISR Register)..................................................... 355
8.4.10 STCSCSCR (Signature Compare Self-Check Register) .................................................. 356
8.5 STC Configuration Example ............................................................................................ 357
8.5.1 Example 1: Self-Test Run for 24 Interval .................................................................... 357
9 CPU Compare Module for Cortex-R4F (CCM-R4F)................................................................. 358
9.1 Main Features............................................................................................................. 359
9.2 Block Diagram............................................................................................................. 359
9.3 Module Operation......................................................................................................... 360
9.3.1 1oo1D Lock Step Mode......................................................................................... 360
9.3.2 Self-Test Mode................................................................................................... 360
9.3.3 Error Forcing Mode.............................................................................................. 362
9.3.4 Self-Test Error Forcing Mode .................................................................................. 362
9.3.5 Operation During CPU Debug Mode.......................................................................... 363
9.4 CCM-R4F Control Registers ............................................................................................ 363
9.4.1 CCM-R4F Status Register (CCMSR) ......................................................................... 364
9.4.2 CCM-R4F Key Register (CCMKEYR)......................................................................... 365
10 Oscillator and PLL ........................................................................................................... 366
10.1 Introduction ................................................................................................................ 367
10.1.1 Features.......................................................................................................... 367
10.2 Quick Start................................................................................................................. 368
10.3 Oscillator................................................................................................................... 369
10.3.1 Oscillator Implementation...................................................................................... 370
10.3.2 Oscillator Enable................................................................................................ 370
10.3.3 Oscillator Disable ............................................................................................... 370
10.4 Low-Power Oscillator and Clock Detect (LPOCLKDET)............................................................. 371
10.4.1 Clock Detect..................................................................................................... 371
10.4.2 Behavior on Oscillator Failure................................................................................. 371
10.4.3 Recovery from Oscillator Failure ............................................................................. 372
10.4.4 LPOCLKDET Enable........................................................................................... 372
10.4.5 LPOCLKDET Disable .......................................................................................... 373
10.4.6 Trimming the HF LPO Oscillator.............................................................................. 373
10.5 PLL ......................................................................................................................... 374

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10.5.1 Modulation....................................................................................................... 376
10.5.2 PLL Output Control............................................................................................. 377
10.5.3 Behavior on PLL Fail........................................................................................... 380
10.5.4 Recovery from a PLL Failure.................................................................................. 381
10.5.5 PLL Modulation Depth Measurement........................................................................ 382
10.5.6 PLL Frequency Measurement Circuit ........................................................................ 383
10.5.7 PLL2.............................................................................................................. 383
10.6 PLL Control Registers.................................................................................................... 384
10.6.1 PLL Modulation Depth Measurement Control Register (SSWPLL1)..................................... 385
10.6.2 SSW PLL BIST Control Register 2 (SSWPLL2)............................................................ 386
10.6.3 SSW PLL BIST Control Register 3 (SSWPLL3)............................................................ 387
10.7 Phase-Locked Loop Theory of Operation ............................................................................. 388
10.7.1 Phase-Frequency Detector.................................................................................... 388
10.7.2 Charge Pump and Loop Filter................................................................................. 389
10.7.3 Voltage-Controlled Oscillator.................................................................................. 389
10.7.4 Frequency Modulation ......................................................................................... 390
10.8 Programming Example................................................................................................... 390
11 Dual-Clock Comparator (DCC) Module ................................................................................ 392
11.1 Introduction ................................................................................................................ 393
11.1.1 Main Features................................................................................................... 393
11.1.2 Block Diagram................................................................................................... 393
11.2 Module Operation......................................................................................................... 394
11.2.1 Continuous Monitoring Mode.................................................................................. 394
11.2.2 Single-Shot Measurement Mode ............................................................................. 397
11.3 Clock Source Selection for Counter0 and Counter1 ................................................................. 398
11.4 DCC Control Registers................................................................................................... 399
11.4.1 DCC Global Control Register (DCCGCTRL) ............................................................... 400
11.4.2 DCC Revision Id Register (DCCREV) ...................................................................... 401
11.4.3 DCC Counter0 Seed Register (DCCCNT0SEED) ......................................................... 401
11.4.4 DCC Valid0 Seed Register (DCCVALID0SEED) .......................................................... 402
11.4.5 DCC Counter1 Seed Register (DCCCNT1SEED) ......................................................... 402
11.4.6 DCC Status Register (DCCSTAT) ........................................................................... 403
11.4.7 DCC Counter0 Value Register (DCCCNT0) ................................................................ 404
11.4.8 DCC Valid0 Value Register (DCCVALID0) ................................................................. 405
11.4.9 DCC Counter1 Value Register (DCCCNT1) ................................................................ 405
11.4.10 DCC Counter1 Clock Source Selection Register (DCCCNT1CLKSRC) .............................. 406
11.4.11 DCC Counter0 Clock Source Selection Register (DCCCNT0CLKSRC) .............................. 407
12 Error Signaling Module (ESM) ........................................................................................... 408
12.1 Overview .................................................................................................................. 409
12.1.1 Features.......................................................................................................... 409
12.1.2 Block Diagram .................................................................................................. 409
12.2 Module Operation ........................................................................................................ 411
12.2.1 Reset Behavior ................................................................................................. 411
12.2.2 ERROR Pin Timing ............................................................................................ 412
12.2.3 Forcing an Error Condition .................................................................................... 414
12.3 Recommended Programming Procedure ............................................................................. 415
12.4 Control Registers ......................................................................................................... 416
12.4.1 ESM Enable ERROR Pin Action/Response Register 1 (ESMEEPAPR1)............................... 417
12.4.2 ESM Disable ERROR Pin Action/Response Register 1 (ESMDEPAPR1).............................. 417
12.4.3 ESM Interrupt Enable Set Register 1 (ESMIESR1)........................................................ 418
12.4.4 ESM Interrupt Enable Clear Register 1 (ESMIECR1) ..................................................... 418
12.4.5 ESM Interrupt Level Set Register 1 (ESMILSR1) .......................................................... 419
12.4.6 ESM Interrupt Level Clear Register 1 (ESMILCR1)........................................................ 419

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12.4.7 ESM Status Register 1 (ESMSR1)........................................................................... 420
12.4.8 ESM Status Register 2 (ESMSR2)........................................................................... 420
12.4.9 ESM Status Register 3 (ESMSR3)........................................................................... 421
12.4.10 ESM ERROR Pin Status Register (ESMEPSR) .......................................................... 421
12.4.11 ESM Interrupt Offset High Register (ESMIOFFHR) ...................................................... 422
12.4.12 ESM Interrupt Offset Low Register (ESMIOFFLR) ....................................................... 423
12.4.13 ESM Low-Time Counter Register (ESMLTCR) ........................................................... 424
12.4.14 ESM Low-Time Counter Preload Register (ESMLTCPR)................................................ 424
12.4.15 ESM Error Key Register (ESMEKR)........................................................................ 425
12.4.16 ESM Status Shadow Register 2 (ESMSSR2) ............................................................. 425
12.4.17 ESM Influence ERROR Pin Set Register 4 (ESMIEPSR4) ............................................. 426
12.4.18 ESM Influence ERROR Pin Clear Register 4 (ESMIEPCR4) .......................................... 426
12.4.19 ESM Interrupt Enable Set Register 4 (ESMIESR4) ...................................................... 427
12.4.20 ESM Interrupt Enable Clear Register 4 (ESMIECR4) ................................................... 427
12.4.21 ESM Interrupt Level Set Register 4 (ESMILSR4) ........................................................ 428
12.4.22 ESM Interrupt Level Clear Register 4 (ESMILCR4) ..................................................... 428
12.4.23 ESM Status Register 4 (ESMSR4) ......................................................................... 429
13 Real-Time Interrupt (RTI) Module........................................................................................ 430
13.1 Overview................................................................................................................... 431
13.1.1 Features.......................................................................................................... 431
13.1.2 Industry Standard Compliance Statement................................................................... 431
13.2 Module Operation......................................................................................................... 432
13.2.1 Counter Operation.............................................................................................. 432
13.2.2 Interrupt/DMA Requests ....................................................................................... 434
13.2.3 RTI Clocking..................................................................................................... 435
13.2.4 Synchronizing Timer Events to Network Time (NTU)...................................................... 435
13.2.5 Digital Watchdog (DWD)....................................................................................... 438
13.2.6 Low Power Modes.............................................................................................. 441
13.2.7 Halting Debug Mode Behaviour............................................................................... 441
13.3 RTI Control Registers .................................................................................................... 442
13.3.1 RTI Global Control Register (RTIGCTRL)................................................................... 443
13.3.2 RTI Timebase Control Register (RTITBCTRL) ............................................................. 444
13.3.3 RTI Capture Control Register (RTICAPCTRL).............................................................. 445
13.3.4 RTI Compare Control Register (RTICOMPCTRL) ......................................................... 446
13.3.5 RTI Free Running Counter 0 Register (RTIFRC0) ......................................................... 447
13.3.6 RTI Up Counter 0 Register (RTIUC0)........................................................................ 447
13.3.7 RTI Compare Up Counter 0 Register (RTICPUC0)........................................................ 448
13.3.8 RTI Capture Free Running Counter 0 Register (RTICAFRC0)........................................... 448
13.3.9 RTI Capture Up Counter 0 Register (RTICAUC0).......................................................... 449
13.3.10 RTI Free Running Counter 1 Register (RTIFRC1)........................................................ 449
13.3.11 RTI Up Counter 1 Register (RTIUC1) ...................................................................... 450
13.3.12 RTI Compare Up Counter 1 Register (RTICPUC1)....................................................... 451
13.3.13 RTI Capture Free Running Counter 1 Register (RTICAFRC1) ......................................... 452
13.3.14 RTI Capture Up Counter 1 Register (RTICAUC1)........................................................ 452
13.3.15 RTI Compare 0 Register (RTICOMP0)..................................................................... 453
13.3.16 RTI Update Compare 0 Register (RTIUDCP0)............................................................ 453
13.3.17 RTI Compare 1 Register (RTICOMP1)..................................................................... 454
13.3.18 RTI Update Compare 1 Register (RTIUDCP1)............................................................ 454
13.3.19 RTI Compare 2 Register (RTICOMP2)..................................................................... 455
13.3.20 RTI Update Compare 2 Register (RTIUDCP2)............................................................ 455
13.3.21 RTI Compare 3 Register (RTICOMP3)..................................................................... 456
13.3.22 RTI Update Compare 3 Register (RTIUDCP3)............................................................ 456
13.3.23 RTI Timebase Low Compare Register (RTITBLCOMP) ................................................. 457

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13.3.24 RTI Timebase High Compare Register (RTITBHCOMP) ................................................ 457
13.3.25 RTI Set Interrupt Enable Register (RTISETINTENA) .................................................... 458
13.3.26 RTI Clear Interrupt Enable Register (RTICLEARINTENA) .............................................. 460
13.3.27 RTI Interrupt Flag Register (RTIINTFLAG) ................................................................ 462
13.3.28 Digital Watchdog Control Register (RTIDWDCTRL) ..................................................... 463
13.3.29 Digital Watchdog Preload Register (RTIDWDPRLD)..................................................... 464
13.3.30 Watchdog Status Register (RTIWDSTATUS) ............................................................. 465
13.3.31 RTI Watchdog Key Register (RTIWDKEY) ................................................................ 466
13.3.32 RTI Digital Watchdog Down Counter (RTIDWDCNTR) .................................................. 467
13.3.33 Digital Windowed Watchdog Reaction Control (RTIWWDRXNCTRL) ................................. 467
13.3.34 Digital Windowed Watchdog Window Size Control (RTIWWDSIZECTRL)............................ 468
13.3.35 RTI Compare Interrupt Clear Enable Register (RTIINTCLRENABLE)................................. 469
13.3.36 RTI Compare 0 Clear Register (RTICMP0CLR) .......................................................... 470
13.3.37 RTI Compare 1 Clear Register (RTICMP1CLR) .......................................................... 470
13.3.38 RTI Compare 2 Clear Register (RTICMP2CLR) .......................................................... 471
13.3.39 RTI Compare 3 Clear Register (RTICMP3CLR) .......................................................... 471
14 Cyclic Redundancy Check (CRC) Controller Module ............................................................. 472
14.1 Overview .................................................................................................................. 473
14.1.1 Features ......................................................................................................... 473
14.1.2 Block Diagram................................................................................................... 474
14.2 Module Operation ........................................................................................................ 475
14.2.1 General Operation ............................................................................................. 475
14.2.2 CRC Modes of Operation...................................................................................... 475
14.2.3 PSA Signature Register........................................................................................ 476
14.2.4 PSA Sector Signature Register............................................................................... 477
14.2.5 CRC Value Register............................................................................................ 478
14.2.6 Raw Data Register ............................................................................................. 478
14.2.7 Example DMA Controller Setup............................................................................... 478
14.2.8 Pattern Count Register......................................................................................... 480
14.2.9 Sector Count Register/Current Sector Register ............................................................ 480
14.2.10 Interrupt......................................................................................................... 481
14.2.11 CPU Data Trace............................................................................................... 484
14.2.12 Power Down Mode............................................................................................ 485
14.2.13 Emulation ...................................................................................................... 485
14.2.14 Peripheral Bus Interface...................................................................................... 485
14.3 Example ................................................................................................................... 486
14.3.1 Example: Auto Mode Using Time Based Event Triggering ............................................... 486
14.3.2 Example: Auto Mode Without Using Time Based Triggering ............................................. 487
14.3.3 Example: Semi-CPU Mode.................................................................................... 488
14.3.4 Example: Full-CPU Mode...................................................................................... 488
14.4 CRC Control Registers................................................................................................... 489
14.4.1 CRC Global Control Register 0 (CRC_CTRL0)............................................................. 490
14.4.2 CRC Global Control Register (CRC_CTRL1)............................................................... 490
14.4.3 CRC Global Control Register 2 (CRC_CTRL2)............................................................. 491
14.4.4 CRC Interrupt Enable Set Register (CRC_INTS) .......................................................... 492
14.4.5 CRC Interrupt Enable Reset Register (CRC_INTR) ....................................................... 494
14.4.6 CRC Interrupt Status Register (CRC_STATUS)............................................................ 496
14.4.7 CRC Interrupt Offset (CRC_INT_OFFSET_REG).......................................................... 497
14.4.8 CRC Busy Register (CRC_BUSY) ........................................................................... 499
14.4.9 CRC Pattern Counter Preload Register 1 (CRC_PCOUNT_REG1)..................................... 499
14.4.10 CRC Sector Counter Preload Register 1 (CRC_SCOUNT_REG1) .................................... 500
14.4.11 CRC Current Sector Register 1 (CRC_CURSEC_REG1) ............................................... 500
14.4.12 CRC Channel 1 Watchdog Timeout Preload Register A (CRC_WDTOPLD1)........................ 501

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Contents
14.4.13 CRC Channel 1 Block Complete Timeout Preload Register B (CRC_BCTOPLD1).................. 501
14.4.14 Channel 1 PSA Signature Low Register (PSA_SIGREGL1) ............................................ 502
14.4.15 Channel 1 PSA Signature High Register (PSA_SIGREGH1) ........................................... 502
14.4.16 Channel 1 CRC Value Low Register (CRC_REGL1)..................................................... 502
14.4.17 Channel 1 CRC Value High Register (CRC_REGH1).................................................... 503
14.4.18 Channel 1 PSA Sector Signature Low Register (PSA_SECSIGREGL1).............................. 503
14.4.19 Channel 1 PSA Sector Signature High Register (PSA_SECSIGREGH1)............................. 503
14.4.20 Channel 1 Raw Data Low Register (RAW_DATAREGL1)............................................... 504
14.4.21 Channel 1 Raw Data High Register (RAW_DATAREGH1).............................................. 504
14.4.22 CRC Pattern Counter Preload Register 2 (CRC_PCOUNT_REG2) ................................... 504
14.4.23 CRC Sector Counter Preload Register 2 (CRC_SCOUNT_REG2) .................................... 505
14.4.24 CRC Current Sector Register 2 (CRC_CURSEC_REG2) ............................................... 505
14.4.25 CRC Channel 2 Watchdog Timeout Preload Register A (CRC_WDTOPLD2)........................ 506
14.4.26 CRC Channel 2 Block Complete Timeout Preload Register B (CRC_BCTOPLD2).................. 506
14.4.27 Channel 2 PSA Signature Low Register (PSA_SIGREGL2) ............................................ 507
14.4.28 Channel 2 PSA Signature High Register (PSA_SIGREGH2) ........................................... 507
14.4.29 Channel 2 CRC Value Low Register (CRC_REGL2)..................................................... 507
14.4.30 Channel 2 CRC Value High Register (CRC_REGH2).................................................... 508
14.4.31 Channel 2 PSA Sector Signature Low Register (PSA_SECSIGREGL2).............................. 508
14.4.32 Channel 2 PSA Sector Signature High Register (PSA_SECSIGREGH2)............................. 508
14.4.33 Channel 2 Raw Data Low Register (RAW_DATAREGL2)............................................... 509
14.4.34 Channel 2 Raw Data High Register (RAW_DATAREGH2).............................................. 509
14.4.35 Data Bus Selection Register (CRC_TRACE_BUS_SEL)................................................ 510
15 Vectored Interrupt Manager (VIM) Module............................................................................ 511
15.1 Overview................................................................................................................... 512
15.2 Device Level Interrupt Management ................................................................................... 512
15.2.1 Interrupt Generation at the Peripheral ....................................................................... 513
15.2.2 Interrupt Handling at the CPU................................................................................. 513
15.2.3 Software Interrupt Handling Options ......................................................................... 514
15.3 Interrupt Handling Inside VIM ........................................................................................... 515
15.3.1 VIM Interrupt Channel Mapping............................................................................... 516
15.3.2 VIM Input Channel Management ............................................................................. 518
15.4 Interrupt Vector Table (VIM RAM)...................................................................................... 519
15.4.1 Interrupt Vector Table Operation ............................................................................. 519
15.4.2 Enabling and Controlling the VIM Parity..................................................................... 520
15.4.3 Interrupt Vector Table Initialization........................................................................... 520
15.4.4 Interrupt Vector Table Parity Testing......................................................................... 521
15.5 VIM Wakeup Interrupt.................................................................................................... 522
15.6 Capture Event Sources .................................................................................................. 523
15.7 Examples .................................................................................................................. 523
15.7.1 Examples - Configure CPU To Receive Interrupts......................................................... 523
15.7.2 Examples - Register Vector Interrupt and Index Interrupt Handling ..................................... 524
15.8 VIM Control Registers.................................................................................................... 526
15.8.1 Interrupt Vector Table Parity Flag Register (PARFLG) ................................................... 527
15.8.2 Interrupt Vector Table Parity Control Register (PARCTL)................................................. 527
15.8.3 Address Parity Error Register (ADDERR)................................................................... 528
15.8.4 Fall-Back Address Parity Error Register (FBPARERR).................................................... 528
15.8.5 VIM Offset Vector Registers................................................................................... 529
15.8.6 IRQ Index Offset Vector Register (IRQINDEX)............................................................. 530
15.8.7 FIQ Index Offset Vector Registers (FIQINDEX) ............................................................ 530
15.8.8 FIQ/IRQ Program Control Registers (FIRQPR[0:2]) ....................................................... 531
15.8.9 Pending Interrupt Read Location Registers (INTREQ[0:2])............................................... 532
15.8.10 Interrupt Enable Set Registers (REQENASET[0:2])...................................................... 533