Texas Instruments RM48 series Product manual

RM48x 16/32-Bit RISC Flash Microcontroller
Technical Reference Manual
Literature Number: SPNU503C
March 2018

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Contents
Contents
Preface....................................................................................................................................... 87
1 Introduction....................................................................................................................... 89
1.1 Designed for Safety Applications......................................................................................... 90
1.2 Family Description.......................................................................................................... 90
1.3 Endianism Considerations ................................................................................................ 93
1.3.1 RM48x: Little Endian (LE)........................................................................................ 93
2 Architecture....................................................................................................................... 94
2.1 Introduction.................................................................................................................. 95
2.1.1 Architecture Block Diagram...................................................................................... 95
2.1.2 Definitions of Terms............................................................................................... 96
2.1.3 Bus Master / Slave Access Privileges.......................................................................... 98
2.2 Memory Organization...................................................................................................... 99
2.2.1 Memory-Map Overview........................................................................................... 99
2.2.2 Memory-Map Table.............................................................................................. 100
2.2.3 Flash Memory .................................................................................................... 104
2.2.4 On-Chip SRAM................................................................................................... 106
2.3 Exceptions................................................................................................................. 111
2.3.1 Resets............................................................................................................. 111
2.3.2 Aborts ............................................................................................................. 111
2.3.3 System Software Interrupts..................................................................................... 113
2.4 Clocks ...................................................................................................................... 114
2.4.1 Clock Sources.................................................................................................... 114
2.4.2 Clock Domains................................................................................................... 115
2.4.3 Low Power Modes............................................................................................... 117
2.4.4 Clock Test Mode................................................................................................. 119
2.4.5 Embedded Trace Macrocell (ETM-R4)........................................................................ 120
2.4.6 Safety Considerations for Clocks.............................................................................. 121
2.5 System and Peripheral Control Registers ............................................................................. 123
2.5.1 Primary System Control Registers (SYS) .................................................................... 123
2.5.2 Secondary System Control Registers (SYS2) ............................................................... 176
2.5.3 Peripheral Central Resource (PCR) Control Registers .................................................... 185
3 Power Management Module (PMM) ..................................................................................... 200
3.1 Overview................................................................................................................... 201
3.1.1 Main Features of the Power Management Module (PMM)................................................. 201
3.1.2 Block Diagram.................................................................................................... 201
3.2 Power Domains ........................................................................................................... 202
3.3 PMM Operation ........................................................................................................... 204
3.3.1 Power Switch..................................................................................................... 204
3.3.2 Power Domain State ............................................................................................ 204
3.3.3 Default Power Domain State................................................................................... 204
3.3.4 Disabling a Power Domain Permanently ..................................................................... 204
3.3.5 Changing Power Domain State................................................................................ 204
3.3.6 Reset Management.............................................................................................. 205
3.3.7 Diagnostic Power State Controller (PSCON) ................................................................ 205
3.3.8 PSCON Compare Block ........................................................................................ 205

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3.4 PMM Registers............................................................................................................ 207
3.4.1 Logic Power Domain Control Register (LOGICPDPWRCTRL0) .......................................... 208
3.4.2 Memory Power Domain Control Register 0 (MEMPDPWRCTRL0)....................................... 209
3.4.3 Power Domain Clock Disable Register (PDCLKDISREG) ................................................. 210
3.4.4 Power Domain Clock Disable Set Register (PDCLKDISSETREG) ...................................... 211
3.4.5 Power Domain Clock Disable Clear Register (PDCLKDISCLRREG)..................................... 212
3.4.6 Logic Power Domain PD2 Power Status Register (LOGICPDPWRSTAT0)............................. 213
3.4.7 Logic Power Domain PD3 Power Status Register (LOGICPDPWRSTAT1)............................. 214
3.4.8 Logic Power Domain PD4 Power Status Register (LOGICPDPWRSTAT2)............................. 215
3.4.9 Logic Power Domain PD5 Power Status Register (LOGICPDPWRSTAT3)............................. 216
3.4.10 Memory Power Domain RAM_PD1 Power Status Register (MEMPDPWRSTAT0) ................... 217
3.4.11 Memory Power Domain RAM_PD2 Power Status Register (MEMPDPWRSTAT1) ................... 218
3.4.12 Memory Power Domain RAM_PD3 Power Status Register (MEMPDPWRSTAT2) ................... 219
3.4.13 Global Control Register 1 (GLOBALCTRL1)................................................................ 220
3.4.14 Global Status Register (GLOBALSTAT)..................................................................... 221
3.4.15 PSCON Diagnostic Compare Key Register (PRCKEYREG) ............................................. 221
3.4.16 LogicPD PSCON Diagnostic Compare Status Register 1 (LPDDCSTAT1)............................. 222
3.4.17 LogicPD PSCON Diagnostic Compare Status Register 2 (LPDDCSTAT2)............................. 223
3.4.18 Memory PD PSCON Diagnostic Compare Status Register 1 (MPDDCSTAT1)........................ 224
3.4.19 Memory PD PSCON Diagnostic Compare Status Register 2 (MPDDCSTAT2)........................ 225
3.4.20 Isolation Diagnostic Status Register (ISODIAGSTAT)..................................................... 226
4 I/O Multiplexing and Control Module (IOMM) ........................................................................ 227
4.1 Overview .................................................................................................................. 228
4.2 Main Features of I/O Multiplexing Module (IOMM) .................................................................. 228
4.3 Control of Multiplexed Functions ....................................................................................... 228
4.3.1 Control of Multiplexed Outputs ................................................................................ 228
4.3.2 Control of Multiplexed Inputs .................................................................................. 229
4.3.3 Control of Special Multiplexed Options ...................................................................... 231
4.4 Safety Features .......................................................................................................... 232
4.4.1 Locking Mechanism for Memory-Mapped Registers ....................................................... 232
4.4.2 Error Conditions ................................................................................................. 232
4.5 IOMM Registers........................................................................................................... 233
4.5.1 REVISION_REG: Revision Register ......................................................................... 233
4.5.2 ENDIAN_REG: Device Endianness Register ............................................................... 234
4.5.3 KICK_REG0: Kicker Register 0 ............................................................................... 235
4.5.4 KICK_REG1: Kicker Register 1 ............................................................................... 235
4.5.5 ERR_RAW_STATUS_REG: Error Raw Status / Set Register ............................................ 236
4.5.6 ERR_ENABLED_STATUS_REG: Error Enabled Status / Clear Register ............................... 237
4.5.7 ERR_ENABLE_REG: Error Signaling Enable Register .................................................... 238
4.5.8 ERR_ENABLE_CLR_REG: Error Signaling Enable Clear Register ...................................... 239
4.5.9 FAULT_ADDRESS_REG: Fault Address Register.......................................................... 239
4.5.10 FAULT_STATUS_REG: Fault Status Register ............................................................ 240
4.5.11 FAULT_CLEAR_REG: Fault Clear Register ............................................................... 241
4.5.12 PINMMRnn: Pin Multiplexing Control Registers ........................................................... 241
4.6 Signal Multiplexing and Control......................................................................................... 242
5 F021 Flash Module Controller (FMC) ................................................................................... 246
5.1 Overview .................................................................................................................. 247
5.1.1 Features .......................................................................................................... 247
5.1.2 Definition of Terms .............................................................................................. 247
5.1.3 F021 Flash Tools ................................................................................................ 248
5.2 Default Flash Configuration ............................................................................................. 248
5.3 SECDED .................................................................................................................. 249
5.3.1 SECDED Initialization ........................................................................................... 249

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5.3.2 ECC Encoding.................................................................................................... 250
5.3.3 Syndrome Table: Decode to Bit in Error...................................................................... 251
5.3.4 Syndrome Table: An Alternate Method ....................................................................... 252
5.4 Memory Map .............................................................................................................. 253
5.4.1 Location of Flash ECC Bits..................................................................................... 253
5.4.2 OTP Memory ..................................................................................................... 254
5.5 Power On, Power Off, and Reset Considerations ................................................................... 256
5.5.1 Error Checking at Power On ................................................................................... 256
5.5.2 Flash Integrity when Reset while Programming or Erasing................................................ 256
5.5.3 Flash Integrity at Power Off .................................................................................... 257
5.6 Emulation and SIL3 Diagnostic Modes ................................................................................ 257
5.6.1 System Emulation ............................................................................................... 257
5.6.2 Diagnostic Mode ................................................................................................. 257
5.6.3 Diagnostic Mode Summary..................................................................................... 262
5.6.4 Read Margin...................................................................................................... 263
5.7 Control Registers ......................................................................................................... 263
5.7.1 Flash Option Control Register (FRDCNTL) .................................................................. 265
5.7.2 Flash Error Detection and Correction Control Register 1 (FEDACCTRL1) ............................. 266
5.7.3 Flash Error Correction and Correction Control Register 2 (FEDACCTRL2) ............................ 268
5.7.4 Flash Correctable Error Count Register (FCOR_ERR_CNT) ............................................. 268
5.7.5 Flash Correctable Error Address Register (FCOR_ERR_ADD) .......................................... 269
5.7.6 Flash Correctable Error Position Register (FCOR_ERR_POS) .......................................... 270
5.7.7 Flash Error Detection and Correction Status Register (FEDACSTATUS) ............................... 271
5.7.8 Flash Uncorrectable Error Address Register (FUNC_ERR_ADD) ....................................... 274
5.7.9 Flash Error Detection and Correction Sector Disable Register (FEDACSDIS) ......................... 275
5.7.10 Primary Address Tag Register (FPRIM_ADD_TAG) ...................................................... 276
5.7.11 Duplicate Address Tag Register (FDUP_ADD_TAG) ..................................................... 276
5.7.12 Flash Bank Protection Register (FBPROT) ................................................................ 277
5.7.13 Flash Bank Sector Enable Register (FBSE) ................................................................ 277
5.7.14 Flash Bank Busy Register (FBBUSY) ....................................................................... 278
5.7.15 Flash Bank Access Control Register (FBAC) .............................................................. 279
5.7.16 Flash Bank Fallback Power Register (FBFALLBACK) .................................................... 280
5.7.17 Flash Bank/Pump Ready Register (FBPRDY) ............................................................. 281
5.7.18 Flash Pump Access Control Register 1 (FPAC1) ......................................................... 282
5.7.19 Flash Pump Access Control Register 2 (FPAC2) ......................................................... 283
5.7.20 Flash Module Access Control Register (FMAC) ........................................................... 283
5.7.21 Flash Module Status Register (FMSTAT) .................................................................. 284
5.7.22 EEPROM Emulation Data MSW Register (FEMU_DMSW)............................................... 286
5.7.23 EEPROM Emulation Data LSW Register (FEMU_DLSW) ................................................ 286
5.7.24 EEPROM Emulation ECC Register (FEMU_ECC)......................................................... 287
5.7.25 EEPROM Emulation Address Register (FEMU_ADDR)................................................... 288
5.7.26 Diagnostic Control Register (FDIAGCTRL) ................................................................. 289
5.7.27 Uncorrected Raw Data High Register (FRAW_DATAH) .................................................. 291
5.7.28 Uncorrected Raw Data Low Register (FRAW_DATAL) ................................................... 291
5.7.29 Uncorrected Raw ECC Register (FRAW_ECC) ............................................................ 292
5.7.30 Parity Override Register (FPAR_OVR) ...................................................................... 293
5.7.31 Flash Error Detection and Correction Sector Disable Register (FEDACSDIS2) ...................... 294
5.7.32 FSM Register Write Enable (FSM_WR_ENA) ............................................................. 295
5.7.33 FSM Sector Register (FSM_SECTOR) ..................................................................... 295
5.7.34 EEPROM Emulation Configuration Register (EEPROM_CONFIG) ..................................... 296
5.7.35 EEPROM Emulation Error Detection and Correction Control Register 1 (EE_CTRL1) .............. 297
5.7.36 EEPROM Emulation Error Correction and Correction Control Register 2 (EE_CTRL2) ............. 299
5.7.37 EEPROM Emulation Correctable Error Count Register (EE_COR_ERR_CNT) ....................... 299

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5.7.38 EEPROM Emulation Correctable Error Address Register (EE_COR_ERR_ADD) .................... 300
5.7.39 EEPROM Emulation Correctable Error Position Register (EE_COR_ERR_POS) .................... 301
5.7.40 EEPROM Emulation Error Status Register (EE_STATUS) .............................................. 302
5.7.41 EEPROM Emulation Uncorrectable Error Address Register (EE_UNC_ERR_ADD) ................. 303
5.7.42 Flash Bank Configuration Register (FCFG_BANK) ....................................................... 304
6 Tightly-Coupled RAM (TCRAM) Module ............................................................................... 305
6.1 Overview................................................................................................................... 306
6.1.1 B0TCM and B1TCM Connection Diagram ................................................................... 306
6.1.2 Main Features.................................................................................................... 306
6.2 RAM Memory Map........................................................................................................ 307
6.3 Safety Features ........................................................................................................... 308
6.3.1 Support for Cortex-R4F CPU's Single-Error-Correction Double-Error-Detection (SECDED).......... 308
6.3.2 Support for Cortex-R4F CPU's Address and Control Bus Parity Checking.............................. 309
6.3.3 Redundant Address Decode ................................................................................... 309
6.4 TCRAM Auto-Initialization ............................................................................................... 309
6.5 Trace Module Support ................................................................................................... 310
6.6 Emulation / Debug Mode Behavior..................................................................................... 310
6.7 Control and Status Registers............................................................................................ 310
6.7.1 TCRAM Module Control Register (RAMCTRL).............................................................. 311
6.7.2 TCRAM Module Single-Bit Error Correction Threshold Register (RAMTHRESHOLD)................. 312
6.7.3 TCRAM Module Single-Bit Error Occurrences Counter Register (RAMOCCUR)....................... 313
6.7.4 TCRAM Module Interrupt Control Register (RAMINTCTRL)............................................... 313
6.7.5 TCRAM Module Error Status Register (RAMERRSTATUS)............................................... 314
6.7.6 TCRAM Module Single-Bit Error Address Register (RAMSERRADDR).................................. 315
6.7.7 TCRAM Module Uncorrectable Error Address Register (RAMUERRADDR) ............................ 316
6.7.8 TCRAM Module Test Mode Control Register (RAMTEST)................................................. 317
6.7.9 TCRAM Module Test Mode Vector Register (RAMADDRDECVECT).................................... 318
6.7.10 TCRAM Module Parity Error Address Register (RAMPERRADDR) ..................................... 318
6.7.11 Auto-Memory Initialization Enable Register (INIT_DOMAIN)............................................. 319
7 Programmable Built-In Self-Test (PBIST) Module.................................................................. 320
7.1 Overview .................................................................................................................. 321
7.1.1 Features of PBIST .............................................................................................. 321
7.1.2 PBIST vs. Application Software-Based Testing.............................................................. 321
7.1.3 PBIST Block Diagram .......................................................................................... 321
7.2 RAM Grouping and Algorithm .......................................................................................... 322
7.3 PBIST Flow ............................................................................................................... 323
7.3.1 PBIST Sequence ................................................................................................ 324
7.4 Memory Test Algorithms on the On-chip ROM ...................................................................... 325
7.5 PBIST Control Registers ................................................................................................ 327
7.5.1 RAM Configuration Register (RAMT) ......................................................................... 328
7.5.2 Datalogger Register (DLR) ..................................................................................... 329
7.5.3 PBIST Activate/Clock Enable Register (PACT).............................................................. 330
7.5.4 PBIST ID Register ............................................................................................... 331
7.5.5 Override Register (OVER)...................................................................................... 332
7.5.6 Fail Status Fail Register (FSRF0) ............................................................................. 333
7.5.7 Fail Status Count Registers (FSRC0 and FSRC1).......................................................... 334
7.5.8 Fail Status Address Registers (FSRA0 and FSRA1) ....................................................... 335
7.5.9 Fail Status Data Registers (FSRDL0 and FSRDL1) ........................................................ 336
7.5.10 ROM Mask Register (ROM)................................................................................... 337
7.5.11 ROM Algorithm Mask Register (ALGO) ..................................................................... 337
7.5.12 RAM Info Mask Lower Register (RINFOL) .................................................................. 338
7.5.13 RAM Info Mask Upper Register (RINFOU).................................................................. 339
7.6 PBIST Configuration Example .......................................................................................... 340

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7.6.1 Example 1 : Configuration of PBIST Controller to Run Self-Test on RAM Group 3 .................... 340
7.6.2 Example 2 : Configuration of PBIST Controller to Run Self-Test on ALL RAM Groups................ 341
8 CPU Self-Test Controller (STC) Module ............................................................................... 342
8.1 General Description ...................................................................................................... 343
8.1.1 CPU Self-Test Controller Features............................................................................ 343
8.1.2 STC Block Diagram ............................................................................................. 343
8.2 Application Self-Test Flow............................................................................................... 345
8.2.1 STC Module Configuration ..................................................................................... 345
8.2.2 Context Saving................................................................................................... 345
8.2.3 Entering CPU Idle Mode........................................................................................ 345
8.2.4 Self-Test Completion and Error Generation.................................................................. 346
8.3 STC Test Coverage and Duration...................................................................................... 347
8.4 STC Control Registers ................................................................................................... 348
8.4.1 STC Global Control Register 0 (STCGCR0) ................................................................. 349
8.4.2 STC Global Control Register 1 (STCGCR1) ................................................................. 349
8.4.3 Self-Test Run Timeout Counter Preload Register (STCTPR) ............................................. 350
8.4.4 STC Current ROM Address Register (STC_CADDR) ...................................................... 350
8.4.5 STC Current Interval Count Register (STCCICR)........................................................... 351
8.4.6 Self-Test Global Status Register (STCGSTAT).............................................................. 352
8.4.7 Self-Test Fail Status Register (STCFSTAT) ................................................................. 353
8.4.8 CPU1 Current MISR Register (CPU1_CURMISR[3:0])..................................................... 354
8.4.9 CPU2_CURMISR[3:0] (CPU2 Current MISR Register)..................................................... 355
8.4.10 STCSCSCR (Signature Compare Self-Check Register) .................................................. 356
8.5 STC Configuration Example ............................................................................................ 357
8.5.1 Example 1: Self-Test Run for 24 Interval .................................................................... 357
9 CPU Compare Module for Cortex-R4F (CCM-R4F)................................................................. 358
9.1 Main Features............................................................................................................. 359
9.2 Block Diagram............................................................................................................. 359
9.3 Module Operation......................................................................................................... 360
9.3.1 1oo1D Lock Step Mode......................................................................................... 360
9.3.2 Self-Test Mode................................................................................................... 360
9.3.3 Error Forcing Mode.............................................................................................. 362
9.3.4 Self-Test Error Forcing Mode .................................................................................. 362
9.3.5 Operation During CPU Debug Mode.......................................................................... 363
9.4 CCM-R4F Control Registers ............................................................................................ 363
9.4.1 CCM-R4F Status Register (CCMSR) ......................................................................... 364
9.4.2 CCM-R4F Key Register (CCMKEYR)......................................................................... 365
10 Oscillator and PLL ........................................................................................................... 366
10.1 Introduction ................................................................................................................ 367
10.1.1 Features.......................................................................................................... 367
10.2 Quick Start................................................................................................................. 368
10.3 Oscillator................................................................................................................... 369
10.3.1 Oscillator Implementation...................................................................................... 370
10.3.2 Oscillator Enable................................................................................................ 370
10.3.3 Oscillator Disable ............................................................................................... 370
10.4 Low-Power Oscillator and Clock Detect (LPOCLKDET)............................................................. 371
10.4.1 Clock Detect..................................................................................................... 371
10.4.2 Behavior on Oscillator Failure................................................................................. 371
10.4.3 Recovery from Oscillator Failure ............................................................................. 372
10.4.4 LPOCLKDET Enable........................................................................................... 372
10.4.5 LPOCLKDET Disable .......................................................................................... 373
10.4.6 Trimming the HF LPO Oscillator.............................................................................. 373
10.5 PLL ......................................................................................................................... 374

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10.5.1 Modulation....................................................................................................... 376
10.5.2 PLL Output Control............................................................................................. 377
10.5.3 Behavior on PLL Fail........................................................................................... 380
10.5.4 Recovery from a PLL Failure.................................................................................. 381
10.5.5 PLL Modulation Depth Measurement........................................................................ 382
10.5.6 PLL Frequency Measurement Circuit ........................................................................ 383
10.5.7 PLL2.............................................................................................................. 383
10.6 PLL Control Registers.................................................................................................... 384
10.6.1 PLL Modulation Depth Measurement Control Register (SSWPLL1)..................................... 385
10.6.2 SSW PLL BIST Control Register 2 (SSWPLL2)............................................................ 386
10.6.3 SSW PLL BIST Control Register 3 (SSWPLL3)............................................................ 387
10.7 Phase-Locked Loop Theory of Operation ............................................................................. 388
10.7.1 Phase-Frequency Detector.................................................................................... 388
10.7.2 Charge Pump and Loop Filter................................................................................. 389
10.7.3 Voltage-Controlled Oscillator.................................................................................. 389
10.7.4 Frequency Modulation ......................................................................................... 390
10.8 Programming Example................................................................................................... 390
11 Dual-Clock Comparator (DCC) Module ................................................................................ 392
11.1 Introduction ................................................................................................................ 393
11.1.1 Main Features................................................................................................... 393
11.1.2 Block Diagram................................................................................................... 393
11.2 Module Operation......................................................................................................... 394
11.2.1 Continuous Monitoring Mode.................................................................................. 394
11.2.2 Single-Shot Measurement Mode ............................................................................. 397
11.3 Clock Source Selection for Counter0 and Counter1 ................................................................. 398
11.4 DCC Control Registers................................................................................................... 399
11.4.1 DCC Global Control Register (DCCGCTRL) ............................................................... 400
11.4.2 DCC Revision Id Register (DCCREV) ...................................................................... 401
11.4.3 DCC Counter0 Seed Register (DCCCNT0SEED) ......................................................... 401
11.4.4 DCC Valid0 Seed Register (DCCVALID0SEED) .......................................................... 402
11.4.5 DCC Counter1 Seed Register (DCCCNT1SEED) ......................................................... 402
11.4.6 DCC Status Register (DCCSTAT) ........................................................................... 403
11.4.7 DCC Counter0 Value Register (DCCCNT0) ................................................................ 404
11.4.8 DCC Valid0 Value Register (DCCVALID0) ................................................................. 405
11.4.9 DCC Counter1 Value Register (DCCCNT1) ................................................................ 405
11.4.10 DCC Counter1 Clock Source Selection Register (DCCCNT1CLKSRC) .............................. 406
11.4.11 DCC Counter0 Clock Source Selection Register (DCCCNT0CLKSRC) .............................. 407
12 Error Signaling Module (ESM) ........................................................................................... 408
12.1 Overview .................................................................................................................. 409
12.1.1 Features.......................................................................................................... 409
12.1.2 Block Diagram .................................................................................................. 409
12.2 Module Operation ........................................................................................................ 411
12.2.1 Reset Behavior ................................................................................................. 411
12.2.2 ERROR Pin Timing ............................................................................................ 412
12.2.3 Forcing an Error Condition .................................................................................... 414
12.3 Recommended Programming Procedure ............................................................................. 415
12.4 Control Registers ......................................................................................................... 416
12.4.1 ESM Enable ERROR Pin Action/Response Register 1 (ESMEEPAPR1)............................... 417
12.4.2 ESM Disable ERROR Pin Action/Response Register 1 (ESMDEPAPR1).............................. 417
12.4.3 ESM Interrupt Enable Set Register 1 (ESMIESR1)........................................................ 418
12.4.4 ESM Interrupt Enable Clear Register 1 (ESMIECR1) ..................................................... 418
12.4.5 ESM Interrupt Level Set Register 1 (ESMILSR1) .......................................................... 419
12.4.6 ESM Interrupt Level Clear Register 1 (ESMILCR1)........................................................ 419

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12.4.7 ESM Status Register 1 (ESMSR1)........................................................................... 420
12.4.8 ESM Status Register 2 (ESMSR2)........................................................................... 420
12.4.9 ESM Status Register 3 (ESMSR3)........................................................................... 421
12.4.10 ESM ERROR Pin Status Register (ESMEPSR) .......................................................... 421
12.4.11 ESM Interrupt Offset High Register (ESMIOFFHR) ...................................................... 422
12.4.12 ESM Interrupt Offset Low Register (ESMIOFFLR) ....................................................... 423
12.4.13 ESM Low-Time Counter Register (ESMLTCR) ........................................................... 424
12.4.14 ESM Low-Time Counter Preload Register (ESMLTCPR)................................................ 424
12.4.15 ESM Error Key Register (ESMEKR)........................................................................ 425
12.4.16 ESM Status Shadow Register 2 (ESMSSR2) ............................................................. 425
12.4.17 ESM Influence ERROR Pin Set Register 4 (ESMIEPSR4) ............................................. 426
12.4.18 ESM Influence ERROR Pin Clear Register 4 (ESMIEPCR4) .......................................... 426
12.4.19 ESM Interrupt Enable Set Register 4 (ESMIESR4) ...................................................... 427
12.4.20 ESM Interrupt Enable Clear Register 4 (ESMIECR4) ................................................... 427
12.4.21 ESM Interrupt Level Set Register 4 (ESMILSR4) ........................................................ 428
12.4.22 ESM Interrupt Level Clear Register 4 (ESMILCR4) ..................................................... 428
12.4.23 ESM Status Register 4 (ESMSR4) ......................................................................... 429
13 Real-Time Interrupt (RTI) Module........................................................................................ 430
13.1 Overview................................................................................................................... 431
13.1.1 Features.......................................................................................................... 431
13.1.2 Industry Standard Compliance Statement................................................................... 431
13.2 Module Operation......................................................................................................... 432
13.2.1 Counter Operation.............................................................................................. 432
13.2.2 Interrupt/DMA Requests ....................................................................................... 434
13.2.3 RTI Clocking..................................................................................................... 435
13.2.4 Synchronizing Timer Events to Network Time (NTU)...................................................... 435
13.2.5 Digital Watchdog (DWD)....................................................................................... 438
13.2.6 Low Power Modes.............................................................................................. 441
13.2.7 Halting Debug Mode Behaviour............................................................................... 441
13.3 RTI Control Registers .................................................................................................... 442
13.3.1 RTI Global Control Register (RTIGCTRL)................................................................... 443
13.3.2 RTI Timebase Control Register (RTITBCTRL) ............................................................. 444
13.3.3 RTI Capture Control Register (RTICAPCTRL).............................................................. 445
13.3.4 RTI Compare Control Register (RTICOMPCTRL) ......................................................... 446
13.3.5 RTI Free Running Counter 0 Register (RTIFRC0) ......................................................... 447
13.3.6 RTI Up Counter 0 Register (RTIUC0)........................................................................ 447
13.3.7 RTI Compare Up Counter 0 Register (RTICPUC0)........................................................ 448
13.3.8 RTI Capture Free Running Counter 0 Register (RTICAFRC0)........................................... 448
13.3.9 RTI Capture Up Counter 0 Register (RTICAUC0).......................................................... 449
13.3.10 RTI Free Running Counter 1 Register (RTIFRC1)........................................................ 449
13.3.11 RTI Up Counter 1 Register (RTIUC1) ...................................................................... 450
13.3.12 RTI Compare Up Counter 1 Register (RTICPUC1)....................................................... 451
13.3.13 RTI Capture Free Running Counter 1 Register (RTICAFRC1) ......................................... 452
13.3.14 RTI Capture Up Counter 1 Register (RTICAUC1)........................................................ 452
13.3.15 RTI Compare 0 Register (RTICOMP0)..................................................................... 453
13.3.16 RTI Update Compare 0 Register (RTIUDCP0)............................................................ 453
13.3.17 RTI Compare 1 Register (RTICOMP1)..................................................................... 454
13.3.18 RTI Update Compare 1 Register (RTIUDCP1)............................................................ 454
13.3.19 RTI Compare 2 Register (RTICOMP2)..................................................................... 455
13.3.20 RTI Update Compare 2 Register (RTIUDCP2)............................................................ 455
13.3.21 RTI Compare 3 Register (RTICOMP3)..................................................................... 456
13.3.22 RTI Update Compare 3 Register (RTIUDCP3)............................................................ 456
13.3.23 RTI Timebase Low Compare Register (RTITBLCOMP) ................................................. 457

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13.3.24 RTI Timebase High Compare Register (RTITBHCOMP) ................................................ 457
13.3.25 RTI Set Interrupt Enable Register (RTISETINTENA) .................................................... 458
13.3.26 RTI Clear Interrupt Enable Register (RTICLEARINTENA) .............................................. 460
13.3.27 RTI Interrupt Flag Register (RTIINTFLAG) ................................................................ 462
13.3.28 Digital Watchdog Control Register (RTIDWDCTRL) ..................................................... 463
13.3.29 Digital Watchdog Preload Register (RTIDWDPRLD)..................................................... 464
13.3.30 Watchdog Status Register (RTIWDSTATUS) ............................................................. 465
13.3.31 RTI Watchdog Key Register (RTIWDKEY) ................................................................ 466
13.3.32 RTI Digital Watchdog Down Counter (RTIDWDCNTR) .................................................. 467
13.3.33 Digital Windowed Watchdog Reaction Control (RTIWWDRXNCTRL) ................................. 467
13.3.34 Digital Windowed Watchdog Window Size Control (RTIWWDSIZECTRL)............................ 468
13.3.35 RTI Compare Interrupt Clear Enable Register (RTIINTCLRENABLE)................................. 469
13.3.36 RTI Compare 0 Clear Register (RTICMP0CLR) .......................................................... 470
13.3.37 RTI Compare 1 Clear Register (RTICMP1CLR) .......................................................... 470
13.3.38 RTI Compare 2 Clear Register (RTICMP2CLR) .......................................................... 471
13.3.39 RTI Compare 3 Clear Register (RTICMP3CLR) .......................................................... 471
14 Cyclic Redundancy Check (CRC) Controller Module ............................................................. 472
14.1 Overview .................................................................................................................. 473
14.1.1 Features ......................................................................................................... 473
14.1.2 Block Diagram................................................................................................... 474
14.2 Module Operation ........................................................................................................ 475
14.2.1 General Operation ............................................................................................. 475
14.2.2 CRC Modes of Operation...................................................................................... 475
14.2.3 PSA Signature Register........................................................................................ 476
14.2.4 PSA Sector Signature Register............................................................................... 477
14.2.5 CRC Value Register............................................................................................ 478
14.2.6 Raw Data Register ............................................................................................. 478
14.2.7 Example DMA Controller Setup............................................................................... 478
14.2.8 Pattern Count Register......................................................................................... 480
14.2.9 Sector Count Register/Current Sector Register ............................................................ 480
14.2.10 Interrupt......................................................................................................... 481
14.2.11 CPU Data Trace............................................................................................... 484
14.2.12 Power Down Mode............................................................................................ 485
14.2.13 Emulation ...................................................................................................... 485
14.2.14 Peripheral Bus Interface...................................................................................... 485
14.3 Example ................................................................................................................... 486
14.3.1 Example: Auto Mode Using Time Based Event Triggering ............................................... 486
14.3.2 Example: Auto Mode Without Using Time Based Triggering ............................................. 487
14.3.3 Example: Semi-CPU Mode.................................................................................... 488
14.3.4 Example: Full-CPU Mode...................................................................................... 488
14.4 CRC Control Registers................................................................................................... 489
14.4.1 CRC Global Control Register 0 (CRC_CTRL0)............................................................. 490
14.4.2 CRC Global Control Register (CRC_CTRL1)............................................................... 490
14.4.3 CRC Global Control Register 2 (CRC_CTRL2)............................................................. 491
14.4.4 CRC Interrupt Enable Set Register (CRC_INTS) .......................................................... 492
14.4.5 CRC Interrupt Enable Reset Register (CRC_INTR) ....................................................... 494
14.4.6 CRC Interrupt Status Register (CRC_STATUS)............................................................ 496
14.4.7 CRC Interrupt Offset (CRC_INT_OFFSET_REG).......................................................... 497
14.4.8 CRC Busy Register (CRC_BUSY) ........................................................................... 499
14.4.9 CRC Pattern Counter Preload Register 1 (CRC_PCOUNT_REG1)..................................... 499
14.4.10 CRC Sector Counter Preload Register 1 (CRC_SCOUNT_REG1) .................................... 500
14.4.11 CRC Current Sector Register 1 (CRC_CURSEC_REG1) ............................................... 500
14.4.12 CRC Channel 1 Watchdog Timeout Preload Register A (CRC_WDTOPLD1)........................ 501

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14.4.13 CRC Channel 1 Block Complete Timeout Preload Register B (CRC_BCTOPLD1).................. 501
14.4.14 Channel 1 PSA Signature Low Register (PSA_SIGREGL1) ............................................ 502
14.4.15 Channel 1 PSA Signature High Register (PSA_SIGREGH1) ........................................... 502
14.4.16 Channel 1 CRC Value Low Register (CRC_REGL1)..................................................... 502
14.4.17 Channel 1 CRC Value High Register (CRC_REGH1).................................................... 503
14.4.18 Channel 1 PSA Sector Signature Low Register (PSA_SECSIGREGL1).............................. 503
14.4.19 Channel 1 PSA Sector Signature High Register (PSA_SECSIGREGH1)............................. 503
14.4.20 Channel 1 Raw Data Low Register (RAW_DATAREGL1)............................................... 504
14.4.21 Channel 1 Raw Data High Register (RAW_DATAREGH1).............................................. 504
14.4.22 CRC Pattern Counter Preload Register 2 (CRC_PCOUNT_REG2) ................................... 504
14.4.23 CRC Sector Counter Preload Register 2 (CRC_SCOUNT_REG2) .................................... 505
14.4.24 CRC Current Sector Register 2 (CRC_CURSEC_REG2) ............................................... 505
14.4.25 CRC Channel 2 Watchdog Timeout Preload Register A (CRC_WDTOPLD2)........................ 506
14.4.26 CRC Channel 2 Block Complete Timeout Preload Register B (CRC_BCTOPLD2).................. 506
14.4.27 Channel 2 PSA Signature Low Register (PSA_SIGREGL2) ............................................ 507
14.4.28 Channel 2 PSA Signature High Register (PSA_SIGREGH2) ........................................... 507
14.4.29 Channel 2 CRC Value Low Register (CRC_REGL2)..................................................... 507
14.4.30 Channel 2 CRC Value High Register (CRC_REGH2).................................................... 508
14.4.31 Channel 2 PSA Sector Signature Low Register (PSA_SECSIGREGL2).............................. 508
14.4.32 Channel 2 PSA Sector Signature High Register (PSA_SECSIGREGH2)............................. 508
14.4.33 Channel 2 Raw Data Low Register (RAW_DATAREGL2)............................................... 509
14.4.34 Channel 2 Raw Data High Register (RAW_DATAREGH2).............................................. 509
14.4.35 Data Bus Selection Register (CRC_TRACE_BUS_SEL)................................................ 510
15 Vectored Interrupt Manager (VIM) Module............................................................................ 511
15.1 Overview................................................................................................................... 512
15.2 Device Level Interrupt Management ................................................................................... 512
15.2.1 Interrupt Generation at the Peripheral ....................................................................... 513
15.2.2 Interrupt Handling at the CPU................................................................................. 513
15.2.3 Software Interrupt Handling Options ......................................................................... 514
15.3 Interrupt Handling Inside VIM ........................................................................................... 515
15.3.1 VIM Interrupt Channel Mapping............................................................................... 516
15.3.2 VIM Input Channel Management ............................................................................. 518
15.4 Interrupt Vector Table (VIM RAM)...................................................................................... 519
15.4.1 Interrupt Vector Table Operation ............................................................................. 519
15.4.2 Enabling and Controlling the VIM Parity..................................................................... 520
15.4.3 Interrupt Vector Table Initialization........................................................................... 520
15.4.4 Interrupt Vector Table Parity Testing......................................................................... 521
15.5 VIM Wakeup Interrupt.................................................................................................... 522
15.6 Capture Event Sources .................................................................................................. 523
15.7 Examples .................................................................................................................. 523
15.7.1 Examples - Configure CPU To Receive Interrupts......................................................... 523
15.7.2 Examples - Register Vector Interrupt and Index Interrupt Handling ..................................... 524
15.8 VIM Control Registers.................................................................................................... 526
15.8.1 Interrupt Vector Table Parity Flag Register (PARFLG) ................................................... 527
15.8.2 Interrupt Vector Table Parity Control Register (PARCTL)................................................. 527
15.8.3 Address Parity Error Register (ADDERR)................................................................... 528
15.8.4 Fall-Back Address Parity Error Register (FBPARERR).................................................... 528
15.8.5 VIM Offset Vector Registers................................................................................... 529
15.8.6 IRQ Index Offset Vector Register (IRQINDEX)............................................................. 530
15.8.7 FIQ Index Offset Vector Registers (FIQINDEX) ............................................................ 530
15.8.8 FIQ/IRQ Program Control Registers (FIRQPR[0:2]) ....................................................... 531
15.8.9 Pending Interrupt Read Location Registers (INTREQ[0:2])............................................... 532
15.8.10 Interrupt Enable Set Registers (REQENASET[0:2])...................................................... 533

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15.8.11 Interrupt Enable Clear Registers (REQENACLR[0:2]) ................................................... 534
15.8.12 Wake-Up Enable Set Registers (WAKEENASET[0:2])................................................... 535
15.8.13 Wake-Up Enable Clear Registers (WAKEENACLR[0:2])................................................ 536
15.8.14 IRQ Interrupt Vector Register (IRQVECREG)............................................................. 537
15.8.15 FIQ Interrupt Vector Register (FIQVECREG) ............................................................. 537
15.8.16 Capture Event Register (CAPEVT) ......................................................................... 538
15.8.17 VIM Interrupt Control Registers (CHANCTRL[0:23]) ..................................................... 539
16 Direct Memory Access Controller (DMA) Module .................................................................. 541
16.1 Overview................................................................................................................... 542
16.1.1 Main Features................................................................................................... 542
16.2 Module Operation......................................................................................................... 543
16.2.1 Memory Space.................................................................................................. 543
16.2.2 DMA Data Access .............................................................................................. 543
16.2.3 Addressing Modes.............................................................................................. 544
16.2.4 DMA Channel Control Packets ............................................................................... 544
16.2.5 Priority Queue................................................................................................... 548
16.2.6 Data Packing and Unpacking ................................................................................. 550
16.2.7 DMA Request ................................................................................................... 553
16.2.8 Auto-Initiation.................................................................................................... 555
16.2.9 Interrupts......................................................................................................... 555
16.2.10 Debugging...................................................................................................... 557
16.2.11 Power Management .......................................................................................... 557
16.2.12 FIFO Buffer..................................................................................................... 557
16.2.13 Channel Chaining ............................................................................................. 558
16.2.14 Memory Protection............................................................................................ 559
16.2.15 Parity Checking................................................................................................ 560
16.2.16 Parity Testing .................................................................................................. 561
16.2.17 Initializing RAM with Parity................................................................................... 561
16.3 Control Registers and Control Packets ................................................................................ 562
16.3.1 Global Configuration Registers ............................................................................... 564
16.3.2 Channel Configuration ......................................................................................... 609
17 External Memory Interface (EMIF)....................................................................................... 615
17.1 Introduction ................................................................................................................ 616
17.1.1 Purpose of the Peripheral ..................................................................................... 616
17.1.2 Features.......................................................................................................... 616
17.1.3 Functional Block Diagram ..................................................................................... 617
17.2 EMIF Module Architecture............................................................................................... 618
17.2.1 EMIF Clock Control............................................................................................. 618
17.2.2 EMIF Requests.................................................................................................. 618
17.2.3 EMIF Signal Descriptions...................................................................................... 618
17.2.4 EMIF Signal Multiplexing Control............................................................................. 619
17.2.5 SDRAM Controller and Interface ............................................................................. 620
17.2.6 Asynchronous Controller and Interface...................................................................... 632
17.2.7 Data Bus Parking............................................................................................... 644
17.2.8 Reset and Initialization Considerations ...................................................................... 645
17.2.9 Interrupt Support................................................................................................ 645
17.2.10 DMA Event Support........................................................................................... 646
17.2.11 EMIF Signal Multiplexing..................................................................................... 646
17.2.12 Memory Map................................................................................................... 646
17.2.13 Priority and Arbitration........................................................................................ 647
17.2.14 System Considerations....................................................................................... 648
17.2.15 Power Management .......................................................................................... 649
17.2.16 Emulation Considerations.................................................................................... 649

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17.3 EMIF Registers............................................................................................................ 650
17.3.1 Module ID Register (MIDR) ................................................................................... 650
17.3.2 Asynchronous Wait Cycle Configuration Register (AWCC)............................................... 651
17.3.3 SDRAM Configuration Register (SDCR) .................................................................... 652
17.3.4 SDRAM Refresh Control Register (SDRCR)................................................................ 653
17.3.5 Asynchronous nConfiguration Registers (CE2CFG-CE5CFG) .......................................... 654
17.3.6 SDRAM Timing Register (SDTIMR).......................................................................... 655
17.3.7 SDRAM Self Refresh Exit Timing Register (SDSRETR) .................................................. 656
17.3.8 EMIF Interrupt Raw Register (INTRAW)..................................................................... 657
17.3.9 EMIF Interrupt Masked Register (INTMSK)................................................................. 658
17.3.10 EMIF Interrupt Mask Set Register (INTMSKSET) ........................................................ 659
17.3.11 EMIF Interrupt Mask Clear Register (INTMSKCLR)...................................................... 660
17.3.12 Page Mode Control Register (PMCR)...................................................................... 661
17.4 Example Configuration................................................................................................... 662
17.4.1 Hardware Interface ............................................................................................. 662
17.4.2 Software Configuration......................................................................................... 662
18 Parameter Overlay Module (POM)....................................................................................... 671
18.1 Introduction ................................................................................................................ 672
18.1.1 Main Features................................................................................................... 672
18.1.2 Parameter Overlay Module (POM) Considerations ........................................................ 672
18.1.3 Block Diagram................................................................................................... 673
18.2 Module Operation......................................................................................................... 673
18.2.1 Decode Regions ................................................................................................ 674
18.2.2 Bus Errors on Accesses via POM............................................................................ 674
18.3 POM Control Registers .................................................................................................. 675
18.3.1 POM Global Control Register (POMGLBCTRL)............................................................ 676
18.3.2 POM Revision ID (POMREV)................................................................................. 677
18.3.3 POM Clock Gate Control Register (POMCLKCTRL) ...................................................... 677
18.3.4 POM Status Register (POMFLG)............................................................................. 678
18.3.5 POM Program Region Start Address Register x (POMPROGSTARTx) ................................ 679
18.3.6 POM Overlay Region Start Address Register x (POMOVLSTARTx).................................... 679
18.3.7 POM Region Size Register x (POMREGSIZEx)............................................................ 680
18.3.8 POM Integration Control Register (POMITCTRL).......................................................... 680
18.3.9 POM Claim Set Register (POMCLAIMSET) ................................................................ 681
18.3.10 POM Claim Clear Register (POMCLAIMCLR) ............................................................ 682
18.3.11 POM Lock Access Register (POMLOCKACCESS) ...................................................... 683
18.3.12 POM Lock Status Register (POMLOCKSTATUS)........................................................ 683
18.3.13 POM Authentication Status Register (POMAUTHSTATUS)............................................. 683
18.3.14 POM Device ID Register (POMDEVID) .................................................................... 684
18.3.15 POM Device Type Register (POMDEVTYPE) ............................................................ 684
18.3.16 POM Peripheral ID 4 Register (POMPERIPHERALID4)................................................. 685
18.3.17 POM Peripheral ID 5 Register (POMPERIPHERALID5)................................................. 685
18.3.18 POM Peripheral ID 6 Register (POMPERIPHERALID6)................................................. 686
18.3.19 POM Peripheral ID 7 Register (POMPERIPHERALID7)................................................. 686
18.3.20 POM Peripheral ID 0 Register (POMPERIPHERALID0)................................................. 687
18.3.21 POM Peripheral ID 1 Register (POMPERIPHERALID1)................................................. 687
18.3.22 POM Peripheral ID 2 Register (POMPERIPHERALID2)................................................. 688
18.3.23 POM Peripheral ID 3 Register (POMPERIPHERALID3)................................................. 688
18.3.24 POM Component ID 0 Register (POMCOMPONENTID0)............................................... 689
18.3.25 POM Component ID 1 Register (POMCOMPONENTID1)............................................... 689
18.3.26 POM Component ID 2 Register (POMCOMPONENTID2)............................................... 690
18.3.27 POM Component ID 3 Register (POMCOMPONENTID3)............................................... 690
19 Analog To Digital Converter (ADC) Module .......................................................................... 691

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19.1 Overview................................................................................................................... 692
19.2 Introduction ................................................................................................................ 693
19.2.1 Input Multiplexor ................................................................................................ 694
19.2.2 Self-Test and Calibration Cell................................................................................. 694
19.2.3 Analog-to-Digital Converter Core............................................................................. 694
19.2.4 Sequencer ....................................................................................................... 695
19.2.5 Conversion Groups............................................................................................. 695
19.3 Basic Features and Usage of the ADC ................................................................................ 696
19.3.1 How to Select Between 12-bit and 10-bit Resolution ...................................................... 696
19.3.2 How to Set Up the ADCLK Speed............................................................................ 696
19.3.3 How to Set Up the Input Channel Acquisition Time........................................................ 696
19.3.4 How to Select an Input Channel for Conversion............................................................ 696
19.3.5 How to Select Between Single Conversion Sequence or Continuous Conversions................... 696
19.3.6 How to Start a Conversion .................................................................................... 697
19.3.7 How to Know When the Group Conversion is Completed ................................................ 697
19.3.8 How Results are Stored in the Results’ Memory ........................................................... 697
19.3.9 How to Read the Results from the Results’ Memory ...................................................... 698
19.3.10 How to Stop a Conversion ................................................................................... 701
19.3.11 Example Sequence for Basic Configuration of ADC Module............................................ 701
19.4 Advanced Conversion Group Configuration Options................................................................. 702
19.4.1 Group Trigger Options ......................................................................................... 703
19.4.2 Single or Continuous Conversion Modes.................................................................... 703
19.4.3 Conversion Group Freeze Capability ........................................................................ 704
19.4.4 Conversion Group Memory Overrun Option ................................................................ 704
19.4.5 Response on Writing Non-Zero Value to Conversion Group’s Channel Select Register ............. 704
19.4.6 Conversion Result Size on Reading: 8-bit, 10-bit or 12-bit ............................................... 705
19.4.7 Option to Read Group Channel ID Along with Conversion Result....................................... 705
19.5 ADC Module Basic Interrupts ........................................................................................... 706
19.5.1 Group Conversion End Interrupt.............................................................................. 706
19.5.2 Group Memory Threshold Interrupt .......................................................................... 706
19.5.3 Group Memory Overrun Interrupt............................................................................. 706
19.6 ADC Module DMA Requests............................................................................................ 707
19.6.1 DMA Request for Each Conversion Result Written to the Results’ Memory............................ 707
19.6.2 DMA Request for a Fixed Number of Conversion Results................................................ 707
19.7 ADC Magnitude Threshold Interrupts .................................................................................. 708
19.7.1 Magnitude Threshold Interrupt Configuration............................................................... 708
19.7.2 Magnitude Threshold Interrupt Comparison Mask Configuration ........................................ 708
19.7.3 Magnitude Threshold Interrupt Enable / Disable Control.................................................. 708
19.7.4 Magnitude Threshold Interrupt Flags......................................................................... 708
19.7.5 Magnitude Threshold Interrupt Offset Register ............................................................. 708
19.8 ADC Special Modes...................................................................................................... 709
19.8.1 ADC Error Calibration Mode .................................................................................. 709
19.8.2 ADC Self-Test Mode ........................................................................................... 713
19.8.3 ADC Power-Down Mode....................................................................................... 715
19.8.4 ADC Sample Capacitor Discharge Mode.................................................................... 716
19.9 ADC Results’ RAM Special Features .................................................................................. 717
19.9.1 ADC Results’ RAM Auto-Initialization........................................................................ 717
19.9.2 ADC Results’ RAM Test Mode................................................................................ 717
19.9.3 ADC Results’ RAM Parity...................................................................................... 717
19.10 ADEVT Pin General Purpose I/O Functionality....................................................................... 718
19.10.1 GPIO Functionality............................................................................................ 718
19.10.2 Summary ....................................................................................................... 719
19.11 ADC Control Registers................................................................................................... 720

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19.11.1 ADC Reset Control Register (ADRSTCR) ................................................................. 722
19.11.2 ADC Operating Mode Control Register (ADOPMODECR) .............................................. 722
19.11.3 ADC Clock Control Register (ADCLOCKCR).............................................................. 724
19.11.4 ADC Calibration Mode Control Register (ADCALCR).................................................... 724
19.11.5 ADC Event Group Operating Mode Control Register (ADEVMODECR) .............................. 726
19.11.6 ADC Group1 Operating Mode Control Register (ADG1MODECR)..................................... 729
19.11.7 ADC Group2 Operating Mode Control Register (ADG2MODECR)..................................... 732
19.11.8 ADC Event Group Trigger Source Select Register (ADEVSRC) ....................................... 735
19.11.9 ADC Group1 Trigger Source Select Register (ADG1SRC).............................................. 736
19.11.10 ADC Group2 Trigger Source Select Register (ADG2SRC) ............................................ 737
19.11.11 ADC Event Interrupt Enable Control Register (ADEVINTENA)........................................ 738
19.11.12 ADC Group1 Interrupt Enable Control Register (ADG1INTENA) ..................................... 739
19.11.13 ADC Group2 Interrupt Enable Control Register (ADG2INTENA) ..................................... 740
19.11.14 ADC Event Group Interrupt Flag Register (ADEVINTFLG) ............................................ 741
19.11.15 ADC Group1 Interrupt Flag Register (ADG1INTFLG) .................................................. 742
19.11.16 ADC Group2 Interrupt Flag Register (ADG2INTFLG) .................................................. 743
19.11.17 ADC Event Group Threshold Interrupt Control Register (ADEVTHRINTCR)........................ 744
19.11.18 ADC Group1 Threshold Interrupt Control Register (ADG1THRINTCR).............................. 744
19.11.19 ADC Group2 Threshold Interrupt Control Register (ADG2THRINTCR).............................. 745
19.11.20 ADC Event Group DMA Control Register (ADEVDMACR) ............................................ 746
19.11.21 ADC Group1 DMA Control Register (ADG1DMACR)................................................... 748
19.11.22 ADC Group2 DMA Control Register (ADG2DMACR)................................................... 750
19.11.23 ADC Results Memory Configuration Register (ADBNDCR) ........................................... 752
19.11.24 ADC Results Memory Size Configuration Register (ADBNDEND).................................... 753
19.11.25 ADC Event Group Sampling Time Configuration Register (ADEVSAMP) ........................... 754
19.11.26 ADC Group1 Sampling Time Configuration Register (ADG1SAMP).................................. 754
19.11.27 ADC Group2 Sampling Time Configuration Register (ADG2SAMP).................................. 755
19.11.28 ADC Event Group Status Register (ADEVSR) .......................................................... 756
19.11.29 ADC Group1 Status Register (ADG1SR)................................................................. 757
19.11.30 ADC Group2 Status Register (ADG2SR)................................................................. 758
19.11.31 ADC Event Group Channel Select Register (ADEVSEL) .............................................. 759
19.11.32 ADC Group1 Channel Select Register (ADG1SEL)..................................................... 760
19.11.33 ADC Group2 Channel Select Register (ADG2SEL)..................................................... 761
19.11.34 ADC Calibration and Error Offset Correction Register (ADCALR).................................... 762
19.11.35 ADC State Machine Status Register (ADSMSTATE)................................................... 762
19.11.36 ADC Channel Last Conversion Value Register (ADLASTCONV)..................................... 763
19.11.37 ADC Event Group Results' FIFO Register (ADEVBUFFER)........................................... 764
19.11.38 ADC Group1 Results FIFO Register (ADG1BUFFER) ................................................. 765
19.11.39 ADC Group2 Results FIFO Register (ADG2BUFFER) ................................................. 766
19.11.40 ADC Event Group Results Emulation FIFO Register (ADEVEMUBUFFER) ........................ 767
19.11.41 ADC Group1 Results Emulation FIFO Register (ADG1EMUBUFFER)............................... 768
19.11.42 ADC Group2 Results Emulation FIFO Register (ADG2EMUBUFFER)............................... 769
19.11.43 ADC ADEVT Pin Direction Control Register (ADEVTDIR)............................................. 770
19.11.44 ADC ADEVT Pin Output Value Control Register (ADEVTOUT)....................................... 771
19.11.45 ADC ADEVT Pin Input Value Register (ADEVTIN) ..................................................... 771
19.11.46 ADC ADEVT Pin Set Register (ADEVTSET) ............................................................ 772
19.11.47 ADC ADEVT Pin Clear Register (ADEVTCLR).......................................................... 772
19.11.48 ADC ADEVT Pin Open Drain Enable Register (ADEVTPDR)......................................... 773
19.11.49 ADC ADEVT Pin Pull Control Disable Register (ADEVTPDIS)........................................ 773
19.11.50 ADC ADEVT Pin Pull Control Select Register (ADEVTPSEL)......................................... 774
19.11.51 ADC Event Group Sample Cap Discharge Control Register (ADEVSAMPDISEN)................. 774
19.11.52 ADC Group1 Sample Cap Discharge Control Register (ADG1SAMPDISEN)....................... 775
19.11.53 ADC Group2 Sample Cap Discharge Control Register (ADG2SAMPDISEN)....................... 776

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19.11.54 ADC Magnitude Compare Interrupt x Control Registers (ADMAGINTxCR) ......................... 777
19.11.55 ADC Magnitude Compare Interrupt x Mask Register (ADMAGxMASK).............................. 779
19.11.56 ADC Magnitude Compare Interrupt Enable Set Register (ADMAGINTENASET)................... 780
19.11.57 ADC Magnitude Compare Interrupt Enable Clear Register (ADMAGINTENACLR) ................ 780
19.11.58 ADC Magnitude Compare Interrupt Flag Register (ADMAGINTFLG) ................................ 781
19.11.59 ADC Magnitude Compare Interrupt Offset Register (ADMAGINTOFF) .............................. 781
19.11.60 ADC Event Group FIFO Reset Control Register (ADEVFIFORESETCR) ........................... 782
19.11.61 ADC Group1 FIFO Reset Control Register (ADG1FIFORESETCR).................................. 782
19.11.62 ADC Group2 FIFO Reset Control Register (ADG2FIFORESETCR).................................. 783
19.11.63 ADC Event Group RAM Write Address Register (ADEVRAMWRADDR)............................ 783
19.11.64 ADC Group1 RAM Write Address Register (ADG1RAMWRADDR) .................................. 784
19.11.65 ADC Group2 RAM Write Address Register (ADG2RAMWRADDR) .................................. 784
19.11.66 ADC Parity Control Register (ADPARCR)................................................................ 785
19.11.67 ADC Parity Error Address Register (ADPARADDR).................................................... 786
19.11.68 ADC Power-Up Delay Control Register (ADPWRUPDLYCTRL)...................................... 786
20 High-End Timer (N2HET) Module ........................................................................................ 787
20.1 Overview................................................................................................................... 788
20.1.1 Features.......................................................................................................... 788
20.1.2 Major Advantages .............................................................................................. 788
20.1.3 Block Diagram................................................................................................... 789
20.1.4 Timer Module Structure and Execution...................................................................... 790
20.1.5 Performance..................................................................................................... 791
20.1.6 N2HET Compared to NHET................................................................................... 791
20.1.7 NHET and N2HET Compared to HET ....................................................................... 791
20.1.8 Instructions Features........................................................................................... 792
20.1.9 Program Usage ................................................................................................. 792
20.2 N2HET Functional Description.......................................................................................... 792
20.2.1 Specialized Timer Micromachine............................................................................. 792
20.2.2 N2HET RAM Organization .................................................................................... 797
20.2.3 Time Base ....................................................................................................... 800
20.2.4 Host Interface ................................................................................................... 803
20.2.5 I/O Control....................................................................................................... 804
20.2.6 Suppression Filters............................................................................................. 820
20.2.7 Interrupts and Exceptions ..................................................................................... 821
20.2.8 Hardware Priority Scheme..................................................................................... 822
20.2.9 N2HET Requests to DMA and HTU.......................................................................... 824
20.3 Angle Functions........................................................................................................... 824
20.3.1 Software Angle Generator..................................................................................... 824
20.3.2 Hardware Angle Generator (HWAG)......................................................................... 829
20.4 N2HET Control Registers................................................................................................ 851
20.4.1 Global Configuration Register (HETGCR)................................................................... 852
20.4.2 Prescale Factor Register (HETPFR)......................................................................... 854
20.4.3 N2HET Current Address Register (HETADDR) ............................................................ 855
20.4.4 Offset Index Priority Level 1 Register (HETOFF1)......................................................... 855
20.4.5 Offset Index Priority Level 2 Register (HETOFF2)......................................................... 856
20.4.6 Interrupt Enable Set Register (HETINTENAS).............................................................. 857
20.4.7 Interrupt Enable Clear Register (HETINTENAC)........................................................... 857
20.4.8 Exception Control Register 1 (HETEXC1)................................................................... 858
20.4.9 Exception Control Register 2 (HETEXC2)................................................................... 859
20.4.10 Interrupt Priority Register (HETPRY)....................................................................... 860
20.4.11 Interrupt Flag Register (HETFLG) .......................................................................... 860
20.4.12 AND Share Control Register (HETAND) .................................................................. 861
20.4.13 HR Share Control Register (HETHRSH)................................................................... 862

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20.4.14 XOR Share Control Register (HETXOR)................................................................... 863
20.4.15 Request Enable Set Register (HETREQENS) ............................................................ 864
20.4.16 Request Enable Clear Register (HETREQENC).......................................................... 864
20.4.17 Request Destination Select Register (HETREQDS)...................................................... 865
20.4.18 NHET Direction Register (HETDIR) ........................................................................ 866
20.4.19 N2HET Data Input Register (HETDIN)..................................................................... 867
20.4.20 N2HET Data Output Register (HETDOUT)................................................................ 867
20.4.21 NHET Data Set Register (HETDSET)...................................................................... 868
20.4.22 N2HET Data Clear Register (HETDCLR).................................................................. 868
20.4.23 N2HET Open Drain Register (HETPDR)................................................................... 869
20.4.24 N2HET Pull Disable Register (HETPULDIS) .............................................................. 869
20.4.25 N2HET Pull Select Register (HETPSL) .................................................................... 870
20.4.26 Parity Control Register (HETPCR).......................................................................... 871
20.4.27 Parity Address Register (HETPAR)......................................................................... 872
20.4.28 Parity Pin Register (HETPPR)............................................................................... 873
20.4.29 Suppression Filter Preload Register (HETSFPRLD) ..................................................... 874
20.4.30 Suppression Filter Enable Register (HETSFENA)........................................................ 874
20.4.31 Loop Back Pair Select Register (HETLBPSEL)........................................................... 875
20.4.32 Loop Back Pair Direction Register (HETLBPDIR) ........................................................ 876
20.4.33 N2HET Pin Disable Register (HETPINDIS) ............................................................... 877
20.5 HWAG Registers.......................................................................................................... 878
20.5.1 HWAG Pin Select Register (HWAPINSEL) ................................................................. 879
20.5.2 HWAG Global Control Register 0 (HWAGCR0) ............................................................ 880
20.5.3 HWAG Global Control Register 1 (HWAGCR1) ............................................................ 880
20.5.4 HWAG Global Control Register 2 (HWAGCR2) ............................................................ 881
20.5.5 HWAG Interrupt Enable Set Register (HWAENASET) .................................................... 882
20.5.6 HWAG Interrupt Enable Clear Register (HWAENACLR).................................................. 883
20.5.7 HWAG Interrupt Level Set Register (HWALVLSET)....................................................... 884
20.5.8 HWAG Interrupt Level Clear Register (HWALVLCLR) .................................................... 884
20.5.9 HWAG Interrupt Flag Register (HWAFLG).................................................................. 885
20.5.10 HWAG Interrupt Offset Register 0 (HWAOFF0) .......................................................... 886
20.5.11 HWAG Interrupt Offset Register 1 (HWAOFF1) .......................................................... 887
20.5.12 HWAG Angle Value Register (HWAACNT)................................................................ 888
20.5.13 HWAG Previous Tooth Period Value Register (HWAPCNT1) .......................................... 889
20.5.14 HWAG Current Tooth Period Value Register (HWAPCNT) ............................................. 889
20.5.15 HWAG Step Width Register (HWASTWD)................................................................. 890
20.5.16 HWAG Teeth Number Register (HWATHNB) ............................................................. 891
20.5.17 HWAG Current Teeth Number Register (HWATHVL).................................................... 891
20.5.18 HWAG Filter Register (HWAFIL)............................................................................ 892
20.5.19 HWAG Filter Register 2 (HWAFIL2)........................................................................ 892
20.5.20 HWAG Angle Increment Register (HWAANGI) ........................................................... 893
20.6 Instruction Set............................................................................................................. 894
20.6.1 Instruction Summary ........................................................................................... 894
20.6.2 Abbreviations, Encoding Formats and Bits ................................................................. 896
20.6.3 Instruction Description ......................................................................................... 899
21 High-End Timer Transfer Unit (HTU) Module ........................................................................ 965
21.1 Overview................................................................................................................... 966
21.1.1 Features.......................................................................................................... 966
21.2 Module Operation......................................................................................................... 967
21.2.1 Data Transfers between Main RAM and N2HET RAM.................................................... 969
21.2.2 Arbitration of HTU Elements and Frames ................................................................... 973
21.2.3 Conditions for Frame Transfer Interruption.................................................................. 974
21.2.4 HTU Overload and Request Lost Detection................................................................. 974

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21.2.5 Memory Protection ............................................................................................. 977
21.2.6 Control Packet RAM Parity Checking........................................................................ 977
21.3 Use Cases................................................................................................................. 979
21.3.1 Example: Single Element Transfer with One Trigger Request ........................................... 979
21.3.2 Example: Multiple Element Transfer with One Trigger Request.......................................... 979
21.3.3 Example: 64-Bit-Transfer of Control Field and Data Fields ............................................... 981
21.4 HTU Control Registers................................................................................................... 982
21.4.1 Global Control Register (HTU GC)........................................................................... 983
21.4.2 Control Packet Enable Register (HTU CPENA) ............................................................ 984
21.4.3 Control Packet (CP) Busy Register 0 (HTU BUSY0) ...................................................... 985
21.4.4 Control Packet (CP) Busy Register 1 (HTU BUSY1) ...................................................... 986
21.4.5 Control Packet (CP) Busy Register 2 (HTU BUSY2) ...................................................... 986
21.4.6 Control Packet (CP) Busy Register 3 (HTU BUSY3) ...................................................... 987
21.4.7 Active Control Packet and Error Register (HTU ACPE)................................................... 987
21.4.8 Request Lost and Bus Error Control Register (HTU RLBECTRL) ....................................... 989
21.4.9 Buffer Full Interrupt Enable Set Register (HTU BFINTS).................................................. 990
21.4.10 Buffer Full Interrupt Enable Clear Register (HTU BFINTC) ............................................. 990
21.4.11 Interrupt Mapping Register (HTU INTMAP) ............................................................... 991
21.4.12 Interrupt Offset Register 0 (HTU INTOFF0) ............................................................... 992
21.4.13 Interrupt Offset Register 1 (HTU INTOFF1) ............................................................... 993
21.4.14 Buffer Initialization Mode Register (HTU BIM) ............................................................ 994
21.4.15 Request Lost Flag Register (HTU RLOSTFL)............................................................. 996
21.4.16 Buffer Full Interrupt Flag Register (HTU BFINTFL)....................................................... 996
21.4.17 BER Interrupt Flag Register (HTU BERINTFL) ........................................................... 997
21.4.18 Memory Protection 1 Start Address Register (HTU MP1S) ............................................. 998
21.4.19 Memory Protection 1 End Address Register (HTU MP1E) .............................................. 998
21.4.20 Debug Control Register (HTU DCTRL) .................................................................... 999
21.4.21 Watch Point Register (HTU WPR) ........................................................................ 1000
21.4.22 Watch Mask Register (HTU WMR)........................................................................ 1000
21.4.23 Module Identification Register (HTU ID).................................................................. 1001
21.4.24 Parity Control Register (HTU PCR) ....................................................................... 1002
21.4.25 Parity Address Register (HTU PAR) ...................................................................... 1003
21.4.26 Memory Protection Control and Status Register (HTU MPCS)........................................ 1004
21.4.27 Memory Protection Start Address Register 0 (HTU MP0S)............................................ 1007
21.4.28 Memory Protection End Address Register (HTU MP0E)............................................... 1007
21.5 Double Control Packet Configuration Memory ...................................................................... 1008
21.5.1 Initial Full Address A Register (HTU IFADDRA) .......................................................... 1009
21.5.2 Initial Full Address B Register (HTU IFADDRB) .......................................................... 1009
21.5.3 Initial N2HET Address and Control Register (HTU IHADDRCT) ....................................... 1010
21.5.4 Initial Transfer Count Register (HTU ITCOUNT).......................................................... 1011
21.5.5 Current Full Address A Register (HTU CFADDRA) ...................................................... 1012
21.5.6 Current Full Address B Register (HTU CFADDRB) ...................................................... 1013
21.5.7 Current Frame Count Register (HTU CFCOUNT) ........................................................ 1014
21.6 Examples................................................................................................................. 1015
21.6.1 Application Examples for Setting the Transfer Modes of CP A and B of a DCP ..................... 1015
21.6.2 Software Example Sequence Assuming Circular Mode for Both CP A and B ........................ 1015
21.6.3 Example of an Interrupt Dispatch Flow for a Request Lost Interrupt................................... 1016
22 General-Purpose Input/Output (GIO) Module ...................................................................... 1017
22.1 Overview.................................................................................................................. 1018
22.2 Quick Start Guide ....................................................................................................... 1019
22.3 Functional Description of GIO Module................................................................................ 1021
22.3.1 I/O Functions................................................................................................... 1021
22.3.2 Interrupt Function ............................................................................................. 1022

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22.3.3 GIO Block Diagram ........................................................................................... 1022
22.4 Device Modes of Operation............................................................................................ 1024
22.4.1 Emulation Mode ............................................................................................... 1024
22.4.2 Power-Down Mode (Low-Power Mode).................................................................... 1024
22.5 GIO Control Registers .................................................................................................. 1025
22.5.1 GIO Global Control Register (GIOGCR0).................................................................. 1026
22.5.2 GIO Interrupt Detect Register (GIOINTDET) .............................................................. 1027
22.5.3 GIO Interrupt Polarity Register (GIOPOL) ................................................................. 1028
22.5.4 GIO Interrupt Enable Registers (GIOENASET and GIOENACLR) ..................................... 1029
22.5.5 GIO Interrupt Priority Registers (GIOLVLSET and GIOLVLCLR)....................................... 1031
22.5.6 GIO Interrupt Flag Register (GIOFLG) ..................................................................... 1034
22.5.7 GIO Offset Register 1 (GIOOFF1) .......................................................................... 1035
22.5.8 GIO Offset B Register (GIOOFF2).......................................................................... 1036
22.5.9 GIO Emulation A Register (GIOEMU1) .................................................................... 1037
22.5.10 GIO Emulation B Register (GIOEMU2)................................................................... 1038
22.5.11 GIO Data Direction Registers (GIODIR[A-B])............................................................ 1039
22.5.12 GIO Data Input Registers (GIODIN[A-B])................................................................. 1039
22.5.13 GIO Data Output Registers (GIODOUT[A-B]) ........................................................... 1040
22.5.14 GIO Data Set Registers (GIODSET[A-B])................................................................ 1040
22.5.15 GIO Data Clear Registers (GIODCLR[A-B]) ............................................................. 1041
22.5.16 GIO Open Drain Registers (GIOPDR[A-B]) .............................................................. 1041
22.5.17 GIO Pull Disable Registers (GIOPULDIS[A-B]).......................................................... 1042
22.5.18 GIO Pull Select Registers (GIOPSL[A-B])................................................................ 1042
22.6 I/O Control Summary ................................................................................................... 1043
23 Controller Area Network (DCAN) Module............................................................................ 1044
23.1 Overview.................................................................................................................. 1045
23.1.1 Features........................................................................................................ 1045
23.1.2 Functional Description........................................................................................ 1045
23.2 CAN Blocks .............................................................................................................. 1046
23.2.1 CAN Core ...................................................................................................... 1046
23.2.2 Message RAM................................................................................................. 1046
23.2.3 Message Handler ............................................................................................. 1046
23.2.4 Message RAM Interface...................................................................................... 1047
23.2.5 Register and Message Object Access ..................................................................... 1047
23.2.6 Dual Clock Source ............................................................................................ 1047
23.3 CAN Bit Timing .......................................................................................................... 1048
23.3.1 Bit Time and Bit Rate......................................................................................... 1048
23.3.2 DCAN Bit Timing Registers.................................................................................. 1050
23.4 CAN Module Configuration............................................................................................. 1052
23.4.1 DCAN RAM Initialization through Hardware............................................................... 1052
23.4.2 CAN Module Initialization .................................................................................... 1052
23.5 Message RAM........................................................................................................... 1054
23.5.1 Structure of Message Objects............................................................................... 1054
23.5.2 Addressing Message Objects in RAM...................................................................... 1056
23.5.3 Message RAM Representation in Debug/Suspend Mode ............................................... 1057
23.5.4 Message RAM Representation in Direct Access Mode.................................................. 1057
23.6 Message Interface Register Sets ..................................................................................... 1058
23.6.1 Message Interface Register Sets 1 and 2 ................................................................. 1058
23.6.2 Using Message Interface Register Sets 1 and 2.......................................................... 1059
23.6.3 Message Interface Register 3 ............................................................................... 1060
23.7 Message Object Configurations....................................................................................... 1061
23.7.1 Configuration of a Transmit Object for Data Frames..................................................... 1061
23.7.2 Configuration of a Transmit Object for Remote Frames ................................................. 1061

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23.7.3 Configuration of a Single Receive Object for Data Frames ............................................. 1061
23.7.4 Configuration of a Single Receive Object for Remote Frames.......................................... 1062
23.7.5 Configuration of a FIFO Buffer .............................................................................. 1062
23.7.6 Reconfiguration of Message Objects for the Reception of Frames..................................... 1062
23.7.7 Reconfiguration of Message Objects for the Transmission of Frames................................. 1062
23.8 Message Handling ...................................................................................................... 1063
23.8.1 Message Handler Overview ................................................................................. 1063
23.8.2 Receive/Transmit Priority..................................................................................... 1063
23.8.3 Transmission of Messages in Event Driven CAN Communication ..................................... 1064
23.8.4 Updating a Transmit Object.................................................................................. 1064
23.8.5 Changing a Transmit Object................................................................................. 1064
23.8.6 Acceptance Filtering of Received Messages.............................................................. 1065
23.8.7 Reception of Data Frames................................................................................... 1065
23.8.8 Reception of Remote Frames ............................................................................... 1065
23.8.9 Reading Received Messages ............................................................................... 1065
23.8.10 Requesting New Data for a Receive Object............................................................. 1066
23.8.11 Storing Received Messages in FIFO Buffers ............................................................ 1066
23.8.12 Reading from a FIFO Buffer............................................................................... 1066
23.9 CAN Message Transfer ................................................................................................ 1068
23.9.1 Automatic Retransmission ................................................................................... 1068
23.9.2 Auto-Bus-On ................................................................................................... 1069
23.10 Interrupt Functionality .................................................................................................. 1069
23.10.1 Message Object Interrupts ................................................................................. 1069
23.10.2 Status Change Interrupts................................................................................... 1070
23.10.3 Error Interrupts............................................................................................... 1070
23.11 Global Power-Down Mode............................................................................................. 1071
23.11.1 Entering Global Power-Down Mode....................................................................... 1071
23.11.2 Wakeup From Global Power-Down Mode................................................................ 1071
23.12 Local Power-Down Mode .............................................................................................. 1072
23.12.1 Entering Local Power-Down Mode........................................................................ 1072
23.12.2 Wakeup From Local Power-Down Mode ................................................................. 1072
23.13 GIO Support ............................................................................................................. 1073
23.14 Test Modes .............................................................................................................. 1074
23.14.1 Silent Mode................................................................................................... 1074
23.14.2 Loop Back Mode............................................................................................. 1075
23.14.3 External Loop Back Mode .................................................................................. 1076
23.14.4 Loop Back Combined with Silent Mode................................................................... 1077
23.14.5 Software Control of CAN_TX Pin.......................................................................... 1077
23.15 Parity Check Mechanism .............................................................................................. 1078
23.15.1 Behavior on Parity Error .................................................................................... 1078
23.15.2 Parity Testing................................................................................................. 1078
23.16 Debug/Suspend Mode.................................................................................................. 1079
23.17 DCAN Control Registers............................................................................................... 1079
23.17.1 CAN Control Register (DCAN CTL)....................................................................... 1081
23.17.2 Error and Status Register (DCAN ES).................................................................... 1083
23.17.3 Error Counter Register (DCAN ERRC) ................................................................... 1085
23.17.4 Bit Timing Register (DCAN BTR).......................................................................... 1086
23.17.5 Interrupt Register (DCAN INT)............................................................................. 1087
23.17.6 Test Register (DCAN TEST) ............................................................................... 1088
23.17.7 Parity Error Code Register (DCAN PERR)............................................................... 1089
23.17.8 Core Release Register (DCAN REL) ..................................................................... 1089
23.17.9 Auto-Bus-On Time Register (DCAN ABOTR)............................................................ 1090
23.17.10 Transmission Request X Register (DCAN TXRQ X) .................................................. 1090

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23.17.11 Transmission Request Registers (DCAN TXRQ12 to DCAN TXRQ78) ............................ 1091
23.17.12 New Data X Register (DCAN NWDAT X)............................................................... 1092
23.17.13 New Data Registers (DCAN NWDAT12 to DCAN NWDAT78) ...................................... 1093
23.17.14 Interrupt Pending X Register (DCAN INTPND X)...................................................... 1094
23.17.15 Interrupt Pending Registers (DCAN INTPND12 to DCAN INTPND78) ............................. 1095
23.17.16 Message Valid X Register (DCAN MSGVAL X)........................................................ 1096
23.17.17 Message Valid Registers (DCAN MSGVAL12 to DCAN MSGVAL78).............................. 1097
23.17.18 Interrupt Multiplexer Registers (DCAN INTMUX12 to DCAN INTMUX78).......................... 1098
23.17.19 IF1/IF2 Command Registers (DCAN IF1CMD, DCAN IF2CMD)..................................... 1099
23.17.20 IF1/IF2 Mask Registers (DCAN IF1MSK, DCAN IF2MSK) ........................................... 1102
23.17.21 IF1/IF2 Arbitration Registers (DCAN IF1ARB, DCAN IF2ARB)...................................... 1103
23.17.22 IF1/IF2 Message Control Registers (DCAN IF1MCTL, DCAN IF2MCTL) .......................... 1104
23.17.23 IF1/IF2 Data A and Data B Registers (DCAN IF1DATA/DATB, DCAN IF2DATA/DATB) ........ 1106
23.17.24 IF3 Observation Register (DCAN IF3OBS)............................................................. 1107
23.17.25 IF3 Mask Register (DCAN IF3MSK)..................................................................... 1109
23.17.26 IF3 Arbitration Register (DCAN IF3ARB) ............................................................... 1110
23.17.27 IF3 Message Control Register (DCAN IF3MCTL) ..................................................... 1111
23.17.28 IF3 Data A and Data B Registers (DCAN IF3DATA/DATB).......................................... 1112
23.17.29 IF3 Update Enable Registers (DCAN IF3UPD12 to IF3UPD78)..................................... 1113
23.17.30 CAN TX IO Control Register (DCAN TIOC) ............................................................ 1114
23.17.31 CAN RX IO Control Register (DCAN RIOC)............................................................ 1115
24 Multi-Buffered Serial Peripheral Interface Module (MibSPI) with Parallel Pin Option (MibSPIP).1117
24.1 Overview.................................................................................................................. 1118
24.1.1 Word Format Options......................................................................................... 1118
24.1.2 Multi-buffering (Mib) Support ................................................................................ 1118
24.1.3 Transmission Lock (Multi-Buffer Mode Master Only)..................................................... 1119
24.2 Operating Modes........................................................................................................ 1119
24.2.1 Pin Configurations............................................................................................. 1120
24.2.2 Data Handling.................................................................................................. 1120
24.2.3 Operation with SPICS ........................................................................................ 1123
24.2.4 Operation with SPIENA....................................................................................... 1124
24.2.5 Five-Pin Operation (Hardware Handshaking) ............................................................. 1125
24.2.6 Data Formats .................................................................................................. 1126
24.2.7 Clocking Modes ............................................................................................... 1127
24.2.8 Data Transfer Example....................................................................................... 1129
24.2.9 Decoded and Encoded Chip Select (Master Only) ....................................................... 1130
24.2.10 Variable Chip Select Setup and Hold Timing (Master Only)........................................... 1130
24.2.11 Hold Chip-Select Active..................................................................................... 1130
24.2.12 Detection of Slave Desynchronization (Master Only)................................................... 1131
24.2.13 ENA Signal Time-Out (Master Only) ...................................................................... 1132
24.2.14 Data-Length Error............................................................................................ 1132
24.2.15 Parallel Mode (Multiple SIMO/SOMI Support, not available on all devices) ......................... 1132
24.2.16 Continuous Self-Test (Master/Slave)...................................................................... 1140
24.2.17 Half Duplex Mode............................................................................................ 1140
24.3 Test Features............................................................................................................ 1140
24.3.1 Internal Loop-Back Test Mode (Master Only) ............................................................. 1140
24.3.2 Input/Output Loopback Test Mode.......................................................................... 1141
24.4 General-Purpose I/O.................................................................................................... 1142
24.5 Low-Power Mode........................................................................................................ 1142
24.6 Interrupts ................................................................................................................. 1143
24.6.1 Interrupts in Multi-Buffer Mode .............................................................................. 1143
24.7 DMA Interface ........................................................................................................... 1145
24.7.1 DMA in Multi-Buffer Mode.................................................................................... 1145