Texas Instruments TMS570LS3137 User manual

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TMS570LS3137
SPNS162C –APRIL 2012–REVISED APRIL 2015
TMS570LS3137 16- and 32-Bit RISC Flash Microcontroller
1 Device Overview
1.1 Features
1
• High-Performance Automotive-Grade • Multiple Communication Interfaces
Microcontroller for Safety-Critical Applications – 10/100 Mbps Ethernet MAC (EMAC)
– Dual CPUs Running in Lockstep • IEEE 802.3 Compliant (3.3-V I/O Only)
– ECC on Flash and RAM Interfaces • Supports MII, RMII, and MDIO
– Built-In Self-Test (BIST) for CPU and On-chip – FlexRay Controller With Two Channels
RAMs • 8KB of Message RAM With Parity Protection
– Error Signaling Module With Error Pin • Dedicated Transfer Unit (FTU)
– Voltage and Clock Monitoring – Three CAN Controllers (DCANs)
• ARM®Cortex®-R4F 32-Bit RISC CPU • 64 Mailboxes, Each With Parity Protection
– Efficient 1.66 DMIPS/MHz With 8-Stage Pipeline • Compliant to CAN Protocol Version 2.0B
– FPU With Single- and Double-Precision – Standard Serial Communication Interface (SCI)
– 12-Region Memory Protection Unit (MPU) – Local Interconnect Network (LIN) Interface
– Open Architecture With Third-Party Support Controller
• Operating Conditions • Compliant to LIN Protocol Version 2.1
– System Clock up to 180 MHz • Can be Configured as a Second SCI
– Core Supply Voltage (VCC): 1.2 V Nominal – Inter-Integrated Circuit (I2C)
– I/O Supply Voltage (VCCIO): 3.3 V Nominal – Three Multibuffered Serial Peripheral Interfaces
– ADC Supply Voltage (VCCAD): 3.0 to 5.25 V (MibSPIs)
• Integrated Memory • 128 Words With Parity Protection Each
– 3MB of Program Flash With ECC – Two Standard Serial Peripheral Interfaces
(SPIs)
– 256KB of RAM With ECC • Two Next Generation High-End Timer (N2HET)
– 64KB of Flash With ECC for Emulated Modules
EEPROM – N2HET1: 32 Programmable Channels
• 16-Bit External Memory Interface – N2HET2: 18 Programmable Channels
• Common Platform Architecture – 160-Word Instruction RAM Each With Parity
– Consistent Memory Map Across Family Protection
– Real-Time Interrupt (RTI) Timer OS Timer – Each N2HET Includes Hardware Angle
– 96-Channel Vectored Interrupt Module (VIM) Generator
– 2-Channel Cyclic Redundancy Checker (CRC) – Dedicated High-End Transfer Unit (HTU) With
• Direct Memory Access (DMA) Controller MPU for Each N2HET
– 16 Channels and 32 Control Packets • Two 12-Bit Multibuffered ADC Modules
– Parity Protection for Control Packet RAM – ADC1: 24 Channels
– DMA Accesses Protected by Dedicated MPU – ADC2: 16 Channels Shared With ADC1
• Frequency-Modulated Phase-Locked Loop – 64 Result Buffers With Parity Protection Each
(FMPLL) With Built-In Slip Detector • General-Purpose Input/Output (GPIO) Pins
• Separate Nonmodulating PLL for FlexRay™ Capable of Generating Interrupts
• Trace and Calibration Capabilities – Sixteen Pins on the ZWT Package
– Embedded Trace Macrocell (ETM-R4) – Four Pins on the PGE Package
– Data Modification Module (DMM) • IEEE 1149.1 JTAG, Boundary Scan and ARM
– RAM Trace Port (RTP) CoreSight™ Components
– Parameter Overlay Module (POM) • JTAG Security Module
• Packages
– 144-Pin Quad Flatpack (PGE) [Green]
– 337-Ball Grid Array (ZWT) [Green]
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
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TMS570LS3137
SPNS162C –APRIL 2012–REVISED APRIL 2015 www.ti.com
1.2 Applications
• Braking Systems (Antilock Brake Systems and • Active Driver Assistance Systems
Electronic Stability Control) • Aerospace and Avionics
• Electric Power Steering • Railway Communications
• HEV and EV Inverter Systems • Off-road Vehicles
• Battery Management Systems
2Device Overview Copyright © 2012–2015, Texas Instruments Incorporated
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TMS570LS3137
www.ti.com SPNS162C –APRIL 2012–REVISED APRIL 2015
1.3 Description
The TMS570LS3137 device is a high-performance automotive-grade microcontroller family for safety
systems. The safety architecture includes dual CPUs in lockstep, CPU and memory BIST logic, ECC on
both the flash and the data SRAM, parity on peripheral memories, and loopback capability on peripheral
I/Os.
The TMS570LS3137 device integrates the ARM Cortex-R4F Floating-Point CPU. The CPU offers an
efficient 1.66 DMIPS/MHz, and has configurations that can run up to 180 MHz, providing up to 298
DMIPS. The device supports the word-invariant big-endian [BE32] format.
The TMS570LS3137 device has 3MB of integrated flash and 256KB of data RAM. Both the flash and RAM
have single-bit error correction and double-bit error detection. The flash memory on this device is a
nonvolatile, electrically erasable, and programmable memory implemented with a 64-bit-wide data bus
interface. The flash operates on a 3.3-V supply input (same level as I/O supply) for all read, program, and
erase operations. When in pipeline mode, the flash operates with a system clock frequency of up to 180
MHz. The SRAM supports single-cycle read and write accesses in byte, halfword, word, and double-word
modes.
The TMS570LS3137 device features peripherals for real-time control-based applications, including two
Next Generation High-End Timer (N2HET) timing coprocessors and two 12-bit Analog-to-Digital
Converters (ADCs) supporting up to 24 inputs.
The N2HET is an advanced intelligent timer that provides sophisticated timing functions for real-time
applications. The timer is software-controlled, using a reduced instruction set, with a specialized timer
micromachine and an attached I/O port. The N2HET can be used for pulse-width-modulated outputs,
capture or compare inputs, or GPIO. The N2HET is especially well suited for applications requiring
multiple sensor information and drive actuators with complex and accurate time pulses. A High-End Timer
Transfer Unit (HTU) can perform DMA-type transactions to transfer N2HET data to or from main memory.
A Memory Protection Unit (MPU) is built into the HTU.
The device has two 12-bit-resolution MibADCs with 24 channels and 64 words of parity-protected buffer
RAM each. The MibADC channels can be converted individually or can be grouped by software for
sequential conversion sequences. Sixteen channels are shared between the two MibADCs. There are
three separate groupings. Each sequence can be converted once when triggered or configured for
continuous conversion mode. The MibADC has a 10-bit mode for use when compatibility with older
devices or faster conversion time is desired.
The device has multiple communication interfaces: three MibSPIs, two SPIs, one LIN, one SCI, three
DCANs, one I2C module, one Ethernet, and one FlexRay controller. The SPIs provide a convenient
method of serial high-speed communication between similar shift-register type devices. The LIN supports
the Local Interconnect standard 2.0 and can be used as a UART in full-duplex mode using the standard
Non-Return-to-Zero (NRZ) format.
The DCAN supports the CAN 2.0 (A and B) protocol standard and uses a serial, multimaster
communication protocol that efficiently supports distributed real-time control with robust communication
rates of up to 1 Mbps. The DCAN is ideal for systems operating in noisy and harsh environments (for
example, automotive vehicle networking and industrial fieldbus) that require reliable serial communication
or multiplexed wiring.
The FlexRay controller uses a dual-channel serial, fixed time base multimaster communication protocol
with communication rates of 10 Mbps per channel. A FlexRay Transfer Unit (FTU) enables autonomous
transfers of FlexRay data to and from the CPU main memory. Transfers are protected by a dedicated,
built-in MPU. The Ethernet module supports MII, RMII, and MDIO interfaces.
The I2C module is a multimaster communication module providing an interface between the
microcontroller and an I2C-compatible device through the I2C serial bus. The I2C supports speeds of 100
and 400 Kbps.
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The Frequency-Modulated Phase-Locked Loop (FMPLL) clock module is used to multiply the external
frequency reference to a higher frequency for internal use. There are two FMPLL modules on this device.
These modules, when enabled, provide two of the seven possible clock source inputs to the Global Clock
Module (GCM). The GCM manages the mapping between the available clock sources and the device
clock domains.
The device also has an External Clock Prescaler (ECP) module that when enabled, outputs a continuous
external clock on the ECLK pin (or ball). The ECLK frequency is a user-programmable ratio of the
peripheral interface clock (VCLK) frequency. This low-frequency output can be monitored externally as an
indicator of the device operating frequency.
The DMA controller has 16 channels, 32 control packets, and parity protection on its memory. An MPU is
built into the DMA to limit the DMA to prescribed areas of memory and to protect the rest of the memory
system from any malfunction of the DMA.
The Error Signaling Module (ESM) monitors all device errors and determines whether an interrupt is
generated or the external ERROR pin is toggled when a fault is detected. The ERROR pin can be
monitored externally as an indicator of a fault condition in the microcontroller.
The External Memory Interface (EMIF) provides off-chip expansion capability with the ability to interface to
synchronous DRAM (SDRAM) devices, asynchronous memories, peripherals or FPGA devices.
Several interfaces are implemented to enhance the debugging capabilities of application code. In addition
to the built-in ARM Cortex-R4F CoreSight debug features, an External Trace Macrocell (ETM) provides
instruction and data trace of program execution. For instrumentation purposes, a RAM Trace Port (RTP)
module is implemented to support high-speed tracing of RAM and peripheral accesses by the CPU or any
other master. A Data Modification Module (DMM) gives the ability to write external data into the device
memory. Both the RTP and DMM have no or only minimum impact on the program execution time of the
application code. A Parameter Overlay Module (POM) can reroute flash accesses to internal memory or to
the EMIF. This rerouting allows the dynamic calibration against production code of parameters and tables
without rebuilding the code to explicitly access RAM or halting the processor to reprogram the data flash.
With integrated safety features and a wide choice of communication and control peripherals, the
TMS570LS3137 device is an ideal solution for high-performance real-time control applications with safety-
critical requirements.
Device Information(1)
PART NUMBER PACKAGE BODY SIZE
TMS570LS3137ZWT NFBGA (337) 16.0 mm × 16.0 mm
TMS570LS3137PGE LQFP (144) 20.0 mm × 20.0 mm
(1) For more information, see Section 9,Mechanical Packaging and Orderable Information.
4Device Overview Copyright © 2012–2015, Texas Instruments Incorporated
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DMA POM DMM HTU1 FTU HTU2 EMAC
Switched Central Resource Switched Central Resource
Main Cross Bar: Arbitration and Prioritization Control
CRC Switched Central Resource Peripheral Central Resource Bridge
Dual Cortex-R4F
CPUs in Lockstep
EMAC Slaves
Switched Central Resource
MibADC1
DCAN1
MibADC2
DCAN2
DCAN3
LIN
SCI
I2CN2HET1 FlexRay GION2HET2
SPI4
64KB Flash
for EEPROM
Emulation
with ECC
MDIO
MII
MibSPI1
CAN1_RX
CAN1_TX
CAN2_RX
CAN2_TX
CAN3_RX
CAN3_TX
MIBSPI1_CLK
MIBSPI1_SIMO[1:0]
MIBSPI1_SOMI[1:0]
MIBSPI1_nCS[5:0]
MIBSPI1_nENA
SPI2
SPI2_CLK
SPI2_SIMO
SPI2_SOMI
SPI2_nCS[1:0]
SPI2_nENA
MibSPI3
MIBSPI3_CLK
MIBSPI3_SIMO
MIBSPI3_SOMI
MIBSPI3_nCS[5:0]
MIBSPI3_nENA
SPI4_CLK
SPI4_SIMO
SPI4_SOMI
SPI4_nCS0
SPI4_nENA
MibSPI5
MIBSPI5_SIMO[3:0]
MIBSPI5_SOMI[3:0]
MIBSPI5_nCS[3:0]
MIBSPI5_nENA
LIN_RX
LIN_TX
SCI_RX
SCI_TX
IOMM
PMM
VIM
RTI
DCC1
DCC2
3MB
Flash
with
ECC ETM-R4
RTP
64K
64K
64K
64K
RTPCLK RTPnENA RTPSYNC RTPDATA[15:0]
TRACECLKIN
TRACECLK
TRACECTL
ETMDATA[31:0]
DMMCLK
DMMnENA DMMSYNC DMMDATA[15:0]
256KB
RAM
with
ECC
MDCLK
MDIO
MII_RXD[3:0]
MII_RXER
MII_TXD[3:0]
MII_TXEN
MII_TXCLK
MII_RXCLK
MII_CRS
MII_RXDV
MII_COL
EMIF
EMIF_CLK
EMIF_CKE
EMIF_nCS[4:2]
EMIF_nCS[0]
EMIF_ADDR[21:0]
EMIF_BA[1:0]
EMIF_DATA[15:0]
EMIF_nDQM[1:0]
EMIF_nOE
EMIF_nWE
EMIF_nRAS
EMIF_nCAS
EMIF_nRW
EMIF_nWAIT
VSSAD
VCCAD
I2C_SCL
I2C_SDA
FRAY_RX1
FRAY_TX1
FRAY_TXEN1
FRAY_RX2
FRAY_TX2
FRAY_TXEN2
GIOB[7:0] GIOA[7:0]
N2HET2[18,16]
N2HET2[15:0] N2HET1[31:0]
VCCAD
VSSAD
ADREFHI
ADREFLO
AD1EVT
AD1IN[7:0]
AD1IN[23:8] AD2IN[15:0]
AD2EVT
ADREFHI
ADREFLO
# 2
# 3
# 4
# 1
# 2
# 1
always on
Core/RAM RAM Core
# 5
# 3
Color Legend for Power Domains
SYS
nPORRST
nRST
ECLK
ESM nERROR
N2HET1_PIN_nDIS N2HET2_PIN_nDIS
TMS570LS3137
www.ti.com SPNS162C –APRIL 2012–REVISED APRIL 2015
1.4 Functional Block Diagram
Figure 1-1. Functional Block Diagram
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TMS570LS3137
SPNS162C –APRIL 2012–REVISED APRIL 2015 www.ti.com
Table of Contents
1 Device Overview ......................................... 16.11 Tightly Coupled RAM (TCRAM) Interface Module .. 80
1.1 Features .............................................. 16.12 Parity Protection for Peripheral RAMs .............. 80
1.2 Applications........................................... 26.13 On-Chip SRAM Initialization and Testing ........... 82
1.3 Description............................................ 36.14 External Memory Interface (EMIF) .................. 84
1.4 Functional Block Diagram ............................ 56.15 Vectored Interrupt Manager......................... 91
2 Revision History ......................................... 76.16 DMA Controller...................................... 94
3 Device Comparison ..................................... 96.17 Real Time Interrupt Module ......................... 96
4 Terminal Configuration and Functions ........... 10 6.18 Error Signaling Module.............................. 98
4.1 PGE QFP Package Pinout (144-Pin) ............... 10 6.19 Reset / Abort / Error Sources...................... 102
4.2 ZWT BGA Package Ball-Map (337-Ball Grid Array) 11 6.20 Digital Windowed Watchdog....................... 104
4.3 Terminal Functions ................................. 12 6.21 Debug Subsystem ................................. 105
5 Specifications .......................................... 41 7 Peripheral Information and Electrical
Specifications ......................................... 116
5.1 Absolute Maximum Ratings ........................ 41 7.1 Peripheral Legend ................................. 116
5.2 ESD Ratings ........................................ 41 7.2 Multibuffered 12-Bit Analog-to-Digital Converter .. 116
5.3 Power-On Hours (POH)............................. 41 7.3 General-Purpose Input/Output..................... 127
5.4 Recommended Operating Conditions............... 42 7.4 Enhanced High-End Timer (N2HET) .............. 128
5.5 Switching Characteristics for Clock Domains....... 43 7.5 FlexRay Interface .................................. 133
5.6 Wait States Required ............................... 43 7.6 Controller Area Network (DCAN) .................. 135
5.7 Power Consumption................................. 44 7.7 Local Interconnect Network Interface (LIN)........ 136
5.8 Input/Output Electrical Characteristics.............. 45 7.8 Serial Communication Interface (SCI) ............. 137
5.9 Thermal Resistance Characteristics ................ 46 7.9 Inter-Integrated Circuit (I2C) ....................... 138
5.10 Output Buffer Drive Strengths ...................... 47 7.10 Multibuffered / Standard Serial Peripheral
5.11 Input Timings........................................ 48 Interface............................................ 141
5.12 Output Timings...................................... 48 7.11 Ethernet Media Access Controller ................. 153
5.13 Low-EMI Output Buffers ............................ 50 8 Device and Documentation Support.............. 157
6 System Information and Electrical 8.1 Device Support..................................... 157
Specifications........................................... 52 8.2 Documentation Support............................ 159
6.1 Device Power Domains ............................. 52 8.3 Community Resources............................. 159
6.2 Voltage Monitor Characteristics..................... 53 8.4 Trademarks ........................................ 159
6.3 Power Sequencing and Power On Reset ........... 54 8.5 Electrostatic Discharge Caution ................... 159
6.4 Warm Reset (nRST)................................. 56 8.6 Glossary............................................ 159
6.5 ARM-R4F CPU Information ......................... 57 8.7 Device Identification Code Register ............... 160
6.6 Clocks ............................................... 60 8.8 Die Identification Registers ....................... 161
6.7 Clock Monitoring .................................... 68 8.9 Module Certifications............................... 161
6.8 Glitch Filters......................................... 70 9 Mechanical Packaging and Orderable
6.9 Device Memory Map ................................ 71 Information............................................. 168
6.10 Flash Memory ....................................... 77 9.1 Packaging Information ............................. 168
6Table of Contents Copyright © 2012–2015, Texas Instruments Incorporated
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TMS570LS3137
www.ti.com SPNS162C –APRIL 2012–REVISED APRIL 2015
2 Revision History
This data manual revision history highlights the technical changes made to the SPNS162B device-specific
data manual to make it an SPNS162C revision.
Scope: Applicable updates to the Hercules™ TMS570 MCU device family, specifically relating to the
TMS570LS3137 devices, which are now in the production data (PD) stage of development have been
incorporated.
Changes from August 1, 2013 to April 30, 2015 (from B Revision (July 2013) to C Revision) Page
•Section 1 (Device Overview): Updated/Changed section title ................................................................. 1
• Updated/Changed the N2HET feature............................................................................................. 1
• (Device Information): Added table.................................................................................................. 4
• Added Section 3, Device Comparison ............................................................................................. 9
•Section 4 (Terminal Configuration and Functions): Updated/Changed section title........................................ 10
•Table 4-2 (PGE Enhanced High-End Timer Modules (N2HET1, N2HET2)): Updated/Changed N2HET1 time
input capture or output compare pin description................................................................................ 14
•Table 4-2: Added N2HET1_PIN_nDIS signal DESCRIPTION ................................................................ 14
•Table 4-2: Updated/Changed N2HET2 time input capture or output compare pin description ........................... 15
•Table 4-2: Added N2HET2_PIN_nDIS signal DESCRIPTION ................................................................ 15
•Table 4-3 Updated description about using GIOB[2] on pin 55 .............................................................. 15
•Table 4-16 (PGE Test and Debug Modules Interface): Updated/Changed TEST pin description........................ 19
•Table 4-22 (ZWT Enhanced High-End Timer (N2HET) Modules): Updated/Changed N2HET1 time input capture
or output compare pin description ................................................................................................ 23
•Table 4-22 Added alternate terminals for N2HET1 pins 17, 19, 21, 23, 25, 27, 29 and 31............................... 23
•Table 4-22: Added N2HET1_PIN_nDIS signal DESCRIPTION............................................................... 23
•Table 4-22: Updated/Changed N2HET2 time input capture or output compare pin description.......................... 24
•Table 4-22: Added N2HET2_PIN_nDIS signal DESCRIPTION............................................................... 24
•Table 4-23 Updated description about using GIOB[2] on ball V10 ........................................................... 25
•Table 4-32: Added "receive" to the RMII_CRS_DV pin Description.......................................................... 29
•Table 4-32: Added "receive" to the MII_CRS pin Description................................................................. 29
•Table 4-34 (External Memory Interface (EMIF)): Global: Deleted EMIF_RNW pin function............................... 30
•Table 4-40 (ZWT Test and Debug Modules Interface): Updated/Changed TEST pin description ....................... 36
•Table 4-42 (No Connects): Deleted NC pins A8, B8, and B9; supported on FlexRay Interface Controller ............. 37
•Section 5 (Specifications): Updated/Changed section title .................................................................... 41
•Section 5.1 (Absolute Maximum Ratings): Reformatted table................................................................. 41
•Section 5.1 (Absolute Maximum Ratings): Updated/Changed VCCAD supply voltage range MAX value from "5.5"
to "6.25" V............................................................................................................................ 41
•Section 5.1: Updated/Changed ADC input pins input voltage range MAX value from "5.5" to "6.25" V................. 41
•Section 5.2 (ESD Ratings): Added table (new).................................................................................. 41
•Section 5.3 (Power-On Hours (POH)): Added table (new) .................................................................... 41
•Section 5.8 (Input/Output Electrical Characteristics): Updated/Changed Input Clamp Current from IIC to IIK........... 45
•Section 5.9 (Thermal Resistance Characteristics): Moved section and updated/changed subsection title. ............ 46
•Table 5-2 (Thermal Resistance Characteristics (PGE Package)): Added test conditions and added ΨJT row for
PGE package........................................................................................................................ 46
•Table 5-3 (Thermal Resistance Characteristics (ZWT Package)): Added test conditions and added ΨJT row for
ZWT package........................................................................................................................ 46
• Clarified impact of SPI2PC9 register on drive strength of SPI2SOMI pin .................................................. 47
• Updated/Changed the MIN value of tv(RST) to 2256tc(OSC) ns .................................................................. 56
•Section 6.6.1 (Clock Sources): Added Table 6-8, Available Clock Source cross-references............................. 60
•Section 6.6.1.1 (Main Oscillator): Added Figure 6-4, Recommended Crystal/Clock Connection cross-reference ..... 60
•Table 6-10 Added limits for HF LPO after software trim ...................................................................... 62
•Table 6-13 (Clock Domain Descriptions): Added missing "1" to the VCLKACON clock source selection register
name for VCLKA3 row.............................................................................................................. 65
•Table 6-20 Corrected size of bank 7 OTP and bank 7 OTP ECC............................................................ 72
•Figure 6-10 (TCRAM Block Diagram): Updated/Changed figure, deleted A TCM.......................................... 80
•Table 6-25 Added table footnotes identifying the address ranges of the ESRAM PBIST groups........................ 82
•Table 6-25 Added RAM power domain information in the table notes....................................................... 82
•Table 6-26(Memory Initialization): Updated/Changed N2HET2 RAM ending address from "0xFF57FFFF" to
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"0xFF45FFFF" ....................................................................................................................... 83
•Table 6-38 Corrected base JTAG ID Base Value From 0xnD8A002F to 0xnB8A002F.................................. 106
•Table 6-38 (JTAG ID Code): Added JTAG Identification Code for Silicon Revision "Rev D" ........................... 106
•Table 7-7 (MibADC Recommended Operating Conditions): Updated/Changed Analog input clamp current from
IAIC to IAIK ............................................................................................................................ 121
• FlexRay Interface, Section 7.5.1 (Features): Updated/Changed "8KB of message ..." bullet for clarification......... 133
• Controller Area Network (DCAN) Section 7.6.1 (Features): Updated/Changed TRM references to the correct
document titles .................................................................................................................... 135
•Table 7-24 (SPI Master Mode External Timing Parameters (CLOCK PHASE = 0, SPICLK = output, SPISIMO =
output, and SPISOMI = input)): Updated/Changed table footnote to "... CLOCK PHASE bit (SPIFMTx.16) is
cleared" ............................................................................................................................. 145
•Section 7.11.1 (Ethernet MII Electrical and Timing Specifications): Updated/Changed the MII parameter names
and parametric descriptions for this section.................................................................................... 153
•Section 7.11.2 (Ethernet RMII Electrical and Timing Specifications): Updated/Changed section title for
clarification.......................................................................................................................... 155
•Section 7.11.2 Updated/Changed the RMII parameter names and parametric descriptions for this section.......... 155
•Section 7.11.3 (Management Data Input/Output (MDIO) Electrical and Timing Specifications): Updated/Changed
section title for clarification ....................................................................................................... 156
•Table 7-32 (Timing Requirements for MDIO Input): Updated/Changed table title and formatting for clarification.... 156
•Section 8 (Device and Documentation Support): Updated/Changed section to meet new requirements, including
addition of several subsections .................................................................................................. 157
•Section 8.7 (Device Identification Code Register): Added Device ID code value for silicon Rev D .................... 160
•Section 8.8 (Die Identification Registers): Updated/Changed the address of the two die identification registers
(DIEIDL and DIEIDH) to point to the original registers at location 0xFFFFFF7C and 0xFFFFFF80 for this section. 161
•Table 8-2 (Die-ID Registers): Updated/Changed the BIT LOCATION column for all ITEM rows....................... 161
•Section 9 (Mechanical Packaging and Orderable Information): Updated/Changed section title........................ 168
•Section 9.1 (Packaging Information): Updated/Changed the paragraph ................................................... 168
8Revision History Copyright © 2012–2015, Texas Instruments Incorporated
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TMS570LS3137
www.ti.com SPNS162C –APRIL 2012–REVISED APRIL 2015
3 Device Comparison
lists the features of the devices.
Table 3-1. TMS570LS3137 Device Comparison(1)(2)
FEATURES DEVICES
Generic Part Number TMS570LC4357ZWT(3) TMS570LS3137ZWT(3) TMS570LS3137PGE(3) TMS570LS3135ZWT TMS570LS3135PGE TMS570LS1227ZWT(3)
Package 337 BGA 337 BGA 144 QFP 337 BGA 144 QFP 337 BGA
CPU ARM Cortex-R5F ARM Cortex-R4F ARM Cortex-R4F ARM Cortex-R4F ARM Cortex-R4F ARM Cortex-R4F
Frequency (MHz) 300 180 160 180 160 180
32 I
Cache (KB) – – – – –
32 D
Flash (KB) 4096 3072 3072 3072 3072 1280
RAM (KB) 512 256 256 256 256 192
Data Flash [EEPROM] 128 64 64 64 64 64
(KB)
EMAC 10/100 10/100 10/100 – – 10/100
FlexRay 2-ch 2-ch 2-ch 2-ch 2-ch 2-ch
CAN 4 3 3 3 3 3
MibADC 2 (41ch) 2 (24ch) 2 (24ch) 2 (24ch) 2 (24ch) 2 (24ch)
12-bit (Ch)
N2HET (Ch) 2 (64) 2 (44) 2 (40) 2 (50) 2 (50) 2 (44)
ePWM Channels 14 – – – – 14
eCAP Channels 6 – – – – 6
eQEP Channels 2 – – – – 2
MibSPI (CS) 5 (4 x 6 + 2) 3 (6 + 6 + 4) 3 (5 + 6 + 1) 3 (6 + 6 + 4) 3 (5 + 6 + 1) 3 (6 + 6 + 4)
SPI (CS) – 2 (2 + 1) 1 (1) 2 (2 + 1) 1 (1) 2 (2 + 1)
SCI (LIN) 4 (2 with LIN) 2 (1 with LIN) 2 (1 with LIN) 2 (1 with LIN) 2 (1 with LIN) 2 (1 with LIN)
2 1 1 1 1 1
I2C
GPIO (INT)(4) 168 (with 16 interrupt capable) 144 (with 16 interrupt capable) 58 (with 4 interrupt capable) 144 (with 16 interrupt capable) 58 (with 4 interrupt capable) 101 (with 16 interrupt capable)
EMIF 16-bit data 16-bit data – 16-bit data – 16-bit data
ETM (Trace) 32-bit 32-bit – 32-bit – –
RTP/DMM 16/16 16/16 – 16/16 – –
Operating -40ºC to 125ºC -40ºC to 125ºC -40ºC to 125ºC -40ºC to 125ºC -40ºC to 125ºC -40ºC to 125ºC
Temperature
Core Supply (V) 1.14 V – 1.32 V 1.14 V – 1.32 V 1.14 V – 1.32 V 1.14 V – 1.32 V 1.14 V – 1.32 V 1.14 V – 1.32 V
I/O Supply (V) 3.0 V – 3.6 V 3.0 V – 3.6 V 3.0 V – 3.6 V 3.0 V – 3.6 V 3.0 V – 3.6 V 3.0 V – 3.6 V
(1) For additional device variants, see www.ti.com/tms570
(2) This table reflects the maximum configuration for each peripheral. Some functions are multiplexed and not all pins are available at the same time.
(3) Superset device
(4) Total number of pins that can be used as general-purpose input or output when not used as part of a peripheral
Copyright © 2012–2015, Texas Instruments Incorporated Device Comparison 9
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1108
2
3
4
5
FRAYTXEN2
nTRST 109
144
110
111
112
113
114
115
116
117
118
119
120
121
AD1IN[10] / AD2IN[10]
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
2323
24
25
26
2727
28
29
30
31
32
33
34
35
36
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
FRAYTX2
FRAYRX2
MIBSPI3NCS[3]
MIBSPI3NCS[2]
N2HET1[11]
FLTP1
FLTP2
GIOA[2]
VCCIO
VSS
CAN3RX
CAN3TX
GIOA[5]
N2HET1[22]
GIOA[6]
VCC
OSCIN
Kelvin_GND
OSCOUT
VSS
GIOA[7]
N2HET1[01]
N2HET1[03]
N2HET1[0]
VCCIO
VSS
VSS
VCC
N2HET1[02]
N2HET1[05]
MIBSPI5NCS[0]
N2HET1[07]
TEST
N2HET1[09]
N2HET1[4]
MIBSPI3NCS[1]
N2HET1[06]
N2HET1[13]
MIBSPI1NCS[2]
N2HET1[15]
VCCIO
VSS
VSS
VCC
nPORRST
VSS
VCC
VCC
VSS
MIBSPI3SOMI
MIBSPI3SIMO
MIBSPI3CLK
MIBSPI3NENA
MIBSPI3NCS[0]
VSS
VCC
AD1IN[16] / AD2IN[0]
AD1IN[17] / AD2IN[01]
AD1IN[0]
AD1IN[07]
AD1IN[18] / AD2IN[02]
AD1IN[19] / AD2IN[03]
AD1IN[20] / AD2IN[04]
AD1IN[21] / AD2IN[05]
ADREFHI
ADREFLO
VSSAD
VCCAD
AD1IN[09] / AD2IN[09]
AD1IN[01]
AD1IN[02]
AD1IN[03]
AD1IN[11] / AD2IN[11]
AD1IN[04]
AD1IN[12] / AD2IN[12]
AD1IN[05]
AD1IN[13] / AD2IN[13]
AD1IN[06]
AD1IN[22] / AD2IN[06]
AD1IN[14] / AD2IN[14]
AD1IN[08] / AD2IN[08]
AD1IN[23] / AD2IN[07]
AD1IN[15] / AD2IN[15]
AD1EVT
VCC
VSS
CAN1TX
CAN1RX
N2HET1[24]
N2HET1[26]
MIBSPI1SIMO
MIBSPI1SOMI
MIBSPI1CLK
MIBSPI1NENA
MIBSPI5NENA
MIBSPI5SOMI[0]
MIBSPI5SIMO[0]
MIBSPI5CLK
VCC
VSS
VSS
VCCIO N2HET1[08]
N2HET1[28]
TMS
TDI
TDO
TCK
RTCK
VCC
VSS
nRST
nERROR
N2HET1[10]
ECLK
VCCIO
VSS
VSS
VCC
N2HET1[12]
N2HET1[14]
FRAYRX1
N2HET1[30]
CAN2TX
CAN2RX
MIBSPI1NCS[1]
LINRX
LINTX
FRAYTX1
VCCP
VSS
VCCIO
VCC
VSS
N2HET1[16]
N2HET1[18]
N2HET1[20]
FRAYTXEN1
VCC
VSS
MIBSPI1NCS[0]
TMS570LS3137
SPNS162C –APRIL 2012–REVISED APRIL 2015 www.ti.com
4 Terminal Configuration and Functions
4.1 PGE QFP Package Pinout (144-Pin)
A. Pins can have multiplexed functions. Only the default function is depicted in the figure.
Figure 4-1. PGE QFP Package Pinout (144-Pin)(A)
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A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
W
19
VSS
VSS
TMS
N2HET1
[10]
MIBSPI5
NCS[0]
MIBSPI1
SIMO
MIBSPI1
NENA
MIBSPI5
CLK
MIBSPI5
SIMO[0]
N2HET1
[28]
DMM_
DATA[0]
CAN3RX
AD1EVT
AD1IN[15]
/
AD2IN[15]
AD1IN[22]
/
AD2IN[06]
AD1IN
[06]
AD1IN[11]
/
AD2IN[11]
VSSAD
VSSAD
19
18
VSS
TCK
TDO
nTRST
N2HET1
[08]
MIBSPI1
CLK
MIBSPI1
SOMI
MIBSPI5
NENA
MIBSPI5
SOMI[0]
N2HET1
[0]
DMM_
DATA[1]
CAN3TX
NC
AD1IN[08]
/
AD2IN[08]
AD1IN[14]
/
AD2IN[14]
AD1IN[13]
/
AD2IN[13]
AD1IN
[04]
AD1IN
[02]
VSSAD
18
17
TDI
RST
EMIF_
ADDR[21]
EMIF_
nWE
MIBSPI5
SOMI[1]
DMM_
CLK
MIBSPI5
SIMO[3]
MIBSPI5
SIMO[2]
N2HET1
[31]
EMIF_
nCS[3]
EMIF_
nCS[2]
EMIF_
nCS[4]
EMIF_
nCS[0]
NC
AD1IN
[05]
AD1IN
[03]
AD1IN[10]
/
AD2IN[10]
AD1IN
[01]
AD1IN[09]
/
AD2IN[09]
17
16
RTCK
FRAY
TXEN1
EMIF_
ADDR[20]
EMIF_
BA[1]
MIBSPI5
SIMO[1]
DMM_
NENA
MIBSPI5
SOMI[3]
MIBSPI5
SOMI[2]
DMM_
SYNC
NC
NC
NC
NC
NC
AD1IN[23]
/
AD2IN[07]
AD1IN[12]
/
AD2IN[12]
AD1IN[19]
/
AD2IN[03]
ADREFLO
VSSAD
16
15
FRAY
RX1
FRAY
TX1
EMIF_
ADDR[19]
EMIF_
ADDR[18]
ETM
DATA[06]
ETM
DATA[05]
ETM
DATA[04]
ETM
DATA[03]
ETM
DATA[02]
ETM
DATA[16] /
EMIF_
DATA[0]
ETM
DATA[17] /
EMIF_
DATA[1]
ETM
DATA[18] /
EMIF_
DATA[2]
ETM
DATA[19] /
EMIF_
DATA[3]
NC
NC
AD1IN[21]
/
AD2IN[05]
AD1IN[20]
/
AD2IN[04]
ADREFHI
VCCAD
15
14
N2HET1
[26]
nERROR
EMIF_
ADDR[17]
EMIF_
ADDR[16]
ETM
DATA[07]
VCCIO
VCCIO
VCCIO
VCC
VCC
VCCIO
VCCIO
VCCIO
VCCIO
NC
NC
AD1IN[18]
/
AD2IN[02]
AD1IN
[07]
AD1IN
[0]
14
13
N2HET1
[17]
N2HET1
[19]
EMIF_
ADDR[15]
NC
ETM
DATA[12] /
EMIF_BA[0]
VCCIO
VCCIO
ETM
DATA[01]
NC
AD1IN[17]
/
AD2IN[01]
AD1IN[16]
/
AD2IN[0]
NC
13
12
ECLK
N2HET1
[04]
EMIF_
ADDR[14]
NC
ETM
DATA[13] /
EMIF_nOE
VCCIO
VSS
VSS
VCC
VSS
VSS
VCCIO
ETM
DATA[0]
MIBSPI5
NCS[3]
NC
NC
NC
12
11
N2HET1
[14]
N2HET1
[30]
EMIF_
ADDR[13]
NC
ETM
DATA[14] /
EMIF_
nDQM[1]
VCCIO
VSS
VSS
VSS
VSS
VSS
VCCPLL
ETME
TRACE
CTL
NC
NC
NC
NC
11
10
CAN1TX
CAN1RX
EMIF_
ADDR[12]
NC
ETM
DATA[15] /
EMIF_
nDQM[0]
VCC
VCC
VSS
VSS
VSS
VCC
VCC
ETM
TRACE
CLKOUT
NC
NC
MIBSPI3
NCS[0]
GIOB[3]
10
9
N2HET1
[27]
FRAY
TXEN2
EMIF_
ADDR[11]
NC
ETM
DATA[08] /
EMIF_
ADDR[5]
VCC
VSS
VSS
VSS
VSS
VSS
VCCIO
ETM
TRACE
CLKIN
NC
NC
MIBSPI3
CLK
MIBSPI3
NENA
9
8
FRAY
RX2
FRAY
TX2
EMIF_
ADDR[10]
NC
ETM
DATA[09] /
EMIF_
ADDR[4]
VCCP
VSS
VSS
VCC
VSS
VSS
VCCIO
ETM
DATA[31] /
EMIF_
DATA[15]
NC
NC
MIBSPI3
SOMI
MIBSPI3
SIMO
8
7
LINRX
LINTX
EMIF_
ADDR[9]
NC
ETM
DATA[10] /
EMIF_
ADDR[3]
VCCIO
VCCIO
ETM
DATA[30] /
EMIF_
DATA[14]
NC
NC
N2HET1
[09]
nPORRST
7
6
GIOA[4]
MIBSPI5
NCS[1]
EMIF_
ADDR[8]
NC
ETM
DATA[11] /
EMIF_
ADDR[2]
VCCIO
VCCIO
VCCIO
VCCIO
VCC
VCC
VCCIO
VCCIO
VCCIO
ETM
DATA[29] /
EMIF_
DATA[13]
NC
NC
N2HET1
[05]
MIBSPI5
NCS[2]
6
5
GIOA[0]
GIOA[5]
EMIF_
ADDR[7]
EMIF_
ADDR[1]
ETM
DATA[20] /
EMIF_
DATA[4]
ETM
DATA[21] /
EMIF_
DATA[5]
ETM
DATA[22] /
EMIF_
DATA[6]
FLTP2
FLTP1
ETM
DATA[23] /
EMIF_
DATA[7]
ETM
DATA[24] /
EMIF_
DATA[8]
ETM
DATA[25] /
EMIF_
DATA[9]
ETM
DATA[26] /
EMIF_
DATA[10]
ETM
DATA[27] /
EMIF_
DATA[11]
ETM
DATA[28] /
EMIF_
DATA[12]
NC
NC
MIBSPI3
NCS[1]
N2HET1
[02]
5
4
N2HET1
[16]
N2HET1
[12]
EMIF_
ADDR[6]
EMIF_
ADDR[0]
NC
NC
NC
N2HET1
[21]
N2HET1
[23]
NC
NC
NC
NC
NC
EMIF_
nCAS
NC
NC
NC
NC
4
3
N2HET1
[29]
N2HET1
[22]
MIBSPI3
NCS[3]
SPI2
NENA
N2HET1
[11]
MIBSPI1
NCS[1]
MIBSPI1
NCS[2]
GIOA[6]
MIBSPI1
NCS[3]
EMIF_
CLK
EMIF_
CKE
N2HET1
[25]
SPI2
NCS[0]
EMIF_
nWAIT
EMIF_
nRAS
NC
NC
NC
N2HET1
[06]
3
2
VSS
MIBSPI3
NCS[2]
GIOA[1]
SPI2
SOMI
SPI2 CLK
GIOB[2]
GIOB[5]
CAN2TX
GIOB[6]
GIOB[1]
KELVIN_
GND
GIOB[0]
N2HET1
[13]
N2HET1
[20]
MIBSPI1
NCS[0]
NC
TEST
N2HET1
[01]
VSS
2
1
VSS
VSS
GIOA[2]
SPI2
SIMO
GIOA[3]
GIOB[7]
GIOB[4]
CAN2RX
N2HET1
[18]
OSCIN
OSCOUT
GIOA[7]
N2HET1
[15]
N2HET1
[24]
NC
N2HET1
[07]
N2HET1
[03]
VSS
VSS
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
W
TMS570LS3137
www.ti.com SPNS162C –APRIL 2012–REVISED APRIL 2015
4.2 ZWT BGA Package Ball-Map (337-Ball Grid Array)
A. Balls can have multiplexed functions. Only the default function, except for the EMIF signals that are multiplexed with
ETM signals, is depicted in the figure.
Figure 4-2. ZWT Package Pinout. Top View(A)
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4.3 Terminal Functions
Section 4.3.1 and Section 4.3.2 identify the external signal names, the associated pin or ball numbers
along with the mechanical package designator, the pin or ball type (Input, Output, I/O, Power, or Ground),
whether the pin or ball has any internal pullup or pulldown, whether the pin or ball can be configured as a
GPIO, and a functional pin or ball description. The first signal name listed is the primary function for that
terminal. The signal name in bold is the function being described. For information on how to select
between different multiplexed functions, see the TMS570LS31x/21x 16/32-Bit RISC Flash Microcontroller
Technical Reference Manual (SPNU499) .
NOTE
In the Terminal Functions table below, the "Reset Pull State" is the state of the pull applied to
the terminal while nPORRST is low and immediately after nPORRST goes High. The default
pull direction may change when software configures the pin for an alternate function. The
"Pull Type" is the type of pull asserted when the signal name in bold is enabled for the given
terminal by the IOMM control registers.
All I/O signals except nRST are configured as inputs while nPORRST is low and
immediately after nPORRST goes High. While nPORRST is low, the input buffers
are disabled, and the output buffers are disabled with the default pulls enabled.
All output-only signals have the output buffer disabled and the default pull enabled
while nPORRST is low, and are configured as outputs with the pulls disabled
immediately after nPORRST goes High.
4.3.1 PGE Package
4.3.1.1 Multibuffered Analog-to-Digital Converters (MibADCs)
Table 4-1. PGE Multibuffered Analog-to-Digital Converters (MibADC1, MibADC2)
TERMINAL RESET
SIGNAL PULL PULL TYPE DESCRIPTION
144 TYPE
SIGNAL NAME STATE
PGE
ADREFHI(1) 66 Input ADC high reference supply
ADREFLO(1) 67 Input ADC low reference supply
N/A None
VCCAD(1) 69 Power Operating supply for ADC
VSSAD(1) 68 Ground
AD1EVT/MII_RX_ER/RMII_RX_ER 86 I/O Pulldown Programmable, 20 µA ADC1 event trigger input, or GPIO
MIBSPI3NCS[0]/AD2EVT/GIOB[2]/N2HET2_PIN_nDIS 55 I/O Pullup Programmable, 20 µA ADC2 event trigger input, or GPIO
AD1IN[0] 60
AD1IN[1] 71
AD1IN[2] 73
AD1IN[3] 74 Input N/A None ADC1 analog input
AD1IN[4] 76
AD1IN[5] 78
AD1IN[6] 80
AD1IN[7] 61
(1) The ADREFHI, ADREFLO, VCCAD and VSSAD connections are common for both ADC cores.
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Table 4-1. PGE Multibuffered Analog-to-Digital Converters (MibADC1, MibADC2) (continued)
TERMINAL RESET
SIGNAL PULL PULL TYPE DESCRIPTION
144 TYPE
SIGNAL NAME STATE
PGE
AD1IN[8] / AD2IN[8] 83
AD1IN[9] / AD2IN[9] 70
AD1IN[10] / AD2IN[10] 72
AD1IN[11] / AD2IN[11] 75
AD1IN[12] / AD2IN[12] 77
AD1IN[13] / AD2IN[13] 79
AD1IN[14] / AD2IN[14] 82
AD1IN[15] / AD2IN[15] 85 Input N/A None ADC1/ADC2 shared analog inputs
AD1IN[16] / AD2IN[0] 58
AD1IN[17] / AD2IN[1] 59
AD1IN[18] / AD2IN[2] 62
AD1IN[19] / AD2IN[3] 63
AD1IN[20] / AD2IN[4] 64
AD1IN[21] / AD2IN[5] 65
AD1IN[22] / AD2IN[6] 81
AD1IN[23] / AD2IN[7] 84
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4.3.1.2 Enhanced High-End Timer (N2HET) Modules
Table 4-2. PGE Enhanced High-End Timer Modules (N2HET1, N2HET2)
TERMINAL SIGNAL RESET PULL PULL TYPE DESCRIPTION
144 TYPE STATE
SIGNAL NAME PGE
N2HET1[0]/SPI4CLK 25
N2HET1[1]/SPI4NENA/N2HET2[8] 23
N2HET1[2]/SPI4SIMO[0] 30
N2HET1[3]/SPI4NCS[0]/N2HET2[10] 24
N2HET1[4] 36
N2HET1[5]/SPI4SOMI[0]/N2HET2[12] 31
N2HET1[6]/SCIRX 38
N2HET1[7]/N2HET2[14] 33 Programmable,
N2HET1[8]/MIBSPI1SIMO[1]/MII_TXD[3] 106 I/O Pulldown 20 µA
N2HET1[9]/N2HET2[16] 35
N2HET1[10]/MII_TX_CLK/MII_TX_AVCLK4 118
N2HET1[11]/MIBSPI3NCS[4]/N2HET2[18] 6
N2HET1[12]/MII_CRS/RMII_CRS_DV 124
N2HET1[13]/SCITX 39
N2HET1[14] 125
N2HET1[15]/MIBSPI1NCS[4] 41
N2HET1[16] 139
Programmable,
MIBSPI1NCS[1]/N2HET1[17]/MII_COL 130 I/O Pullup 20 µA N2HET1 timer input capture
Programmable, or output compare, or GIO.
N2HET1[18] 140 I/O Pulldown 20 µA Each terminal has a
Programmable, suppression filter with a
MIBSPI1NCS[2]/N2HET1[19]/MDIO 40 I/O Pullup 20 µA programmable duration.
Programmable,
N2HET1[20] 141 I/O Pulldown 20 µA
Programmable,
N2HET1[22] 15 I/O Pulldown 20 µA
Programmable,
MIBSPI1NENA/N2HET1[23]/MII_RXD[2] 96 I/O Pullup 20 µA
Programmable,
N2HET1[24]/MIBSPI1NCS[5]/MII_RXD[0]/RMII_RXD[0] 91 I/O Pulldown 20 µA
Programmable,
MIBSPI3NCS[1]/N2HET1[25]/MDCLK 37 I/O Pullup 20 µA
Programmable,
N2HET1[26]/MII_RXD[1]/RMII_RXD[1] 92 I/O Pulldown 20 µA
Programmable,
MIBSPI3NCS[2]/I2C_SDA/N2HET1[27] 4 I/O Pullup 20 µA
Programmable,
N2HET1[28]/MII_RX_CLK/RMII_REFCLK/MII_RX_AVCLK4 107 I/O Pulldown 20 µA
Programmable,
MIBSPI3NCS[3]/I2C_SCL/N2HET1[29] 3 I/O Pullup 20 µA
Programmable,
N2HET1[30]/MII_RX_DV 127 I/O Pulldown 20 µA
Programmable,
MIBSPI3NENA/MIBSPI3NCS[5]/N2HET1[31] 54 I/O Pullup 20 µA
Programmable, Disable selected PWM
GIOA[5]/EXTCLKIN/N2HET1_PIN_nDIS 14 I/O Pulldown 20 µA outputs
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Table 4-2. PGE Enhanced High-End Timer Modules (N2HET1, N2HET2) (continued)
TERMINAL SIGNAL RESET PULL PULL TYPE DESCRIPTION
144 TYPE STATE
SIGNAL NAME PGE
GIOA[2]/N2HET2[0] 9
GIOA[6]/N2HET2[4] 16
GIOA[7]/N2HET2[6] 22 N2HET2 time input capture
N2HET1[1]/SPI4NENA/N2HET2[8] 23 or output compare, or GPIO
Programmable,
N2HET1[3]/SPI4NCS[0]/N2HET2[10] 24 I/O Pulldown Each terminal has a
20 µA suppression filter with a
N2HET1[5]/SPI4SOMI[0]/N2HET2[12] 31 programmable duration.
N2HET1[7]/N2HET2[14] 33
N2HET1[9]/N2HET2[16] 35
N2HET1[11]/MIBSPI3NCS[4]/N2HET2[18] 6
Programmable, Disable selected PWM
MIBSPI3NCS[0]/AD2EVT/GIOB[2]/N2HET2_PIN_nDIS 55 I/O Pullup 20 µA outputs
4.3.1.3 General-Purpose Input/Output (GPIO)
Table 4-3. PGE General-Purpose Input/Output (GPIO)
TERMINAL RESET
SIGNAL PULL PULL TYPE DESCRIPTION
144 TYPE
SIGNAL NAME STATE
PGE
GIOA[2]/N2HET2[0] 9 General-purpose I/O.
GIOA[5]/EXTCLKIN/N2HET1_PIN_nDIS 14 All GPIO terminals are
Programmable,
I/O Pulldown capable of generating
20 µA
GIOA[6]/N2HET2[4] 16 interrupts to the CPU on rising
GIOA[7]/N2HET2[6] 22 / falling / both edges.
The application cannot output
a level onto this terminal
when it is configured as
Programmable, GIOB[2]. A pull-up is enabled
MIBSPI3NCS[0]/AD2EVT/GIOB[2]/N2HET2_PIN_nDIS 55 I/O Pullup 20 µA on this input. This pull cannot
be disabled, and is not
programmable using the GIO
module pull control registers.
4.3.1.4 FlexRay Interface Controller (FlexRay)
Table 4-4. FlexRay Interface Controller (FlexRay)
TERMINAL RESET
SIGNAL PULL PULL TYPE DESCRIPTION
144 TYPE
SIGNAL NAME STATE
PGE
Fixed 100 µA
FRAYRX1 126 Input Pullup FlexRay data receive (channel 1)
Pullup
FRAYTX1 133 Output FlexRay data transmit (channel 1)
N/A None
FRAYTXEN1 142 Output FlexRay transmit enable (channel 1)
Fixed 100 µA
FRAYRX2 2 Input Pullup FlexRay data receive (channel 2)
Pullup
FRAYTX2 1 Output FlexRay data transmit (channel 2)
N/A None
FRAYTXEN2 5 Output FlexRay transmit enable (channel 2)
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4.3.1.5 Controller Area Network Controllers (DCANs)
Table 4-5. PGE Controller Area Network Controllers (DCAN)
TERMINAL RESET
SIGNAL PULL PULL TYPE DESCRIPTION
144 TYPE
SIGNAL NAME STATE
PGE
CAN1RX 90 CAN1 receive, or GPIO
CAN1TX 89 CAN1 transmit, or GPIO
CAN2RX 129 CAN2 receive, or GPIO
Programmable,
I/O Pullup 20 µA
CAN2TX 128 CAN2 transmit, or GPIO
CAN3RX 12 CAN3 receive, or GPIO
CAN3TX 13 CAN3 transmit, or GPIO
4.3.1.6 Local Interconnect Network Interface Module (LIN)
Table 4-6. PGE Local Interconnect Network Interface Module (LIN)
TERMINAL RESET
SIGNAL PULL PULL TYPE DESCRIPTION
144 TYPE
SIGNAL NAME STATE
PGE
LINRX 131 LIN receive, or GPIO
Programmable,
I/O Pullup 20 µA
LINTX 132 LIN transmit, or GPIO
4.3.1.7 Standard Serial Communication Interface (SCI)
Table 4-7. PGE Standard Serial Communication Interface (SCI)
TERMINAL RESET
SIGNAL PULL PULL TYPE DESCRIPTION
144 TYPE
SIGNAL NAME STATE
PGE
N2HET1[6]/SCIRX 38 SCI receive, or GPIO
Programmable,
I/O Pulldown 20 µA
N2HET1[13]/SCITX 39 SCI transmit, or GPIO
4.3.1.8 Inter-Integrated Circuit Interface Module (I2C)
Table 4-8. PGE Inter-Integrated Circuit Interface Module (I2C)
TERMINAL RESET
SIGNAL PULL PULL TYPE DESCRIPTION
144 TYPE
SIGNAL NAME STATE
PGE
MIBSPI3NCS[2]/I2C_SDA/N2HET1[27] 4 I2C serial data, or GPIO
Programmable,
I/O Pullup 20 µA
MIBSPI3NCS[3]/I2C_SCL/N2HET1[29] 3 I2C serial clock, or GPIO
4.3.1.9 Standard Serial Peripheral Interface (SPI)
Table 4-9. PGE Standard Serial Peripheral Interface (SPI)
TERMINAL RESET
SIGNAL PULL PULL TYPE DESCRIPTION
144 TYPE
SIGNAL NAME STATE
PGE
N2HET1[0]/SPI4CLK 25 SPI4 clock, or GPIO
N2HET1[3]/SPI4NCS[0]/N2HET2[10] 24 SPI4 chip select, or GPIO
N2HET1[1]/SPI4NENA/N2HET2[8] 23 SPI4 enable, or GPIO
Programmable,
I/O Pulldown 20 µA SPI4 slave-input master-
N2HET1[2]/SPI4SIMO[0] 30 output, or GPIO
SPI4 slave-output master-
N2HET1[5]/SPI4SOMI[0]/N2HET2[12] 31 input, or GPIO
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4.3.1.10 Multibuffered Serial Peripheral Interface Modules (MibSPI)
Table 4-10. PGE Multibuffered Serial Peripheral Interface Modules (MibSPI)
TERMINAL RESET
SIGNAL PULL PULL TYPE DESCRIPTION
144 TYPE
SIGNAL NAME STATE
PGE
MIBSPI1CLK 95 MibSPI1 clock, or GPIO
MIBSPI1NCS[0]/MIBSPI1SOMI[1]/MII_TXD[2] 105 Programmable,
Pullup 20 µA
MIBSPI1NCS[1]/N2HET1[17]/MII_COL 130 MibSPI1 chip select, or GPIO
MIBSPI1NCS[2]/N2HET1[19]/MDIO 40
N2HET1[15]/MIBSPI1NCS[4] 41 Programmable,
Pulldown MibSPI1 chip select, or GPIO
20 µA
N2HET1[24]/MIBSPI1NCS[5]/MII_RXD[0]/RMII_RXD[0] 91 I/O
MIBSPI1NENA/N2HET1[23]/MII_RXD[2] 96 MibSPI1 enable, or GPIO
Programmable,
Pullup 20 µA
MIBSPI1SIMO[0] 93 MibSPI1 slave-in master-out, or GPIO
Programmable,
N2HET1[8]/MIBSPI1SIMO[1]/MII_TXD[3] 106 Pulldown MibSPI1 slave-in master-out, or GPIO
20 µA
MIBSPI1SOMI[0] 94 Programmable,
Pullup MibSPI1 slave-out master-in, or GPIO
20 µA
MIBSPI1NCS[0]/MIBSPI1SOMI[1]/MII_TXD[2] 105
MIBSPI3CLK 53 MibSPI3 clock, or GPIO
MIBSPI3NCS[0]/AD2EVT/GIOB[2]/N2HET2_PIN_nDIS 55 Programmable,
MIBSPI3NCS[1]/N2HET1[25]/MDCLK 37 Pullup 20 µA MibSPI3 chip select, or GPIO
MIBSPI3NCS[2]/I2C_SDA/N2HET1[27] 4
MIBSPI3NCS[3]/I2C_SCL/N2HET1[29] 3 I/O Programmable,
N2HET1[11]/MIBSPI3NCS[4]/N2HET2[18] 6 Pulldown MibSPI3 chip select, or GPIO
20 µA
MIBSPI3NENA /MIBSPI3NCS[5]/N2HET1[31] 54 MibSPI3 chip select, or GPIO
MIBSPI3NENA/MIBSPI3NCS[5]/N2HET1[31] 54 MibSPI3 enable, or GPIO
Programmable,
Pullup 20 µA
MIBSPI3SIMO[0] 52 MibSPI3 slave-in master-out, or GPIO
MIBSPI3SOMI[0] 51 MibSPI3 slave-out master-in, or GPIO
MIBSPI5CLK/MII_TXEN/RMII_TXEN 100 MibSPI5 clock, or GPIO
MIBSPI5NCS[0] 32 MibSPI5 chip select, or GPIO
Programmable,
MIBSPI5NENA/MII_RXD[3] 97 I/O Pullup MibSPI5 enable, or GPIO
20 µA
MIBSPI5SIMO[0]/MII_TXD[1]/RMII_TXD[1] 99 MibSPI5 slave-in master-out, or GPIO
MIBSPI5SOMI[0]/MII_TXD[0]/RMII_TXD[0] 98 MibSPI5 slave-out master-in, or GPIO
4.3.1.11 Ethernet Controller
Table 4-11. PGE Ethernet Controller: MDIO Interface
TERMINAL RESET
SIGNAL PULL PULL TYPE DESCRIPTION
144 TYPE
SIGNAL NAME STATE
PGE
Programmable,
MIBSPI3NCS[1]/N2HET1[25]/MDCLK 37 Output Pullup Serial clock output
20 µA
Fixed 20 µA
MIBSPI1NCS[2]/N2HET1[19]/MDIO 40 I/O Pullup Serial data input/output
Pullup
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Table 4-12. PGE Ethernet Controller: Reduced Media Independent Interface (RMII)
TERMINAL RESET
SIGNAL PULL PULL TYPE DESCRIPTION
144 TYPE
SIGNAL NAME STATE
PGE
RMII carrier sense and data
N2HET1[12]/MII_CRS/RMII_CRS_DV 124 valid
RMII synchronous reference
N2HET1[28]/MII_RX_CLK/RMII_REFCLK/MII_RX_AVCLK4 107 clock for receive, transmit and
Fixed 20 µA control interface
Input Pulldown Pulldown
AD1EVT/MII_RX_ER/RMII_RX_ER 86 RMII receive error
N2HET1[24]/MIBSPI1NCS[5]/MII_RXD[0]/RMII_RXD[0] 91 RMII receive data
N2HET1[26]/MII_RXD[1]/RMII_RXD[1] 92
MIBSPI5SOMI[0]/MII_TXD[0]/RMII_TXD[0] 98 RMII transmit data
MIBSPI5SIMO[0]/MII_TXD[1]/RMII_TXD[1] 99 Output Pullup None
MIBSPI5CLK/MII_TXEN/RMII_TXEN 100 RMII transmit enable
Table 4-13. PGE Ethernet Controller: Media Independent Interface (MII)
TERMINAL RESET
SIGNAL PULL PULL TYPE DESCRIPTION
144 TYPE
SIGNAL NAME STATE
PGE
MIBSPI1NCS[1]/N2HET1[17]/MII_COL 130 Pullup None Collision detect
Input Fixed 20 µA Carrier sense and receive
N2HET1[12]/MII_CRS/RMII_CRS_DV 124 Pulldown Pulldown valid
N2HET1[28]/MII_RX_CLK/RMII_REFCLK/MII_RX_AVCLK4 107 I/O Pulldown None MII output receive clock
N2HET1[30]/MII_RX_DV 127 Received data valid
Input
AD1EVT/MII_RX_ER/RMII_RX_ER 86 Receive error
Fixed 20 µA
N2HET1[28]/MII_RX_CLK/RMII_REFCLK/MII_RX_AVCLK4 107 I/O Pulldown Receive clock
Pulldown
N2HET1[24]/MIBSPI1NCS[5]/MII_RXD[0]/RMII_RXD[0] 91
N2HET1[26]/MII_RXD[1]/RMII_RXD[1] 92 Input Receive data
MIBSPI1NENA/N2HET1[23]/MII_RXD[2] 96 Fixed 20 µA
Pullup Pulldown
MIBSPI5NENA/MII_RXD[3] 97
N2HET1[10]/MII_TX_CLK/MII_TX_AVCLK4 118 MII output transmit clock
I/O Pulldown None
N2HET1[10]/MII_TX_CLK/MII_TX_AVCLK4 118 Transmit clock
MIBSPI5SOMI[0]/MII_TXD[0]/RMII_TXD[0] 98
MIBSPI5SIMO[0]/MII_TXD[1]/RMII_TXD[1] 99 Pullup None Transmit data
MIBSPI1NCS[0]/MIBSPI1SOMI[1]/MII_TXD[2] 105 Output
N2HET1[8]/MIBSPI1SIMO[1]/MII_TXD[3] 106 Pulldown None
MIBSPI5CLK/MII_TXEN/RMII_TXEN 100 Pullup None Transmit enable
4.3.1.12 System Module Interface
Table 4-14. PGE System Module Interface
TERMINAL RESET
SIGNAL PULL PULL TYPE DESCRIPTION
144 TYPE
SIGNAL NAME STATE
PGE
Power-on reset, cold reset
External power supply monitor
circuitry must drive nPORRST
Fixed 100 µA low when any of the supplies
nPORRST 46 Input Pulldown Pulldown to the microcontroller fall out
of the specified range. This
terminal has a glitch filter.
See Section 6.8.
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Table 4-14. PGE System Module Interface (continued)
TERMINAL RESET
SIGNAL PULL PULL TYPE DESCRIPTION
144 TYPE
SIGNAL NAME STATE
PGE
System reset, warm reset,
bidirectional.
The internal circuitry indicates
any reset condition by driving
nRST low.
The external circuitry can
assert a system reset by
Fixed 100 µA
nRST 116 I/O Pullup driving nRST low. To ensure
Pullup that an external reset is not
arbitrarily generated, TI
recommends that an external
pullup resistor is connected to
this terminal.
This terminal has a glitch
filter. See Section 6.8.
ESM Error Signal
Fixed 20 µA
nERROR 117 I/O Pulldown Indicates error of high
Pulldown severity. See Section 6.18.
4.3.1.13 Clock Inputs and Outputs
Table 4-15. PGE Clock Inputs and Outputs
TERMINAL RESET
SIGNAL PULL PULL TYPE DESCRIPTION
144 TYPE
SIGNAL NAME STATE
PGE
From external
OSCIN 18 Input crystal/resonator, or external
clock input
N/A None
KELVIN_GND 19 Input Kelvin ground for oscillator
OSCOUT 20 Output To external crystal/resonator
Programmable, 20 External prescaled clock
ECLK 119 I/O Pulldown µA output, or GIO.
GIOA[5]/EXTCLKIN/N2HET1_PIN_nDIS 14 Input Pulldown 20 µA External clock input #1
4.3.1.14 Test and Debug Modules Interface
Table 4-16. PGE Test and Debug Modules Interface
TERMINAL RESET
SIGNAL PULL PULL TYPE DESCRIPTION
SIGNAL NAME 144 TYPE STATE
PGE
Test enable. This terminal
must be connected to ground
TEST 34 I/O Fixed 100 µA directly or via a pulldown
Pulldown Pulldown resistor.
nTRST 109 Input JTAG test hardware reset
RTCK 113 Output N/A None JTAG return test clock
Fixed 100 µA
TCK 112 Input Pulldown JTAG test clock
Pulldown
Fixed 100 µA
TDI 110 I/O Pullup JTAG test data in
Pullup
100 µA
TDO 111 Output None JTAG test data out
Pulldown
Fixed 100 µA
TMS 108 I/O Pullup JTAG test select
Pullup
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4.3.1.15 Flash Supply and Test Pads
Table 4-17. PGE Flash Supply and Test Pads
TERMINAL RESET
SIGNAL PULL PULL TYPE DESCRIPTION
144 TYPE
SIGNAL NAME STATE
PGE
3.3-V
VCCP 134 N/A None Flash pump supply
Power
FLTP1 7 Flash test pads. These
terminals are reserved for TI
use only. For proper operation
N/A None these terminals must connect
FLTP2 8only to a test pad or not be
connected at all [no connect
(NC)].
4.3.1.16 Supply for Core Logic: 1.2-V Nominal
Table 4-18. PGE Supply for Core Logic: 1.2-V Nominal
TERMINAL RESET
SIGNAL PULL PULL TYPE DESCRIPTION
144 TYPE
SIGNAL NAME STATE
PGE
VCC 17
VCC 29
VCC 45
VCC 48
VCC 49
VCC 57 1.2-V N/A None 1.2-V Core supply
Power
VCC 87
VCC 101
VCC 114
VCC 123
VCC 137
VCC 143
4.3.1.17 Supply for I/O Cells: 3.3-V Nominal
Table 4-19. PGE Supply for I/O Cells: 3.3-V Nominal
TERMINAL RESET
SIGNAL PULL PULL TYPE DESCRIPTION
SIGNAL NAME 144 TYPE STATE
PGE
VCCIO 10
VCCIO 26
VCCIO 42 3.3-V 3.3-V Operating supply for
N/A None
Power I/Os
VCCIO 104
VCCIO 120
VCCIO 136
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