Texas Instruments SimpleLink CC2620 Product manual

CC13xx, CC26xx SimpleLink™ Wireless MCU
Technical Reference Manual
Literature Number: SWCU117C
February 2015–Revised September 2015

Contents
Revision History: SWCU117C ....................................................................................................... 10
Revision History: SWCU117B ....................................................................................................... 10
Revision History: SWCU117A ....................................................................................................... 11
Preface....................................................................................................................................... 12
1 Architectural Overview........................................................................................................ 14
1.1 Target Applications......................................................................................................... 15
1.2 Overview..................................................................................................................... 15
1.3 Functional Overview ....................................................................................................... 17
1.3.1 ARM Cortex-M3 ................................................................................................... 17
1.3.2 On-chip Memory................................................................................................... 18
1.3.3 Radio................................................................................................................ 19
1.3.4 Advanced Encryption Standard (AES) Engine With 128-bit Key Support ................................. 19
1.3.5 General-Purpose Timers ......................................................................................... 20
1.3.6 Direct Memory Access............................................................................................ 20
1.3.7 System Control and Clock ....................................................................................... 21
1.3.8 Serial Communication Peripherals.............................................................................. 21
1.3.9 Programmable I/Os ............................................................................................... 24
1.3.10 Sensor Controller ................................................................................................ 24
1.3.11 Random Number Generator .................................................................................... 25
1.3.12 cJTAG and JTAG ................................................................................................ 25
1.3.13 Power Supply System ........................................................................................... 26
2 The Cortex-M3 Processor.................................................................................................... 28
2.1 The Cortex-M3 Processor Introduction.................................................................................. 29
2.2 Block Diagram .............................................................................................................. 29
2.3 Overview..................................................................................................................... 30
2.3.1 System-level Interface............................................................................................ 30
2.3.2 Integrated Configurable Debug.................................................................................. 30
2.3.3 Trace Port Interface Unit ......................................................................................... 31
2.3.4 Cortex-M3 System Component Details......................................................................... 31
2.4 Programming Model ....................................................................................................... 31
2.4.1 Processor Mode and Privilege Levels for Software Execution.............................................. 32
2.4.2 Stacks............................................................................................................... 32
2.4.3 Exceptions and Interrupts........................................................................................ 32
2.4.4 Data Types......................................................................................................... 32
2.5 Cortex-M3 Core Registers ................................................................................................ 33
2.5.1 Core Register Map................................................................................................ 34
2.5.2 Core Register Descriptions ...................................................................................... 34
2.6 Instruction Set Summary .................................................................................................. 47
2.7 Cortex-M3 Processor Registers.......................................................................................... 51
2.7.1 CPU_DWT Registers ............................................................................................. 51
2.7.2 CPU_FPB Registers .............................................................................................. 77
2.7.3 CPU_ITM Registers............................................................................................... 88
2.7.4 CPU_SCS Registers ............................................................................................ 128
2.7.5 CPU_TPIU Registers............................................................................................ 207
2Contents SWCU117C–February 2015–Revised September 2015
Submit Documentation Feedback
Copyright © 2015, Texas Instruments Incorporated

www.ti.com
3 Cortex-M3 Peripherals....................................................................................................... 220
3.1 Cortex-M3 Peripherals Introduction .................................................................................... 221
3.2 Functional Description.................................................................................................... 221
3.2.1 SysTick............................................................................................................ 222
3.2.2 NVIC............................................................................................................... 222
3.2.3 SCB................................................................................................................ 223
3.2.4 ITM................................................................................................................. 224
3.2.5 FPB................................................................................................................ 224
3.2.6 TPIU ............................................................................................................... 224
3.2.7 DWT ............................................................................................................... 225
3.2.8 Cortex-M3 Memory .............................................................................................. 226
4 Interrupts and Events........................................................................................................ 228
4.1 Exception Model .......................................................................................................... 229
4.1.1 Exception States................................................................................................. 229
4.1.2 Exception Types ................................................................................................. 229
4.1.3 Exception Handlers.............................................................................................. 232
4.1.4 Vector Table...................................................................................................... 232
4.1.5 Exception Priorities .............................................................................................. 233
4.1.6 Interrupt Priority Grouping ...................................................................................... 233
4.1.7 Exception Entry and Return .................................................................................... 234
4.2 Fault Handling............................................................................................................. 236
4.2.1 Fault Types ....................................................................................................... 236
4.2.2 Fault Escalation and Hard Faults.............................................................................. 237
4.2.3 Fault Status Registers and Fault Address Registers........................................................ 237
4.2.4 Lockup............................................................................................................. 237
4.3 Event Fabric............................................................................................................... 238
4.3.1 Introduction ....................................................................................................... 238
4.3.2 Event Fabric Overview.......................................................................................... 239
4.4 AON Event Fabric ........................................................................................................ 239
4.4.1 Common Input Event List....................................................................................... 240
4.4.2 Event Subscribers ............................................................................................... 240
4.5 MCU Event Fabric ........................................................................................................ 241
4.5.1 Common Input Event List....................................................................................... 241
4.5.2 Event Subscribers ............................................................................................... 245
4.6 Memory Map .............................................................................................................. 246
4.7 Interrupts and Events Registers ........................................................................................ 247
4.7.1 AON_EVENT Registers......................................................................................... 247
4.7.2 EVENT Registers................................................................................................ 271
5 JTAG Interface ................................................................................................................. 390
5.1 Top Level Debug System................................................................................................ 391
5.2 cJTAG...................................................................................................................... 394
5.2.1 JTAG Commands................................................................................................ 396
5.2.2 Programming Sequences....................................................................................... 398
5.3 ICEPick..................................................................................................................... 399
5.3.1 Secondary TAPs................................................................................................. 399
5.3.2 ICEPick Registers ............................................................................................... 401
5.3.3 ROUTER Scan Chain........................................................................................... 404
5.3.4 TAP Routing Registers ......................................................................................... 405
5.4 ICEMelter .................................................................................................................. 409
5.5 Serial Wire Viewer (SWV) ............................................................................................... 409
5.6 Halt In Boot (HIB)......................................................................................................... 410
5.7 Debug and Shutdown .................................................................................................... 410
5.8 Debug Features Supported Through WUC TAP ..................................................................... 411
3
SWCU117C–February 2015–Revised September 2015 Contents
Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated

www.ti.com
5.9 Profiler Register........................................................................................................... 412
6 Power, Reset, and Clock Management................................................................................. 413
6.1 Introduction ................................................................................................................ 414
6.1.1 System CPU Mode .............................................................................................. 415
6.1.2 Supply System ................................................................................................... 416
6.1.3 Digital Power Partitioning....................................................................................... 418
6.1.4 Clock Management.............................................................................................. 419
6.1.5 Power Modes..................................................................................................... 425
6.1.6 Reset .............................................................................................................. 429
6.2 PRCM Registers .......................................................................................................... 432
6.2.1 DDI_0_OSC Registers.......................................................................................... 432
6.2.2 AON_SYSCTL Registers ....................................................................................... 452
6.2.3 AON_WUC Registers ........................................................................................... 458
6.2.4 PRCM Registers ................................................................................................. 474
7 Versatile Instruction Memory System (VIMS)........................................................................ 533
7.1 VIMS Configurations ..................................................................................................... 535
7.1.1 VIMS Modes...................................................................................................... 535
7.1.2 VIMS Flash Line Buffering...................................................................................... 538
7.1.3 VIMS Arbitration.................................................................................................. 538
7.1.4 VIMS Cache TAG Prefetch..................................................................................... 538
7.2 VIMS Software Remarks................................................................................................. 539
7.2.1 Flash Program or Update....................................................................................... 539
7.2.2 VIMS Retention .................................................................................................. 539
7.3 ROM........................................................................................................................ 540
7.4 FLASH...................................................................................................................... 540
7.4.1 FLASH Memory Protection..................................................................................... 540
7.4.2 Memory Programming .......................................................................................... 541
7.4.3 FLASH Memory Programming................................................................................. 541
7.5 Power Management Requirements .................................................................................... 541
7.6 ROM Functions ........................................................................................................... 543
7.7 SRAM ...................................................................................................................... 544
7.8 VIMS Registers ........................................................................................................... 545
7.8.1 FLASH Registers ................................................................................................ 545
7.8.2 VIMS Registers .................................................................................................. 671
8 Bootloader....................................................................................................................... 674
8.1 Bootloader Functionality ................................................................................................. 675
8.1.1 Bootloader Disabling ............................................................................................ 675
8.1.2 Bootloader Backdoor............................................................................................ 675
8.2 Bootloader Interfaces..................................................................................................... 675
8.2.1 Packet Handling.................................................................................................. 676
8.2.2 Transport Layer .................................................................................................. 677
8.2.3 Serial Bus Commands .......................................................................................... 679
9 Device Configuration......................................................................................................... 688
9.1 Customer Configuration (CCFG) ....................................................................................... 689
9.1.1 CCFG Registers ................................................................................................. 690
9.2 Factory Configuration (FCFG) .......................................................................................... 718
9.2.1 FCFG1 Registers ................................................................................................ 719
10 Cryptography ................................................................................................................... 801
10.1 AES Cryptoprocessor Overview ........................................................................................ 802
10.1.1 Functional Description ......................................................................................... 802
10.1.2 Power Management and Sleep Modes ...................................................................... 803
10.1.3 Hardware Description .......................................................................................... 803
4Contents SWCU117C–February 2015–Revised September 2015
Submit Documentation Feedback
Copyright © 2015, Texas Instruments Incorporated

www.ti.com
10.1.4 Module Description............................................................................................. 804
10.1.5 Performance..................................................................................................... 815
10.1.6 Programming Guidelines ...................................................................................... 816
10.1.7 Conventions and Compliances ............................................................................... 827
10.2 Cryptography Registers.................................................................................................. 829
10.2.1 CRYPTO Registers............................................................................................. 829
11 I/O Control ....................................................................................................................... 873
11.1 Introduction ................................................................................................................ 874
11.2 IOC Overview ............................................................................................................. 874
11.3 I/O Mapping and Configuration ......................................................................................... 875
11.3.1 Basic I/O Mapping.............................................................................................. 875
11.3.2 MAP AUXIO From the Sensor Controller to DIO Pin ...................................................... 875
11.3.3 Map 32-kHz System Clock (LF Clock) to DIO/PIN......................................................... 876
11.4 Edge Detection on Pin (DIO)............................................................................................ 876
11.4.1 Configure DIO as GPIO Input to Generate Interrupt on EDGE DETECT............................... 876
11.5 AON IOC State Latching When Powering Off the MCU Domain .................................................. 876
11.6 Unused I/O Pins........................................................................................................... 877
11.7 GPIO........................................................................................................................ 877
11.8 I/O Pin Mapping........................................................................................................... 878
11.9 Peripheral PORTIDs...................................................................................................... 879
11.10 I/O Pin...................................................................................................................... 879
11.10.1 Physical Pin.................................................................................................... 879
11.10.2 Pin Configuration.............................................................................................. 880
11.11 I/O Control Registers..................................................................................................... 881
11.11.1 AON_IOC Registers .......................................................................................... 881
11.11.2 GPIO Registers................................................................................................ 887
11.11.3 IOC Registers.................................................................................................. 910
12 Micro Direct Memory Access (µDMA) ................................................................................ 1039
12.1 μDMA Introduction ...................................................................................................... 1040
12.2 Block Diagram ........................................................................................................... 1041
12.3 Functional Description.................................................................................................. 1041
12.3.1 Channel Assignments ........................................................................................ 1042
12.3.2 Priority .......................................................................................................... 1043
12.3.3 Arbitration Size ................................................................................................ 1043
12.3.4 Request Types ................................................................................................ 1043
12.3.5 Channel Configuration........................................................................................ 1044
12.3.6 Transfer Modes................................................................................................ 1046
12.3.7 Transfer Size and Increments ............................................................................... 1053
12.3.8 Peripheral Interface........................................................................................... 1053
12.3.9 Software Request ............................................................................................. 1053
12.3.10 Interrupts and Errors ........................................................................................ 1054
12.4 Initialization and Configuration......................................................................................... 1054
12.4.1 Module Initialization........................................................................................... 1054
12.4.2 Configuring a Memory-to-Memory Transfer ............................................................... 1055
12.5 µDMA Registers......................................................................................................... 1056
12.5.1 UDMA Registers............................................................................................... 1056
13 Timers ........................................................................................................................... 1077
13.1 General-purpose Timers ............................................................................................... 1078
13.2 Block Diagram ........................................................................................................... 1079
13.3 Functional Description.................................................................................................. 1079
13.3.1 GPTM Reset Conditions ..................................................................................... 1080
13.3.2 Timer Modes................................................................................................... 1080
13.3.3 Wait-for-Trigger Mode ........................................................................................ 1087
5
SWCU117C–February 2015–Revised September 2015 Contents
Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated

www.ti.com
13.3.4 Synchronizing GPT Blocks................................................................................... 1088
13.3.5 Accessing Concatenated 16- and 32-Bit GPTM Register Values ...................................... 1088
13.4 Initialization and Configuration......................................................................................... 1089
13.4.1 One-shot and Periodic Timer Modes ....................................................................... 1089
13.4.2 Input Edge-count Mode....................................................................................... 1090
13.4.3 Input Edge-timing Mode...................................................................................... 1090
13.4.4 PWM Mode..................................................................................................... 1091
13.4.5 Producing DMA Trigger Events ............................................................................. 1091
13.5 General-purpose Timer Registers..................................................................................... 1092
13.5.1 GPT Registers................................................................................................. 1092
14 Real-Time Clock.............................................................................................................. 1127
14.1 Introduction............................................................................................................... 1128
14.2 Functional Specifications............................................................................................... 1128
14.2.1 Functional Overview .......................................................................................... 1128
14.2.2 Free-Running Counter........................................................................................ 1128
14.2.3 Channels ....................................................................................................... 1128
14.2.4 Events .......................................................................................................... 1129
14.3 RTC Registers........................................................................................................... 1129
14.3.1 Register Access ............................................................................................... 1129
14.3.2 Entering Sleep and Wake Up From Sleep ................................................................ 1130
14.3.3 AON_RTC:SYNC Register................................................................................... 1130
14.4 Real-Time Clock Registers............................................................................................. 1131
14.4.1 AON_RTC Registers.......................................................................................... 1131
15 Watchdog Timer.............................................................................................................. 1145
15.1 WDT Introduction........................................................................................................ 1146
15.2 WDT Functional Description........................................................................................... 1146
15.3 WDT Initialization and Configuration.................................................................................. 1147
15.4 Watchdog Timer Registers............................................................................................. 1148
15.4.1 WDT Registers ................................................................................................ 1148
16 Random Number Generator.............................................................................................. 1158
16.1 Overview.................................................................................................................. 1159
16.2 Block Diagram ........................................................................................................... 1159
16.3 TRNG Software Reset.................................................................................................. 1160
16.4 Interrupt Requests....................................................................................................... 1160
16.5 TRNG Operation Description .......................................................................................... 1161
16.5.1 TRNG Shutdown .............................................................................................. 1161
16.5.2 TRNG Alarms.................................................................................................. 1162
16.5.3 TRNG Entropy................................................................................................. 1162
16.6 TRNG Low-level Programing Guide .................................................................................. 1163
16.6.1 Initialization..................................................................................................... 1163
16.7 Random Number Generator Registers............................................................................... 1166
16.7.1 TRNG Registers............................................................................................... 1166
17 AUX – Sensor Controller with Digital and Analog Peripherals .............................................. 1189
17.1 Introduction............................................................................................................... 1190
17.1.1 AUX Hardware Overview..................................................................................... 1191
17.2 Memory Mapping........................................................................................................ 1192
17.2.1 Alias of Commonly Used Registers......................................................................... 1192
17.3 I/O Mapping.............................................................................................................. 1194
17.4 Modules................................................................................................................... 1195
17.4.1 Sensor Controller.............................................................................................. 1195
17.4.2 GPIO Control .................................................................................................. 1206
17.4.3 AUX Timers.................................................................................................... 1208
6Contents SWCU117C–February 2015–Revised September 2015
Submit Documentation Feedback
Copyright © 2015, Texas Instruments Incorporated

www.ti.com
17.4.4 Time-to-Digital Converter..................................................................................... 1208
17.4.5 Semaphores ................................................................................................... 1210
17.4.6 Oscillator Configuration Interface (DDI).................................................................... 1210
17.4.7 Analog MUX ................................................................................................... 1211
17.4.8 ADC............................................................................................................. 1211
17.5 Power Management..................................................................................................... 1214
17.5.1 Start-up......................................................................................................... 1214
17.5.2 Power Mode Management................................................................................... 1214
17.5.3 Wake-up Events............................................................................................... 1216
17.5.4 MCU Bus Connection......................................................................................... 1217
17.6 Clock Management ..................................................................................................... 1217
17.6.1 System Clocks................................................................................................. 1217
17.6.2 Sensor Controller Clock...................................................................................... 1218
17.6.3 Peripheral Clocks ............................................................................................. 1218
17.7 AUX – Sensor Controller Registers................................................................................... 1219
17.7.1 ADI_4_AUX Registers........................................................................................ 1219
17.7.2 AUX_AIODIO Registers...................................................................................... 1231
17.7.3 AUX_EVCTL Registers....................................................................................... 1240
17.7.4 AUX_SMPH Registers........................................................................................ 1262
17.7.5 AUX_TDC Registers.......................................................................................... 1272
17.7.6 AUX_TIMER Registers....................................................................................... 1286
17.7.7 AUX_WUC Registers......................................................................................... 1295
17.7.8 AUX_ANAIF Registers ....................................................................................... 1316
18 Battery Monitor and Temperature Sensor........................................................................... 1323
18.1 Introduction............................................................................................................... 1324
18.2 Functional Description.................................................................................................. 1324
18.3 BATMON Registers..................................................................................................... 1325
18.3.1 AON_BATMON Registers.................................................................................... 1325
19 Universal Asynchronous Receivers and Transmitters (UARTS) ............................................ 1339
19.1 Universal Asynchronous Receiver/Transmitter...................................................................... 1340
19.2 Block Diagram ........................................................................................................... 1341
19.3 Signal Description....................................................................................................... 1341
19.4 Functional Description ................................................................................................. 1341
19.4.1 Transmit and Receive Logic................................................................................. 1342
19.4.2 Baud-rate Generation......................................................................................... 1342
19.4.3 Data Transmission ............................................................................................ 1342
19.4.4 Modem Handshake Support................................................................................. 1343
19.4.5 FIFO Operation................................................................................................ 1344
19.4.6 Interrupts ....................................................................................................... 1344
19.4.7 Loopback Operation .......................................................................................... 1345
19.5 Interface to DMA ........................................................................................................ 1345
19.6 Initialization and Configuration......................................................................................... 1346
19.7 UARTS Registers ....................................................................................................... 1348
19.7.1 UART Registers ............................................................................................... 1348
20 Synchronous Serial Interface (SSI).................................................................................... 1369
20.1 Synchronous Serial Interface.......................................................................................... 1370
20.2 Block Diagram ........................................................................................................... 1371
20.3 Signal Description....................................................................................................... 1372
20.4 Functional Description.................................................................................................. 1372
20.4.1 Bit Rate Generation........................................................................................... 1372
20.4.2 FIFO Operation................................................................................................ 1372
20.4.3 Interrupts ....................................................................................................... 1373
20.4.4 Frame Formats ................................................................................................ 1374
7
SWCU117C–February 2015–Revised September 2015 Contents
Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated

www.ti.com
20.5 DMA Operation .......................................................................................................... 1381
20.6 Initialization and Configuration......................................................................................... 1381
20.7 SSI Registers ............................................................................................................ 1383
20.7.1 SSI Registers .................................................................................................. 1383
21 Inter-Integrated Circuit (I2C) Interface ................................................................................ 1395
21.1 Inter-Integrated Circuit Interface....................................................................................... 1396
21.2 Block Diagram ........................................................................................................... 1396
21.3 Functional Description.................................................................................................. 1397
21.3.1 I2C Bus Functional Overview ................................................................................ 1397
21.3.2 Available Speed Modes ...................................................................................... 1399
21.3.3 Interrupts ....................................................................................................... 1400
21.3.4 Loopback Operation .......................................................................................... 1400
21.3.5 Command Sequence Flow Charts.......................................................................... 1400
21.4 Initialization and Configuration......................................................................................... 1408
21.5 I2C Registers............................................................................................................. 1409
21.5.1 I2C Registers .................................................................................................. 1409
22 Integrated Interchip Sound (I2S) Module............................................................................ 1429
22.1 Introduction .............................................................................................................. 1430
22.2 Digital Audio Interface .................................................................................................. 1430
22.3 Frame Configuration .................................................................................................... 1431
22.4 Pin Configuration........................................................................................................ 1431
22.5 Clock Configuration ..................................................................................................... 1431
22.5.1 WCLK, BCLK, and MCLK Division Ratio................................................................... 1432
22.6 Serial Interface Formats................................................................................................ 1432
22.6.1 I2S............................................................................................................... 1432
22.6.2 Left Justified (LJF) ............................................................................................ 1433
22.6.3 Right Justified (RJF) .......................................................................................... 1433
22.6.4 DSP ............................................................................................................. 1434
22.7 Memory Interface........................................................................................................ 1435
22.7.1 Word Lengths.................................................................................................. 1435
22.7.2 Audio Channels................................................................................................ 1435
22.7.3 Memory Buffers and Pointers................................................................................ 1436
22.8 Samplestamp Generator ............................................................................................... 1436
22.8.1 Counters and Registers ...................................................................................... 1437
22.8.2 Starting Input and Output Pins .............................................................................. 1438
22.8.3 Samplestamp Capturing...................................................................................... 1438
22.9 Usage..................................................................................................................... 1439
22.9.1 Start-up Sequence ............................................................................................ 1439
22.9.2 Termination Sequence ....................................................................................... 1440
22.10 I2S Registers ............................................................................................................ 1441
22.10.1 I2S Registers................................................................................................. 1441
23 Radio............................................................................................................................. 1472
23.1 RF Core................................................................................................................... 1473
23.1.1 High-level Description and Overview....................................................................... 1473
23.2 Radio Doorbell........................................................................................................... 1474
23.2.1 Command and Status Register and Events ............................................................... 1475
23.2.2 RF Core Interrupts ............................................................................................ 1475
23.2.3 Radio Timer.................................................................................................... 1476
23.3 RF Core HAL ............................................................................................................ 1478
23.3.1 Hardware Support............................................................................................. 1478
23.3.2 Firmware Support ............................................................................................. 1478
23.3.3 Command Definitions......................................................................................... 1491
8Contents SWCU117C–February 2015–Revised September 2015
Submit Documentation Feedback
Copyright © 2015, Texas Instruments Incorporated

www.ti.com
23.3.4 Protocol-Independent Direct and Immediate Commands................................................ 1505
23.3.5 Immediate Commands for Data Queue Manipulation.................................................... 1515
23.4 Data Queue Usage...................................................................................................... 1518
23.4.1 Operations on Data Queues Only Available for Internal Radio CPU Operations..................... 1518
23.4.2 Radio CPU Usage Model .................................................................................... 1521
23.5 IEEE 802.15.4 ........................................................................................................... 1522
23.5.1 IEEE 802.15.4 Commands................................................................................... 1522
23.5.2 Interrupts ....................................................................................................... 1530
23.5.3 Data Handling.................................................................................................. 1530
23.5.4 Radio Operation Commands ................................................................................ 1531
23.5.5 Immediate Commands ....................................................................................... 1544
23.6 Bluetooth Low Energy .................................................................................................. 1545
23.6.1 Bluetooth Low Energy Commands.......................................................................... 1546
23.6.2 Interrupts ....................................................................................................... 1554
23.6.3 Data Handling.................................................................................................. 1555
23.6.4 Radio Operation Command Descriptions.................................................................. 1556
23.6.5 Immediate Commands ....................................................................................... 1577
23.7 Proprietary Radio........................................................................................................ 1578
23.7.1 Packet Formats................................................................................................ 1578
23.7.2 Commands..................................................................................................... 1578
23.7.3 Interrupts ....................................................................................................... 1586
23.7.4 Data Handling.................................................................................................. 1587
23.7.5 Radio Operation Command Descriptions.................................................................. 1588
23.7.6 Immediate Commands ....................................................................................... 1599
23.8 Radio Registers.......................................................................................................... 1600
23.8.1 RFC_RAT Registers.......................................................................................... 1600
23.8.2 RFC_DBELL Registers....................................................................................... 1610
23.8.3 RFC_PWR Registers ......................................................................................... 1626
9
SWCU117C–February 2015–Revised September 2015 Contents
Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated

Revision History: SWCU117C www.ti.com
Revision History: SWCU117C
Changes from June 10, 2015 to September 4, 2015 ....................................................................................................... Page
• Added CC13xx part number to the block diagram .................................................................................. 15
• Changed Radio chapter.............................................................................................................. 1475
• Added Proprietary Radio section ................................................................................................... 1578
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Revision History: SWCU117B
Changes from March 6, 2015 to June 9, 2015 ................................................................................................................. Page
• Changed Architectural Overview chapter............................................................................................. 15
• Changed register names in the Architectural Overview chapter .................................................................. 27
• Updated links in Cortex-M3 Processor chapter...................................................................................... 29
• Changed CPU Block Diagram ......................................................................................................... 30
• Changed TPIU Block Diagram......................................................................................................... 31
• Changed Cortex-M3 Processor registers............................................................................................. 51
• Changed Cortex-M3 Peripherals chapter ........................................................................................... 221
• Added Cortex-M3 Memory Map...................................................................................................... 226
• Changed register names in the Interrupts and Events chapter .................................................................. 229
• Changed Interrupts and Events registers........................................................................................... 247
• Changed register names in the Power, Reset, and Clock Management chapter ............................................. 414
• Changed PRCM registers............................................................................................................. 432
• Changed register names in the Versatile Instruction Memory System (VIMS) chapter....................................... 535
• Added the Power Management Requirements section ........................................................................... 541
• Deleted FLASHMEM register subsection ........................................................................................... 545
• Changed VIMS registers .............................................................................................................. 545
• Changed register names in the Device Configuration chapter................................................................... 689
• Changed Device Configuration registers............................................................................................ 689
• Changed register names in the Cryptography chapter............................................................................ 802
• Changed DMA Controller and Integration diagram ................................................................................ 806
• Changed values in the Performance Table for DMA-Based Operations........................................................ 816
• Changed register names in the I/O Control chapter............................................................................... 874
• Changed IOC Overview section...................................................................................................... 874
• Changed I/O Control registers........................................................................................................ 881
• Changed register names in the Micro Direct Memory Access (µDMA) chapter. ............................................. 1040
• Changed µDMA registers............................................................................................................ 1056
• Changed register names in the Timers chapter .................................................................................. 1078
• Changed General-purpose Timer registers ....................................................................................... 1092
• Changed register names in the Real-Time Clock chapter....................................................................... 1128
• Changed RTC registers.............................................................................................................. 1131
• Changed register names in the Watchdog Timer chapter....................................................................... 1146
• Changed Watchdog registers ....................................................................................................... 1148
• Changed Random Number Generator registers.................................................................................. 1166
• Changed the AUX – Sensor Controller with Digital and Analog Peripherals chapter........................................ 1189
• Changed AUX – Sensor Controller registers...................................................................................... 1219
• Changed register names in the Battery Monitor and Temperature Sensor chapter ......................................... 1324
• Changed BATMON registers........................................................................................................ 1325
• Changed register names in the UARTS chapter ................................................................................. 1340
• Changed UARTS registers .......................................................................................................... 1348
10 Revision History SWCU117C–February 2015–Revised September 2015
Submit Documentation Feedback
Copyright © 2015, Texas Instruments Incorporated

www.ti.com Revision History: SWCU117A
• Changed register names in the SSI chapter ...................................................................................... 1370
• Changed SSI registers............................................................................................................... 1383
• Changed register names in the Inter-Integrated Circuit (I2C) Interface chapter .............................................. 1396
• Changed I2C registers................................................................................................................ 1409
• Changed register names in the I2S chapter ...................................................................................... 1430
• Changed I2S registers ............................................................................................................... 1441
• Changed register names in the Radio chapter ................................................................................... 1473
• Changed CMD_UPDATE_FS Command Format table.......................................................................... 1513
• Changed Radio registers ............................................................................................................ 1600
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Revision History: SWCU117A
Changes from February 21, 2015 to March 5, 2015 ........................................................................................................ Page
• Changed Functional Description section............................................................................................... 7
• Changed Cortex-M3 Processor registers............................................................................................. 51
• Changed Interrupts and Events registers........................................................................................... 247
• Changed PRCM registers............................................................................................................. 432
• Changed VIMS registers .............................................................................................................. 545
• Changed Device Configuration registers............................................................................................ 689
• Changed Detailed Memory Map table............................................................................................... 804
• Changed Cryptography registers..................................................................................................... 829
• Changed I/O Control registers........................................................................................................ 881
• Updated image. ....................................................................................................................... 1047
• Changed µDMA registers............................................................................................................ 1056
• Changed General-purpose Timer registers ....................................................................................... 1092
• Changed RTC registers.............................................................................................................. 1131
• Changed Watchdog registers ....................................................................................................... 1148
• Changed Random Number Generator registers.................................................................................. 1166
• Changed AUX – Sensor Controller registers...................................................................................... 1219
• Changed BATMON registers........................................................................................................ 1325
• Changed Functional Description section .......................................................................................... 1339
• Changed UART feature list.......................................................................................................... 1340
• Changed Signals for UART table................................................................................................... 1341
• Changed Functional Description section .......................................................................................... 1341
• Changed Functional Description section .......................................................................................... 1342
• Changed Functional Description section .......................................................................................... 1343
• Changed Functional Description section .......................................................................................... 1344
• Changed Functional Description section .......................................................................................... 1345
• Changed Initialization and Configurations section................................................................................ 1346
• Changed UARTS registers .......................................................................................................... 1348
• Changed SSI Signals table.......................................................................................................... 1372
• Changed SSI registers............................................................................................................... 1383
• Changed I2C registers................................................................................................................ 1409
• Changed I2S registers ............................................................................................................... 1441
• Changed Radio chapter.............................................................................................................. 1473
• Changed Radio registers ............................................................................................................ 1600
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
11
SWCU117C–February 2015–Revised September 2015 Revision History
Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated

Preface
SWCU117C–February 2015–Revised September 2015
Read This First
Trademarks
SimpleLink is a trademark of Texas Instruments. ARM7, ARM®CoreSight are trademarks of ARM Limited.
ARM, Cortex, Thumb, AMBA, ARM PrimeCell are registered trademarks of ARM Limited.
About This Document
This technical reference manual provides information on how to use the CC26xx and the CC13xx
SimpleLink™ ultra-low power wireless microcontroller devices. The CC26xx and the CC13xx families
share the same MCU architecture and most of the peripherals, but the CC13xx radio is designed for use
in the sub-1 GHz frequency bands while the CC26xx radio operates in the 2.4-GHz ISM frequency band.
This document covers the whole family of devices, so please see the individual device data sheet for
supported modules and features.
Audience
This manual is intended for system software developers, hardware designers, and application developers.
About This Manual
This document is organized into sections that correspond to each major feature. It explains the features
and functionality of each module, and explains how to use them. For each feature, references are given to
the corresponding operating systems driver documentation. This document does not contain performance
characteristics of the device or modules. These are gathered in the corresponding device data sheet.
Related Documents
The following related documents are available on the CC26xx product pages at www.ti.com:
• CC2620 Data Sheet and Errata (CC2620 Technical Documents)
• CC2630 Data Sheet and Errata (CC2630 Technical Documents)
• CC2640 Data Sheet and Errata (CC2640 Technical Documents)
• CC2650 Data Sheet and Errata (CC2650 Technical Documents)
• CC1310 Data Sheet and Errata (CC1310 Technical Documents)
This list of documents was current as of publication date. Check the web site for additional documentation,
including application notes and white papers.
Devices
The CC26xx and the CC13xx family of devices includes both 2.4-GHz and Sub-1 GHz radios and a variety
of different memory sizes, peripherals and package options. All devices are centered around an ARM®
Cortex®-M series processor that handles the application layer and protocol stack, as well as an
autonomous radio core centered around an ARM Cortex-M0 processor that handles all the low-level radio
control and processing. Network processor options are available.
The availability of several a wide range of different radio and MCU system combination makes these
families very well suited for almost any low-power RF node implementation.
12 Read This First SWCU117C–February 2015–Revised September 2015
Submit Documentation Feedback
Copyright © 2015, Texas Instruments Incorporated

www.ti.com Related Documents
Feedback
Help us meet your expectations:
We are always exploring ways to develop our service and improve our quality to fit your needs. Please
contact your TI representative and take a few minutes to provide general suggestions, give document
feedback, or submit an error.
Thank you.
Community Resources
All technical support is channeled through the TI Product Information Centers (PIC) - www.ti.com/support.
To send an E-mail request, please enter your contact information, along with your request at the following
link – PIC request form.
The following link connects to TI community resources. Linked contents are provided "AS IS" by the
respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views;
see TI's Terms of Use.
TI Embedded Processors Wiki – Texas Instruments Embedded Processors Wiki
TI BLE Wiki – Texas Instruments Bluetooth Smart Wiki
Established to assist developers using the many Embedded Processors from TI to get started, help each
other innovate, and foster the growth of general knowledge about the hardware and software surrounding
these devices.
Register, Field, and Bit Calls
The naming convention applied for a call consists of:
• For a register call: <Module name>.<Register name>; for example: UART.UASR
• For a bit field call:
–<Module name>.<Register name>[End:Start] <Field name> field; for example, UART.UASR[4:0]
SPEED bit field
–<Field name> field <Module name>.<Register name>[End:Start]; for example, SPEED bit field
UART.UASR[4:0]
• For a bit call:
–<Module name>.<Register name>[pos] <Bit name> bit; for example, UART.UASR[5]
BIT_BY_CHAR bit
–<Bit name> bit <Module name>.<Register name>[pos]; for example, BIT_BY_CHAR bit
UART.UASR[5]
13
SWCU117C–February 2015–Revised September 2015 Read This First
Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated

Chapter 1
SWCU117C–February 2015–Revised September 2015
Architectural Overview
The CC26xx and CC13xx SimpleLink™ ultra-low power wireless MCU platforms provide solutions for a
wide range of applications. To help the user develop these applications, this user's guide focuses on the
use of the different building blocks of the devices. For detailed device descriptions, complete feature lists,
and performance numbers, see the data sheet. To provide easy access to relevant information, the
following subsections guide the reader to the different chapters in this guide.
The CC26xx and CC13xx SimpleLink ultra-low power wireless MCU platform system-on-chips (SoCs) are
optimized for ultra low power, while providing fast and capable MCU systems to enable short processing
times and high integration. The combination of an ARM®Cortex®-M3 processing core of up to 48 MHz,
flash memory, and a wide selection of peripherals makes the CC26xx and CC13xx device families ideal
for single-chip implementation or network processor implementations of lower power RF nodes.
Topic ........................................................................................................................... Page
1.1 Target Applications ............................................................................................ 15
1.2 Overview........................................................................................................... 15
1.3 Functional Overview........................................................................................... 17
14 Architectural Overview SWCU117C–February 2015–Revised September 2015
Submit Documentation Feedback
Copyright © 2015, Texas Instruments Incorporated

www.ti.com Target Applications
1.1 Target Applications
The CC26xx and CC13xx SimpleLink ultra-low power wireless MCU platforms are positioned for low-
power wireless applications such as:
• Consumer Electronics
• Mobile Phone Accessories
• Sports and Fitness Equipment
• HID Applications
• Home and Building Automation
• Lighting Control
• Alarm and Security
• Electronic Shelf Labeling
• Proximity Tags
• Medical
• Remote Controls
• Wireless Sensor Networks
1.2 Overview
Figure 1-1 shows the building blocks of the CC26xx and CC13xx devices.
Figure 1-1. CC26xx and CC13xx Block Diagram
15
SWCU117C–February 2015–Revised September 2015 Architectural Overview
Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated

Overview www.ti.com
The CC26xx and CC13xx devices have the following features:
• ARM Cortex-M3 processor core
– 48-MHz RC oscillator and 24-MHz xtal oscillator with internal doubler
– 32-kHz xtal oscillator, 32-kHz RC oscillator or low-power 24-MHz xtal derivate clock for timing
maintenance while in low-power modes
– ARM Cortex SysTick timer
– Nested vectored interrupt controller (NVIC)
• On-chip memory
– Flash with 8KB of 4-way set-associative cache RAM for speed and low power
– System RAM with configurable retention in 4-KB blocks
• Power management
– Wide supply voltage range
– Efficient on-chip DC-DC converter for reduced power consumption
– High granularity clock gating and power gating of device parts
– Flexible frequency of operation
• Flexible low-power modes allowing low energy consumption in duty cycled applications
• Sensor interface
– Autonomous, intelligent sensor interface that can wake up independently of the main CPU system
to perform sensor readings, collect data, and determine if the main CPU must be woken
– 12-bit analog-to-digital converter (ADC) with eight analog input channels
– Low-power analog comparator
– SPI or I2C master bit-banged
• Advanced serial integration
– Universal asynchronous receiver and transmitter (UART)
– Inter-integrated circuit (I2C) module
– Synchronous serial interface modules (SSIs)
– Audio interface I2S module
• System integration
– Direct memory access (DMA) controller
– Four 32-bit timers (up to eight 16-bit) with pulse width modulation (PWM) capability and
synchronization
– 32-kHz real-time clock (RTC)
– Watchdog timer
– On-chip temperature and supply voltage sensing
– GPIO with normal or high-drive capabilities
– GPIOs with analog capability for ADC and comparator
– Fully flexible digital pin muxing allows use as GPIO or any peripheral function
• IEEE 1149.7 compliant 2-pin cJTAG with legacy 1149.1 JTAG support
• 4-mm × 4-mm, 5-mm × 5-mm, and 7-mm × 7-mm QFN packages
For applications requiring extreme conservation of power, the CC26xx and CC13xx devices feature a
power-management system to efficiently power down the CC26xx or CC13xx devices to a low-power state
during extended periods of inactivity. A power-up and power-down sequencer, a 32-bit sleep timer (a real-
time clock [RTC]), with interrupt and 20KB of RAM with retention in all power modes positions the CC26xx
and CC13xx microcontroller perfectly for battery applications.
16 Architectural Overview SWCU117C–February 2015–Revised September 2015
Submit Documentation Feedback
Copyright © 2015, Texas Instruments Incorporated

www.ti.com Functional Overview
In addition, the CC26xx and CC13xx microcontroller offers the advantages of the widely available
development tools of ARM, SoC infrastructure IP applications, and a large user community. Additionally,
the microcontroller uses ARMThumb®-compatible Thumb-2 instruction set to reduce memory requirements
and, thereby, cost.
TI offers a complete solution to get to market quickly, with evaluation and development boards, white
papers and application notes, an easy-to-use peripheral driver library, and a strong support, sales, and
distributor network.
1.3 Functional Overview
The following subsections provide an overview of the features of the CC26xx and CC13xx microcontroller.
1.3.1 ARM Cortex-M3
The following subsections provide an overview of the ARM Cortex-M3 processor core and instruction set,
the integrated system timer (SysTick), and the NVIC.
1.3.1.1 Processor Core
The CC26xx and CC13xx devices are designed around an ARM Cortex-M3 processor core. The ARM
Cortex-M3 processor provides the core for a high-performance, low-cost platform that meets the needs of
minimal memory implementation, reduced pin count, and low power consumption, while delivering
outstanding computational performance and exceptional system response to interrupts.
The following are features of the processor core:
• 32-bit ARM Cortex-M3 architecture optimized for small-footprint embedded applications
• Outstanding processing performance combined with fast interrupt handling
• Thumb-2 mixed 16- and 32-bit instruction set delivers the high performance expected of a 32-bit ARM
core in a compact memory size, usually associated with 8- and 16-bit devices, typically in the range of
a few kilobytes of memory for microcontroller-class applications
– Single-cycle multiply instruction and hardware divide
– Atomic bit manipulation (bit-banding), delivering maximum memory use and streamlined peripheral
control
– Unaligned data access, enabling efficient packing of data into memory
• Fast code execution permits slower processor clock or increases sleep mode time
• Harvard architecture characterized by separate buses for instruction and data
• Efficient processor core, system, and memories
• Hardware division and fast multiplier
• Deterministic, high-performance interrupt handling for time-critical applications
• Enhanced system debug with extensive breakpoint capabilities and debugging through power modes
• Compact JTAG interface reduces the number of pins required for debugging
• Ultra-low power consumption with integrated sleep modes
• Up to 48-MHz operation
17
SWCU117C–February 2015–Revised September 2015 Architectural Overview
Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated

Functional Overview www.ti.com
1.3.1.2 System Timer (SysTick)
ARM Cortex-M3 includes an integrated system timer (SysTick). SysTick provides a simple, 24-bit, clear-
on-write, decrementing, wrap-on-zero counter with a flexible control mechanism. The counter can be used
in several different ways; for example:
• An RTOS tick timer that fires at a programmable rate (for example, 100 Hz) and invokes a SysTick
routine
• A high-speed alarm timer using system clock 11
• A variable rate alarm or signal timer—the duration is range-dependent on the reference clock used and
the dynamic range of the counter
• A simple counter used to measure time to completion and time used
• An internal clock-source control based on missing or meeting durations
1.3.1.3 Nested Vector Interrupt Controller (NVIC)
The CC26xx and CC13xx device controller includes the ARM NVIC. The NVIC and Cortex-M3 prioritize
and handle all exceptions in handler mode. The processor state is automatically stored to the stack on an
exception and automatically restored from the stack at the end of the interrupt service routine (ISR). The
interrupt vector is fetched in parallel to state saving, thus enabling efficient interrupt entry. The processor
supports tail-chaining, that is, back-to-back interrupts can be performed without the overhead of state
saving and restoration. Software can set eight priority levels on seven exceptions (system handlers) and
can set CC26xx and CC13xx device interrupts.
Features of the NVIC are as follows:
• Deterministic, fast interrupt processing
– Always 12 cycles, or just 6 cycles with tail-chaining
• External nonmaskable interrupt (NMI) signal available for immediate execution of NMI handler for
safety-critical applications
• Dynamically reprioritizable interrupts
• Exceptional interrupt handling through hardware implementation of required register manipulations
1.3.1.4 System Control Block
The system control block (SCB) provides system implementation information and system control
(configuration, control, and reporting of system exceptions).
1.3.2 On-chip Memory
The following subsections describe the on-chip memory modules.
1.3.2.1 SRAM
The CC26xx and CC13xx devices provide low leakage on-chip SRAM with optional retention in all power
modes. Retention can be configured per block, and the device contains two blocks of 6KB and two blocks
of 4KB. Additionally, the flash cache RAM can be reconfigured to operate as normal system RAM.
Because read-modify-write (RMW) operations are very time consuming, ARM has introduced bit-banding
technology in the Cortex-M3 processor. With a bit-band-enabled processor, certain regions in the memory
map (SRAM and peripheral space) can use address aliases to access individual bits in a single, atomic
operation.
Data can be transferred to and from the SRAM using the micro DMA (µDMA) controller.
18 Architectural Overview SWCU117C–February 2015–Revised September 2015
Submit Documentation Feedback
Copyright © 2015, Texas Instruments Incorporated

www.ti.com Functional Overview
1.3.2.2 Flash Memory
The flash block provides an in-circuit, programmable, nonvolatile program memory for the device. The
flash memory is organized as a set of 4-KB pages that can be individually erased. Erasing a block causes
the entire contents of the block to be reset to all 1s. These pages can be individually protected. Read-only
blocks cannot be erased or programmed, protecting the contents of those blocks from being modified. In
addition to holding program code and constants, the nonvolatile memory allows the application to save
data that must be preserved so that it is available after restarting the device. Using this feature lets the
user use saved network-specific data to avoid the need for a full start-up and network find-and-join
process.
1.3.2.3 ROM
The ROM is preprogrammed with a boot sequence, device driver functions, low-level protocol stack
components, and a serial bootloader (SPI or UART).
1.3.3 Radio
The CC26xx and CC13xx device family provides a highly integrated low-power 2.4-GHz radio transceiver
with support for multiple modulations and packet formats. The CC13xx provides similar functionality
optimized for the sub-1 GHz bands and also allows limited operation in the 2.4-GHz band. The radio
subsystem provides an interface between the MCU and the radio, which makes it possible to issue
commands, read status, and automate and sequence radio events.
1.3.4 Advanced Encryption Standard (AES) Engine With 128-bit Key Support
The security core of the CC26xx and CC13xx devices features an AES module with 128-bit key support,
local key storage, and DMA capability.
Features of the AES engine are as follows:
• CCM, CTR, CBC-MAC, and ECB modes of operation
• 118-Mbps throughput
• Secure key storage memory
• Low latency
19
SWCU117C–February 2015–Revised September 2015 Architectural Overview
Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated

Functional Overview www.ti.com
1.3.5 General-Purpose Timers
General-purpose timers can be used to count or time external events that drive the timer-input pins. Each
16- or 32-bit GPTM block provides two 16-bit timers or counters that can be configured to operate
independently as timers or event counters, or configured to operate as one 32-bit timer.
The general-purpose timer module (GPTM) contains four 16- or 32-bit GPTM blocks with the following
functional options:
• 16- or 32-bit operating modes:
– 16- or 32-bit programmable one-shot timer
– 16- or 32-bit programmable periodic timer
– 16-bit general-purpose timer with an 8-bit prescaler
– 16-bit input-edge count- or time-capture modes with an 8-bit prescaler
– 16-bit PWM mode with an 8-bit prescaler and software-programmable output inversion of the PWM
signal
• Count up or down
• Four 32-bit counters or up to eight 16-bit counters
• Up to eight capture/compare pins
• Up to four PWM pins (one PWM pin per 32-bit timer)
• Daisy-chaining of timer modules allows a single timer to initiate multiple timing events
• Timer synchronization allows selected timers to start counting on the same clock cycle
• User-enabled stalling when the microcontroller asserts CPU halt flag during debug
• Ability to determine the elapsed time between the assertion of the timer interrupt and entry into the
interrupt service routine
• Efficient transfers using the µDMA controller
1.3.5.1 Watchdog Timer
The watchdog timer is used to regain control when the system fails because of a software error or an
external device fails to respond properly. The watchdog timer can generate an interrupt or a reset when a
predefined time-out value is reached.
1.3.5.2 Always-on Domain
The AON domain contains circuitry that is always enabled, except for the shutdown mode (where the
digital supply is off). This domain includes the following:
• The RTC can be used to wake the CC26xx and CC13xx devices from any state where it is active. The
RTC contains three match registers and one compare register. With software support, the RTC can be
used for clock and calendar operation. The RTC is clocked from the 32-kHz RC oscillator or the
32-kHz crystal oscillator.
• The battery monitor and temperature sensors are accessible by software. The battery monitor and
temperature sensors provide continuous monitoring of battery state as well as coarse temperature.
1.3.6 Direct Memory Access
The CC26xx and CC13xx microcontroller includes a DMA controller, known as μDMA. The μDMA
controller provides a way to offload data transfer tasks from the Cortex-M3 processor, allowing more
efficient use of the processor and the available bus bandwidth. The μDMA controller can perform transfers
between memory and peripherals. Channels in the μDMA are dedicated for each supported on-chip
module and can be programmed to automatically perform transfers between peripherals and memory, as
the peripheral is ready to transfer more data.
20 Architectural Overview SWCU117C–February 2015–Revised September 2015
Submit Documentation Feedback
Copyright © 2015, Texas Instruments Incorporated