Toshiba TC78B002FNG User manual

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TOSHIBA CMOS Integrated Circuit Silicon Monolithic
TC78B002FNG
Single Phase Full-wave Driver for Fan Motor
TC78B002FNG is a single phase full-wave driver for fan motor. It
has a DMOS device in an output transistor.
A highly effective drive is possible by adopting a DMOS output driver
with low ON resistance and a PWM drive system.
Features
•Single-phase full-wave drive
•Motor power supply voltage: VM =16V (maximum operating range)
•Output current: Iout = 1.5A (max.)
•PWM control
•Built-in oscillation circuit (External resistor)
•Soft switching drive
•Lock protection, Automatic recovery
•Quick start
•Built in hall bias
•Rotation Speed Detection (FG) and Lock Detection (RDO) Output
•Current limit function
•Built in over current protection
•Built in thermal shut down circuit
TC78B002FNG
Weight: 0.07g (typ)
SSOP16-P-225-0.65B

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Block Diagram (Application circuit)
5V Regulator
Control
Logic
Pre
Driver
TSD
M
Lock Protection
OSC
Hall
Ele.
OUT1
OUT2
FG
RDO
RS
VM
GND
OSCR
VMI
LA
HM
HP
VREG
7bit
A/D
VOFF
ISD
VSOFT
VSP
0.1uF
24kΩ
0.1μF

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Pin Assignment
VMI
LA
VOFF
VSOFT
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9 VM
GND
RS
VSP
FGOUT1
OUT2
OSCR
VREG
HP
HM
RDO

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Pin Description
Pin No. Pin name Description
1
VREG
Output pin for reference voltage of 5 V
2
HP
Hall signal input pin +
3
HM
Hall signal input pin
－
4
OSCR
Connection pin for resistor of oscillation circuit
5
RDO
Output pin for lock detection
6
OUT1
Motor output pin 1
7
GND
Connection pin for ground
8
RS
Connection pin for detecting resistor of output current
9
VM
Power supply pin
10
OUT2
Motor output pin 2
11
FG
Rotating output pin
12
VSP
Setting pin for output duty
13
VOFF
Setting pin for OFF term in switching conducting phase
14
LA
Setting pin for lead angle
15
VMI
Setting pin for minimum output duty
16
VSOFT
Setting pin for soft switching term

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Absolute Maximum Ratings (Ta = 25°C)
Characteristics Symbol Rating Unit
Power supply voltage VM 18 V
Input voltage VIN -0.3~6 (Note 1) V
Output voltage VOUT 18 (Note 2) V
Output current
OUT1,OUT2 IOUT 1.5 (Note 3)
A
VREG IOUT 10 mA
FG pin sink current IFG 10 mA
RDO pin sink current IRDO 10 mA
Power dissipation PD0.96 (Note 4) W
Operating temperature Topr -40 to 105 °C
Storage temperature Tstg -55 to 150 °C
Note: The absolute maximum ratings of a semiconductor device are a set of ratings that must not be exceeded, even for a
moment. Do not exceed any of these ratings. Exceeding the rating (s) may cause the device breakdown, damage or
deterioration, and may result injury by explosion or combustion. Please use the IC within the specified operating ranges.
Note 1: VMI, VSP, VSOFT, VOFF, and LA pins
Note 2: OUT1, OUT2, FG and RDO pins
Note 3: Power dissipation must not be exceed
Note 4: Mounted on a glass epoxy board
Package Power Dissipation
(1) When mounted on the board (40mm×30mm×1.6mm 2 layers, FR-4 board) Rth(j-a)=130℃/W
(2) IC only Rth(j-a)=400℃/W
Operating Ranges (Ta = 25°C)
Characteristics Symbol Min Typ. Max Unit
Power supply voltage VMopr15.5 12 16 V
Power supply for low voltage
operation VMopr2 3.5 4.5 5.5 V
Internal oscillation frequency (Note 1) fOSC 8 10 12 MHz
PWM frequency fPWM 20 25 30 kHz
Input voltage (Note 2) VIN 0 VREG V
Note 1: In low-voltage operation, operation with frequency more than 10MHz is not covered under guarantee.
Note 2: VMI, VSOFT, VOFF, and LA pins
0
0.2
0.4
0.6
0.8
1
1.2
025 50 75 100 125 150
P
D
(W)
Ta (℃)
(1)
(2)

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Electrical Characteristics (Ta = 25°C and VM = 12 V, unless otherwise specified.)
Characteristics Symbol Test conditions Min Typ. Max Unit
Power supply current IVM VM =12 V, VREG =OPEN
Hall input=100Hz, output OPEN 3 5 mA
Hall signal
input
Common mode input voltage
range VCMRH 0 VREG
-1.5 V
Input voltage swing VH40 mV
Input current IH|VHP-VHM|≧100mV 1 μA
Hysteresis＋Voltage VHHYS+ (Design target value) (Note 1) 5 10 15 mV
Hysteresis－Voltage VHHYS-(Design target value) (Note 1) -15 -10 -5 mV
VREG pin voltage VREG VREG pin output source current=10mA 4.5 5.0 5.5 V
Maximum voltage of ADC convertor VADC (Design target value) (Note 1) VREG
-0.75 V
Output On Duty (Note 1)
Duty(20)
ROSC=24kΩ, output load:1kΩ
VSP=1.2V, VMI=0V or
VMI=1.2V, VSP=0V
15 20 25 %
Duty(50)
ROSC=24kΩ, output load:1kΩ
VSP=2.2V, VMI=0V or
VMI=2.2V, VSP=0V
43 50 57 %
Duty(80)
ROSC=24kΩ, output load:1kΩ
VSP=3.2V, VMI=0V or
VMI=3.2V, VSP=0V
70 80 90 %
VSP threshold
VAD (L) Threshold voltage of stopping output 0.5 0.55 
V
VAD (H) Threshold voltage of full output 3.9 4.3
VSP response time TVSP (Design target value) (Note 1) 10 ms
Internal oscillation frequency fOSC ROSC=24kΩ
Measured by internal divided frequency 8 10 12 MHz
PWM frequency fPWM ROSC=24kΩ 20 25 30 kHz
Pin input current IIN VSP,VMI,VSOFT,VOFF, and LA pins
input voltage 0~VREG 1 μA
Output ON resistance Ron(H+L) IOUT = 0.2A 1.6 2.5 Ω
Soft switching time (Note 1)
TSOFT(0) ROSC=24kΩ, Hall input=100Hz
VOFF=0V , VSOFT=0V
0
°
TSOFT(45) ROSC=24kΩ, Hall input=100Hz
VOFF=0V , VSOFT=VREG*0.45 43 47
TSOFT(90) ROSC=24kΩ, Hall input=100Hz
VOFF=0V , VSOFT= VREG 84 90
OFF term
(Note 1)
TOFF(0) ROSC=24kΩ, Hall input=100Hz
VSOFT=0V, VOFF=0V
0
°
TOFF(45) ROSC=24kΩ, Hall input=100Hz
VSOFT=0V, VOFF= VREG*0.45 43 47
TOFF(90) ROSC=24kΩ, Hall input=100Hz
VSOFT=0V, VOFF= VREG 84 90
Lead angle correction
(Note 1)
TLA(0) ROSC=24kΩ, Hall input=100Hz
LA=0V
0
°
TLA(11.25) ROSC=24kΩ, Hall input=100Hz
LA= VREG*0.23 10 12
TLA(22.5) ROSC=24kΩ, Hall input=100Hz
LA= VREG 21 24

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Characteristics Symbol Test conditions Min Typ. Max Unit
FG
RDO
pin
Output low voltage VOUT(L) IFG/RDO=5mA 0.3 V
Output leakage current IOUT(H) VFG/RDO=5V 1 μA
Current limit detecting voltage for RS pin VRS 0.27 0.3 0.33 V
Masking time of current limit detection Tmask (Design target value) (Note 1) 1.2 1.5 1.8 μs
Operating current of over current protection ILIM (Design target value) (Note 1) 2.5 A
Masking time of over current protection TISDMASK (Design target value) (Note 1) 2 μs
OFF time of over current protection TISDOFF (Design target value) (Note 1) 100 ms
Operating temperature of thermal shutdown
circuit TSD Junction temperature
(Design target value) (Note 1)
170 ℃
Hysteresis of thermal shutdown circuit ΔTSD (Design target value) (Note 1) 40 ℃
ON time of lock detection TON ROSC=24kΩ
(Design target value) (Note 1) 0.32 0.4 0.48 s
OFF time of lock detection TOFF ROSC=24kΩ
(Design target value) (Note 1) 3.2 4 4.8 s
Detecting voltage for low voltage
VUVLO Operation voltage
(Design target value) (Note 1) 2.6 2.9 3.2 V
VPORRL Recovery voltage
(Design target value) (Note 1) 2.9 3.2 3.5 V
Output switching characteristics
tr(Design target value) (Note 1) 100 
ns
tf(Design target value) (Note 1) 100 
Note 1: Pre-shipment testing is not performed.

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Reference Data
Fig.1 Power supply current
Fig.2 Hall input Hysteresis voltage
Fig.3 VREG pin voltage (VM=12V)
Fig.4 VREG pin voltage (Ta=25℃)
Fig.5 Output ON resistance (VM=12V)
Fig.6 Output ON resistance ( Ta = 2 5 ℃)
-20
-10
0
10
20
36912 15 18
Hall input hysteresis voltage. VHHYS [mV]
Supply voltage. VM[V]
125℃
25℃
-40℃
Operation Voltage Range
-40℃
25℃
125℃
4.6
4.7
4.8
4.9
5
0246810
VREG output voltage. VREG[V]
Output Current. I
VREG
[mA]
125℃
25℃
-40℃
2
3
4
5
6
0 2 4 6 8 10
VREG output voltage. VREG[V]
Output Current. I
VREG
[mA]
18V
12V
3.5V
0
1
2
3
4
00.3 0.6 0.9 1.2 1.5
Ouput ON resistance.RON(H+L) [Ω]
Output Current. IOUT[A]
125℃
25℃
-40℃
0
1
2
3
4
00.3 0.6 0.9 1.2 1.5
Ouput ON resistance.RON(H+L) [Ω]
Output Current. I
OUT
[A]
3.5V
12V
1
2
3
3 6 9 12 15 18
Power supply current. I
VM
[mA]
Supply voltage. VM[V]
125℃
25℃
-40℃
Operation Voltage Range

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Fig.7 FG/RDO pin Output low voltage (VM=12V)
Fig.8 FG/RDO pin Output low voltage (Ta=25℃)
Fig.9 Internal oscillation frequency
Fig.10 Current limit detecting voltage for RS pin
0
0.2
0.4
0.6
0.8
1
0 2 4 6 8 10
FG low voltage. V
OUT(L)
[V]
Output Current. I
FG/RDO
[mA]
125℃
25℃
-40℃
0
0.2
0.4
0.6
0.8
1
0 2 4 6 8 10
FG low voltage. VOUT(L)[V]
Output Current. IFG/RDO[mA]
3.5V
12V
8
9
10
11
12
36912 15 18
Internaloscillation frequency. fOSC [MHz]
Supply voltage. VM[V]
125℃
25℃
-40℃
Operation Voltage Range
0.28
0.29
0.3
0.31
0.32
36912 15 18
Current limit detecting voltage
. V
RS
[V]
Supply voltage. VM[V]
125℃
25℃
-40℃
Operation Voltage Range

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I/O Equivalent Circuits
Pin name
I/O signal
Equivalent circuit
HP
HM
Hall signal input pin
In-phase input voltage range
0V to VREG-1.5V
VSP
VMI
LA
Control voltage input pin
VSOFT
VOFF
Control voltage input pin
VREG
Voltage output pin
VREG = 5V (typ)
FG
RDO
Digital output pin
Open drain output
It should be pulled up externally to output
High.
VSP
VMI
LA
FG
RDO
HP
HM
VREG VREG
VSOFT
VOFF
VREG
VREG
VM

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Pin name
I/O signal
Equivalent circuit
VM
OUT1
OUT2
RS
Motor output pin
OSCR Connection pin for resistor of oscillation circuit
OUT1
OUT2
VM
RS
0.3V
OSCR
VREG VREG

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Functional Description
The equivalent circuit diagrams may be simplified or some parts of them may be omitted for explanatory purposes.
Timing charts may be simplified for explanatory purposes.
1. Basic Operation
At startup, the motor is driven by a square-wave drive by determining the conducting phase with hall input
signal.
When hall signal frequency reaches 5Hz (typ) or more, the motor is driven by the conducting pattern which is
generated by estimating the next conducting timing from the hall input signal.
<I/O function table>
HP
HM
OUT1
OUT2
FG
RDO
Mode
H
L
L
PWM
OFF
L
Rotating (Note 1)
L
H
PWM
L
L
L
H
L
L
OFF
OFF

Current limit drive (Note 2)
L
H
OFF
L
L



OFF
OFF

OFF
Lock protection (Note 3)
 
OFF
OFF
 
Thermal shutdown
Note 1：Conducting phase is switched by the hall input signal. FG signal is outputted according to the phase-switching.
Conducting timing may be preceded depending on the lead angle set.
Note 2：Upper power transistor is turned off during current limitation. It recovers automatically every PWM frequency.
Note 3：FG output changes depending on the rotor position in the lock protection mode the same as rotating mode.
Timing chart (Normal rotation)
With soft switching, with lead angle
Without soft switching,
without lead angle
HP
HM
OUT1
OUT2
FG
OUT1
OUT2
FG
0 < Hall < 5Hz
5Hz < Hall

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Timing chart (Lock protection)
2. VSP/ VMI Input Pin
Output starts when VSP pin at the voltage of more than VAD(L). And it turns off at the voltage of VAD(L) or less.
Minimum voltage of VSP pin is clipped by the voltage of VMI pin.
In case the minimum duty setting by VMI pin is not used, connect the VMI pin to the GND pin.
Analog voltage which is input to VSP pin and VMI pin is converted by AD convertor of 7 bit, and the output
PWM duty is controlled.
0
≤VSP, VMI ≤
VAD (L)
→
Duty = 0%
VAD (L)
< VSP, VMI ≤
VAD (H)
→
Below figure (17/127 to 116/127)
VAD (H)
< VSP, VMI ≤
VREG
→
Duty = 100% (117/127 to 127/127)
(PWM duty indicates the peak value of output because this circuit has a soft switching function.)
3. Hall Input Signal
Characteristics of hall signal shown below are inputted to the hall input pin.
Duty
Vsp
100%
0
V
AD(L) VAD(H)
Vsp
100%
0VMI
Duty
VAD(L) VAD(H)
HP
HM
ホール入力電圧範囲
V
REG
V
REG
-1.5V
GND
HP
HM
VH
V
HHYS-
V
HHYS+
V
H
: 40mV or more
V
HHYS+=10mV, VHHYS-=-10mV
*Though hall amplifier operates when V
His 40mV or
more, please widen the oscillation as possible to
stabilize the time width.
(200mV or more is recommended.)
Voltage range of hall input
HP-HM
FG
OUT2
OUT1 OFF (Hi-Z)
OFF (Hi-Z)
RDO
T
ON
T
OFF

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4. OSC Frequency and PWM Frequency
Oscillation frequency is approximated by below formula.
fOSC = 1/(2C[F]×ROSC[Ω]) [Hz]= 1/(2×2.08e-12[F]×ROSC[Ω]) [Hz]
Oscillation frequency fOSC is 10MHz(typ) when external resistor ROSC is 24kΩ
PWM frequency fPWM=fOSC/400.
5. PWM Output Drive
In PWM drive, upper power transistor is turned on and off repeatedly.
In switching phase, power transistor operates in below order.
6. Startup Sequence
Output starts when VSP pin at the voltage of VAD(L) or more. In order to ensure the starting torque, PWM
output is 50% duty when the motor rotating speed is lower than 5Hz (typ).
When output phase is switched during startup sequence, PWM OFF term of 1ms (typ) is inserted to reduce the
regenerating current to the power supply.
VM
R
F
M
RS
VM
R
F
M
RS
VM
R
F
M
RS
PWM ON
PWM ON
→
OFF
PWM ON
VM
R
F
M
RS
VM
R
F
M
RS
VM
R
F
M
RS
VM
R
F
M
RS
VM
R
F
M
RS
PWM ON
PWM OFF
PWM OFF
PWM ON
Short brake
200ns (Design target value)
0.55V
VSP
HP
HM
OFF
（Hi-Z)
OFF
（Hi-Z)
OUT1
OUT2
f<5Hz f>5Hz
50% Duty出力
1ms
VSP電圧によるDutyを出力
50% duty output
Duty is output by VSP voltage

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7. Turning Off
Output turns off when the voltage of VSP pin is VAD(L) or less.
Before all output power transistors are turned off, the time, until the edge of FG signal is detected twice or the
frequency of 5 Hz or less is detected, is defined PWM OFF term.
VSP
FG
OUT1
OUT2
0.5V
OFF
（Hi-
Z)
OFF
（Hi-Z)
OFF
（Hi-Z)
VSP
FG
OUT1
OUT2
0.5V
OFF
（Hi-Z)
OFF
（Hi-Z)
OFF
（Hi-Z)
Detecting
5Hz or less
0.55V
0.55V

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8. Soft Switching
Soft switching is performed by changing the output PWM duty gradually when conducting phase switches.
The time of soft switching is determined by the voltage of VSOFT pin and that of VOFF pin.
Tsoft > Toff Tsoft < Toff
Voltage of VSOFT > Voltage of VOFF:
Total term of soft switching (Tsoft) is determined by the time of prior hall signal (180°) and the voltage of
VSOFT pin. OFF term is provided during soft switching. The time of OFF term (Toff) is determined by the prior
hall signal (180°) and the voltage of VOFF pin. During OFF term, the state of the power transistor is in the PWM
OFF mode. Soft switching operates in the period other than the OFF term, and output PWM duty changes by 16
steps in maximum.
Voltage of VSOFT < Voltage of VOFF:
It does not have the term of soft switching operation which changes the duty, but it has the OFF term. OFF
term (Toff) is determined by the time of the prior hall signal (180°) and the voltage of VOFF pin. During OFF
term, the sate of the power transistor is in the PWM OFF mode.
When next edge does not occur though time of T1’ passes, last output state continues.
Conducting pattern is reset in synchronization with the up edge and the down edge of the hall signal.
So, waveform indicates non-contiguous every reset when hall signal is offset and in speed up/slow down mode.
HP-PM
OUT1
OUT2
T1
T1'
T
off
T
soft
T
off
T
soft
T
soft
①
②
③
⑭⑮⑯
④
T
off
T
soft
T
off
HP-PM
OUT1
OUT2
T1
T1'
T
off
T
soft
T
off
T
soft

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<Relation between the voltage of VSOFT pin and the term of soft switching>
VSOFT
＝
0V
→
0°
VSOFT
＝
VADC
→
87.2° (In case voltage of VADC or more is input, it is set to 87.2°.)
Step
VSOFT
(V)
Ter m
(°)
Step
VSOFT
(V)
Ter m
(°)
Step
VSOFT
(V)
Ter m
(°)
1 0.00 0.0 12 1.51 30.9 23 3.02 61.9
2 0.14 2.8 13 1.65 33.8 24 3.15 64.7
3 0.27 5.6 14 1.78 36.6 25 3.29 67.5
4 0.41 8.4 15 1.92 39.4 26 3.43 70.3
5 0.55 11.3 16 2.06 42.2 27 3.56 73.1
6 0.69 14.1 17 2.19 45.0 28 3.70 75.9
7 0.82 16.9 18 2.33 47.8 29 3.84 78.8
8 0.96 19.7 19 2.47 50.6 30 3.98 81.6
9 1.10 22.5 20 2.60 53.4 31 4.11 84.4
10 1.23 25.3 21 2.74 56.3 32 4.25 87.2
11 1.37 28.1 22 2.88 59.1
Term

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< Relation between the voltage of VOFF pin and the term of turning off>
VOFF
＝
0V
→
0°
VOFF
＝
VADC
→
87.2° (In case voltage of VADC or more is input, it is set to 87.2°)
Step
VOFF
(V)
Ter m
(°)
Step
VOFF
(V)
Ter m
(°)
Step
VOFF
(V)
Ter m
(°)
1 0.00 0.0 12 1.51 30.9 23 3.02 61.9
2 0.14 2.8 13 1.65 33.8 24 3.15 64.7
3 0.27 5.6 14 1.78 36.6 25 3.29 67.5
4 0.41 8.4 15 1.92 39.4 26 3.43 70.3
5 0.55 11.3 16 2.06 42.2 27 3.56 73.1
6 0.69 14.1 17 2.19 45.0 28 3.70 75.9
7 0.82 16.9 18 2.33 47.8 29 3.84 78.8
8 0.96 19.7 19 2.47 50.6 30 3.98 81.6
9 1.10 22.5 20 2.60 53.4 31 4.11 84.4
10 1.23 25.3 21 2.74 56.3 32 4.25 87.2
11 1.37 28.1 22 2.88 59.1
Term

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<PWM change during soft switching>
Soft switching after conducting phase switch:
It changes gradually from 4% to 100% of output PWM duty determined by the voltage of VSP pin. Its number
of steps is 16 in maximum.
Soft switching before conducting phase switch:
It changes gradually from 100% to 4% of output PWM duty determined by the voltage of VSP pin. Its number
of steps is 16 in maximum.
In case the term of soft switching operation is 22.5° or less, number of steps is less than16 in the soft switching
term.
The relation of steps of soft switching and the output PWM duty ratio is shown below.
Step Output ratio (%) Step Output ratio (%) Step Output ratio (%)
1 4 7 59 13 94
2 14 8 67 14 97
3 25 9 74 15 99
4 34 10 80 16 100
5 42 11 86
6 52 12 91
Output ratio
Steps of PWM change
Term of soft switching operation