TQ-Systems TQMa6x User manual

TQMa6x & TQMa6xP
User's Manual
TQMa6x & TQMa6xP UM 0403
19.09.2019

User's Manual l TQMa6x & TQMa6xP UM 0403 l © 2019, TQ-Systems GmbH Page i
TABLE OF CONTENTS
1. ABOUT THIS MANUAL ........................................................................................................................................................................1
1.1 Copyright and license expenses .....................................................................................................................................................1
1.2 Registered trademarks.......................................................................................................................................................................1
1.3 Disclaimer...............................................................................................................................................................................................1
1.4 Imprint.....................................................................................................................................................................................................1
1.5 Tips on safety ........................................................................................................................................................................................2
1.6 Symbols and typographic conventions........................................................................................................................................2
1.7 Handling and ESD tips........................................................................................................................................................................2
1.8 Naming of signals ................................................................................................................................................................................3
1.9 Further applicable documents / presumed knowledge..........................................................................................................3
2. BRIEF DESCRIPTION.............................................................................................................................................................................4
2.1 Key functions and characteristics ...................................................................................................................................................4
3. ELECTRONICS ........................................................................................................................................................................................4
3.1 System overview..................................................................................................................................................................................4
3.1.1 System architecture / block diagram.............................................................................................................................................4
3.1.2 Functionality .........................................................................................................................................................................................5
3.2 System components...........................................................................................................................................................................6
3.2.1 i.MX6........................................................................................................................................................................................................6
3.2.1.1 i.MX6 derivatives..................................................................................................................................................................................6
3.2.1.2 eFUSEs.....................................................................................................................................................................................................6
3.2.1.3 i.MX6 errata............................................................................................................................................................................................6
3.2.1.4 Boot modes............................................................................................................................................................................................7
3.2.1.5 Boot configuration ..............................................................................................................................................................................8
3.2.1.6 Boot interfaces......................................................................................................................................................................................9
3.2.1.7 Boot device eMMC ..............................................................................................................................................................................9
3.2.1.8 Boot device SPI NOR flash.............................................................................................................................................................. 10
3.2.1.9 Boot device SD card......................................................................................................................................................................... 11
3.2.2 Memory................................................................................................................................................................................................ 12
3.2.2.1 DDR3L SDRAM ................................................................................................................................................................................... 12
3.2.2.2 eMMC NAND flash............................................................................................................................................................................ 13
3.2.2.3 SPI NOR flash...................................................................................................................................................................................... 13
3.2.2.4 EEPROM ............................................................................................................................................................................................... 14
3.2.3 RTC......................................................................................................................................................................................................... 15
3.2.4 Temperature sensor......................................................................................................................................................................... 15
3.2.5 Interfaces............................................................................................................................................................................................. 16
3.2.5.1 Overview.............................................................................................................................................................................................. 16
3.2.5.2 AUDMUX.............................................................................................................................................................................................. 17
3.2.5.3 CCM....................................................................................................................................................................................................... 17
3.2.5.4 ECSPI..................................................................................................................................................................................................... 17
3.2.5.5 ENET...................................................................................................................................................................................................... 18
3.2.5.6 FLEXCAN.............................................................................................................................................................................................. 20
3.2.5.7 GPIO ...................................................................................................................................................................................................... 20
3.2.5.8 HDMI..................................................................................................................................................................................................... 21
3.2.5.9 I2C........................................................................................................................................................................................................... 21
3.2.5.10 I2C / ENET-Patch Variants................................................................................................................................................................ 22
3.2.5.11 IPU ......................................................................................................................................................................................................... 23
3.2.5.12 LDB ........................................................................................................................................................................................................ 24
3.2.5.13 MIPI_CSI............................................................................................................................................................................................... 25
3.2.5.14 MIPI_DSI............................................................................................................................................................................................... 25
3.2.5.15 MLB ....................................................................................................................................................................................................... 25
3.2.5.16 PCIe ....................................................................................................................................................................................................... 26
3.2.5.17 PWM...................................................................................................................................................................................................... 26
3.2.5.18 SATA...................................................................................................................................................................................................... 26
3.2.5.19 SJC ......................................................................................................................................................................................................... 27
3.2.5.20 S/PDIF................................................................................................................................................................................................... 27

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TABLE OF CONTENTS (continued)
3.2.5.21 Tamper................................................................................................................................................................................................. 27
3.2.5.22 UART ..................................................................................................................................................................................................... 28
3.2.5.23 USB ........................................................................................................................................................................................................ 29
3.2.5.24 uSDHC .................................................................................................................................................................................................. 29
3.2.5.25 Watchdog............................................................................................................................................................................................ 30
3.2.5.26 XTAL...................................................................................................................................................................................................... 30
3.2.6 Reset ..................................................................................................................................................................................................... 31
3.2.7 Power supply...................................................................................................................................................................................... 32
3.2.7.1 Overview TQMa6x power supply................................................................................................................................................. 32
3.2.7.2 Voltage monitoring VCC5V............................................................................................................................................................ 33
3.2.7.3 Power consumption TQMa6x ....................................................................................................................................................... 34
3.2.7.4 Power-Up sequence TQMa6x / carrier board........................................................................................................................... 35
3.3 TQMa6x interface.............................................................................................................................................................................. 35
3.3.1 Pin multiplexing................................................................................................................................................................................ 35
3.3.2 Pinout connector X1........................................................................................................................................................................ 36
3.3.3 Pinout connector X2........................................................................................................................................................................ 38
3.3.4 Pinout connector X3........................................................................................................................................................................ 40
3.3.5 Pinout differences connector X2, TQMa6x Rev. 02xx / Rev. 04xx ...................................................................................... 40
4. MECHANICS........................................................................................................................................................................................ 41
4.1 Connectors.......................................................................................................................................................................................... 41
4.2 Dimensions......................................................................................................................................................................................... 41
4.3 Component placement................................................................................................................................................................... 43
4.4 Adaptation to the environment................................................................................................................................................... 44
4.5 Protection against external effects.............................................................................................................................................. 44
4.6 Thermal management..................................................................................................................................................................... 44
4.7 Structural requirements.................................................................................................................................................................. 44
4.8 Notes of treatment........................................................................................................................................................................... 44
5. SOFTWARE .......................................................................................................................................................................................... 45
6. SAFETY REQUIREMENTS AND PROTECTIVE REGULATIONS.................................................................................................. 45
6.1 EMC ....................................................................................................................................................................................................... 45
6.2 ESD ........................................................................................................................................................................................................ 45
6.3 Operational safety and personal security.................................................................................................................................. 45
6.4 Climatic and operational conditions .......................................................................................................................................... 46
6.5 Shock and Vibration......................................................................................................................................................................... 47
6.6 Reliability and service life............................................................................................................................................................... 47
6.7 Environmental protection.............................................................................................................................................................. 48
6.7.1RoHS...................................................................................................................................................................................................... 48
6.7.2 WEEE®................................................................................................................................................................................................... 48
6.7.3 REACH®................................................................................................................................................................................................ 48
6.7.4 EuP......................................................................................................................................................................................................... 48
6.7.5 Battery.................................................................................................................................................................................................. 48
6.7.6 Packaging............................................................................................................................................................................................ 48
6.7.7 Other entries ...................................................................................................................................................................................... 48
7. APPENDIX............................................................................................................................................................................................ 49
7.1 Acronyms and definitions.............................................................................................................................................................. 49
7.2 References........................................................................................................................................................................................... 51

User's Manual l TQMa6x & TQMa6xP UM 0403 l © 2019, TQ-Systems GmbH Page iii
TABLE DIRECTORY
Table 1: Terms and Conventions .............................................................................................................................................................2
Table 2: Processor derivatives...................................................................................................................................................................6
Table 3: Boot modes and BT_FUSE_SEL ................................................................................................................................................7
Table 4: General boot settings..................................................................................................................................................................8
Table 5: Boot configuration eMMC at uSDHC3 ...................................................................................................................................9
Table 6: uSDHC3 eMMC modes................................................................................................................................................................9
Table 7: Boot configuration SPI NOR flash at eCSPI1...................................................................................................................... 10
Table 8: Boot configuration SD card at uSDHC2.............................................................................................................................. 11
Table 9: uSDHC2 SD card modes .......................................................................................................................................................... 11
Table 10: i.MX6 SDRAM interface according to i.MX6 derivative.................................................................................................. 12
Table 11: DDR3L SDRAM memory size options.................................................................................................................................. 12
Table 12: DDR3L SDRAM address range ............................................................................................................................................... 12
Table 13: SPI NOR flash assembly options............................................................................................................................................ 13
Table 14: EEPROM, component ............................................................................................................................................................... 14
Table 15: EEPROM, TQMa6x-specific data............................................................................................................................................ 14
Table 16: Current consumption RTC at pin LICELL ............................................................................................................................ 15
Table 17: Temperature sensor.................................................................................................................................................................. 15
Table 18: Internally used interfaces........................................................................................................................................................ 16
Table 19: Externally available interfaces ............................................................................................................................................... 16
Table 20: Signals AUD3 .............................................................................................................................................................................. 17
Table 21: Signals CCM................................................................................................................................................................................. 17
Table 22: Signals ECSPI1, ECSPI5 ............................................................................................................................................................. 17
Table 23: Signals RGMII .............................................................................................................................................................................. 18
Table 24: ENET-Patch variants.................................................................................................................................................................. 19
Table 25: Signals FLEXCAN........................................................................................................................................................................ 20
Table 26: Signals GPIO................................................................................................................................................................................ 20
Table 27: Signals HDMI............................................................................................................................................................................... 21
Table 28: Signals I2C..................................................................................................................................................................................... 21
Table 29: I2C address assignment............................................................................................................................................................ 21
Table 30: Signals DISP0 .............................................................................................................................................................................. 23
Table 31: Signals LVDS0, LVDS1............................................................................................................................................................... 24
Table 32: Signals MIPI_CSI......................................................................................................................................................................... 25
Table 33: Signals MIPI_DSI ........................................................................................................................................................................ 25
Table 34: Signals MLB ................................................................................................................................................................................. 25
Table 35: Signals PCIe ................................................................................................................................................................................. 26
Table 36: Signals PWM................................................................................................................................................................................ 26
Table 37: Signals SATA ............................................................................................................................................................................... 26
Table 38: JTAG modes ................................................................................................................................................................................ 27
Table 39: Signals JTAG................................................................................................................................................................................ 27
Table 40: Signals S/PDIF............................................................................................................................................................................. 27
Table 41:Signal TAMPER ........................................................................................................................................................................... 27
Table 42: Signals UARTs ............................................................................................................................................................................. 28
Table 43: Signals USB_H1 .......................................................................................................................................................................... 29
Table 44: Signals USB_OTG....................................................................................................................................................................... 29
Table 45: Signals uSDHC2.......................................................................................................................................................................... 29
Table 46:Signal WDOG .............................................................................................................................................................................. 30
Table 47: Signals XTAL................................................................................................................................................................................ 30
Table 48: Reset signals................................................................................................................................................................................ 31
Table 49: Power consumption TQMa6x................................................................................................................................................ 34

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TABLE DIRECTORY (continued)
Table 50: Pinout connector X1................................................................................................................................................................. 36
Table 51: Pinout connector X2................................................................................................................................................................. 38
Table 52: Pinout connector X3................................................................................................................................................................. 40
Table 53: Pinout differences TQMa6x revision 02xx and TQMa6x revision 04xx ..................................................................... 40
Table 54: TQMa6x, connectors................................................................................................................................................................. 41
Table 55: Carrier board mating connectors......................................................................................................................................... 41
Table 56: TQMa6x, heights ....................................................................................................................................................................... 41
Table 57: Labels on TQMa6x..................................................................................................................................................................... 43
Table 58: Climate and operational conditions extended temperature range –25 °C to +85 °C.......................................... 46
Table 59: Climate and operational conditions industrial temperature range –40 °C to +85 °C .......................................... 46
Table 60: Shock resistance ........................................................................................................................................................................ 47
Table 61: Vibration resistance.................................................................................................................................................................. 47
Table 62: Acronyms..................................................................................................................................................................................... 49
Table 63: Further applicable documents.............................................................................................................................................. 51
ILLUSTRATION DIRECTORY
Illustration 1: Block diagram TQMa6x...............................................................................................................................................................4
Illustration 2: Block diagram i.MX6....................................................................................................................................................................6
Illustration 3: Block diagram DDR3L SDRAM connection........................................................................................................................ 12
Illustration 4: Block diagram eMMC NAND flash connection................................................................................................................. 13
Illustration 5: Block diagram SPI NOR flash connection........................................................................................................................... 13
Illustration 6: Block diagram EEPROM interface......................................................................................................................................... 14
Illustration 7: Block diagram RTC .................................................................................................................................................................... 15
Illustration 8: Block diagram temperature sensor interface................................................................................................................... 15
Illustration 9: ENET-Patch Variant “A”............................................................................................................................................................ 22
Illustration 10: ENET-Patch Variant “B” ............................................................................................................................................................ 22
Illustration 11: ENET-Patch Variant “C” ............................................................................................................................................................ 22
Illustration 12: Block diagram UART interfaces............................................................................................................................................. 28
Illustration 13: Block diagram Reset ................................................................................................................................................................. 31
Illustration 14: Block diagram power supply ................................................................................................................................................. 32
Illustration 15: Block diagram PMIC signals ................................................................................................................................................... 32
Illustration 16: Block diagram VCC5V monitoring........................................................................................................................................ 33
Illustration 17: Block diagram power supply carrier board....................................................................................................................... 35
Illustration 18: TQMa6x dimensions, side view............................................................................................................................................. 41
Illustration 19: TQMa6x dimensions, top view.............................................................................................................................................. 42
Illustration 20: TQMa6x dimensions, top view
through
TQMa6x........................................................................................................... 42
Illustration 21: TQMa6x, component placement top.................................................................................................................................. 43
Illustration 22: TQMa6x, component placement bottom.......................................................................................................................... 43

User's Manual l TQMa6x & TQMa6xP UM 0403 l © 2019, TQ-Systems GmbH Page v
REVISION HISTORY
Rev. Date Name Pos. Modification
0203 10.02.2018 Petz Initial document
0400 19.04.2018 Petz All Complete rework, DualPlus and QuadPlus CPUs added
0401 21.10.2018 Petz
All
Table 10
3.2.7.4
3.2.5.23, 6.5, Illustration 22
Table 58, Table 59
Formatting, links updated,
Clocks corrected
Warning updated
Updated
“Package temperature” replaced with “Case temperature”
Case temperature DDR3L SDRAM changed to +95 °C
0402 29.04.2019 Petz 6.5 Added
0403 19.09.2019 Petz
1.9
Table 4
Footnote 4
Footnote 5
3.3.5
Table 53
Link to Yocto added
CPU derivate-dependent BOOT_CFG3[1:0] settings added
Updated
Added
Chapter headline added
“X2-“ in column “Pin” added

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1.
ABOUT THIS MANUAL
1.1
Copyright and license expenses
Copyright protected © 2019 by TQ-Systems GmbH.
This User's Manual may not be copied, reproduced, translated, changed or distributed, completely or partially in electronic,
machine readable, or in any other form without the written consent of TQ-Systems GmbH.
The drivers and utilities for the components used as well as the BIOS are subject to the copyrights of the respective
manufacturers. The licence conditions of the respective manufacturer are to be adhered to.
Bootloader-licence expenses are paid by TQ-Systems GmbH and are included in the price.
Licence expenses for the operating system and applications are not taken into consideration and must be calculated / declared
separately.
1.2
Registered trademarks
TQ-Systems GmbH aims to adhere to copyrights of all graphics and texts used in all publications, and strives to use original
or license-free graphics and texts.
All brand names and trademarks mentioned in this User's Manual, including those protected by a third party, unless specified
otherwise in writing, are subjected to the specifications of the current copyright laws and the proprietary laws of the present
registered proprietor without any limitation. One should conclude that brand and trademarks are rightly protected by a third
party.
1.3
Disclaimer
TQ-Systems GmbH does not guarantee that the information in this User's Manual is up-to-date, correct, complete or of good
quality. Nor does TQ-Systems GmbH assume guarantee for further usage of the information. Liability claims against TQ-Systems
GmbH, referring to material or non-material related damages caused, due to usage or non-usage of the information given in this
User's Manual, or due to usage of erroneous or incomplete information, are exempted, as long as there is no proven intentional
or negligent fault of TQ-Systems GmbH.
TQ-Systems GmbH explicitly reserves the rights to change or add to the contents of this User's Manual or parts of it without
special notification.
Important Notice:
Before using the Starterkit MBa6x or parts of the schematics of the MBa6x, you must evaluate it and determine if it is suitable for
your intended application. You assume all risks and liability associated with such use. TQ-Systems GmbH makes no other
warranties including, but not limited to, any implied warranty of merchantability or fitness for a particular purpose. Except where
prohibited by law, TQ-Systems GmbH will not be liable for any indirect, special, incidental or consequential loss or damage
arising from the usage of the Starterkit MBa6x or schematics used, regardless of the legal theory asserted.
1.4
Imprint
TQ-Systems GmbH
Gut Delling, Mühlstraße 2
D-82229 Seefeld
Tel: +49 8153 9308–0
Fax: +49 8153 9308–4223
E-Mail: Info@TQ-Group
Web: TQ-Group

User's Manual l TQMa6x & TQMa6xP UM 0403 l © 2019, TQ-Systems GmbH Page 2
1.5
Tips on safety
Improper or incorrect handling of the product can substantially reduce its life span.
1.6
Symbols and typographic conventions
Table 1: Terms and Conventions
Symbol Meaning
This symbol represents the handling of electrostatic-sensitive modules and / or components. These
components are often damaged / destroyed by the transmission of a voltage higher than about 50 V.
A human body usually only experiences electrostatic discharges above approximately 3,000 V.
This symbol indicates the possible use of voltages higher than 24 V.
Please note the relevant statutory regulations in this regard.
Non-compliance with these regulations can lead to serious damage to your health and may damage
or destroy the component.
This symbol indicates a possible source of danger.
Ignoring the instructions described can cause health damage, or damage the hardware.
This symbol represents important details or aspects for working with TQ-products.
Command
A font with fixed-width is used to denote commands, contents, file names, or menu items.
1.7
Handling and ESD tips
General handling of your TQ-products
The TQ-product may only be used and serviced by certified personnel who have taken note of the
information, the safety regulations in this document and all related rules and regulations.
A general rule is not to touch the TQ-product during operation. This is especially important when
switching on, changing jumper settings or connecting other devices without ensuring beforehand
that the power supply of the system has been switched off.
Violation of this guideline may result in damage / destruction of the TQMa6x and be dangerous
to your health.
Improper handling of your TQ-product would render the guarantee invalid.
Proper ESD handling
The electronic components of your TQ-product are sensitive to electrostatic discharge (ESD).
Always wear antistatic clothing, use ESD-safe tools, packing materials etc., and operate your TQ-
product in an ESD-safe environment. Especially when you switch modules on, change jumper settings,
or connect other devices.

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1.8
Naming of signals
A hash mark (#) at the end of the signal name indicates a low-active signal.
Example: RESET#
If a signal can switch between two functions and if this is noted in the name of the signal, the low-active function is marked with
a hash mark and shown at the end.
Example: C / D#
If a signal has multiple functions, the individual functions are separated by slashes when they are important for the wiring.
The identification of the individual functions follows the above conventions.
Example: WE2# / OE#
1.9
Further applicable documents / presumed knowledge
•
Specifications and manual of the modules used:
These documents describe the service, functionality and special characteristics of the module used (incl. BIOS).
•
Specifications of the components used:
The manufacturer's specifications of the components used, for example CompactFlash cards, are to be taken note of.
They contain, if applicable, additional information that must be taken note of for safe and reliable operation.
These documents are stored at TQ-Systems GmbH.
•
Chip errata:
It is the user's responsibility to make sure all errata published by the manufacturer of each component are taken note of.
The manufacturer’s advice should be followed.
•
Software behaviour:
No warranty can be given, nor responsibility taken for any unexpected software behaviour due to deficient components.
•
General expertise:
Expertise in electrical engineering / computer engineering is required for the installation and the use of the device.
The following documents are required to fully comprehend the following contents:
•MBa6x circuit diagram
•MBa6x User's Manual
•i.MX6 Data Sheets
•i.MX6 Reference Manuals
•U-Boot documentation: www.denx.de/wiki/U-Boot/Documentation
•PTXdist documentation: www.ptxdist.de
•Yocto documentation: support.tq-group.com/en/arm/tqma6x/yocto/meta-tq_qs
•TQ-Support Wiki: support.tq-group.com/doku.php?id=en:arm:tqma6x

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2.
BRIEF DESCRIPTION
This User's Manual describes the hardware of the TQMa6x revision 04xx, and refers to some software settings.
A certain derivative of the TQMa6x does not necessarily provide all features described in this User's Manual.
Functional differences between Dual/Quad and DualPlus/QuadPlus are referred to in the relevant passages.
This User's Manual does also not replace the NXP i.MX6 Reference Manuals (4), (5), and (6).
The TQMa6x is a universal Minimodule based on the NXP ARM CPU MCIMX6 (i.MX6).
The Cortex™ A9 core of this i.MX6 is typically clocked with 800 MHz.
The TQMa6x extends the TQC product range and offers an outstanding computing performance.
A suitable i.MX6 derivative (Single, Dual, Quad core) can be chosen for each requirement.
2.1
Key functions and characteristics
The TQMa6x provides the following key functions and characteristics:
•NXP i.MX6 (Solo, DualLite, Dual, Quad, DualPlus, QuadPlus)
•Up to 2 Gbyte DDR3L SDRAM, 64 bit interface (except “Solo”: 32 bit interface)
•Up to 8 Gbyte eMMC NAND flash
•Up to 128 Mbyte SPI NOR flash 1
•64 kbit EEPROM
•Temperature sensor
•NXP PMIC (Power Management Integrated Circuit)
•Extended temperature range
•Single 5 V power supply
•Hardware is backward compatible with TQMa6x revision 02xx
All essential i.MX6 pins are routed to the connectors.
There are therefore no restrictions for customers using the TQMa6x with respect to an integrated customised design.
3.
ELECTRONICS
The information provided in this User's Manual is only valid in connection with the tailored boot loader,
which is preinstalled on the TQMa6x, and the BSP provided by TQ-Systems GmbH, see also chapter 5.
3.1
System overview
3.1.1 System architecture / block diagram
i.MX6x
DDR3L SDRAM
Connector 160 pins
eMMC
EEPROM
Temperature
sensor
PMIC
PF0100
DC/DC 4V2
Connector 160 pins
5V
SPI NOR flash
Connector
40 pins Supervisor
Illustration 1: Block diagram TQMa6x
1: It is not possible to boot from an SPI NOR flash bigger than 16 Mbyte.

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3.1.2 Functionality
The following key functions are implemented on the TQMa6x:
•i.MX6 CPU
•DDR3L SDRAM
•eMMC NAND flash
•SPI NOR flash
•EEPROM
•Temperature sensor
•Supervisor
•PMIC / DC/DC converter
The following interfaces are provided at the connectors of the TQMa6x: 2
•1 × Ethernet 10/100/1000 RGMII
•1 × HDMI 1.4
•1 × I2S
•1 × JTAG
•1 × MIPI CSI
•1 × MIPI DSI
•1 × MLB
•1 × Parallel display RGB 24 bit
•1 × PCIe 2.0 (1 Lane)
•1 × SATA 3.0
•1 × SD 8 Bit (SDIO / MMC / SD card)
•1 × S/PDIF
•2 × CAN
•2 × General Purpose Clocks
•2 × I2C
•2 × LVDS display
•2 × SPI
•2 × USB 2.0 Hi-Speed (1 × USB Host, 1 × USB-OTG)
•40 × GPIO
•4 × PWM
•4 × UART (with Handshake)
Further interfaces of the i.MX6 are also available as an alternative to the mentioned factory configuration,
by adapting the pin configuration. These are amongst other:
•Camera Sensor Interfaces
•EIM bus
•Enhanced Periodic Interrupt Timer EPIT
•Enhanced Serial Audio Interface ESAI
•Ethernet 10/100 RMII
•General Purpose Media Interface GPMI
•General Purpose Timer GPT
•Keypad port
•MIPI HSI Host Controller
•More audio interfaces
•More I2C interfaces
•More SPI interfaces
•More UARTs
•One additional parallel display
2: Quantity of interfaces depends on the i.MX6 derivative.

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3.2
System components
3.2.1 i.MX6
The following block diagram shows the main features of the i.MX6 processor family.
Illustration 2: Block diagram i.MX6
(Source: NXP)
3.2.1.1 i.MX6 derivatives
Depending on the TQMa6x derivative, one of the following i.MX6 derivatives is assembled:
Table 2: Processor derivatives
Description Clock CPU Die temperature range TQ-BSP
i.MX6S Solo Industrial 800 MHz –40 °C to +105 °C Yes
i.MX6U DualLite Industrial 800 MHz –40 °C to +105 °C Yes
i.MX6D Dual Industrial 800 MHz –40 °C to +105 °C Yes
i.MX6Q Quad Industrial 800 MHz –40 °C to +105 °C Yes
i.MX6DP DualPlus Industrial 800 MHz –40 °C to +105 °C Yes
i.MX6QP QuadPlus Industrial 800 MHz –40 °C to +105 °C Yes
3.2.1.2 eFUSEs
The eFUSEs in the i.MX6 are available for the user, except for the MAC address eFUSEs.
TQMa6x modules are delivered pre-programmed with MAC addresses from the TQ-Systems MAC address pool.
The MAC addresses are burned in the designated OCOTP eFUSEs (bank 4, word 2, 3).
The MAC address LOCK-FUSE WP (Write Protect) is burnt, which permits to temporarily overwrite the MAC address for test
purposes. If this is not desired, the MAC address LOCK-FUSE OP (Overwrite Protect) can be burned by the user.
3.2.1.3 i.MX6 errata
Attention: Malfunction
Please take note of the current i.MX6 errata (7), (8).

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3.2.1.4 Boot modes
The i.MX6 contains a ROM with integrated boot loader.
After power-up, the boot code initializes the hardware and then loads the program image from the selected boot device.
The eMMC or the SPI NOR flash integrated on the TQMa6x can for example be selected as the standard boot device.
More boot interfaces are available as an alternative to booting from the integrated eMMC or the SPI NOR flash, see 3.2.1.6.
More information about boot interfaces and its configuration is to be taken from the i.MX6 data sheets (1), (2), and (3) as well as
the i.MX6 Reference Manuals (4), (5), and (6).
The boot device and its configuration, as well as different i.MX6 settings have to be set via different boot mode registers.
Therefore, the i.MX6 provides two possibilities:
•Burning internal eFuses
•Reading dedicated GPIO pins
The exact behaviour during booting depends on the value of the register BT_FUSE_SEL.
The following table shows the behaviour of the bit BT_FUSE_SEL in dependence of the selected boot mode.
Table 3: Boot modes and BT_FUSE_SEL
BOOT_MODE[1:0] Boot type
BT_FUSE_SEL
Usage
00 (default) Boot from eFuses BT_FUSE_SEL = 0: Boot using Serial Loader (default)
BT_FUSE_SEL
= 1: Boot configuration is taken from eFuses Series
01 Serial Downloader n/a Development
/ production
10 Internal Boot BT_FUSE_SEL = 0: Boot configuration is taken from BOOT_CFG pins (default)
BT_FUSE_SEL
= 1: Boot configuration is taken from eFuses Development
11 Reserved n/a n/a
Attention: Malfunction
Burning an eFuse is irreversible!
TQ-Systems GmbH takes no responsibility for the correct operation of the TQMa6x,
if the user burns eFuses.
Attention: Boot configuration
It is recommended to implement a redundant update concept for field software updates
during the carrier board design.

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3.2.1.5 Boot configuration
Note: Boot configuration
No boot device is preset when the TQMa6x is delivered.
Some general settings are defined by eFuses independent from the boot device.
Table 4: General boot settings
i.MX6 TQMa6x
eFuse Option Setting 3Signal Pin
BOOT_CFG1[7:0]
Boot configuration 1:
Specific to selected boot mode – BOOT_CFG1_7:0 –
BOOT_CFG2[7:0]
Boot configuration 2:
Specific to selected boot mode – BOOT_CFG2_7:0 –
BOOT_CFG3[7]
L1 I-Cache DISABLE:
0 = Enabled
1 = Disabled
0 BOOT_CFG3_7 X2-97
BOOT_CFG3[6]
BT_MMU_DISABLE:
0 = MMU / L1 D Cache / PL310 enabled
1 = MMU / L1 D Cache / PL310 disabled
0 BOOT_CFG3_6 X2-98
BOOT_CFG3[5]
DDR Memory Map Config:
00 = Single DDR channel
01 = 2 × 32 Map
10 = 4 KB interleaving
11 = Reserved (Solo / DualLite / Dual / Quad)
11 = Extension Mode (DualPlus / QuadPlus)
(see BOOT_CFG3[1:0])
0 BOOT_CFG3_5 X2-99
BOOT_CFG3[4] 0 BOOT_CFG3_4 X2-100
BOOT_CFG3[3] Reserved 0 BOOT_CFG3_3 X2-101
BOOT_CFG3[2]
Boot Frequencies ARM / DDR / AXI:
Solo / DualLite:
0 = 792 / 396 / 264 MHz
1 = 396 / 352 / 176 MHz
Dual / Quad / DualPlus / QuadPlus:
0 = 792 / 528 / 264 MHz
1 = 396 / 352 / 176 MHz
0 BOOT_CFG3_2 X2-102
BOOT_CFG3[1]
DDR Memory Map Extension Config:
4
Quad-Plus/Dual-Plus:
00 = Single DDR Channel / NOC disabled / MMDC reorder enabled
01 = Fixed 2x32 mapping / NOC enabled / MMDC reorder disabled
10 = Reserved
11 = Reserved
Quad/Dual:
Reserved
DualLite/Solo:
Disable SDMMC Manufacture mode: 5
x0 = Enable
x1 = Disable
0 BOOT_CFG3_1 X2-103
BOOT_CFG3[0] 0 BOOT_CFG3_0 X2-104
BOOT_CFG4[7]
Debug loop:
0 = Loop disabled
1 = Loop enabled
0 BOOT_CFG4_7 X2-85
BOOT_CFG4[6:0]
Boot configuration 4:
Specific to selected boot mode – BOOT_CFG4_6:0 –
3: Voltage level or condition of eFuse.
4: Only valid when BOOT_CFG3[5:4] = 0b11.
5: BOOT_CFG3[1] = Reserved

User's Manual l TQMa6x & TQMa6xP UM 0403 l © 2019, TQ-Systems GmbH Page 9
3.2.1.6 Boot interfaces
In the next chapters, the configuration of the following boot devices is described:
•eMMC
•SPI NOR flash 6
•SD card
3.2.1.7 Boot device eMMC
Table 5: Boot configuration eMMC at uSDHC3
i.MX6 TQMa6x
eFuse Option Setting 7Signal Pin
BOOT_CFG1[7]
Boot Device Selection:
01 = Boot from uSDHC Interfaces
0 BOOT_CFG1_7 X2-115
BOOT_CFG1[6] 1 BOOT_CFG1_6 X2-116
BOOT_CFG1[5]
SD / MMC-Selection:
0 = SD / eSD / SDXC
1 = MMC / eMMC
1 BOOT_CFG1_5 X2-117
BOOT_CFG1[4]
Fast Boot Support:
0 = Regular
1 = Fast Boot
0 BOOT_CFG1_4 X2-118
BOOT_CFG1[3]
MMC Speed Mode:
0x = High Speed Mode
1x = Normal Speed Mode
0 BOOT_CFG1_3 X2-119
BOOT_CFG1[2] 0 BOOT_CFG1_2 X2-120
BOOT_CFG1[1]
eMMC Reset Enable:
0 = eMMC-Reset disabled
1 = eMMC-Reset enabled
1 BOOT_CFG1_1 X2-121
BOOT_CFG2[7]
eMMC Bus Width:
000 = 1 bit
001 = 4 bit
010 = 8 bit
101 = 4 bit DDR (MMC 4.4)
110 = 8 bit DDR (MMC 4.4)
0 BOOT_CFG2_7 X2-107
BOOT_CFG2[6] 1 BOOT_CFG2_6 X2-108
BOOT_CFG2[5] 0 BOOT_CFG2_5 X2-109
BOOT_CFG2[4]
Port Select:
00 = uSDHC1
01 = uSDHC2
10 = uSDHC3
11 = uSDHC4
1 BOOT_CFG2_4 X2-110
BOOT_CFG2[3] 0 BOOT_CFG2_3 X2-111
BOOT_CFG2[2]
DLL Override:
0 = Boot ROM
1 = Apply value per eFuse field MMC_DLL_DLY[6:0]
0 BOOT_CFG2_2 X2-112
BOOT_CFG2[1]
Boot Acknowledge:
0 = Boot Acknowledge enable
1 = Boot Acknowledge disable
0 BOOT_CFG2_1 X2-113
BOOT_CFG2[0]
Override Pad Settings:
0 = default values
1 = Use PAD_SETTINGS values
0 BOOT_CFG2_0 X2-114
In addition to the mode listed above the following eMMC modes are supported at port uSDHC3.
Table 6: uSDHC3 eMMC modes
eMMC mode 1 Bit 4 Bit 8 Bit Fast Boot DDR
Normal Speed – 8– 8
High Speed – 8– 8
6: It is not possible to boot from an SPI NOR flash bigger than 16 Mbyte.
7: Voltage level or condition of eFuse.
8: Not yet supported by software.

User's Manual l TQMa6x & TQMa6xP UM 0403 l © 2019, TQ-Systems GmbH Page 10
3.2.1.8 Boot device SPI NOR flash
Table 7: Boot configuration SPI NOR flash at eCSPI1
i.MX6 TQMa6x
eFuse Option Setting 9Signal Pin
BOOT_CFG1[7]
Boot Device Selection:
0011 = Boot from Serial ROM
0 BOOT_CFG1_7 X2-115
BOOT_CFG1[6] 0 BOOT_CFG1_6 X2-116
BOOT_CFG1[5] 1 BOOT_CFG1_5 X2-117
BOOT_CFG1[4] 1 BOOT_CFG1_4 X2-118
BOOT_CFG4[6]
EEPROM Recovery:
10
0 = disabled
1 = enabled
0 BOOT_CFG4_6 X2-86
BOOT_CFG4[5]
CS select (SPI only):
00 = CS#0
01 = CS#1
10 = CS#2
11 = CS#3
0 BOOT_CFG4_5 X2-89
BOOT_CFG4[4] 1 BOOT_CFG4_4 X2-90
BOOT_CFG4[3]
SPI Addressing (SPI only)
0 = 2-bytes (16-bit) (3.75 MHz Clock)
1 = 3 Bytes (24-bit) (15 MHz Clock)
1 BOOT_CFG4_3 X2-91
BOOT_CFG4[2]
Port Select:
000 = ECSPI-1
001 = ECSPI-2
010 = ECSPI-3
001 = ECSPI-4
100 = ECSPI-5
101 = I2C-1
110 = I2C-2
111 = I2C-3
0 BOOT_CFG4_2 X2-92
BOOT_CFG4[1] 0 BOOT_CFG4_1 X2-93
BOOT_CFG4[0] 0 BOOT_CFG4_0 X2-96
Note: SPI NOR flash size
It is not possible to boot from an SPI NOR flash bigger than 16 Mbyte.
9: Voltage level or condition of eFuse.
10: The i.MX6 supports recovery devices. If this bit is set, the SPI NOR flash serves as recovery boot device.

User's Manual l TQMa6x & TQMa6xP UM 0403 l © 2019, TQ-Systems GmbH Page 11
3.2.1.9 Boot device SD card
Table 8: Boot configuration SD card at uSDHC2
i.MX6 TQMa6x
eFuse Option Setting 11 Signal Pin
BOOT_CFG1[7]
Boot Device Selection:
01 = Boot from uSDHC Interfaces
0 BOOT_CFG1_7 X2-115
BOOT_CFG1[6] 1 BOOT_CFG1_6 X2-116
BOOT_CFG1[5]
SD / MMC-Selection:
0 = SD / eSD / SDXC
1 = MMC / eMMC
0 BOOT_CFG1_5 X2-117
BOOT_CFG1[4]
Fast Boot:
0 = Regular
1 = Fast Boot
1 BOOT_CFG1_4 X2-118
BOOT_CFG1[3]
SD Speed Mode:
00 = Normal / SDR12
01 = High / SDR25
10 = SDR50 (on uSDHC3 and uSDHC4 only)
11 = SDR104 (on uSDHC3 and uSDHC4 only)
0 BOOT_CFG1_3 X2-119
BOOT_CFG1[2] 0 BOOT_CFG1_2 X2-120
BOOT_CFG1[1]
SD Power Cycle Enable:
0 = No Power Cycle
1 = Power cycle enabled via SD_RST pad (on uSDHC3 and uSDHC4 only)
0 BOOT_CFG1_1 X2-121
BOOT_CFG1[0]
SD Loopback Clock Source Sel (for SDR50 and SDR104 only)
0 = through SD pad
1 = direct
0 BOOT_CFG1_0 X2-122
BOOT_CFG2[7]
SD Calibration Step:
00 = 1 delay cell
01 = 1 delay cell
10 = 2 delay cell
11 = 3 delay cell
0 BOOT_CFG2_7 X2-107
BOOT_CFG2[6] 0 BOOT_CFG2_6 X2-108
BOOT_CFG2[5]
Bus Width:
0 = 1 bit
1 = 4 bit
1 BOOT_CFG2_5 X2-109
BOOT_CFG2[4]
Port:
00 = uSDHC1
01 = uSDHC2
10 = uSDHC3
11 = uSDHC4
0 BOOT_CFG2_4 X2-110
BOOT_CFG2[3] 1 BOOT_CFG2_3 X2-111
BOOT_CFG2[1]
Pull-Down during SD Power Cycle:
0 = Use default SD pad settings during power cycle
1 = Set pull-down on SD pads during power cycle
(only used if "SD Power Cycle Enable" enabled)
0 BOOT_CFG2_1 X2-113
BOOT_CFG2[0]
Override Pad Settings:
0 = Use default values
1 = Use PAD_SETTINGS values
0 BOOT_CFG2_0 X2-114
In addition to the mode listed above the following SD card modes are supported at port uSDHC2:
Table 9: uSDHC2 SD card modes
SD mode 1 Bit 4 Bit Fast Boot
SDR12
SDR25
SDR50 – – –
SDR104 – – –
11: Voltage level or condition of eFuse.

User's Manual l TQMa6x & TQMa6xP UM 0403 l © 2019, TQ-Systems GmbH Page 12
3.2.2 Memory
3.2.2.1 DDR3L SDRAM
Depending on the i.MX6 derivative either two or four DDR3L SDRAM chips are assembled on the TQMa6x.
All chips have one common chip select. The chips are connected to the i.MX6 with a 64-bit bus.
(Exception: The i.MX6 “Solo” is connected with a 32-bit bus.)
The following block diagram shows how the DDR3L SDRAM is connected to the i.MX6.
i.MX6 DDR3L#1 Top DDR3L#2 Top
DDR3L#1 Bot
A[15:0]
D[15:0]
D[31:16]
CS0#
CTRL
DDR3L#2 Bot
CLK1
D[47:32]
D[63:48]
CLK0
DQM[M;S][3:0]
DQM[M;S][7:4]
Illustration 3: Block diagram DDR3L SDRAM connection
The characteristics of the memory interface depend on the i.MX6 derivative.
The following table shows the different possibilities.
Table 10: i.MX6 SDRAM interface according to i.MX6 derivative
i.MX6 derivative Bus width Clock SDRAM chips TQ-BSP
i.MX6 Solo × 32 396 MHz 2 Yes
i.MX6 DualLite × 64 396 MHz 4 Yes
i.MX6 Dual × 64 528 MHz 4 Yes
i.MX6 DualPlus × 64 528 MHz 4 Yes
i.MX6 Quad × 64 528 MHz 4 Yes
i.MX6 QuadPlus × 64 528 MHz 4 Yes
The assembly options of DDR3L SDRAM on the TQMa6x are listed in the following table.
Table 11: DDR3L SDRAM memory size options
Assembly option Size
2 × DDR3L 128M16 / ×32 512 Mbyte
2 × DDR3L 256M16 / ×32 1 Gbyte
4 × DDR3L 128M16 / ×64 1 Gbyte
4 × DDR3L 256M16 / ×64 2 Gbyte
The following address range is reserved for the DDR controller in
mode X32 / X64 fixed
:
Table 12: DDR3L SDRAM address range
Start address Size Chip Select Remark
0x1000_0000
0xFFFF_FFFF
CS0# 3840 Mbyte

User's Manual l TQMa6x & TQMa6xP UM 0403 l © 2019, TQ-Systems GmbH Page 13
3.2.2.2 eMMC NAND flash
Attention: Malfunction or destruction
Some Micron eMMC have a too high drive-strength. This can lead to poor signal integrity and a life time
reduction of the i.MX6. When using an own bootloader or operating system it is essential to implement
the SET_DSR routine, which is part of the BSP as of revision 0102.
The SET_DSR routine as of BSP revision 0102
must not
be implemented for TQMa6x as of revision
04xx
!
An eMMC NAND flash for the boot loader and the application software is assembled. The Hardware Reset function depends on
the BSP implementation. The following block diagram shows how the eMMC flash is connected to the i.MX6.
i.MX6eMMC
SD3_CLK
SD3_CMD
CLK
CMD
SD3_DATA[7:0] DAT[7:0]
RESET#
SD3_RESET
Illustration 4: Block diagram eMMC NAND flash connection
3.2.2.3 SPI NOR flash
An SPI NOR flash is also available. It can e.g., serve as boot device or as recovery device.
The following block diagram shows how the SPI NOR flash is connected to the i.MX6.
i.MX6 SPI NOR flash
ECSPI1_SCK
ECSPI1_SS1#
C
S#
ECSPI1_MOSI DQ0
DQ1
ECSPI1_MISO
W#
Connector X3-40
SPI-NOR_WP#
10 kΩ
VCC3V3
Illustration 5: Block diagram SPI NOR flash connection
The write protection pin of the SPI NOR flash is available at connector X3-40.
The reset pin is not connected by default. A reset can only be carried out via a complete power cycle of the TQMa6x.
The SPI NOR flash can be reset by one or more of the following sources (assembly option).
•WDOG1# (see 3.2.5.25)
•MX6_POR# (see 3.2.6)
•GPIO2_IO01 (see 3.2.5.7)
The SPI NOR flashes, which can be assembled on the TQMa6x, are listed in the following table.
Table 13: SPI NOR flash assembly options
Manufacturer Size Temperature range
Micron
16 Mbyte 12
–40 °C to +85 °C
Micron
32 Mbyte 13
–40 °C to +85 °C
Micron
64 Mbyte 13
–40 °C to +85 °C
Micron
128 Mbyte 13
–40 °C to +85 °C
Attention: Malfunction in SPI-mode
During the boot process, the i.MX6 only supports the 3-byte mode.
Special hardware mechanisms are required for 4-byte mode operation
else erroneous reboots might occur.
12: Maximum size of SPI NOR flash to boot from.
13: Qualification pending.

User's Manual l TQMa6x & TQMa6xP UM 0403 l © 2019, TQ-Systems GmbH Page 14
3.2.2.4 EEPROM
A serial EEPROM is available for permanent storage of e.g. TQMa6x characteristics or customers parameters.
Depending on the TQMa6x version, the I2C1 or the I2C3 bus of the i.MX6 controls the EEPROM, see also 3.2.5.9.
Write-Protection (WP) is not supported.
The following block diagram shows how the EEPROM is connected to the i.MX6.
i.MX6 EEPROM
I2C[1/3]_SCL
I2C[1/3]_SDA
SCL
SDA
Illustration 6: Block diagram EEPROM interface
The following table shows the EEPROM used.
Table 14: EEPROM, component
Manufacturer Part number Size Temperature range
STM M24C64-WDW6TP 64 kbit –45 °C to +85 °C
The I2C address of the EEPROM is 0x50 / 101 0000b
In the EEPROM, TQMa6x-specific data is stored. It is, however, not essential for the correct operation of the TQMa6x.
The user can delete or alter the data.
In the following table, the parameters stored in the EEPROM are shown.
Table 15: EEPROM, TQMa6x-specific data
Offset Payload (byte) Padding (byte) Size (byte) Type Remark
0x00
Variable Variable 32(10)Binary Hard Reset Configuration Word (HRCW), (optional)
0x20
6(10)10(10)16(10)Binary MAC address
0x30
8(10)8(10)16(10)ASCII Serial number
0x40
Variable Variable 64(10)ASCII Order code
0x80
– – 8064(10)– (Unused)
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