TQ TQMa8MxML User manual

TQMa8MxML & TQMa8MxNL
User's Manual
TQMa8MxML UM 0103
04.07.2022

User's Manual l TQMa8MxML UM 0103 l © 2022, TQ-Systems GmbH Page I
TABLE OF CONTENTS
1. ABOUT THIS MANUAL......................................................................................................................................................................................1
1.1 Copyright and license expenses..................................................................................................................................................................1
1.2 Registered trademarks ....................................................................................................................................................................................1
1.3 Disclaimer ............................................................................................................................................................................................................1
1.4 Imprint...................................................................................................................................................................................................................1
1.5 Tips on safety......................................................................................................................................................................................................2
1.6 Symbols and typographic conventions....................................................................................................................................................2
1.7 Handling and ESD tips.....................................................................................................................................................................................2
1.8 Naming of signals..............................................................................................................................................................................................3
1.9 Further applicable documents / presumed knowledge.....................................................................................................................3
2. BRIEF DESCRIPTION ..........................................................................................................................................................................................4
2.1 Key functions and characteristics................................................................................................................................................................4
2.2 CPU block diagrams .........................................................................................................................................................................................5
3. ELECTRONICS......................................................................................................................................................................................................6
3.1 Interfaces to other systems and devices...................................................................................................................................................6
3.1.1 Pin multiplexing ................................................................................................................................................................................................6
3.1.1.1 Pinout TQMa8MxML ........................................................................................................................................................................................7
3.1.1.2 TQMa8MxML signals........................................................................................................................................................................................8
3.1.1.3 Pinout TQMa8MxNL ......................................................................................................................................................................................13
3.1.1.4 TQMa8MxNL signals......................................................................................................................................................................................14
3.1.1.5 Differences between TQMa8MxML and TQMa8MxNL .....................................................................................................................18
3.2 System components .....................................................................................................................................................................................19
3.2.1 i.MX 8M Mini and i.MX 8M Nano derivatives........................................................................................................................................19
3.2.1.1 i.MX 8M Mini derivatives..............................................................................................................................................................................19
3.2.1.2 i.MX 8M Nano derivatives............................................................................................................................................................................19
3.2.1.3 i.MX 8M Mini / i.MX 8M Nano, main differences .................................................................................................................................19
3.2.1.4 i.MX 8M Mini errata........................................................................................................................................................................................19
3.2.1.5 Boot Modes ......................................................................................................................................................................................................20
3.2.1.6 Boot configuration i.MX 8M Mini .............................................................................................................................................................20
3.2.1.6.1 Boot device eMMC.........................................................................................................................................................................................21
3.2.1.6.2 Boot device SD card ......................................................................................................................................................................................22
3.2.1.6.3 Boot device QSPI NOR..................................................................................................................................................................................22
3.2.1.7 Boot configuration i.MX 8M Nano ...........................................................................................................................................................23
3.2.2 Memory..............................................................................................................................................................................................................23
3.2.2.1 LPDDR4 SDRAM..............................................................................................................................................................................................23
3.2.2.2 eMMC NAND Flash.........................................................................................................................................................................................23
3.2.2.3 QSPI NOR Flash ...............................................................................................................................................................................................24
3.2.2.4 EEPROM 24LC64T...........................................................................................................................................................................................24
3.2.2.5 EEPROM with temperature sensor SE97BTP ........................................................................................................................................24
3.2.3 Trust Secure Element SE050.......................................................................................................................................................................25
3.2.4 RTC.......................................................................................................................................................................................................................26
3.2.4.1 i.MX 8M Mini-internal RTC...........................................................................................................................................................................26
3.2.4.2 Discrete RTC PCF85063A.............................................................................................................................................................................26
3.2.5 Interfaces...........................................................................................................................................................................................................27
3.2.5.1 Overview ...........................................................................................................................................................................................................27
3.2.5.2 ENET ....................................................................................................................................................................................................................27
3.2.5.3 GPIO ....................................................................................................................................................................................................................28
3.2.5.4 I2C.........................................................................................................................................................................................................................29
3.2.5.5 JTAG ....................................................................................................................................................................................................................30
3.2.5.6 MIPI CSI ..............................................................................................................................................................................................................31
3.2.5.7 MIPI DSI..............................................................................................................................................................................................................32
3.2.5.8 PCIe......................................................................................................................................................................................................................33
3.2.5.9 SAI........................................................................................................................................................................................................................34
3.2.5.10 SPDIF...................................................................................................................................................................................................................36
3.2.5.11 ECSPI ...................................................................................................................................................................................................................37
3.2.5.12 QSPI.....................................................................................................................................................................................................................37
3.2.5.13 UART ...................................................................................................................................................................................................................38
3.2.5.14 USB ......................................................................................................................................................................................................................39
3.2.5.15 USDHC (SD card).............................................................................................................................................................................................40
3.2.5.16 External clock sources ..................................................................................................................................................................................41
3.2.6 Unspecific signals...........................................................................................................................................................................................41

User's Manual l TQMa8MxML UM 0103 l © 2022, TQ-Systems GmbH Page II
3.2.7 Reset....................................................................................................................................................................................................................42
3.2.8 Differences between TQMa8MxML and TQMa8MxNL .....................................................................................................................43
3.2.8.1 CPU......................................................................................................................................................................................................................43
3.2.8.2 SDRAM ...............................................................................................................................................................................................................43
3.2.8.3 Boot Mode ........................................................................................................................................................................................................43
3.2.8.4 SAI........................................................................................................................................................................................................................43
3.2.8.5 PCIe......................................................................................................................................................................................................................43
3.2.8.6 USB ......................................................................................................................................................................................................................43
3.2.9 Power..................................................................................................................................................................................................................44
3.2.9.1 Power supply ...................................................................................................................................................................................................44
3.2.9.2 Power consumption......................................................................................................................................................................................44
3.2.9.3 Voltage monitoring .......................................................................................................................................................................................45
3.2.9.4 Other supply voltages ..................................................................................................................................................................................45
3.2.9.5 Supply outputs................................................................................................................................................................................................45
3.2.9.6 I/O voltages ......................................................................................................................................................................................................46
3.2.9.7 Power-Up sequence TQMa8MxML / carrier board.............................................................................................................................46
3.2.9.8 Standby and SNVS .........................................................................................................................................................................................46
3.2.9.9 PMIC....................................................................................................................................................................................................................47
3.2.10 Impedances......................................................................................................................................................................................................48
4. SOFTWARE........................................................................................................................................................................................................48
5. MECHANICS......................................................................................................................................................................................................49
5.1 Dimensions.......................................................................................................................................................................................................49
5.2 Component placement................................................................................................................................................................................50
5.3 Adaptation to the environment ...............................................................................................................................................................51
5.4 Protection against external effects..........................................................................................................................................................51
5.5 Thermal management..................................................................................................................................................................................51
5.6 Structural requirements...............................................................................................................................................................................51
6. SAFETY REQUIREMENTS AND PROTECTIVE REGULATIONS ............................................................................................................52
6.1 EMC .....................................................................................................................................................................................................................52
6.2 ESD.......................................................................................................................................................................................................................52
6.3 Operational safety and personal security..............................................................................................................................................52
6.4 Climate and operational conditions........................................................................................................................................................53
6.5 Reliability and service life............................................................................................................................................................................53
7. ENVIRONMENT PROTECTION.....................................................................................................................................................................54
7.1 RoHS....................................................................................................................................................................................................................54
7.2 WEEE®.................................................................................................................................................................................................................54
7.3 REACH®..............................................................................................................................................................................................................54
7.4 EuP.......................................................................................................................................................................................................................54
7.5 Battery ................................................................................................................................................................................................................54
7.6 Packaging..........................................................................................................................................................................................................54
7.7 Other entries ....................................................................................................................................................................................................54
8. APPENDIX..........................................................................................................................................................................................................55
8.1 Acronyms and definitions...........................................................................................................................................................................55
8.2 References ........................................................................................................................................................................................................57

User's Manual l TQMa8MxML UM 0103 l © 2022, TQ-Systems GmbH Page III
TABLE DIRECTORY
Table 1: Terms and conventions ..................................................................................................................................................................................2
Table 2: Pinout TQMa8MxML, top view through TQMa8MxML ......................................................................................................................7
Table 3: TQMa8MxML, signals.......................................................................................................................................................................................8
Table 4: Pinout TQMa8MxNL, top view through TQMa8MxNL.....................................................................................................................13
Table 5: TQMa8MxNL, signals.....................................................................................................................................................................................14
Table 6: Differences between TQMa8MxML and TQMa8MxNL .....................................................................................................................18
Table 7: i.MX 8M Mini derivatives..............................................................................................................................................................................19
Table 8: i.MX 8M Nano derivatives............................................................................................................................................................................19
Table 9: i.MX 8M Mini / i.MX 8M Nano, main differences .................................................................................................................................19
Table 10: Boot Modes i.MX 8M Mini ...........................................................................................................................................................................20
Table 11: General boot configuration........................................................................................................................................................................20
Table 12: Boot configuration eMMC at USDHC3 ...................................................................................................................................................21
Table 13: Boot configuration SD card at USDHC2.................................................................................................................................................22
Table 14: Boot configuration QSPI NOR at QSPI_A ...............................................................................................................................................22
Table 15: Boot configuration i.MX 8M Nano ...........................................................................................................................................................23
Table 16: LPDDR4 SDRAM on TQMa8MxML or TQMa8MxNL............................................................................................................................23
Table 17: Trust Secure Element signals .....................................................................................................................................................................25
Table 18: Internal interfaces ..........................................................................................................................................................................................27
Table 19: ENET signals in RGMII mode.......................................................................................................................................................................27
Table 20: GPIO signals......................................................................................................................................................................................................28
Table 21: I2C signals ..........................................................................................................................................................................................................29
Table 22: Address assignment I2C1 bus....................................................................................................................................................................29
Table 23: JTAG signals .....................................................................................................................................................................................................30
Table 24: MIPI CSI signals................................................................................................................................................................................................31
Table 25: MIPI DSI signals...............................................................................................................................................................................................32
Table 26: PCIe signals.......................................................................................................................................................................................................33
Table 27: SAI signals .........................................................................................................................................................................................................35
Table 28: SPDIF signals....................................................................................................................................................................................................36
Table 29: ECSPI signals ....................................................................................................................................................................................................37
Table 30: UART signals.....................................................................................................................................................................................................38
Table 31: USB_OTG signals ............................................................................................................................................................................................39
Table 32: USDHC2 signals...............................................................................................................................................................................................40
Table 33: SD2_VSELECT logic........................................................................................................................................................................................40
Table 34: XTAL signals .....................................................................................................................................................................................................41
Table 35: Unspecific signals...........................................................................................................................................................................................41
Table 36: Reset signals.....................................................................................................................................................................................................42
Table 37: TQMa8MxML power consumption..........................................................................................................................................................44
Table 38: Voltages provided by TQMa8MxML........................................................................................................................................................45
Table 39: Configurable voltages..................................................................................................................................................................................46
Table 40: PMIC signals .....................................................................................................................................................................................................47
Table 41: Impedances......................................................................................................................................................................................................48
Table 42: TQMa8MxML heights....................................................................................................................................................................................49
Table 43: Labels on TQMa8MxML................................................................................................................................................................................50
Table 44: Climate and operational conditions........................................................................................................................................................53
Table 45: Maximum operating temperatures.........................................................................................................................................................53
Table 46: Acronyms ..........................................................................................................................................................................................................55
Table 47: Further applicable documents..................................................................................................................................................................57

User's Manual l TQMa8MxML UM 0103 l © 2022, TQ-Systems GmbH Page IV
FIGURE DIRECTORY
Figure 1: Block diagram i.MX 8M Mini..........................................................................................................................................................................5
Figure 2: Block diagram i.MX 8M Nano........................................................................................................................................................................5
Figure 3: Block diagram TQMa8MxML / TQMa8MxNL (simplified)....................................................................................................................6
Figure 4: Block diagram QSPI NOR Flash interface...............................................................................................................................................24
Figure 5: Block diagram EEPROM interface.............................................................................................................................................................24
Figure 6: Block diagram Trust Secure Element ......................................................................................................................................................25
Figure 7: Termination of unused SE050 signals.....................................................................................................................................................25
Figure 8: Block diagram RTC supply (TQMa8MxML without discrete RTC) .................................................................................................26
Figure 9: Block diagram RTC supply (TQMa8MxML with discrete RTC)........................................................................................................26
Figure 10: Block diagram I2C ...........................................................................................................................................................................................29
Figure 11: Block diagram JTAG interface....................................................................................................................................................................30
Figure 12: Block diagram MIPI CSI.................................................................................................................................................................................31
Figure 13: Block diagram MIPI DSI ................................................................................................................................................................................32
Figure 14: Block diagram PCIe........................................................................................................................................................................................33
Figure 15: Block diagram SAI1........................................................................................................................................................................................34
Figure 16: Block diagram SPDIF.....................................................................................................................................................................................36
Figure 17: Block diagram ECSPI .....................................................................................................................................................................................37
Figure 18: Block diagram UART interfaces.................................................................................................................................................................38
Figure 19: Block diagram USB interfaces....................................................................................................................................................................39
Figure 20: Block diagram SD card interface...............................................................................................................................................................40
Figure 21: Block diagram Reset......................................................................................................................................................................................42
Figure 22: Block diagram TQMa8MxML power supply..........................................................................................................................................44
Figure 23: Block diagram power supply carrier board ..........................................................................................................................................46
Figure 24: Block diagram PMIC interface....................................................................................................................................................................47
Figure 25: TQMa8MxML dimensions, side view.......................................................................................................................................................49
Figure 26: TQMa8MxML dimensions, top view........................................................................................................................................................49
Figure 27: TQMa8MxML dimensions, bottom view................................................................................................................................................49
Figure 28: TQMa8MxML, component placement top............................................................................................................................................50
Figure 29: TQMa8MxML, LGA pad numbering scheme, bottom view............................................................................................................50

User's Manual l TQMa8MxML UM 0103 l © 2022, TQ-Systems GmbH Page V
REVISION HISTORY
Rev. Date Name Pos. Modification
0100 20.02.2021 Petz First issue
0101 04.05.2021 Petz
All
3.2.5.15
Table 37
Non-functional changes, expressions, formatting
Information regarding pull-ups added
Values added
0102 27.10.2021 Kreuzer Table 37 Values added
0104 01.07.2022 Kreuzer
Old Table 10
Table 12
Table 13
Old Table 10 removed and subsequent numbering
adjusted
Recommendations changed
Recommendations changed

User's Manual l TQMa8MxML UM 0103 l © 2022, TQ-Systems GmbH Page 1
1. ABOUT THIS MANUAL
1.1 Copyright and license expenses
Copyright protected © 2022 by TQ-Systems GmbH.
This User's Manual may not be copied, reproduced, translated, changed or distributed, completely or partially in electronic,
machine readable, or in any other form without the written consent of TQ-Systems GmbH.
The drivers and utilities for the components used as well as the BIOS are subject to the copyrights of the respective
manufacturers. The licence conditions of the respective manufacturer are to be adhered to.
Bootloader-licence expenses are paid by TQ-Systems GmbH and are included in the price.
Licence expenses for the operating system and applications are not taken into consideration and must be calculated / declared
separately.
1.2 Registered trademarks
TQ-Systems GmbH aims to adhere to copyrights of all graphics and texts used in all publications, and strives to use original
or license-free graphics and texts.
All brand names and trademarks mentioned in this User's Manual, including those protected by a third party, unless specified
otherwise in writing, are subjected to the specifications of the current copyright laws and the proprietary laws of the present
registered proprietor without any limitation. One should conclude that brand and trademarks are rightly protected by a third
party.
1.3 Disclaimer
TQ-Systems GmbH does not guarantee that the information in this User's Manual is up-to-date, correct, complete or of good
quality. Nor does TQ-Systems GmbH assume guarantee for further usage of the information. Liability claims against TQ-Systems
GmbH, referring to material or non-material related damages caused, due to usage or non-usage of the information given in this
User's Manual, or due to usage of erroneous or incomplete information, are exempted, as long as there is no proven intentional
or negligent fault of TQ-Systems GmbH.
TQ-Systems GmbH explicitly reserves the rights to change or add to the contents of this User's Manual or parts of it without
special notification.
Important Notice:
Before using the Starterkit MBa8Mx or parts of the schematics of the MBa8Mx, you must evaluate it and determine if it is suitable
for your intended application. You assume all risks and liability associated with such use. TQ-Systems GmbH makes no other
warranties including, but not limited to, any implied warranty of merchantability or fitness for a particular purpose. Except where
prohibited by law, TQ-Systems GmbH will not be liable for any indirect, special, incidental or consequential loss or damage
arising from the usage of the Starterkit MBa8Mx or schematics used, regardless of the legal theory asserted.
1.4 Imprint
TQ-Systems GmbH
Gut Delling, Mühlstraße 2
D-82229 Seefeld
Tel: [phone]
Fax: [phone]
E-Mail: Info@TQ-Group
Web: TQ-Group

User's Manual l TQMa8MxML UM 0103 l © 2022, TQ-Systems GmbH Page 2
1.5 Tips on safety
Improper or incorrect handling of the product can substantially reduce its life span.
1.6 Symbols and typographic conventions
Table 1: Terms and conventions
Symbol Meaning
This symbol represents the handling of electrostatic-sensitive modules and / or components. These
components are often damaged / destroyed by the transmission of a voltage higher than about 50 V.
A human body usually only experiences electrostatic discharges above approximately 3,000 V.
This symbol indicates the possible use of voltages higher than 24 V.
Please note the relevant statutory regulations in this regard.
Non-compliance with these regulations can lead to serious damage to your health and may damage
or destroy the component.
This symbol indicates a possible source of danger.
Ignoring the instructions described can cause health damage, or damage the hardware.
This symbol represents important details or aspects for working with TQ-products.
Command
A font with fixed-width is used to denote commands, contents, file names, or menu items.
1.7 Handling and ESD tips
General handling of your TQ-products
The TQ-product may only be used and serviced by certified personnel who have taken note of the
information, the safety regulations in this document and all related rules and regulations.
A general rule is not to touch the TQ-product during operation. This is especially important when
switching on, changing jumper settings or connecting other devices without ensuring beforehand
that the power supply of the system has been switched off.
Violation of this guideline may result in damage / destruction of the TQMa8MxML and be dangerous
to your health.
Improper handling of your TQ-product would render the guarantee invalid.
Proper ESD handling
The electronic components of your TQ-product are sensitive to electrostatic discharge (ESD).
Always wear antistatic clothing, use ESD-safe tools, packing materials etc., and operate your TQ-
product in an ESD-safe environment. Especially when you switch modules on, change jumper settings,
or connect other devices.

User's Manual l TQMa8MxML UM 0103 l © 2022, TQ-Systems GmbH Page 3
1.8 Naming of signals
A hash mark (#) at the end of the signal name indicates a low-active signal.
Example: RESET#
If a signal can switch between two functions and if this is noted in the name of the signal, the low-active function is marked with
a hash mark and shown at the end.
Example: C / D#
If a signal has multiple functions, the individual functions are separated by slashes when they are important for the wiring.
The identification of the individual functions follows the above conventions.
Example: WE2# / OE#
1.9 Further applicable documents / presumed knowledge
•Specifications and manual of the modules used:
These documents describe the service, functionality and special characteristics of the module used (incl. BIOS).
•Specifications of the components used:
The manufacturer's specifications of the components used, for example CompactFlash cards, are to be taken note of.
They contain, if applicable, additional information that must be taken note of for safe and reliable operation.
These documents are stored at TQ-Systems GmbH.
•Chip errata:
It is the user's responsibility to make sure all errata published by the manufacturer of each component are taken note of.
The manufacturer’s advice should be followed.
•Software behaviour:
No warranty can be given, nor responsibility taken for any unexpected software behaviour due to deficient components.
•General expertise:
Expertise in electrical engineering / computer engineering is required for the installation and the use of the device.
The following documents are required to fully comprehend the following contents:
•MBa8Mx circuit diagram
•MBa8Mx User’s Manual
•i.MX 8M Mini Data Sheet
•i.MX 8M Mini Reference Manual
•U-Boot documentation: www.denx.de/wiki/U-Boot/Documentation
•PTXdist documentation: www.ptxdist.de
•Yocto documentation: www.yoctoproject.org/docs/
•TQ-Support Wiki: Support-Wiki TQMa8MxML

User's Manual l TQMa8MxML UM 0103 l © 2022, TQ-Systems GmbH Page 4
2. BRIEF DESCRIPTION
This User's Manual describes the TQMa8MxML and the TQMa8MxNL each as of revision 0200 and refers to some software settings.
This User's Manual does also not replace the NXP i.MX 8M Mini or i.MX 8M Nano documentation, see Table 47.
Note: Designations "TQMa8MxML" and "TQMa8MxNL", available features and interfaces
In order to facilitate the readability of this User's Manual, the designations "TQMa8MxML" and
"i.MX 8M Mini" are used throughout. If technical aspects require a differentiation between
"TQMa8MxML" and "TQMa8MxNL", or "i.MX 8M Mini" and "i.MX 8M Nano", the appropriate designation
is used.
This User's Manual describes all features and interfaces provided by the TQMa8MxML or TQMa8MxNL
family. A certain TQMa8MxML or TQMa8MxNL derivative does not necessarily provide all features and
interfaces described in this User's Manual.
The TQMa8MxML is a universal Minimodule based on the NXP ARM CPU i.MX 8M CPU family with ARM Cortex®-A53.
With a TQMa8MxML soldered on the adapter “TQMa8MxML-MB-ADAP”, the TQMa8MxML can be operated on the MBa8Mx.
2.1 Key functions and characteristics
The TQMa8MxML extends the TQ-Systems GmbH product range and offers an outstanding computing performance.
All essential i.MX 8M Mini pins are routed to the TQMa8MxML LGA pads. There are therefore no restrictions for customers using
the TQMa8MxML with respect to an integrated customised design. All essential components like CPU, LPDDR4, eMMC, and PMIC
are already integrated on the TQMa8MxML.
The main features of the TQMa8MxML are:
•64 bit NXP i.MX 8M Mini CPU, up to 4 × ARM Cortex®-A53 and 1 × Cortex®-M4F
oMini Solo, Mini SoloLite, Mini Dual, Mini DualLite, Mini Quad, and Mini QuadLite
•Up to 4 Gbyte 32-bit LPDDR4-3000
•Up to 64 Gbyte eMMC NAND Flash, eMMC standard 5.1
•Up to 256 Mbyte QSPI NOR Flash
•64 Kbit EEPROM
•Temperature sensor + EEPROM
•RTC
•NXP Power Management Integrated Circuit PCA9450
•All essential i.MX 8M Mini pins are routed to the TQMa8MxML LGA pads
•Plug & Trust Secure Element
•Single supply voltage 5 V
The main features of the TQMa8MxNL are:
•64 bit NXP i.MX 8M Nano CPU, up to 4 × ARM Cortex®-A53 and 1 × Cortex®-M7
oNano Solo, Nano SoloLite, Nano Dual, Nano DualLite, Nano Quad, and Nano QuadLite
•Up to 2 Gbyte 16-bit LPDDR4-3200
•Up to 64 Gbyte eMMC NAND Flash, eMMC standard 5.1
•Up to 256 Mbyte QSPI NOR Flash
•64 Kbit EEPROM
•Temperature sensor + EEPROM
•RTC
•NXP Power Management Integrated Circuit PCA9450
•All essential i.MX 8M Nano pins are routed to the TQMa8MxNL LGA pads
•Plug & Trust Secure Element
•Single supply voltage 5 V

User's Manual l TQMa8MxML UM 0103 l © 2022, TQ-Systems GmbH Page 5
2.2 CPU block diagrams
Figure 1: Block diagram i.MX 8M Mini
(Source: NXP)
Figure 2: Block diagram i.MX 8M Nano
(Source: NXP)

User's Manual l TQMa8MxML UM 0103 l © 2022, TQ-Systems GmbH Page 6
3. ELECTRONICS
The information provided in this User's Manual is only valid in connection with the tailored boot loader,
which is preinstalled on the TQMa8MxML, and the BSP provided by TQ-Systems GmbH, see also chapter 4.
i.MX 8M Mini Solo / SoloLite
i.MX 8M Mini Dual / DualLite
i.MX 8M Mini Quad / QuadLite
i.MX 8M Nano Solo / SoloLite
i.MX 8M Nano Dual / DualLite
i.MX 8M Nano Quad / QuadLite
LPDDR4
281 ball LGA
eMMC 5.1
(optional)
EEPROM
(optional)
Temperature
sensor
PMIC NXP
PCA9450
QSPI NOR
(optional)
5 V
RTC
(optional)
Security Chip
(optional)
5
V
Supervisor
Figure 3: Block diagram TQMa8MxML / TQMa8MxNL (simplified)
3.1 Interfaces to other systems and devices
3.1.1 Pin multiplexing
The multiple pin configurations by different i.MX 8M Mini/Nano-internal function units must be taken note of.
The pin assignment in Table 3 refers to a TQMa8MxML with i.MX 8M Mini Quad CPU in combination with the Starterkit MBa8Mx.
The pin assignment in Table 5 refers to a TQMa8MxNL with i.MX 8M Nano Quad CPU in combination with the Starterkit MBa8Mx.
A certain i.MX 8M Mini or i.MX 8M Nano derivative listed in Table 7 and Table 8 does not necessarily provide all features
described in Table 3 and Table 5. Details are to be taken from (3) and (4).
NXP provides a pin multiplexing tool, which simplifies the selection and configuration (i.MX Pins Tool – NXP Tool).
The electrical and pin characteristics are to be taken from the i.MX 8M Mini and PMIC documentation, see Table 47.
Attention: Destruction or malfunction, pin multiplexing
Depending on the configuration, many i.MX 8M Mini pins can provide several different functions.
Please take note of the information concerning the configuration of these pins in the i.MX 8M Mini
Reference Manual (1), before integration or start-up of your carrier board / Starterkit.
Improper programming by operating software can cause malfunctions, deterioration or
destruction of the TQMa8MxML.
The descriptions given in the following tables should be taken note of:
−DNC: These pins must never be connected and have to be left open.
Please contact TQ-Support for details.

User's Manual l TQMa8MxML UM 0103 l © 2022, TQ-Systems GmbH Page 7
3.1.1.1 Pinout TQMa8MxML
The TQMa8MxML has a total of 281 LGA pads. The TQMa8MxML is soldered and thus permanently connected to the carrier board.
It is not trivial and it is not recommended to remove the TQMa8MxML.
The following table shows the TQMa8MxML pad-out, top view through the TQMa8MxML.
Table 2: Pinout TQMa8MxML, top view through TQMa8MxML
A B C D E F G H J K L M N P R T U V W
19 ECSPI2_
SCLK
ECSPI2_
MISO
ECSPI2_
MOSI GND DSI_CL K_N
DSI_CL
K_P GND CSI_D0 _N
CSI_D0
_P GND CSI_D2 _N
CSI_D2
_P
PCIE_T
XN
PCIE_T
XP GND USB1_ DN
USB1_
DP 19
18 ECSPI1_
MISO
ECSPI1_
MOSI GND DSI_D0 _N
DSI_D0
_P GND DSI_D2 _N
DSI_D2
_P GND CSI_D1 _N
CSI_D1
_P GND CSI_D3 _N
CSI_D3
_P
PCIE_R
XN
PCIE_R
XP GND USB2_ DN
USB2_
DP 18
17 ECSPI1_
SCLK GND ECSPI2_ SS0 GND DSI_D1 _N
DSI_D1
_P GND DSI_D3 _N
DSI_D3
_P GND CSI_CL K_N
CSI_CL
K_P GND USB2_I D
USB2_V
BUS
PCIE_R
EF_CLK
N
PCIE_R
EF_CLK
P
GND CLK1_O
UT 17
16 GND ECSPI1_
SS0 GND UART1_ TXD
UART1_
RXD
UART2_
TXD
UART2_
RXD
UART3_
TXD
UART3_
RXD
UART4_
TXD
UART4_
RXD GND USB1_I D
USB1_V
BUS GND JTAG_T RST#
JTAG_T
DI
CLK2_O
UT
CLK1_I
N 16
15 V_ECSP
I
V_UAR
T GND V_LICEL L GND ISO_78 16_CLK GND JTAG_T DO
JTAG_T
MS GND CLK2_I N 15
14 GND SAI3_T
XD
I2C4_S
CL GND RTC_EV ENT#
ISO_78
16_IO1 JTAG_T CK GND GPIO2_I O10 GND 14
13 SAI3_T
XC
SAI3_T
XFS
I2C3_S
CL
I2C4_S
DA GND ISO_78 16_IO2 GND GPIO2_I O02
GPIO2_I
O09
GPIO2_I
O07 13
12 SAI3_M
CLK
SAI3_R
XD
I2C3_S
DA GND TEMP_E VENT#
ISO_78
16_RST GPIO3_I O14
QSPI_A
_SCLK GND V_ENET 12
11 GND SAI3_R
XFS GND I2C2_S CL
TEST_M
ODE GND GPIO2_I O00 GND GPIO2_I O11 GND 11
10 SAI3_R
XC GND I2C1_S CL
I2C2_S
DA GND BOOT_ MODE1 GND QSPI_A _SS0#
QSPI_A
_DATA
0
GPIO2_I
O08 10
9 SAI5_R
XD0
SAI5_R
XD1
I2C1_S
DA GND SPDIF_ TX
BOOT_
MODE0 GPIO2_I O01
QSPI_A
_DATA
1
QSPI_A
_DATA
2
QSPI_A
_DATA
3 9
8 GND SAI5_R
XD2 GND
SPDIF_
EXT_CL
K
GND SPDIF_
RX GND GPIO2_I O06
GPIO2_I
O05
GPIO2_I
O04
GPIO2_I
O03 8
7 SAI5_M
CLK GND SAI5_R XFS GND RESET_I N#
RESET_
OUT# ONOFF GND GND SD2_RS T# GND GND GND 7
6 SAI5_R
XC
SAI5_R
XD3 GND GND PMIC_R ST#
V_3V3_S
D
USB2_
OTG_O
C
USB1_
OTG_O
C
USB2_
OTG_ID
PMIC_
WDOG# GND GPIO1_I O06
GPIO1_I
O01
GPIO1_I
O00
SD2_W
P GND ENET_ MDIO
ENET_
MDC
ENET_R
D3 6
5 GND GND GND GND GND GND
USB2_
OTG_P
WR
USB1_
OTG_P
WR
USB1_
OTG_ID
M4_NM
I
GPIO1_I
O09
GPIO1_I
O07
GPIO1_I
O03
SD2_C
D# GND SD2_C MD
SD2_CL
K GND ENET_R D2 5
4 V_5V_I
N
V_5V_I
N
V_5V_I
N GND GND GND SAI1_R XFS
SAI1_R
XD4 GND SAI1_R XD7
SAI1_T
XFS GND SAI1_T XD5
SAI1_T
XD6
SD2_D
ATA3
SD2_D
ATA1 GND ENET_R D1 GND 4
3 V_5V_I
N
V_5V_I
N
V_5V_I
N GND GND GND GND SAI1_R XD3
SAI1_R
XD6 GND SAI1_T XD1
SAI1_T
XD3 GND SAI1_T XD7
SD2_D
ATA2 GND SD2_D ATA0
ENET_R
D0
ENET_R
XC 3
2 V_5V_I
N GND SAI2_R XD
SAI2_R
XFS GND SAI2_T XFS
SAI1_R
XD1 GND SAI1_R XD5
SAI1_T
XC GND SAI1_T XD2
SAI1_T
XD4 GND ENET_T X_CTL
ENET_T
D3
ENET_T
D1 GND ENET_R X_CTL 2
1 SAI2_R
XC
SAI2_M
CLK
SAI2_T
XC
SAI2_T
XD
SAI1_R
XC
SAI1_R
XD0
SAI1_R
XD2 GND SAI1_M CLK
SAI1_T
XD0 GND V_1V8 V_3V3 GND ENET_T XC
ENET_T
D2
ENET_T
D0 1
A B C D E F G H J K L M N P R T U V W

User's Manual l TQMa8MxML UM 0103 l © 2022, TQ-Systems GmbH Page 8
3.1.1.2 TQMa8MxML signals
Details about the electrical characteristics of single pins and interfaces are to be taken from the i.MX 8M Mini documentation
(1), (3), (5), as well as the PMIC Data Sheet (7).
Table 3: TQMa8MxML, signals
CPU ball Signal Group Dir. Level TQMa8MxML pad
G26 BOOT_MODE0 Boot_Mode I 3.3 V F9
G27 BOOT_MODE1 Boot_Mode I 3.3 V F10
H27 CLK1_IN CLK I 1.8 V W16
H26 CLK1_OUT CLK O 1.8 V W17
J27 CLK2_IN CLK I 1.8 V W15
J26 CLK2_OUT CLK O 1.8 V V16
A7 ECSPI1_MISO ECSPI I V_ECSPI A18
B7 ECSPI1_MOSI ECSPI O V_ECSPI B18
D6 ECSPI1_SCLK ECSPI O V_ECSPI A17
B6 ECSPI1_SS0 ECSPI O V_ECSPI B16
A8 ECSPI2_MISO ECSPI I V_ECSPI C19
B8 ECSPI2_MOSI ECSPI O V_ECSPI D19
E6 ECSPI2_SCLK ECSPI O V_ECSPI B19
A6 ECSPI2_SS0 ECSPI O V_ECSPI C17
AC27 ENET_MDC ENET O V_ENET V6
AB27 ENET_MDIO ENET I/O V_ENET U6
AE27 ENET_RD0 ENET I V_ENET V3
AD27 ENET_RD1 ENET I V_ENET V4
AD26 ENET_RD2 ENET I V_ENET W5
AC26 ENET_RD3 ENET I V_ENET W6
AF27 ENET_RX_CTL ENET I V_ENET W2
AE26 ENET_RXC ENET I V_ENET W3
AG26 ENET_TD0 ENET O V_ENET V1
AF26 ENET_TD1 ENET O V_ENET U2
AG25 ENET_TD2 ENET O V_ENET U1
AF25 ENET_TD3 ENET O V_ENET T2
AF24 ENET_TX_CTL ENET O V_ENET R2
AG24 ENET_TXC ENET O V_ENET T1
– RTC_EVENT# Event O OD 1E14
– TEMP_EVENT# Event O OD 1E12
1: Requires PU to 3.3 V.

User's Manual l TQMa8MxML UM 0103 l © 2022, TQ-Systems GmbH Page 9
3.1.1.2 TQMa8MxML signals (continued)
Table 3: TQMa8MxML, signals (continued)
CPU ball Signal Group Dir. Level TQMa8MxML pad
AG14 GPIO1_IO00 GPIO I/O 3.3 V P6
AF14 GPIO1_IO01 GPIO I/O 3.3 V N6
AF13 GPIO1_IO03 GPIO I/O 3.3 V N5
AG11 GPIO1_IO06 GPIO I/O 3.3 V M6
AF11 GPIO1_IO07 GPIO I/O 3.3 V M5
AF10 GPIO1_IO09 GPIO I/O 3.3 V L5
V26 GPIO2_IO00 GPIO I/O 1.8 V T11
V27 GPIO2_IO01 GPIO I/O 1.8 V T9
Y27 GPIO2_IO02 GPIO I/O 1.8 V U13
Y26 GPIO2_IO03 GPIO I/O 1.8 V W8
T27 GPIO2_IO04 GPIO I/O 1.8 V V8
T26 GPIO2_IO05 GPIO I/O 1.8 V U8
U27 GPIO2_IO06 GPIO I/O 1.8 V T8
U26 GPIO2_IO07 GPIO I/O 1.8 V W13
W27 GPIO2_IO08 GPIO I/O 1.8 V W10
W26 GPIO2_IO09 GPIO I/O 1.8 V V13
R23 GPIO2_IO10 GPIO I/O 1.8 V V14
R24 GPIO2_IO11 GPIO I/O 1.8 V V11
R22 GPIO3_IO14 GPIO I/O 1.8 V T12
E9 I2C1_SCL I2C O 3.3 V C10
F9 I2C1_SDA I2C I/O 3.3 V C9
D10 I2C2_SCL I2C O 3.3 V D11
D9 I2C2_SDA I2C I/O 3.3 V D10
E10 I2C3_SCL I2C O 3.3 V C13
F10 I2C3_SDA I2C I/O 3.3 V C12
D13 I2C4_SCL I2C O 3.3 V C14
E13 I2C4_SDA I2C I/O 3.3 V D13
– ISO_7816_CLK ISO_7816 I 3.3 V F15
– ISO_7816_IO1 ISO_7816 I/O 3.3 V F14
– ISO_7816_IO2 ISO_7816 I/O 3.3 V F13
– ISO_7816_RST ISO_7816 I 3.3 V F12
F26 JTAG_TCK JTAG I 3.3 V T14
E27 JTAG_TDI JTAG I 3.3 V U16
E26 JTAG_TDO JTAG O 3.3 V T15
F27 JTAG_TMS JTAG I 3.3 V U15
C27 JTAG_TRST# JTAG I 3.3 V T16
AF12 M4_NMI NMI I 3.3 V K5
AG13 PMIC_WDOG# WDOG O 3.3 V K6

User's Manual l TQMa8MxML UM 0103 l © 2022, TQ-Systems GmbH Page 10
3.1.1.2 TQMa8MxML signals (continued)
Table 3: TQMa8MxML, signals (continued)
CPU ball Signal Group Dir. Level TQMa8MxML pad
– GND
A5, A8, A11, A14, A16, B2, B5, B7, B10, B17, C5, C6, C8, C11, C15, C16, C18, D3, D4,
D5, D6, D7, D9, D12, D14, D17, E2, E3, E4, E5, E8, E10, E13, E15, E19, F3, F4, F5, F11,
F18, G3, G8, G15, G17, H2, H7, H19, J1, J4, J18, K3, K17, L2, L6, L19, M1, M4, M16,
M18, N3, N17, P2, R1, R5, R7, R16, T3, T6, T10, T13, T19, U4, U7, U11, U14, U18, V2,
V5, V7, V12, V15, V17, W4, W7, W11, W14
– V_1V8 Power Pout 1.8 V 2N1
– V_3V3 Power Pout 3.3 V 2P1
– V_3V3_SD Power Pout 3.3 V 3F6
– V_5V_IN Power Pin 5 V A2, A3, A4, B3, B4, C3, C4
H10 V_ECSPI Power Pin 1.8 / 3.3 V A15
W22
V_ENET
Power
P
in
1.8 / 2.5 / 3.3 V
W12
– V_LICELL Power Pin 3 V D15
J12 V_UART Power Pin 1.8 / 3.3 V B15
A16 CSI_CLK_N MIPI_CSI I 1.8 V L17
B16 CSI_CLK_P MIPI_CSI I 1.8 V M17
A14 CSI_D0_N MIPI_CSI I 1.8 V J19
B14 CSI_D0_P MIPI_CSI I 1.8 V K19
A15 CSI_D1_N MIPI_CSI I 1.8 V K18
B15 CSI_D1_P MIPI_CSI I 1.8 V L18
A17 CSI_D2_N MIPI_CSI I 1.8 V M19
B17 CSI_D2_P MIPI_CSI I 1.8 V N19
A18 CSI_D3_N MIPI_CSI I 1.8 V N18
B18 CSI_D3_P MIPI_CSI I 1.8 V P18
A11 DSI_CLK_N MIPI_DSI O 1.8 V F19
B11 DSI_CLK_P MIPI_DSI O 1.8 V G19
A9 DSI_D0_N MIPI_DSI O 1.8 V D18
B9 DSI_D0_P MIPI_DSI O 1.8 V E18
A10 DSI_D1_N MIPI_DSI O 1.8 V E17
B10 DSI_D1_P MIPI_DSI O 1.8 V F17
A12 DSI_D2_N MIPI_DSI O 1.8 V G18
B12 DSI_D2_P MIPI_DSI O 1.8 V H18
A13 DSI_D3_N MIPI_DSI O 1.8 V H17
B13
DSI_D3_P
MIPI_DSI
O
1.8 V
J17
A21 PCIE_REF_CLKN PCIe I/O 0.7 V T17
B21 PCIE_REF_CLKP PCIe I/O 0.7 V U17
A19 PCIE_RXN PCIe I 0.7 V R18
B19 PCIE_RXP PCIe I 0.7 V T18
A20 PCIE_TXN PCIe O 0.7 V P19
B20 PCIE_TXP PCIe O 0.7 V R19
2: Maximum load of 500 mA.
3: Maximum load of 400 mA.

User's Manual l TQMa8MxML UM 0103 l © 2022, TQ-Systems GmbH Page 11
3.1.1.2 TQMa8MxML signals (continued)
Table 3: TQMa8MxML, signals (continued)
CPU ball Signal Group Dir. Level TQMa8MxML pad
AB18 SAI1_MCLK SAI I/O 3.3 V K1
AF16 SAI1_RXC SAI I 3.3 V F1
AG15 SAI1_RXD0 SAI I 3.3 V G1
AF15 SAI1_RXD1 SAI I 3.3 V G2
AG17 SAI1_RXD2 SAI I 3.3 V H1
AF17 SAI1_RXD3 SAI I 3.3 V H3
AG18 SAI1_RXD4 SAI I 3.3 V H4
AF18 SAI1_RXD5 SAI I 3.3 V J2
AG19 SAI1_RXD6 SAI I 3.3 V J3
AF19 SAI1_RXD7 SAI I 3.3 V K4
AG16 SAI1_RXFS SAI I 3.3 V G4
AC18 SAI1_TXC SAI O 3.3 V K2
AG20 SAI1_TXD0 SAI O 3.3 V L1
AF20 SAI1_TXD1 SAI O 3.3 V L3
AG21 SAI1_TXD2 SAI O 3.3 V M2
AF21 SAI1_TXD3 SAI O 3.3 V M3
AG22 SAI1_TXD4 SAI O 3.3 V N2
AF22 SAI1_TXD5 SAI O 3.3 V N4
AG23 SAI1_TXD6 SAI O 3.3 V P4
AF23 SAI1_TXD7 SAI O 3.3 V P3
AB19 SAI1_TXFS SAI O 3.3 V L4
AD19 SAI2_MCLK SAI I/O 3.3 V C1
AB22 SAI2_RXC SAI I 3.3 V B1
AC24 SAI2_RXD SAI I 3.3 V C2
AC19 SAI2_RXFS SAI I 3.3 V D2
AD22 SAI2_TXC SAI O 3.3 V D1
AC22 SAI2_TXD SAI O 3.3 V E1
AD23 SAI2_TXFS SAI O 3.3 V F2
AD6 SAI3_MCLK SAI I/O 3.3 V A12
AG7 SAI3_RXC SAI I 3.3 V A10
AF7 SAI3_RXD SAI I 3.3 V B12
AG8 SAI3_RXFS SAI I 3.3 V B11
AG6 SAI3_TXC SAI O 3.3 V A13
AF6 SAI3_TXD SAI O 3.3 V B14
AC6 SAI3_TXFS SAI O 3.3 V B13
AD15 SAI5_MCLK SAI I/O 3.3 V A7
AC15 SAI5_RXC SAI I 3.3 V A6
AD18 SAI5_RXD0 SAI I 3.3 V A9
AC14 SAI5_RXD1 SAI I 3.3 V B9
AD13 SAI5_RXD2 SAI I 3.3 V B8
AC13 SAI5_RXD3 SAI I 3.3 V B6
AB15 SAI5_RXFS SAI I 3.3 V C7

User's Manual l TQMa8MxML UM 0103 l © 2022, TQ-Systems GmbH Page 12
3.1.1.2 TQMa8MxML signals (continued)
Table 3: TQMa8MxML, signals (continued)
CPU ball Signal Group Dir. Level TQMa8MxML pad
P23
QSPI_A_DATA0
QSPI
I/O
1.8 V
V10
K24
QSPI_A_DATA1
QSPI
I/O
1.8 V
U9
K23
QSPI_A_DATA2
QSPI
I/O
1.8 V
V9
N23
QSPI_A_DATA3
QSPI
I/O
1.8 V
W9
N22
QSPI_A_SCLK
QSPI
O
1.8 V
U12
N24
QSPI_A_SS0#
QSPI
O
1.8 V
U10
–
PMIC_RST#
Reset
I
1.8 V
E6
–
RESET_IN#
Reset
I
OD 4
E7
–
RESET_OUT#
Reset
O
OD 4
F7
AA26
SD2_CD#
SD
I
1.8 / 3.3 V
P5
W23
SD2_CLK
SD
O
1.8 / 3.3 V
U5
W24
SD2_CMD
SD
I/O
1.8 / 3.3 V
T5
AB23
SD2_DATA0
SD
I/O
1.8 / 3.3 V
U3
AB24
SD2_DATA1
SD
I/O
1.8 / 3.3 V
T4
V24
SD2_DATA2
SD
I/O
1.8 / 3.3 V
R3
V23
SD2_DATA3
SD
I/O
1.8 / 3.3 V
R4
AB26
SD2_RST#
SD
O
1.8 / 3.3 V
T7
AA27
SD2_WP
SD
I
1.8 / 3.3 V
R6
A25
ONOFF
SNVS
I
1.8 V
G7
AF8
SPDIF_EXT_CLK
SPDIF
I
3.3 V
D8
AG9
SPDIF_RX
SPDIF
I
3.3 V
F8
AF9
SPDIF_TX
SPDIF
O
3.3 V
E9
D26
TEST_MODE
TEST
I
3.3 V
E11
E14
UART1_RXD
UART
I
V_UART
E16
F13
UART1_TXD
UART
O
V_UART
D16
F15
UART2_RXD
UART
I
V_UART
G16
E15
UART2_TXD
UART
O
V_UART
F16
E18
UART3_RXD
UART
I
V_UART
J16
D18
UART3_TXD
UART
O
V_UART
H16
F19
UART4_RXD
UART
I
V_UART
L16
F18
UART4_TXD
UART
O
V_UART
K16
A22
USB1_DN
USB
I/O
3.3 V
U19
B22
USB1_DP
USB
I/O
3.3 V
V19
D22
USB1_ID
USB
I
1.8 V
N16
F22
USB1_VBUS
USB
P
5 V
P16
AD10
USB1_OTG_ID
USB
I
3.3 V
J5
AD9
USB1_OTG_OC
USB
I
3.3 V
H6
AB10
USB1_OTG_PWR
USB
O
3.3 V
H5
A23
USB2_DN
USB
I/O
3.3 V
V18
B23
USB2_DP
USB
I/O
3.3 V
W18
D23
USB2_ID
USB
I
1.8 V
P17
F23
USB2_VBUS
USB
P
5 V
R17
AC10
USB2_OTG_ID
USB
I
3.3 V
J6
AB9
USB2_OTG_OC
USB
I
3.3 V
G6
AC9
USB2_OTG_PWR
USB
O
3.3 V
G5
4: Requires PU to 1.8 V, max. 3.6 V.

User's Manual l TQMa8MxML UM 0103 l © 2022, TQ-Systems GmbH Page 13
3.1.1.3 Pinout TQMa8MxNL
The TQMa8MxNL has a total of 281 LGA pads. The TQMa8MxNL is soldered and thus permanently connected to the carrier board.
It is not trivial and it is not recommended to remove the TQMa8MxNL.
The following table shows the TQMa8MxNL pad-out, top view through the TQMa8MxNL.
Table 4: Pinout TQMa8MxNL, top view through TQMa8MxNL
A B C D E F G H J K L M N P R T U V W
19 ECSPI2_
SCLK
ECSPI2_
MISO
ECSPI2_
MOSI GND DSI_CL K_N
DSI_CL
K_P GND CSI_D0 _N
CSI_D0
_P GND CSI_D2 _N
CSI_D2
_P (NC) (NC) GND USB1_ DN
USB1_
DP 19
18 ECSPI1_
MISO
ECSPI1_
MOSI GND DSI_D0 _N
DSI_D0
_P GND DSI_D2 _N
DSI_D2
_P GND CSI_D1 _N
CSI_D1
_P GND CSI_D3 _N
CSI_D3
_P (NC) (NC) GND (NC) (NC) 18
17 ECSPI1_
SCLK GND ECSPI2_ SS0 GND DSI_D1 _N
DSI_D1
_P GND DSI_D3 _N
DSI_D3
_P GND CSI_CL K_N
CSI_CL
K_P GND (NC) (NC) (NC) (NC) GND CLK1_O UT 17
16 GND ECSPI1_
SS0 GND UART1_ TXD
UART1_
RXD
UART2_
TXD
UART2_
RXD
UART3_
TXD
UART3_
RXD
UART4_
TXD
UART4_
RXD GND USB1_I D
USB1_V
BUS GND BOOT_ MODE2
JTAG_T
DI
CLK2_O
UT
CLK1_I
N 16
15 V_ECSP
I
V_UAR
T GND V_LICEL L GND ISO_78 16_CLK GND JTAG_T DO
JTAG_T
MS GND CLK2_I N 15
14 GND SAI3_T
XD
I2C4_S
CL GND RTC_EV ENT#
ISO_78
16_IO1 JTAG_T CK GND GPIO2_I O10 GND 14
13 SAI3_T
XC
SAI3_T
XFS
I2C3_S
CL
I2C4_S
DA GND ISO_78 16_IO2 GND GPIO2_I O02
GPIO2_I
O09
GPIO2_I
O07 13
12 SAI3_M
CLK
SAI3_R
XD
I2C3_S
DA GND TEMP_E VENT#
ISO_78
16_RST GPIO3_I O14
QSPI_A
_SCLK GND V_ENET 12
11 GND SAI3_R
XFS GND I2C2_S CL
BOOT_
MODE3 GND GPIO2_I O00 GND GPIO2_I O11 GND 11
10 SAI3_R
XC GND I2C1_S CL
I2C2_S
DA GND BOOT_ MODE1 GND QSPI_A _SS0#
QSPI_A
_DATA
0
GPIO2_I
O08 10
9 SAI5_R
XD0
SAI5_R
XD1
I2C1_S
DA GND SPDIF_ TX
BOOT_
MODE0 GPIO2_I O01
QSPI_A
_DATA
1
QSPI_A
_DATA
2
QSPI_A
_DATA
3 9
8 GND SAI5_R
XD2 GND
SPDIF_
EXT_CL
K
GND SPDIF_
RX GND GPIO2_I O06
GPIO2_I
O05
GPIO2_I
O04
GPIO2_I
O03 8
7 SAI5_M
CLK GND SAI5_R XFS GND RESET_I N#
RESET_
OUT# ONOFF GND GND SD2_RS T# GND GND GND 7
6 SAI5_R
XC
SAI5_R
XD3 GND GND PMIC_R ST#
V_3V3_S
D
GPIO1_I
O15
USB1_
OTG_O
C
GPIO1_I
O11
PMIC_
WDOG# GND GPIO1_I O06
GPIO1_I
O01
GPIO1_I
O00
SD2_W
P GND ENET_ MDIO
ENET_
MDC
ENET_R
D3 6
5 GND GND GND GND GND GND GPIO1_I
O14
USB1_
OTG_P
WR
USB1_
OTG_ID
M7_NM
I
GPIO1_I
O09
GPIO1_I
O07
GPIO1_I
O03
SD2_C
D# GND SD2_C MD
SD2_CL
K GND ENET_R D2 5
4 V_5V_I
N
V_5V_I
N
V_5V_I
N GND GND GND (NC) (NC) GND (NC) (NC) GND (NC) (NC) SD2_D ATA3
SD2_D
ATA1 GND ENET_R D1 GND 4
3 V_5V_I
N
V_5V_I
N
V_5V_I
N GND GND GND GND (NC) (NC) GND (NC) (NC) GND (NC) SD2_D ATA2 GND SD2_D ATA0
ENET_R
D0
ENET_R
XC 3
2 V_5V_I
N GND SAI2_R XD
SAI2_R
XFS GND SAI2_T XFS (NC) GND (NC) (NC) GND (NC) (NC) GND ENET_T X_CTL
ENET_T
D3
ENET_T
D1 GND ENET_R X_CTL 2
1 SAI2_R
XC
SAI2_M
CLK
SAI2_T
XC
SAI2_T
XD (NC) (NC) (NC) GND (NC) (NC) GND V_1V8 V_3V3 GND ENET_T XC
ENET_T
D2
ENET_T
D0 1
A B C D E F G H J K L M N P R T U V W

User's Manual l TQMa8MxML UM 0103 l © 2022, TQ-Systems GmbH Page 14
3.1.1.4 TQMa8MxNL signals
Details about the electrical characteristics of single pins and interfaces are to be taken from the i.MX 8M Nano documentation
(2), (4), (6), as well as the PMIC Data Sheet (7).
Table 5: TQMa8MxNL, signals
CPU ball Signal Group Dir. Level TQMa8MxNL pad
G26 BOOT_MODE0 Boot_Mode I 3.3 V F9
G27 BOOT_MODE1 Boot_Mode I 3.3 V F10
C27 BOOT_MODE2 Boot_Mode I 3.3 V T16
D26 BOOT_MODE3 Boot_Mode I 3.3 V E11
H27 CLK1_IN CLK I 1.8 V W16
H26 CLK1_OUT CLK O 1.8 V W17
J27 CLK2_IN CLK I 1.8 V W15
J26 CLK2_OUT CLK O 1.8 V V16
A7 ECSPI1_MISO ECSPI I V_ECSPI A18
B7 ECSPI1_MOSI ECSPI O V_ECSPI B18
D6 ECSPI1_SCLK ECSPI O V_ECSPI A17
B6 ECSPI1_SS0 ECSPI O V_ECSPI B16
A8 ECSPI2_MISO ECSPI I V_ECSPI C19
B8 ECSPI2_MOSI ECSPI O V_ECSPI D19
E6 ECSPI2_SCLK ECSPI O V_ECSPI B19
A6 ECSPI2_SS0 ECSPI O V_ECSPI C17
AC27 ENET_MDC ENET O V_ENET V6
AB27 ENET_MDIO ENET I/O V_ENET U6
AE27 ENET_RD0 ENET I V_ENET V3
AD27 ENET_RD1 ENET I V_ENET V4
AD26 ENET_RD2 ENET I V_ENET W5
AC26 ENET_RD3 ENET I V_ENET W6
AF27 ENET_RX_CTL ENET I V_ENET W2
AE26 ENET_RXC ENET I V_ENET W3
AG26 ENET_TD0 ENET O V_ENET V1
AF26 ENET_TD1 ENET O V_ENET U2
AG25 ENET_TD2 ENET O V_ENET U1
AF25 ENET_TD3 ENET O V_ENET T2
AF24 ENET_TX_CTL ENET O V_ENET R2
AG24 ENET_TXC ENET O V_ENET T1
–
RTC_EVENT#
Event
O
OD
5
E14
– TEMP_EVENT# Event O OD 5E12
E9 I2C1_SCL I2C O 3.3 V C10
F9 I2C1_SDA I2C I/O 3.3 V C9
D10 I2C2_SCL I2C O 3.3 V D11
D9 I2C2_SDA I2C I/O 3.3 V D10
E10 I2C3_SCL I2C O 3.3 V C13
F10 I2C3_SDA I2C I/O 3.3 V C12
D13 I2C4_SCL I2C O 3.3 V C14
E13 I2C4_SDA I2C I/O 3.3 V D13
AF12 M7_NMI NMI I 3.3 V K5
AG13 PMIC_WDOG# WDOG O 3.3 V K6
5: Requires PU to 3.3 V.