TQ Ma8XxS User manual

TQMa8XxS
User's Manual
TQMa8XxS UM 0101
25.01.2022

User's Manual l TQMa8XxS UM 0101 l © 2022, TQ-Systems GmbH Page i
TABLE OF CONTENTS
1. ABOUT THIS MANUAL......................................................................................................................................................................................1
1.1 Copyright and license expenses..................................................................................................................................................................1
1.2 Registered trademarks ....................................................................................................................................................................................1
1.3 Disclaimer ............................................................................................................................................................................................................1
1.4 Imprint...................................................................................................................................................................................................................1
1.5 Tips on safety......................................................................................................................................................................................................2
1.6 Symbols and typographic conventions ....................................................................................................................................................2
1.7 Handling and ESD tips.....................................................................................................................................................................................2
1.8 Naming of signals..............................................................................................................................................................................................3
1.9 Further applicable documents / presumed knowledge.....................................................................................................................3
2. BRIEF DESCRIPTION ..........................................................................................................................................................................................4
2.1 Block diagram i.MX 8X.....................................................................................................................................................................................4
2.2 Key functions and characteristics................................................................................................................................................................5
3. ELECTRONICS......................................................................................................................................................................................................6
3.1 Interfaces to other systems and devices...................................................................................................................................................7
3.1.1 Pin multiplexing ................................................................................................................................................................................................7
3.1.2 SMARC connector X1.......................................................................................................................................................................................8
3.2 System components .....................................................................................................................................................................................11
3.2.1 i.MX 8X CPU......................................................................................................................................................................................................11
3.2.1.1 i.MX 8X derivatives.........................................................................................................................................................................................11
3.2.1.2 i.MX 8X errata...................................................................................................................................................................................................11
3.2.1.3 Boot modes ......................................................................................................................................................................................................12
3.2.2 Memory..............................................................................................................................................................................................................13
3.2.2.1 LPDDR4 SDRAM..............................................................................................................................................................................................13
3.2.2.2 eMMC NAND flash .........................................................................................................................................................................................13
3.2.2.3 QSPI NOR flash ................................................................................................................................................................................................14
3.2.2.4 EEPROM .............................................................................................................................................................................................................15
3.2.2.5 SE97B EEPROM with temperature sensor .............................................................................................................................................15
3.2.3 RTC.......................................................................................................................................................................................................................16
3.2.3.1 i.MX 8X internal RTC......................................................................................................................................................................................16
3.2.3.2 RTC PCF85063..................................................................................................................................................................................................17
3.3 TQMa8XxS interfaces....................................................................................................................................................................................18
3.3.1 Gigbit Ethernet................................................................................................................................................................................................18
3.3.2 USB ......................................................................................................................................................................................................................19
3.3.3 LVDS / DSI / Display-Port .............................................................................................................................................................................21
3.3.4 Camera Serial Interface (CSI) ......................................................................................................................................................................21
3.3.5 SDIO card interface........................................................................................................................................................................................22
3.3.6 Audio ..................................................................................................................................................................................................................22
3.3.7 SPI ........................................................................................................................................................................................................................23
3.3.8 eSPI......................................................................................................................................................................................................................23
3.3.9 Serial ports........................................................................................................................................................................................................23
3.3.10 CAN bus .............................................................................................................................................................................................................24
3.3.11 PCI Express........................................................................................................................................................................................................24
3.3.12 I2C.........................................................................................................................................................................................................................24
3.3.13 GPIO ....................................................................................................................................................................................................................25
3.3.14 Boot Select........................................................................................................................................................................................................26
3.3.15 Watchdog..........................................................................................................................................................................................................26
3.3.16 JTAG ....................................................................................................................................................................................................................26
3.4 Management pins..........................................................................................................................................................................................26
3.5 Trust Secure Element....................................................................................................................................................................................27
3.6 Unused CPU signals.......................................................................................................................................................................................28
3.7 CPLD....................................................................................................................................................................................................................29
3.8 Power..................................................................................................................................................................................................................30
3.8.1 Power supply rails ..........................................................................................................................................................................................30
3.8.1.1 V_VDD_IN..........................................................................................................................................................................................................31
3.8.1.2 V_VDD_RTC......................................................................................................................................................................................................32
3.8.1.3 USB_OTG[2:1]_VBUS .....................................................................................................................................................................................32
3.8.2 Voltage monitoring .......................................................................................................................................................................................32
3.8.3 Power-Up sequence TQMa8XxS / carrier board .................................................................................................................................32
3.8.4 PMIC....................................................................................................................................................................................................................33
4. MECHANICS......................................................................................................................................................................................................35

User's Manual l TQMa8XxS UM 0101 l © 2022, TQ-Systems GmbH Page ii
4.1 Connector .........................................................................................................................................................................................................35
4.2 Dimensions.......................................................................................................................................................................................................35
4.3 Component placement................................................................................................................................................................................36
4.4 Adaptation to the environment ...............................................................................................................................................................37
4.5 Protection against external effects..........................................................................................................................................................37
4.6 Thermal management..................................................................................................................................................................................37
4.7 Structural requirements...............................................................................................................................................................................38
5. SOFTWARE........................................................................................................................................................................................................38
6. SAFETY REQUIREMENTS AND PROTECTIVE REGULATIONS ............................................................................................................39
6.1 EMC .....................................................................................................................................................................................................................39
6.2 ESD.......................................................................................................................................................................................................................39
6.3 Operational safety and personal security..............................................................................................................................................39
6.4 Climate and operational conditions........................................................................................................................................................40
6.5 Reliability and service life............................................................................................................................................................................40
7. ENVIRONMENT PROTECTION.....................................................................................................................................................................41
7.1 RoHS....................................................................................................................................................................................................................41
7.2 WEEE®.................................................................................................................................................................................................................41
7.3 REACH®..............................................................................................................................................................................................................41
7.4 EuP.......................................................................................................................................................................................................................41
7.5 Battery ................................................................................................................................................................................................................41
7.6 Packaging..........................................................................................................................................................................................................41
7.7 Other entries ....................................................................................................................................................................................................41
8. APPENDIX..........................................................................................................................................................................................................42
8.1 Acronyms and definitions...........................................................................................................................................................................42
8.2 References ........................................................................................................................................................................................................44

User's Manual l TQMa8XxS UM 0101 l © 2022, TQ-Systems GmbH Page iii
TABLE DIRECTORY
Table 1: Terms and conventions ..................................................................................................................................................................................2
Table 2: Pinout SMARC connector X1.........................................................................................................................................................................8
Table 3: i.MX 8X derivatives.........................................................................................................................................................................................11
Table 4: Boot sources.....................................................................................................................................................................................................12
Table 5: 24LC64T EEPROM...........................................................................................................................................................................................15
Table 6: SE97BT EEPROM..............................................................................................................................................................................................15
Table 7: SE97B temperature sensor..........................................................................................................................................................................15
Table 8: RTC variants......................................................................................................................................................................................................16
Table 9: Current consumption LICELL with i.MX 8X internal RTC .................................................................................................................16
Table 10: Current consumption V_VDD_RTC with discrete RTC......................................................................................................................17
Table 11: USB ports...........................................................................................................................................................................................................20
Table 12: Assembly option USB3_EN_OC#..............................................................................................................................................................20
Table 13: I2C interface ......................................................................................................................................................................................................24
Table 14: I2C addresses ....................................................................................................................................................................................................25
Table 15: GPIO pins and alternative functions........................................................................................................................................................25
Table 16: Pin assignment JTAG connector...............................................................................................................................................................26
Table 17: Management pins..........................................................................................................................................................................................26
Table 18: Optional CPU signals.....................................................................................................................................................................................28
Table 19: TQMa8XxS power consumption with different supply voltages..................................................................................................31
Table 20: Provided PMIC signals ..................................................................................................................................................................................34
Table 21: TQMa8XxS mating connectors..................................................................................................................................................................35
Table 22: Heights...............................................................................................................................................................................................................36
Table 23: Labels on TQMa8XxS ....................................................................................................................................................................................37
Table 24: Climate and operational conditions industrial temperature range ............................................................................................40
Table 25: Acronyms ..........................................................................................................................................................................................................42
Table 26: Further applicable documents..................................................................................................................................................................44

User's Manual l TQMa8XxS UM 0101 l © 2022, TQ-Systems GmbH Page iv
FIGURE DIRECTORY
Figure 1: Block diagram i.MX 8X CPU ...........................................................................................................................................................................4
Figure 2: Block diagram TQMa8XxS..............................................................................................................................................................................6
Figure 3: Block diagram Boot-Mode..........................................................................................................................................................................12
Figure 4: Block diagram LPDDR4 ................................................................................................................................................................................13
Figure 5: Block diagram eMMC....................................................................................................................................................................................13
Figure 6: Block diagram QSPI .......................................................................................................................................................................................14
Figure 7: Block diagram 24LC64T EEPROM .............................................................................................................................................................15
Figure 8: Block diagram i.MX 8X internal RTC supply (TQMa8XxS without discrete RTC) .....................................................................16
Figure 9: Block diagram RTC supply (TQMa8XxS with discrete RTC).............................................................................................................17
Figure 10: Block diagram Ethernet ...............................................................................................................................................................................18
Figure 11: Block diagram Ethernet PHYs ....................................................................................................................................................................19
Figure 12: Block diagram USB interfaces....................................................................................................................................................................19
Figure 13: Connection of control signals USB0 and USB3....................................................................................................................................19
Figure 14: Block diagram LVDS / DSI / Display-Port ...............................................................................................................................................21
Figure 15: Block diagram CSI ..........................................................................................................................................................................................21
Figure 16: Block diagram SDIO.......................................................................................................................................................................................22
Figure 17: Block diagram Audio.....................................................................................................................................................................................22
Figure 18: Block diagram SPI...........................................................................................................................................................................................23
Figure 19: Block diagram eSPI ........................................................................................................................................................................................23
Figure 20: Block diagram Serial Ports ..........................................................................................................................................................................23
Figure 21: Block diagram CAN........................................................................................................................................................................................24
Figure 22: Block diagram PCI Express..........................................................................................................................................................................24
Figure 23: Block diagram Watchdog............................................................................................................................................................................26
Figure 24: Block diagram CARRIER_STBY#.................................................................................................................................................................27
Figure 25: Block diagram Trust Secure Element ......................................................................................................................................................27
Figure 26: Connecting the NC-Pins ..............................................................................................................................................................................28
Figure 27: Block diagram CPLD......................................................................................................................................................................................29
Figure 28: Block diagram PMIC power rails ...............................................................................................................................................................30
Figure 29: Block diagram module supply...................................................................................................................................................................31
Figure 30: Block diagram power supply carrier board ..........................................................................................................................................32
Figure 31: Power-up sequenz PMIC .............................................................................................................................................................................33
Figure 32: Block diagram PMIC signals........................................................................................................................................................................33
Figure 33: TQMa8XxS dimensions ................................................................................................................................................................................35
Figure 34: TQMa8XxS heights with heatspreader...................................................................................................................................................36
Figure 35: TQMa8XxS, component placement top ................................................................................................................................................36
Figure 36: TQMa8XxS, component placement bottom ........................................................................................................................................37
REVISION HISTORY
Rev. Date Name Pos. Modification
0100 01.12.2021 Kreuzer All Initial release
0101 25.01.2022 Kreuzer 3.8.1, 3.8.1.1
Table 19, Figure 29
Voltage input range VDD_IN corrected
Clearer wording

User's Manual l TQMa8XxS UM 0101 l © 2022, TQ-Systems GmbH Page 1
1. ABOUT THIS MANUAL
1.1 Copyright and license expenses
Copyright protected © 2022 by TQ-Systems GmbH.
This User's Manual may not be copied, reproduced, translated, changed or distributed, completely or partially
in electronic, machine readable, or in any other form without the written consent of TQ-Systems GmbH.
The drivers and utilities for the components used as well as the BIOS are subject to the copyrights of the respective
manufacturers. The licence conditions of the respective manufacturer are to be adhered to.
Bootloader-licence expenses are paid by TQ-Systems GmbH and are included in the price.
Licence expenses for the operating system and applications are not taken into consideration and must be calculated / declared
separately.
1.2 Registered trademarks
TQ-Systems GmbH aims to adhere to copyrights of all graphics and texts used in all publications, and strives to use original
or license-free graphics and texts.
All brand names and trademarks mentioned in this User's Manual, including those protected by a third party, unless specified
otherwise in writing, are subjected to the specifications of the current copyright laws and the proprietary laws of the present
registered proprietor without any limitation. One should conclude that brand and trademarks are rightly protected
by a third party.
1.3 Disclaimer
TQ-Systems GmbH does not guarantee that the information in this User's Manual is up-to-date, correct, complete or of good
quality. Nor does TQ-Systems GmbH assume guarantee for further usage of the information. Liability claims against TQ-Systems
GmbH, referring to material or non-material related damages caused, due to usage or non-usage of the information given in this
User's Manual, or due to usage of erroneous or incomplete information, are exempted, as long as there is no proven intentional
or negligent fault of TQ-Systems GmbH.
TQ-Systems GmbH explicitly reserves the rights to change or add to the contents of this User's Manual or parts of it without
special notification.
Important Notice:
Before using the MB-SMARC-2 or parts of the schematics of the MB-SMARC-2, you must evaluate it and determine if it is suitable
for your intended application. You assume all risks and liability associated with such use. TQ-Systems GmbH makes no other
warranties including, but not limited to, any implied warranty of merchantability or fitness for a particular purpose. Except where
prohibited by law, TQ-Systems GmbH will not be liable for any indirect, special, incidental or consequential loss or damage
arising from the usage of the MB-SMARC-2 or schematics used, regardless of the legal theory asserted.
1.4 Imprint
TQ-Systems GmbH
Gut Delling, Mühlstraße 2
D-82229 Seefeld
Tel: [phone]
Fax: [phone]
E-Mail: Info@TQ-Group
Web: TQ-Group

User's Manual l TQMa8XxS UM 0101 l © 2022, TQ-Systems GmbH Page 2
1.5 Tips on safety
Improper or incorrect handling of the product can substantially reduce its life span.
1.6 Symbols and typographic conventions
Table 1: Terms and conventions
Symbol Meaning
This symbol represents the handling of electrostatic-sensitive modules and / or components. These
components are often damaged / destroyed by the transmission of a voltage higher than about 50 V.
A human body usually only experiences electrostatic discharges above approximately 3,000 V.
This symbol indicates the possible use of voltages higher than 24 V.
Please note the relevant statutory regulations in this regard.
Non-compliance with these regulations can lead to serious damage to your health and may damage
or destroy the component.
This symbol indicates a possible source of danger.
Ignoring the instructions described can cause health damage, or damage the hardware.
This symbol represents important details or aspects for working with TQ-products.
Command
A font with fixed-width is used to denote commands, contents, file names, or menu items.
1.7 Handling and ESD tips
General handling of your TQ-products
The TQ-product may only be used and serviced by certified personnel who have taken note of the
information, the safety regulations in this document and all related rules and regulations.
A general rule is not to touch the TQ-product during operation. This is especially important when
switching on, changing jumper settings or connecting other devices without ensuring beforehand
that the power supply of the system has been switched off.
Violation of this guideline may result in damage / destruction of the TQMa8XxS and be dangerous
to your health.
Improper handling of your TQ-product would render the guarantee invalid.
Proper ESD handling
The electronic components of your TQ-product are sensitive to electrostatic discharge (ESD).
Always wear antistatic clothing, use ESD-safe tools, packing materials etc., and operate your TQ-
product in an ESD-safe environment. Especially when you switch modules on, change jumper settings,
or connect other devices.

User's Manual l TQMa8XxS UM 0101 l © 2022, TQ-Systems GmbH Page 3
1.8 Naming of signals
A hash mark (#) at the end of the signal name indicates a low-active signal.
Example: RESET#
If a signal can switch between two functions and if this is noted in the name of the signal, the low-active function is marked with
a hash mark and shown at the end.
Example: C / D#
If a signal has multiple functions, the individual functions are separated by slashes when they are important for the wiring.
The identification of the individual functions follows the above conventions.
Example: WE2# / OE#
1.9 Further applicable documents / presumed knowledge
•Specifications and manual of the modules used:
These documents describe the service, functionality and special characteristics of the module used (incl. BIOS).
•Specifications of the components used:
The manufacturer's specifications of the components used, for example CompactFlash cards, are to be taken note of.
They contain, if applicable, additional information that must be taken note of for safe and reliable operation.
These documents are stored at TQ-Systems GmbH.
•Chip errata:
It is the user's responsibility to make sure all errata published by the manufacturer of each component are taken note of.
The manufacturer’s advice should be followed.
•Software behaviour:
No warranty can be given, nor responsibility taken for any unexpected software behaviour due to deficient components.
•General expertise:
Expertise in electrical engineering / computer engineering is required for the installation and the use of the device.
The following documents are required to fully comprehend the following contents:
•MB-SMARC-2 circuit diagram
•MB-SMARC-2 User’s Manual
•i.MX 8X Data Sheet
•i.MX 8X Reference Manual
•U-Boot documentation: www.denx.de/wiki/U-Boot/Documentation
•Yocto documentation: www.yoctoproject.org/docs/
•TQ-Support Wiki: Support-Wiki TQMa8XxS

User's Manual l TQMa8XxS UM 0101 l © 2022, TQ-Systems GmbH Page 4
2. BRIEF DESCRIPTION
This User's Manual describes the hardware of TQMa8XxS revision 03xx in combination with the MB-SMARC-2 and refers to some
software settings. The MB-SMARC-2 serves as an evaluation board for the TQMa8XxS. A certain TQMa8XxS derivative does not
necessarily provide all features described in this User's Manual. This User's Manual does also not replace the NXP i.MX 8X
Reference Manual (2). The CPU derivatives provide dual, and quad ARM®Cortex®-A35 cores, and up to two Dual ARM®Cortex®-
M4 co-processors. In addition, the CPUs include an OpenGL ES 3.0 or 3.1 GPU as well as a VPU supporting up to 4K h.265 decoder.
The TQMa8XxS is a universal Minimodule based on these NXP ARM®Cortex®-A35 i.MX 8X CPUs, see also Table 3.
An i.MX 8X Cortex®-A35 core typically operates at 1.2 GHz.
2.1 Block diagram i.MX 8X
Figure 1: Block diagram i.MX 8X CPU
(Source: NXP)

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2.2 Key functions and characteristics
The TQMa8XxS extends the TQ-Systems GmbH product range and offers an outstanding computing performance.
A suitable i.MX 8X derivative (i.MX 8DualX, i.MX 8DualXPlus or i.MX 8QuadXPlus) can be selected for each requirement.
The signals are routed to the card edge connector according to SMARC 2.0. All essential components like CPU, LPDDR4 SDRAM,
eMMC, and power management are already integrated on the TQMa8XxS. The main features of the TQMa8XxS are:
•64-bit NXP i.MX 8X CPU with up to 4 × ARM®Cortex®-A35 and 1 × ARM®Cortex®-M4F
•Derivatives: i.MX 8DualX / i.MX 8DualXPlus / i.MX 8QuadXPlus
•Standard form factor according to SMARC 2.0 (82 mm x 50 mm)
•Up to 4 GByte LPDDR4 SDRAM (32 bit)
•Up to 32 Gbyte eMMC NAND flash
•Up to 256 Mbyte QSPI NOR flash (optional)
•64 kbit EEPROM
•EEPROM + temperature sensor
•DSI-to-eDP bridge
•PCIe clock generator
•NXP Power Management, “ASIL B” ready
•RTC (optional)
•Trust Secure Element (optional)
•Temperature sensor
•Interface compatibility according to SMARC 2.0
•Boot mode selection on TQMa8XxS
•3.3 V fixed supply voltage (optional: extended voltage range of 3.0 V to 5.25 V)
•Form factor 82 mm x 50 mm
The IO voltage of most interfaces is set to 1.8 V by the SMARC standard. Signals for differential high-speed interfaces have
different standardized IO levels.

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3. ELECTRONICS
The information provided in this User's Manual is only valid in connection with the tailored boot loader,
which is preinstalled on the TQMa8XxS, and the BSP provided by TQ-Systems GmbH, see also section 5.
i.MX 8QXP/
i.MX 8DXP/
i.MX 8DX
1x LPDDR4
SMARC pin strip 314 Pins
e-MMC 5.1
EEPROM
Temperature
sensor
PMIC
PF8100
QSPI-NOR-
flash
3,0...5,25 V
RTC
Buck/Boost
LTC3113
Ethernet-
PHY
Ethernet-
PHY
USB-
Hub
DP-
Transceiver Option
Security chip
3,3 V
Figure 2: Block diagram TQMa8XxS

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3.1 Interfaces to other systems and devices
The TQMa8XxS has a SMARC pin strip with a total of 314 pins, divided between the top and bottom of the board, via which it is
connected to the baseboard. Furthermore, the module has four holes with which it can be fixed to the carrier board by means of
screws.
3.1.1 Pin multiplexing
When using the CPU signals, the multiple pin configurations by different CPU-internal function units must be taken note of.
The pin assignment listed in Table 2 refers to the corresponding BSP provided by TQ-Systems GmbH
in combination with the MB-SMARC-2.
The electrical and pin characteristics are to be taken from the i.MX 8X Data Sheet (1), the i.MX 8X Reference Manual (2),
and the PMIC Data Sheet (6).
Some signals are not present on the TQMa8XxS with i.MX 8X Dual CPU or they have different functions.
Attention: Destruction or malfunction
Depending on the configuration, many i.MX 8X balls can provide several different functions.
Please take note of the information in the i.MX 8X Reference Manual (2), and the i.MX 8X Errata (3)
concerning the configuration of these pins before integration or start-up of your carrier board.
Improper programming by operating software can cause malfunctions, deterioration or
destruction of the TQMa8XxS.
The meanings given in the following tables must be observed:
RFU: Reserved pins without function.
To support future TQMa8XxS versions, these pins must not be connected.
DNC: These pins must not be connected, they have to be left open.

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3.1.2 SMARC connector X1
Table 2: Pinout SMARC connector X1
Ball Dir. Level Group Signal Pin Signal Group Level Dir. Ball
– – – – – – S1 MIPI_CSI_I2C0_SCL CSI1 1.8 V O AP26
G35 I 1.8 V CONFIG SMB_ALERT# P1 S2 MIPI_CSI_I2C0_SDA CSI1 1.8 V I/O AM24
– – 0 V Power GND P2 S3 GND Power 0 V – –
AR21 O 1.8 V CSI1 MIPI_CSI_CLKP P3 S4 RFU – – – –
AN21 O 1.8 V CSI1 MIPI_CSI_CLKN P4 S5 DNC – – – –
– – – – DNC P5 S6 MIPI_CSI_MCLK CSI1 1.8 V – AN25
– I/O 3.3 V GBE0 GBE0_SDP P6 S7 DNC – – – –
AP22 I 1.8 V CSI1 MIPI_CSI_DP0 P7 S8 DNC – – – –
AM22 I 1.8 V CSI1 MIPI_CSI_DN0 P8 S9 DNC – – – –
– – 0 V Power GND P9 S10 GND Power 0 V – –
AP20 I 1.8 V CSI1 MIPI_CSI_DP1 P10 S11 DNC – – – –
AM20 I 1.8 V CSI1 MIPI_CSI_DN1 P11 S12 DNC – – – –
– – 0 V Power GND P12 S13 GND Power 0 V – –
AR23 I 1.8 V CSI1 MIPI_CSI_DP2 P13 S14 DNC – – – –
AN23 I 1.8 V CSI1 MIPI_CSI_DN2 P14 S15 DNC – – - –
– – 0 V Power GND P15 S16 GND Power 0 V – –
AR19 I 1.8 V CSI1 MIPI_CSI_DP3 P16 S17 GBE1_MDI_P0 GBE1 – A –
AN19 I 1.8 V CSI1 MIPI_CSI_DN3 P17 S18 GBE1_MDI_N0 GBE1 – A –
– – 0 V Power GND P18 S19 DNC – – – –
– A – GBE0 GBE0_MDI_N3 P19 S20 GBE1_MDI_P1 GBE1 – A –
– A – GBE0 GBE0_MDI_P3 P20 S21 GBE1_MDI_N1 GBE1 – A –
– – – – DNC P21 S22 GBE1_LINK1000# GBE1 3.3 V O –
– O 3.3 V GBE0 GBE0_LINK1000# P22 S23 GBE1_MDI_P2 GBE1 – A –
– A – GBE0 GBE0_MDI_N2 P23 S24 GBE1_MDI_N2 GBE1 – A –
– A – GBE0 GBE0_MDI_P2 P24 S25 GND Power 0 V – –
– O 3.3 V GBE0 GBE0_LINK_ACT# P25 S26 GBE1_MDI_P3 GBE1 – A –
– A – GBE0 GBE0_MDI_N1 P26 S27 GBE1_MDI_N3 GBE1 – A –
– A – GBE0 GBE0_MDI_P1 P27 S28 DNC – – – –
– – – – DNC P28 S29 DNC – 1.8 V I AR29
– A – GBE0 GBE0_MDI_N0 P29 S30 DNC – 1.8 V I AL27
– A – GBE0 GBE0_MDI_P0 P30 S31 GBE1_LINK_ACT# GBE1 3.3 V O –
M32 O 1.8 V SPI1 SPI1_CS1 P31 S32 DNC – 1.8 V O AM26
– – 0 V Power GND P32 S33 DNC – 1.8 V I AK26
D24 I 3.3 V SDIO SD1_WP P33 S34 GND Power 0 V – –
C25 I/O 1.8 V / 3.3 V SDIO SD1_CMD P34 S35 USB4_P USB4 – I/O –
E23 I 3.3 V SDIO SD1_CD# P35 S36 USB4_N USB4 – I/O –
G23 O 1.8 V / 3.3 V SDIO SD1_CLK P36 S37 USB_OTG2_VBUS USB3 5 V I H16
B24 O 3.3 V SDIO SDIO_PWR_EN P37 S38 MCLK_OUT0 CLK 1.8 V O L29
– – 0 V Power GND P38 S39 SAI1_TXFS I2C 1.8 V O N35
A27 I/O 1.8 V / 3.3 V SDIO SD1_DATA0 P39 S40 SAI1_TXD I2C 1.8 V O AA33
B26 I/O 1.8 V / 3.3 V SDIO SD1_DATA1 P40 S41 SAI1_RXD I2C 1.8 V I AA35
D26 I/O 1.8 V / 3.3 V SDIO SD1_DATA2 P41 S42 SAI1_TXC I2C 1.8 V O L35
E25 I/O 1.8 V / 3.3 V SDIO SD1_DATA3 P42 S43 QSPI_ALERT0# eSPI 1.8 V I AE33
M34 O 1.8 V SPI1 SPI1_CS0 P43 S44 DNC – – – –
L33 O 1.8 V SPI1 SPI1_SCK P44 S45 RFU – – – –
J35 I 1.8 V SPI1 SPI1_SDI P45 S46 RFU – – – –
K34 O 1.8 V SPI1 SPI1_SDO P46 S47 GND Power 0 V – –
– – 0 V Power GND P47 S48 I2C0_SCL_1V8 I2C 1.8 V O AR25
– – – – DNC P48 S49 I2C0_SDA_1V8 I2C 1.8 V I/O AP24
– – – – DNC P49 S50 DNC – – – –
– – 0 V Power GND P50 S51 DNC – – – –
– – – – DNC P51 S52 DNC – – – –
– – – – DNC P52 S53 DNC – – – –
– – 0 V Power GND P53 S54 DNC – – – –

User's Manual l TQMa8XxS UM 0101 l © 2022, TQ-Systems GmbH Page 9
3.1.2 SMARC connector X1 (continued)
Table 2: Pinout SMARC connector X1 (continued)
Ball Dir. Level Group Signal Pin Signal Group Level Dir. Ball
AH10 O 1.8 V eSPI QSPIB_SS0# P54 S55 DNC – – – –
AJ9 O 1.8 V eSPI QSPIB_SS1# P55 S56 QSPIB_DATA2 eSPI 1.8 V I/O AJ11
AR11 O 1.8 V eSPI QSPIB_SCLK P56 S57 QSPIB_DATA3 eSPI 1.8 V I/O AM8
AL9 I/O 1.8 V eSPI QSPIB_DATA1 P57 S58 QSPI_RESET# eSPI 1.8 V O R35
AM10 I/O 1.8 V eSPI QSPIB_DATA0 P58 S59 DNC – – – –
– – 0 V Power GND P59 S60 DNC – – – –
D18 I/O – USB0 USB_OTG1_DP P60 S61 GND Power 0 V – –
E19 I/O – USB0 USB_OTG1_DN P61 S62 USB3_SS_TX_P USB3_SS 1.0 V O –
G15 I/O 3.3 V USB0 USB_OTG1_OC P62 S63 USB3_SS_TX_N USB3_SS 1.0 V O –
H18 I 5 V USB0 USB_OTG1_VBUS P63 S64 GND Power 0 V – –
G17 I 3.3 V USB0 USB_OTG1_ID P64 S65 USB3_SS_RX_P USB3_SS 1.0 V I –
– I/O – USB1 USB1_P P65 S66 USB3_SS_RX_N USB3_SS 1.0 V I –
– I/O – USB1 USB1_N P66 S67 GND Power 0 V – –
– I/O 3.3 V USB1 USB1_EN_OC# P67 S68 USB3_P USB3 – I/O –
– – 0 V Power GND P68 S69 USB3_N USB3 – I/O –
– I/O – USB2 USB2_P P69 S70 GND Power 0 V – –
– I/O – USB2 USB2_N P70 S71 USB2_SS_TX_P USB2_SS 1.0 V O –
– I/O 3.3 V USB2 USB2_EN_OC# P71 S72 USB2_SS_TX_N USB2_SS 1.0 V O –
– – – – RFU P72 S73 GND Power 0 V – –
– – – – RFU P73 S74 USB2_SS_RX_P USB2_SS 1.0 V I –
– I/O 3.3 V USB3 USB3_EN_OC# P74 S75 USB2_SS_RX_N USB2_SS 1.0 V I –
Key
H10 O 3.3 V PCIE PCIE_PERST# P75 S76 DNC – – – –
– I/O 3.3 V USB4 USB4_EN_OC# P76 S77 DNC – – – –
– – – – RFU P77 S78 DNC – – – –
– – – – RFU P78 S79 DNC – – – –
– – 0 V Power GND P79 S80 GND Power 0 V – –
– – – – DNC P80 S81 DNC – – – –
– – – – DNC P81 S82 DNC – – – –
– – 0 V Power GND P82 S83 GND Power 0 V – –
– O 1.0 V PCIE PCIE_REFCLK_P P83 S84 DNC – – – –
– O 1.0 V PCIE PCIE_REFCLK_N P84 S85 DNC – – – –
– – 0 V Power GND P85 S86 GND Power 0 V – –
A13 I 1.0 V PCIE PCIE_RX_P P86 S87 DNC – – – –
B12 I 1.0 V PCIE PCIE_RX_N P87 S88 DNC – – – –
– – 0 V Power GND P88 S89 GND Power 0 V – –
B10 O 1.0 V PCIE PCIE_TX_P P89 S90 DNC – – – –
A9 O 1.0 V PCIE PCIE_TX_N P90 S91 DNC – – – –
– – 0 V Power GND P91 S92 GND Power 0 V – –
– – – – DNC P92 S93 DP0_LANE0_P DP 1.2 V O –
– – – – DNC P93 S94 DP0_LANE0_N DP 1.2 V O –
– – 0 V Power GND P94 S95 DP0_AUX_SEL DP 0 V – –
– – – – DNC P95 S96 DP0_LANE1_P DP 1.2 V O –
– – – – DNC P96 S97 DP0_LANE1_N DP 1.2 V O –
– – 0 V Power GND P97 S98 DP0_HPD DP 5 V I –
– – – – DNC P98 S99 DNC – – – –
– – – – DNC P99 S100 DNC – – – –
– – 0 V Power GND P100 S101 GND Power – – –
– – – – DNC P101 S102 DNC – – – –
– – – – DNC P102 S103 DNC – – – –
– – 0 V Power GND P103 S104 USB_OTG2_ID USB3 3.3 V I F16
– – – – DNC P104 S105 DP0_AUX_P DP 1.2 V I/O –
– – – – DNC P105 S106 DP0_AUX_N DP 1.2 V I/O –

User's Manual l TQMa8XxS UM 0101 l © 2022, TQ-Systems GmbH Page 10
3.1.2 SMARC connector X1 (continued)
Table 2: Pinout SMARC connector X1 (continued)
Ball Dir. Level Group Signal Pin Signal Group Level Dir. Ball
– – – – DNC P106 S107 LCD1_BKLT_EN LVDS / DSI 1.8 V O P28
– – – – DNC P107 S108 MIPI_DSI1_CLKP LVDS / DSI 1.8 V O AP16
P30 I/O 1.8 V GPIO GPIO1_IO04 P108 S109 MIPI_DSI1_CLKN LVDS / DSI 1.8 V O AM16
P34 I/O 1.8 V GPIO GPIO1_IO05 P109 S110 GND Power 0 V – –
R31 I/O 1.8 V GPIO GPIO1_IO06 P110 S111 MIPI_DSI1_DP0 LVDS / DSI 1.8 V O AR15
R33 I/O 1.8 V GPIO GPIO1_IO08 P111 S112 MIPI_DSI1_DN0 LVDS / DSI 1.8 V O AN15
V34 I/O 1.8 V GPIO GPIO1_IO13 P112 S113 DNC – – – –
L31 I/O 1.8 V GPIO GPIO0_IO22 P113 S114 MIPI_DSI1_DP1 LVDS / DSI 1.8 V O AR17
H34 I/O 1.8 V GPIO GPIO0_IO21 P114 S115 MIPI_DSI1_DN1 LVDS / DSI 1.8 V O AN17
U35 I/O 1.8 V GPIO GPIO1_IO10 P115 S116 LCD1_VDD_EN LVDS / DSI 1.8 V O P32
U33 I/O 1.8 V GPIO GPIO1_IO09 P116 S117 MIPI_DSI1_DP2 LVDS / DSI 1.8 V O AP14
V32 I/O 1.8 V GPIO GPIO1_IO12 P117 S118 MIPI_DSI1_DN2 LVDS / DSI 1.8 V O AM14
V30 I/O 1.8 V GPIO GPIO1_IO11 P118 S119 GND Power 0 V – –
– – – – DNC P119 S120 MIPI_DSI1_DP3 LVDS / DSI 1.8 V O AP18
– – 0 V Power GND P120 S121 MIPI_DSI1_DN3 LVDS / DSI 1.8 V O AM18
AJ35 O 1.8 V I2C PMIC_I2C_SCL P121 S122 MIPI_DSI1_PWM LVDS / DSI 1.8 V O AD30
AH32 I/O 1.8 V I2C PMIC_I2C_SDA P122 S123 RFU – – – –
– I 1.8 V BOOT BOOT_SEL0# P123 S124 GND Power 0 V – –
– I 1.8 V BOOT BOOT_SEL1# P124 S125 MIPI_DSI0_DP0 LVDS / DSI 1.8 V O AK22
– I 1.8 V BOOT BOOT_SEL2# P125 S126 MIPI_DSI0_DN0 LVDS / DSI 1.8 V O AJ21
– O 1.8 V CONFIG RESET_OUT# P126 S127 LCD0_BKLT_EN LVDS / DSI 1.8 V O N31
– I 1.8 V CONFIG RESET_IN# P127 S128 MIPI_DSI0_DP1 LVDS / DSI 1.8 V O AK18
AH28 I 1.8 V CONFIG IMX_ONOFF P128 S129 MIPI_DSI0_DN1 LVDS / DSI 1.8 V O AJ17
AA29 O 1.8 V SER UART0_TX P129 S130 GND Power 0 V – –
AB32 I 1.8 V SER UART0_RX P130 S131 MIPI_DSI0_DP2 LVDS / DSI 1.8 V O AK24
Y34 O 1.8 V SER UART0_RTS# P131 S132 MIPI_DSI0_DN2 LVDS / DSI 1.8 V O AJ23
Y32 I 1.8 V SER UART0_CTS# P132 S133 LCD0_VDD_EN LVDS / DSI 1.8 V O R29
– – 0 V Power GND P133 S134 MIPI_DSI0_CLKP LVDS / DSI 1.8 V O AK20
AH30 O 1.8 V SER SCU_UART_TX P134 S135 MIPI_DSI0_CLKN LVDS / DSI 1.8 V O AJ19
AF28 I 1.8 V SER SCU_UART_RX P135 S136 GND Power 0 V – –
– – – – DNC P136 S137 MIPI_DSI0_DP3 LVDS / DSI 1.8 V O AK16
– – – – DNC P137 S138 MIPI_DSI0_DN3 LVDS / DSI 1.8 V O AJ15
– – – – DNC P138 S139 MIPI_DSI0_I2C0_SCL I2C 1.8 V O AC31
– – – – DNC P139 S140 MIPI_DSI0_I2C0_SDA I2C 1.8 V I/O AB28
– – – – DNC P140 S141 MIPI_DSI0_PWM LVDS / DSI 1.8 V O AD32
– – – – DNC P141 S142 RFU – – – –
– – 0 V Power GND P142 S143 GND Power 0 V – –
AC35 O 1.8 V CAN CAN1_TX P143 S144 DNC – – – –
AD34 I 1.8 V CAN CAN1_RX P144 S145 WDT_TIME_OUT# (SCU_WDOG_OUT) CONFIG 1.8 V O AD28
AA31 O 1.8 V CAN CAN2_TX P145 S146 PCIE_WAKE# PCIE 3.3 V I A11
AB34 I 1.8 V CAN CAN2_RX P146 S147 VDD_RTC POWER 3.0 V P –
– P – Power VDD_IN P147 S148 LID# CONFIG 1.8 V I E35
– P – Power VDD_IN P148 S149 SLEEP# CONFIG 1.8 V I H32
– P – Power VDD_IN P149 S150 VIN_PWR_BAD# CONFIG VDD_IN I –
– P – Power VDD_IN P150 S151 CHARGING# CONFIG 1.8 V I F34
– P – Power VDD_IN P151 S152 CHARGER_PRSNT# (CHG_PRSNT#) CONFIG 1.8 V I G33
– P – Power VDD_IN P152 S153 CARRIER_STBY# CONFIG 1.8 V O AG29
– P – Power VDD_IN P153 S154 CARRIER_PWR_ON CONFIG 1.8 V O –
– P – Power VDD_IN P154 S155 FORCE_RECOV# BOOT 1.8 V I –
– P – Power VDD_IN P155 S156 BATLOW# CONFIG 1.8 V I J31
– P – Power VDD_IN P156 S157 TEST# CONFIG 1.8 V – –
– – – – – – S158 GND Power 0 V – –
The pins assignment listed in Table 2 refers to the corresponding BSP provided by TQ-Systems GmbH.
For information regarding I/O pins in Table 2 refers to the i.MX 8X Data Sheet (1).

User's Manual l TQMa8XxS UM 0101 l © 2022, TQ-Systems GmbH Page 11
3.2 System components
3.2.1 i.MX 8X CPU
3.2.1.1 i.MX 8X derivatives
Depending on the TQMa8XxS version, one of the following i.MX 8X derivatives is assembled.
Table 3: i.MX 8X derivatives
TQMa8XxS variant CPU derivative Cortex®-A35 clock Cortex®-M4 clock TJ, temperature range
TQMa8XDS-xx i.MX 8DualX 1.2 GHz 264 MHz –40 °C to +125 °C
TQMa8XDPS-xx i.MX 8DualXPlus 1.2 GHz 264 MHz –40 °C to +125 °C
TQMa8XQPS-xx i.MX 8QuadXPlus 1.2 GHz 264 MHz –40 °C to +125 °C
3.2.1.2 i.MX 8X errata
Attention: Malfunction
Please take note of the current i.MX 8X errata (3).

User's Manual l TQMa8XxS UM 0101 l © 2022, TQ-Systems GmbH Page 12
3.2.1.3 Boot modes
After the release of RESET_IN# / IMX_POR# the system controller (SCU) boots from the internal ROM. Depending on the OPT fuses
(eFuse) and the boot mode settings of the system controller the system boots from the selected boot source. The following
interfaces are available as boot source:
•eMMC
•QSPI-NOR flash
•SD card
The SMARC standard requires, depending on the selected boot mode, a defined wiring of the SMARC connector pins
BOOT_SEL[2:0]. These are converted with a CPLD to the boot mode pins BOOT_MODE[3:0].
The FORCE_RECOV# signal is used to switch to the "Force Recovery" mode or the "Serial Downloader", see (1) and (6).
More information about boot interfaces and its configuration is to be taken from the i.MX 8X Data Sheet (1) and the i.MX 8X
Reference Manual (2). Alternatively, an image can be loaded into the internal RAM via serial downloader.
i.MX 8X SMARC contacts
BOOT_MODE0
BOOT_MODE1 BOOT_SEL0#
BOOT_SEL1#
BOOT_MODE2
BOOT_MODE3 BOOT_SEL2#
CPLD
FORCE_RECOV#
Figure 3: Block diagram Boot-Mode
The following boot media are provided according to the SMARC standard:
Table 4: Boot sources
i.MX 8X
BOOT_MODE[3:0] FORCE_RECOV# BOOT_SEL[2:0]# 1Boot Source
0000 1 101 Remote / Internal eFuses. Defined as Boot from eFuses,
since the i.MX 8X does not define a remote mode.
0001 0 xxx Recovery-Mode / Serial-Downloader
0010 1 110 eMMC
0011 1 001 SD card
0110 1 100 QSPI NOR flash
Note: Field software updates
When designing a carrier board, it is recommended to have a redundant update concept for field
software updates.
1: Floating inputs are taken as "1" due to the pull-up on the TQMa8XxS.

User's Manual l TQMa8XxS UM 0101 l © 2022, TQ-Systems GmbH Page 13
3.2.2 Memory
3.2.2.1 LPDDR4 SDRAM
LPDDR4 SDRAM with an effective memory bandwidth of 32 bits is used on the TQMa8XxS. The fifth byte lane of the i.MX 8X CPU
is unused.
i.MX 8X
DQ[15:0]_A
LPDDR4
DQ[15:0]_B
x16
x16
CA[5:0]_A Channel0
Channel1
CA[5:0]_B
Figure 4: Block diagram LPDDR4
The interface timing corresponds to the JEDEC standard LPDDR4-2400 with a max. clock rate of 1200 MHz.
The use of LPDDR4 memory eliminates the ECC feature of the RAM controller. However, special ECC memories can be used that
protect the memory content via ECC independently of the controller. Through correspondingly fewer refresh cycles of the cells,
the power consumption is thereby reduced or the memory is used energy neutral (compared to use without ECC) at higher
temperatures.
The IO voltage of the LPDDR4 is 1.1 V.
The standard memory size of the TQMa8XxS is 2 GByte. Variants with 1 GByte and 4 GByte are available.
Attention: Malfunction
The TQMa8XxS uses a specially developed RAM timing. Each memory expansion level required its own
LPDDR4 configuration.
The standard memory for TQMa8XxS is Samsungs K4F6E3S4HM-GFCL03V (LPDDR4-1866 2048Mx32).
3.2.2.2 eMMC NAND flash
An eMMC is available on the TQMa8XxS as non-volatile memory for programs and data (e.g. bootloader, operating system,
application). The following figure shows the interface of the eMMC to the i.MX 8X:
i.MX 8X
eMMC 5.x
EMMC0_CLK
EMMC0_CMD CLK CMD
EMMC0_DATA[7:0] DAT[7:0]
EMMC0_RESET_B RST#
EMMC0_STROBE DS
VCC
VCCQ
1,8 V 3,3 V
Figure 5: Block diagram eMMC

User's Manual l TQMa8XxS UM 0101 l © 2022, TQ-Systems GmbH Page 14
The i.MX 8X supports MMC card transmission modes up to the current eMMC standard v5.
The I/O voltage is 1.8 V to support the maximum clock rate of 200 MHz. This allows a data rate of up to 400 Mbyte/s in DDR mode
(HS400).
The eMMC can be used as boot medium. The boot configuration is described in 3.2.1.3.
Additional series terminations are inserted in the data and clock signals to influence the driver strength starting from the eMMC.
The standard eMMC size is 8 GByte. Variants with 4 GByte, 16 GByte, 32 GByte, 64 GByte and without eMMc are available. The
standard eMMC ist SanDisks SDINBDG4-8G-T (8 GByte/5.1/SLC).
3.2.2.3 QSPI NOR flash
The i.MX 8X provides two QSPI interfaces, which can be combined to an Octal-SPI or Twin-Quad-SPI on the TQMa8XxS.
In addition, both interfaces feature a data strobe signal with a maximum clock rate of up to 200 MHz, which however, is only
used with QSPI_A. The second QSPI interface is also available on SMARC pins.
i.MX 8X
QSPIA_DATA[3:0]
SPI-NOR
Octal-/Twin-Quad
QSPI-NOR
D[3:0]
D[7:4]
SMARC-Pins
QSPIA_DQS DQS
QSPIA_SS[1:0]_B
C1
QSPIA_SCLK
QSPIB_DATA[3:0]
QSPIB_SS[1:0]_B
QSPIB_SCLK
S1#
S2#
C2
ESPI_CK
ESPI_IO_[4:0]
ESPI_CS[1:0]#
ESPI_ALERT0
MIPI_DSI1_I2C0_SCL
ESPI_RESET#
SPI0_CS1
OPT
OPT
OPT
Figure 6: Block diagram QSPI
Different types of serial NOR-Flashes can be used on the TQMa8XxS, which use one or both QSPI interfaces depending on the
type. The following types can be used:
•QSPI Flash - Simple NOR-Flashes use only one of the two QSPI interfaces. The remaining balls of the second interface
are not connected internally and can be used via the module connectors on the mainboard.
•Octal-SPI / Twin-Quad-SPI - These NOR Flashes represent a dual die Flash, which uses additional pins for the second
QSPI interface compared to the single NOR Flash. The latter cannot be used on the mainboard in this case. All signals of
the QSPIB interface are to be treated as NC in this case.
•Hyperflash / Xccela Flash - The modern serial Flash devices are connected similar to an Octal-SPI / Twin-Quad-SPI, but
have a DQS signal (RX clock) to increase the transfer rate. Thus, up to 400 MB/s can be achieved. Also in this case, the
QSPIB interface cannot be used on the mainboard.

User's Manual l TQMa8XxS UM 0101 l © 2022, TQ-Systems GmbH Page 15
3.2.2.4 EEPROM
For non-volatile storage of e.g. module characteristics or customer specific parameters, a serial EEPROM is optionally available,
which is connected to the I2C0 bus of the i.MX 8X via a level translator.
The write protection (WP) of the EEPROM is not available.
i.MX 8X EEPROM
MIPI_CSI0_GPIO0_00
MIPI_CSI0_GPIO0_01
SCL
SDA
Level-
Translator
Figure 7: Block diagram 24LC64T EEPROM
The following table shows details of the EEPROM.
Table 5: 24LC64T EEPROM
Manufacturer Part number Size Temperature range
Microchip 24LC64T-I/MC MCH 64 Kbit –45 °C to +85 °C
The EEPROM has I2C address 0x50 / 101 0000b
3.2.2.5 SE97B EEPROM with temperature sensor
A serial EEPROM including temperature sensor, controlled by the I2C1 bus, is assembled.
The lower 128 bytes (address 00h to 7Fh) can be Permanent Write Protected (PWP) or Reversible Write Protected (RWP) by
software. The upper 128 bytes (address 80h to FFh) are not write protected and can be used for general purpose data storage.
The EEPROM also provides a temperature sensor to monitor the temperature of the TQMa8XxS.
The following table shows details of the SE97B EEPROM.
Table 6: SE97BT EEPROM
Manufacturer Part number Size Temperature range
NXP SE97B,547 2 × 128 bytes –45 °C to +85 °C
The device has the following I2C addresses:
oEEPROM (normal): 0x53 / 101 0011b
oEEPROM (Protection Command): 0x33 / 011 0011b
oTemperature sensor: 0x1B / 001 1011b
The EEPROM with temperature sensor (D7) is assembled on the bottom side of the TQMa8XxS, see Figure 30.
The temperature sensor is connected to the I2C0 bus of the processor via a level translator.
The overtemperature output of the sensor is connected to the i.MX 8X ball QSPI0A_SS1#.
The following table shows details of the SE97B temperature sensor.
Table 7: SE97B temperature sensor
Manufacturer Part number Resolution Accuracy Temperature range
NXP SE97B,547 11 bits Max. ±3 °C –40 °C to +125 °C