Ublox JODY-W1 Series Quick setup guide

UBX-16012621 - R18
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JODY-W1 series
Host-based modules with Wi-Fi and dual-mode Bluetooth
System integration manual
Abstract
This integration manual describes JODY-W1 series modules with 2x2 MIMO 802.11n/ac and dual-
mode Bluetooth® 5. JODY-W1 is ideal for in-vehicle-infotainment and telematics applications with
simultaneous use cases requiring high data rates, such as in-car hotspots, Wi-Fi display applications
such as Apple CarPlay, or video streaming across multiple clients. Connection to a host processor is
through PCIe, SDIO, or high speed UART interfaces. It comes in an SMD form-factor, providing a
complete solution for easy integration into the application.

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Document information
Title
JODY-W1 series
Subtitle
Host-based modules with Wi-Fi and dual-mode Bluetooth
Document type
System integration manual
Document number
UBX-16012621
Revision and date
R18
23-Aug-2022
Disclosure Restriction
C1-Public
Document status description
Draft
For functional testing. Revised and supplementary data will be published later.
Objective Specification
Target values. Revised and supplementary data will be published later.
Advance Information
Data based on early testing. Revised and supplementary data will be published later.
Early Production Information
Data from product verification. Revised and supplementary data may be published later.
Production Information
Document contains the final product specification.
This document applies to the following products:
Product name
Document status
JODY-W163-A
Initial production
JODY-W164-A
Initial production
JODY-W167-A
Initial production
JODY-W174-A
Engineering sample
For information about the related hardware, software, and status of listed product types, refer to
the respective data sheet [2].
u-blox or third parties may hold intellectual property rights in the products, names, logos and designs included in this
document. Copying, reproduction, or modification of this document or any part thereof is only permitted with the express
written permission of u-blox. Disclosure to third parties is permitted for clearly public documents only.
The information contained herein is provided “as is”. No warranty of any kind, either express or implied, is made in relation to
the accuracy, reliability, fitness for a particular purpose or content of this document. This document may be revised by u-blox
at any time. For most recent documents, please visit www.u-blox.com.
Copyright © u-blox AG.

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Contents
Document information................................................................................................................................2
Contents ..........................................................................................................................................................3
1System description...............................................................................................................................6
1.1 Overview and applications ........................................................................................................................ 6
1.1.1 Module architecture...........................................................................................................................7
1.1.2 Radio interfaces ..................................................................................................................................9
1.1.3 Power management ...........................................................................................................................9
1.2 Pin configuration and function...............................................................................................................10
1.2.1 Pin attributes.....................................................................................................................................10
1.2.2 Pin list..................................................................................................................................................10
1.3 Supply interfaces ......................................................................................................................................13
1.3.1 Main supply inputs ...........................................................................................................................13
1.3.2 Power-up sequence ..........................................................................................................................14
1.4 System function interfaces ....................................................................................................................14
1.4.1 Module Power-on ..............................................................................................................................14
1.4.2 Module Power-off..............................................................................................................................15
1.4.3 Wake-up signals................................................................................................................................15
1.4.4 Host interface configuration ..........................................................................................................15
1.5 Data communication interfaces ............................................................................................................16
1.5.1 PCIe 3.0 interface..............................................................................................................................16
1.5.2 SDIO 3.0 interface.............................................................................................................................16
1.5.3 High Speed UART interface............................................................................................................17
1.5.4 PCM/I2S –Audio interfaces ............................................................................................................18
1.5.5 LTE Coexistence UART....................................................................................................................19
1.5.6 Low Power Oscillator........................................................................................................................19
1.6 Antenna interfaces...................................................................................................................................19
1.6.1 Wi-Fi and Bluetooth antennas .......................................................................................................19
1.6.2 Approved antenna designs.............................................................................................................20
1.7 Other remarks............................................................................................................................................20
1.7.1 Unused pins .......................................................................................................................................20
2Design-in................................................................................................................................................ 21
2.1 Overview......................................................................................................................................................21
2.2 Antenna interfaces...................................................................................................................................21
2.2.1 RF transmission line design ...........................................................................................................22
2.2.2 Antenna design .................................................................................................................................23
2.3 Supply interfaces ......................................................................................................................................27
2.3.1 Module supply design ......................................................................................................................27
2.4 Data communication interfaces ............................................................................................................29
2.4.1 PCI express.........................................................................................................................................29
2.4.2 SDIO 3.0 ..............................................................................................................................................29

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2.4.3 High-speed UART interface............................................................................................................31
2.5 General high speed layout guidelines ...................................................................................................31
2.5.1 General considerations for schematic design and PCB floor planning .................................31
2.5.2 Component placement ....................................................................................................................31
2.5.3 Layout and manufacturing.............................................................................................................32
2.5.4 Layout considerations to reduce spurious emissions ..............................................................32
2.6 Module footprint and stencil design .....................................................................................................33
2.7 Thermal guidelines ...................................................................................................................................34
2.8 ESD guidelines ...........................................................................................................................................35
2.9 Design-in checklist....................................................................................................................................36
2.9.1 Schematic checklist.........................................................................................................................36
2.9.2 Layout checklist................................................................................................................................36
3Software ................................................................................................................................................ 37
3.1 Available software packages ..................................................................................................................37
3.1.1 Supported kernel versions ..............................................................................................................37
3.2 Software package content......................................................................................................................38
3.2.1 Wi-Fi firmware images.....................................................................................................................38
3.2.2 Additional u-blox software deliverables .......................................................................................39
3.3 Software architecture overview .............................................................................................................39
3.3.1 Wi-Fi driver.........................................................................................................................................39
3.3.2 Bluetooth host stack........................................................................................................................39
3.4 Compiling the software............................................................................................................................40
3.4.1 Prerequisites......................................................................................................................................40
3.5 Deploying the software............................................................................................................................40
3.5.1 Additional software requirements ................................................................................................41
3.6 Loading the Wi-Fi driver ..........................................................................................................................41
3.7 Bluetooth initialization.............................................................................................................................42
3.8 Usage examples ........................................................................................................................................43
3.8.1 5G SoftAP + 2G SoftAP ...................................................................................................................44
3.8.2 2G SoftAP + 2G Station...................................................................................................................45
3.8.3 Country code selection ....................................................................................................................46
3.8.4 Bluetooth inquiry...............................................................................................................................46
3.9 Bluetooth vendor specific HCI commands...........................................................................................46
3.9.1 SCO/PCM interface configuration ................................................................................................46
3.9.2 PCM/I2S audio interface configuration........................................................................................47
3.9.3 PCM loopback mode.........................................................................................................................48
3.9.4 Set sleep mode parameters ...........................................................................................................49
3.9.5 Enable wide band speech ................................................................................................................51
4Handling and soldering ..................................................................................................................... 52
4.1 Special ESD handling precautions.........................................................................................................52
4.2 Packaging, shipping, storage, and moisture preconditioning .........................................................52
4.3 Reflow soldering process.........................................................................................................................53

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4.3.1 Cleaning ..............................................................................................................................................54
4.3.2 Other notes ........................................................................................................................................54
5Regulatory compliance ..................................................................................................................... 56
5.1 General requirements ..............................................................................................................................56
5.2 FCC/ISED End-product regulatory compliance ..................................................................................56
5.2.1 Referring to the u-blox FCC/ISED certification ID ......................................................................57
5.2.2 Obtaining own FCC/ISED certification ID ....................................................................................58
5.2.3 Antenna requirements ....................................................................................................................58
5.2.4 Configuration control and software security of end-products ...............................................59
5.2.5 Operating frequencies .....................................................................................................................60
5.2.6 End product labeling requirements ..............................................................................................60
5.2.7 Original FCC and ISED grant ..........................................................................................................61
5.3 CE end-product regulatory compliance................................................................................................62
5.3.1 Safety standard ................................................................................................................................62
5.3.2 CE Equipment classes .....................................................................................................................62
5.4 Regulatory configuration.........................................................................................................................62
5.4.1 Overview of the regulatory CLM process.....................................................................................63
6Product testing ................................................................................................................................... 64
6.1 u-blox in-line production testing ............................................................................................................64
6.2 OEM manufacturer production test .....................................................................................................65
Appendix ....................................................................................................................................................... 66
ARegulatory transmit output power limits................................................................................... 66
A.1 FCC/IC..........................................................................................................................................................66
A.2 ETSI..............................................................................................................................................................67
BGlossary ................................................................................................................................................. 68
Related documents ................................................................................................................................... 70
Revision history.......................................................................................................................................... 71
Contact.......................................................................................................................................................... 72

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1System description
1.1 Overview and applications
The JODY-W1 series is a range of compact modules based on the Infineon CYW88359/CYW89359
(JODY-W16x) and CYW89459 (JODY-W17x) AEC-Q100 compliant chipsets. The modules enable
Wi-Fi, Bluetooth®, and Bluetooth low energy communication, and is thus ideal for in-vehicle-
infotainment and telematics applications with simultaneous use cases requiring high data rates,
such as in-car hotspots, Wi-Fi display applications such as Apple CarPlay, or video streaming across
multiple clients. JODY-W1 modules can be operated in the following modes:
•Wi-Fi 2x2 MIMO 802.11n/ac in 2.4 GHz or 5 GHz
•Wi-Fi 1x1 802.11ac in 2.4 / 5 GHz real simultaneous dual band (RSDB)
•Dual-mode Bluetooth v5, including audio, can be operated simultaneously with both Wi-Fi modes
JODY-W1 undergoes extended automotive qualification according to ISO 16750-4 and is
manufactured in line with ISO/TS 16949. Connection to a host processor is through PCIe, SDIO, or
High-Speed UART interfaces. The JODY-W1 series modules are radio type approved for Europe, USA
and Canada. Refer to the JODY-W1 series data sheet [2] for the complete list of approvals.
JODY-W1 series modules are suitable for a large number of automotive and industrial applications.
Some example applications are shown in the list below.
Automotive applications
•In-car Access-Point for internet access
•Usage of in-car applications, such as Apple CarPlay, Miracast, etc.
•Rear-seat display
•Rapid sync-n-go applications and fast content download to the vehicle
•Hands-free equipment (Bluetooth)
Industrial applications
•Manufacturing floor automation, wireless control terminals and point-to-point backhaul
•Machine control
•Medical in-hospital applications
•Security and surveillance
•Outdoor content distribution
•Robust wireless connectivity in a broad range of industrial applications

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1.1.1 Module architecture
Table 1 shows the available antenna and host interface configurations for JODY-W1 series module
variants.
Product variant
LTE
filter
Antenna configuration
Host
interface
ANT0
ANT1
ANT2
JODY-W163-04A
JODY-W164-27A
-
•
2.4 GHz Bluetooth
2.4/5 GHz Wi-Fi (RSDB
operation supported)
-
SDIO
JODY-W163-13A
•
5 GHz Wi-Fi and 2.4 GHz
Bluetooth (5 GHz 2x2
MIMO operation supported
in single band mode)
2.4/5 GHz Wi-Fi (RSDB
operation supported)
-
SDIO
JODY-W164-15A
•
2.4 GHz Bluetooth
2.4/5 GHz Wi-Fi (RSDB
operation supported)
-
PCIe
JODY-W164-03A
JODY-W164-13A
JODY-W174-03A
JODY-W174-13A
-
•
-
•
5 GHz Wi-Fi and 2.4 GHz
Bluetooth (5 GHz 2x2
MIMO operation supported
in single band mode)
2.4/5 GHz Wi-Fi (RSDB
operation supported)
-
PCIe
JODY-W167-00A
JODY-W167-03A
-
-
-
2.4/5 GHz Wi-Fi
(2x2 MIMO operation
supported in single band
mode)
2.4/5 GHz Wi-Fi
(2x2 MIMO operation
supported in single band
mode)
2.4 GHz Bluetooth
PCIe
Table 1: Supported configurations of the JODY-W1 module series
☞Some JODY-W1 series modules use an LTE coexistence band-pass filter for BPF_1 (TDK B8343).
All other band-pass filters are normal multilayer ceramic band-pass filters. Module variants
equipped with an LTE coexistence filter, as shown in Table 2, are recommended when co-located
with LTE devices operating in LTE bands 7, 38, 40 or 41.
The module host interface configuration is programmed in OTP memory during production.

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Block diagrams of the JODY-W1 series modules are shown in Figure 1 and Figure 2.
Figure 1: Block diagram of JODY-W163-A, JODY-W164-A, and JODY-W174-A
Figure 2: Block diagram of JODY-W167-A

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1.1.2 Radio interfaces
JODY-W1 series modules support Wi-Fi 5 802.11a/b/g/n/ac and Bluetooth operations:
•JODY-W163/-W164/-W174 provide two antenna ports, one for dual band Wi-Fi (2.4 GHz and
5 GHz) and one for Bluetooth, shared with 5 GHz Wi-Fi on some variants. See also Table 1.
•JODY-W167 provides three antenna ports, two for dual band Wi-Fi (2.4 GHz and 5 GHz) and one
dedicated for Bluetooth.
1.1.3 Power management
The JODY-W1 series modules have different power management states. Guidelines for Wi-Fi and
Bluetooth operations in different power states are defined in Table 2.
General Status
Power State
Description
Power-Off
Not Powered
VBAT and VIO/VIO_SD supply not present or
below operating range: module is switched off.
VIO supply can be on in order to reduce leakage
current from other devices connected to the I/O’s.
Power Down
Power Down
The module is effectively powered off by shutting
down all internal regulators. This is done by de-
asserting WL_EN and BT_EN. The chip is brought
out of this mode by external logic re-enabling the
internal regulators. The WL_EN and BT_EN pins
can also be used for separate system reset.
Normal Operation
Deep Sleep
Most analog and digital domains of the chip and
most of the regulators are powered off. All main
clocks are shut down to reduce active power to the
minimum. The 32.768 kHz LPO clock is available
only for the PMU sequencer. Upon a wake-up event
triggered by the PMU timers, an external interrupt,
or a host resume through the SDIO bus, logic
states in the digital core are restored to their pre-
deep-sleep settings to avoid lengthy HW re-
initialization. In deep sleep mode, the main source
of power consumption is leakage current.
Active
All blocks are powered up and fully functional with
active carrier sensing and frame transmission and
receiving. All required regulators are enabled and
put in the most efficient mode based on the load
current. Clock speeds are dynamically adjusted by
the PMU sequencer.
Table 2: Description for Wi-Fi power states

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1.2 Pin configuration and function
1.2.1 Pin attributes
1. Function: Pin function.
2. Pin name: The name of the package pin or terminal.
3. Pin number: Package pin numbers associated with each signals.
4. Power: The voltage domain that powers the pin
5. Type: Signal type description:
I = Input
PD = Internal Pull-Down
PWR = Power
I/O = Input and Output
RF = Radio interface
PU = Internal Pull-Up
DS = Differential
O = Output
H = High-Impedance pin
GND = Ground
OD = Open drain
6. Signal name: The signal name for that pin in the mode being used.
7. Remarks: Pin description and notes.
1.2.2 Pin list
Figure 3 and Table 3 list the pin-out of the JODY-W1 module, with pins grouped by function.
Figure 3: JODY-W1 pin assignment (top view)

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Function
Pin name
Pin no.
Power
Type
Signal name
Remarks
Active
Power down
Power
VBAT
2
VBAT
PWR
Module supply input
Voltage supply range: 3.2 V –
4.8 V
VBAT
VBAT
VIO
3
VIO
PWR
VIO supply
Nominal supply range: 1.8 V
or 3.3 V
VIO
VIO
VIO_SD
4
VIO_SD
PWR
VIO supply for SDIO
Nominal supply range: 1.8 V
or 3.3 V.
Also used for PCIe out-of-
band signals.
VIO_SD
VIO_SD
GND
1, 5, 19,
20, 22,
23, 25,
27, 28,
30, 31,
49
GND
GND
GND
GND
Exposed Pins
-
GND
GND
Connect to Ground
GND
GND
Digital
SD_CLK
53
VIO_SD
I
SDIO Clock
SDIO Clock input
I
Tristate
SD_CMD
52
VIO_SD
I/O
SDIO Command
SDIO command line
I/O
Tristate
SD_D0
54
VIO_SD
I/O
SDIO data 0
SDIO data line bit [0]
I/O
Tristate
SD_D1
55
VIO_SD
I/O
SDIO data 1
SDIO data line bit [1]
I/O
Tristate
SD_D2
50
VIO_SD
I/O
SDIO data 2
SDIO data line bit [2]
I/O
Tristate
SD_D3
51
VIO_SD
I/O
SDIO data 3
SDIO data line bit [3]
I/O
Tristate
PCIE_REFCLKN
43
-
I
PCIe 100 MHz clock
differential input
AC coupling capacitors 100
pF included in the module
I
Disabled
PCIE_REFCLKP
44
-
I
I
Disabled
PCIE_RDN
45
-
I
PCIe receiver
differential input
DC coupled inputs. Place 100
nF AC coupling capacitors
close to the host TDN/TDP
differential output.
I
Disabled
PCIE_RDP
46
-
I
I
Disabled
PCIE_TDN
47
-
O
PCIe transmitter
differential output
AC coupling capacitors100 nF
included in the module.
Connect to the host RDN/RDP
differential input directly.
O
Tristate
PCIE_TDP
48
-
O
O
Tristate
BT_UART_TX
36
VIO
O
UART TX
BT UART, connect to Host RX
O
Tristate
BT_UART_RX
37
VIO
I
UART RX
BT UART, connect to Host TX
I
Tristate
BT_UART_RTS
38
VIO
O
UART RTS
BT UART, connect to Host
CTSn
O
Tristate
BT_UART_CTS
39
VIO
I
UART CTS
BT UART, connect to Host
RTSn
I
Tristate
PCM_CLK
16
VIO
I/O
PCM clock
Input if slave, Output if
master
Alternate function: I2S clock
I/O
Tristate
PCM_SYNC
15
VIO
I/O
PCM Frame Sync
Input if slave, Output if
master
Alternate function: I2S Word
Select
I/O
Tristate
PCM_IN
18
VIO
I
PCM data in
Alternate function: I2S data in
I
Tristate
PCM_OUT
17
VIO
O
PCM data out
Alternate function: I2S data
out
O
Tristate
I2S_CLK
34
VIO
I/O
I2S clock
Reserved for additional I2S
interface. Do not connect.
The I2S interface shares the
pins with the PCM interface.
Use the PCM pins to connect
I/O
Tristate
I2S_WS
35
VIO
I/O
I2S Word Sel.
I/O
Tristate
I2S_DI
32
VIO
I
I2S data in
I
Tristate
I2S_DO
33
VIO
O
I2S data out
O
Tristate

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Function
Pin name
Pin no.
Power
Type
Signal name
Remarks
Active
Power down
an I2S interface for Bluetooth
audio.
LTE_COEX_TX
13
VIO
O
UART TX
LTE coexistence UART1
O
Tristate
LTE_COEX_RX
14
VIO
I
UART RX
LTE coexistence UART1
I
Disabled
Control
PCIE_EN
6
VIO
I
Configuration pin
See Table 7 for bootstrap
configuration
I
Disabled
SD_DES
7
VIO
I
Configuration pin
See Table 7 for bootstrap
configuration
I
Disabled
SD_VDD_SEL
8
VIO
I
Configuration pin
See Table 7 for bootstrap
configuration
I
Disabled
WL_DEV_WAKE
9
VIO
I
Wi-Fi device wake-
up signal input
Asserted: Wi-Fi device must
wake-up or remain awake
Deasserted: Wi-Fi device may
sleep when the sleep criteria
is met.
I
Tristate
WL_HOST_WAK
E
10
VIO
O
Wi-Fi Host wake-up
signal output
Asserted: Host device must
wake-up or remain awake
Deasserted: Host device may
sleep when the sleep criteria
is met
O
Tristate
BT_DEV_WAKE
11
VIO
I
Bluetooth device
wake-up signal
Asserted: Bluetooth device
must wake-up or remain
awake
Deasserted: Bluetooth device
may sleep when sleep criteria
are met.
I
Tristate
BT_HOST_WAKE
12
VIO
O
Bluetooth Host
wake-up signal
Asserted: Host device must
wake-up or remain awake
Deasserted: Host device may
sleep when sleep criteria are
met
O
Tristate
PCIE_PME#
40
VIO_SD
OD
PCIe control signal
PCIe power management
event output
OD
OD
PCIE_CLKREQ#
41
VIO_SD
OD
PCIe control signal
PCIe clock request signal
OD
OD
PCIE_PERST#
42
VIO_SD
I
PCIe control signal
PCIe System reset
I
Disable
WL_EN
58
VIO
I/PD
Wi-Fi power enable
I/PD
I/PD
BT_EN
59
VIO
I/PD
BT power enable
I/PD
I/PD
LPO_IN
60
-
I
Sleep clock input
32.768 kHz clock input, fail
safe pin.
I
I
Radio
ANT0
24
VBAT
RF
Antenna signal
See also Module architecture
RF
RF
ANT1
29
VBAT
RF
Antenna signal
See also Module architecture
RF
RF
ANT2
21
VBAT
RF
Antenna signal
See also Module architecture
RF
RF
Other
NC
26, 56,
57
-
-
Reserved
Do not connect
NC
NC
Table 3: JODY-W1 pinout grouped by function
☞Logical pin states are the same for active mode and sleep mode.
⚠Do not apply any voltage to the digital, control, and radio signal groups while in Not Powered mode
to avoid damaging the module.
1
Not supported in current firmware releases

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1.3 Supply interfaces
1.3.1 Main supply inputs
JODY-W1 series modules must be supplied through the VBAT/VIO/VIO_SD pins. All supply voltages
used inside the modules are generated from the VBAT rail through internal DC/DC converters.
The current drawn by the JODY-W1 series through the VBAT pin can vary by several orders of
magnitude depending on the operation mode and state. In connected mode, high-current
consumption is expected at a maximum RF power level during Wi-Fi transmission. With the power
saving configuration enabled, low current consumption is expected in the low power idle mode.
Supply voltages and other electrical requirements are shown in the JODY-W1 series data sheet [2].
Rail
Allowable ripple (peak to peak)2over DC supply
Current consumption, peak
10-100 kHz
100 kHz-1 MHz
>1 MHz
VBAT (3.3 V)
65 mVpk-pk
25 mVpk-pk
10 mVpk-pk
Wi-Fi: 1050 mA
BT: 60 mA
VIO + VIO_SD
65 mVpk-pk
25 mVpk-pk
10 mVpk-pk
400 µA
Table 4: Summary of voltage supply requirements
The JODY-W1 series modules can be powered by one of the following DC supplies:
•Switching Mode Power Supply (SMPS)
•Low Drop Out (LDO) regulator
The SMPS is the ideal choice when the available primary supply source has higher value than the
operating supply voltage of the JODY-W1 series modules. The use of SMPS provides the best power
efficiency for the overall application and minimizes current drawn from the main supply source.
⚠While selecting the SMPS, ensure that the AC voltage ripple at switching frequency does not
violate the requirements as specified in Table 4. Layout shall be implemented to minimize the
impact of high frequency ringing. See also Guidelines for VCC supply circuit design using a
switching regulator.
The use of an LDO linear regulator is convenient for a primary supply with a relatively low voltage
where the typical 85-90% efficiency of the switching regulator leads to minimal current saving. Linear
regulators are not recommended for high voltage step-down as they will dissipate a considerable
amount of energy.
Independent of the selected DC power supply, it is crucial that it can handle the high peak current
generated by the module. It is recommended to provide at least 20% margin overstated peak current
when designing the power supply for this module.
2
Ripple measured on the power connectors of u-blox EVK.

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1.3.2 Power-up sequence
Figure 4 shows the recommended power sequence of the module. When WL_EN and BT_EN pins are
driven by the host, it is required to apply at least 60 μs delay (two 32.768 clock cycles) with respect to
VBAT/VIO/VIO_SD ramp-up.
⚠Partial power down of the module is not allowed.
Parameter
Min.
Typ.
Max.
Unit
Remarks
t_dly
0
-
-
ms
VIO or VIO_SD should NOT be present before VBAT is high.
T_ramp-up
40
-
-
µs
All Power rails should not rise 10%-90% faster than 40 µs.
t_PD
60
-
-
µs
Power down signals release delay.
T_init
150
-
-
ms
Waiting time before initiating SDIO/PCIe access.
Table 5: Power sequence timings
Figure 4: Power sequence of JODY-W1 module
The WL_EN and BT_EN signals should be kept low during startup (internal pull-down) and driven high
when the power is stable or later when the module must be turned on. Those signals are powered by
VIO voltage domain.
☞Power down mode can be entered only by WL_EN and BT_EN deassertion by the host.
☞The 32.768 kHz clock signal can be applied to the LPO pin before VBAT ramp-up.
1.4 System function interfaces
1.4.1 Module Power-on
The power-on sequence of a JODY-W1 series module can be initiated by applying the respective
voltage to VBAT/VIO/VIO_SD supply pins and asserting the two EN signals (logic level 1). Firmware
download is required each time WL_EN or BT_EN are asserted. External reset is not needed for proper
operation due to internal power-up reset logic though it can be used by the host controller through
the WL_EN / BT_EN in case of an abnormal module behavior.

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1.4.2 Module Power-off
The JODY-W1 modules can enter Power Down mode by de-asserting WL_EN and BT_EN signals.
After de-assertion, power on VBAT/VIO/VIO_SD can be removed to enter Power Off mode.
1.4.3 Wake-up signals
JODY-W1 modules provide several wake-up signals to handle low power modes for both Wi-Fi and
Bluetooth as described in Table 6:
•WL_DEV_WAKE (Wi-Fi only): Host-to-module wake-up signal from Deep Sleep mode (input)
•WL_HOST_WAKE (Wi-Fi only): Module-to-host wake-up signal that can be used to exit Host from
Deep Sleep modes and out-of-band SDIO interrupt signaling (output)
•BT_DEV_WAKE (Bluetooth only): Host-to-Module wake-up signal from Deep Sleep mode (input)
•BT_HOST_WAKE (Bluetooth only): Module-to-host wake-up signal that can be used to exit Host
from Deep Sleep modes (output)
The wakeup signals are powered by VIO voltage domain. For information about how to configure the
Bluetooth sleep mode, see also PCM/I2S audio interface configuration.
Name
I/O
Description
WL_DEV_WAKE
I
Host-to-Module Wake-Up signal, Wi-Fi interface
WL_HOST_WAKE
O
Module-to-Host Wake-Up signal, Wi-Fi interface
BT_DEV_WAKE
I
Host-to-Module Wake-Up signal, Bluetooth interface
BT_HOST_WAKE
O
Module-to-Host Wake-Up signal, Bluetooth interface
Table 6: Wake-up signal definition
1.4.4 Host interface configuration
A JODY-W1 series module uses the PCIE_EN/SD_DES/SD_VDD_SEL pins as host interface
configuration input to set the desired operation mode following a Power on sequence. To configure
the pins for a certain module operation mode, you need to provide a 10 kΩpull down resistor to the
ground. No external circuitry is required to set a configuration pin to high logical level.
Bootstrap configuration options are listed in Table 7 and are used to determine the configuration of
communication busses and host-side drivers.
•PCIe mode: Commands and data regarding the Wi-Fi traffic will be transferred through the PCI
express bus to the module.
•SDIO mode: Commands and data regarding the Wi-Fi traffic will be transferred through the SDIO
bus to the module. The SDIO operates at the voltage selected by the strap option.
•Other configurations are reserved.
The configuration signals are powered by the VIO voltage domain.
PCIE_EN (pin 6)
SD_DES (pin 7)
SD_VDD_SEL (pin 8)
VIO_SD supply (pin 4)
Wi-Fi interface
1
1
1
3.3 V or 1.8 V3
PCIe
0
0
1
1.8 V
1.8V SDIO
0
0
0
3.3 V
3.3V SDIO
Table 7: Bootstrap configuration options
⚠The available host interface depends on the product variant. See Table 1 for the host interfaces
supported for different JODY-W1 module variants.
3
The PCIe control pins of the PCIe bus are powered by the VIO_SD voltage domain.

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⚠When SDIO modes are selected, the host interface signal voltage must match the voltage provided
on the VIO_SD domain during both card identification process and data transfer mode.
1.5 Data communication interfaces
JODY-W1 series modules use PCI express v3.0, SDIO 3.0 and high-speed UART as host interfaces.
The Wi-Fi traffic will always be communicated via the PCI express or the SDIO host interface while the
Bluetooth traffic via the UART interface only.
1.5.1 PCIe 3.0 interface
JODY-W1 modules include a PCIe v3.0-compliant interface running at Gen1 speeds and allow a host
controller using the PCIe bus protocol to access the Wi-Fi function. Table 8 describes the PCIe
interface signals.
Name
I/O
Description
Remarks
PCIE_REFCLKN
I
100MHz clock negative input
AC coupling capacitors 100 pF included to the module
PCIE_REFCLKP
I
100MHz clock positive input
PCIE_RDN
I
Receiver negative input
Module has no AC coupling capacitors (DC coupled inputs).
Place 100 nF AC coupling capacitors close to the Host
TDN/TDP output.
PCIE_RDP
I
Receiver positive input
PCIE_TDN
O
Transmitter negative output
AC coupling capacitors 100 nF included to the module.
Connect to Host RDN/RDP inputs directly.
PCIE_TDP
O
Transmitter positive output
PCIE_PME#
OD
Power management event output
Control pin, open drain. 10 KΩpull-up must be provided on
the Host side.
PCIE_CLKREQ#
OD
Clock request
Control pin, open drain. 10 KΩpull-up must be provided on
the Host side.
PCIE_PERST#
I
Interface reset
Control pin.
Table 8: PCI express signal definition
The PCIe control pins of the PCIe bus are powered by the VIO_SD voltage domain.
1.5.2 SDIO 3.0 interface
JODY-W1 series modules include an SDIO device interface compatible with the industry standard
SDIO 3.0 specification (UHS-I, up to 104 Mbyte/s) and allows a host controller using the SDIO bus
protocol to access the Wi-Fi function. The modules also support legacy modes like default speed and
High-Speed modes.
⚠SDIO supported modes may not be able to support the full throughput capability of the module. If
maximum performance is needed, it is recommended to use the PCI express interface.
The module acts as a device on the SDIO bus. Table 9 summarizes the supported bus speed modes.
Bus speed mode
Max. bus speed [MB/s]
Max. clock frequency [MHz]
Signal voltage (VIO_SD) [V]
SDR104
104
208
1.8
SDR50
50
100
1.8
DDR50
50
50
1.8
SDR25
25
50
1.8
SDR12
12.5
25
1.8
High Speed
25
50
3.3
Default Speed
12.5
25
3.3
Table 9: SDIO supported rates for JODY-W1

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Pull-up resistors are required for all SDIO data and command lines. These pull-up resistors can be
provided either externally on the host PCB or internally in the host application processor. Depending
on the routing of the SDIO lines on the host, termination resistors in series to the lines might also be
needed. See also Data communication interfaces.
Name
I/O
Description
Remarks
SD_CLK
I
SDIO Clock input
SD_CMD
I/O
SDIO Command line
External PU required
SD_D0
I/O
SDIO Data line bit [0]
External PU required
SD_D1
I/O
SDIO Data line bit [1]
External PU required
SD_D2
I/O
SDIO Data line bit [2]
External PU required
SD_D3
I/O
SDIO Data line bit [3]
External PU required
Table 10: SDIO signal definition
The SDIO host interface pins of the module are powered by the VIO_SD voltage domain.
1.5.3 High Speed UART interface
The JODY-W1 series modules support a high-speed Universal Asynchronous Receiver/Transmitter
(UART) interface with the following features:
•Two 1040-byte FIFO for transmit and receive to support BT EDR
•Bluetooth UART HCI transport specification: H4
•2 pins for transmit and receive operations
•2 flow control pins (RTS/CTS)
•Interrupt triggers for low-power, high throughput operation
•Supports standard baud rates and high throughput up to 4 Mbps. The default baud rate after reset
is 115.2 kbaud.
An example of common baud rates supported by the UART interface is listed in Table 12. For proper
operation, baud rate error must be kept within ±2%.
Name
I/O
Description
Remarks
BT_UART_TX
O
UART TX signal
Connect to Host RX
BT_UART_RX
I
UART RX signal
Connect to Host TX
BT_UART_RTS
O
UART RTS signal
Connect to Host CTS
BT_UART_CTS
I
UART CTS signal
Connect to Host RTS
Table 11: UART signal description
Desired Rate [kbaud]
Actual Rate [kbaud]
Error [%]
4000.0
4000.0
0.00
3692.0
3692.308
0.01
3000.0
3000.0
0.00
2000.0
2000.0
0.00
1500.0
1500.0
0.00
1444.444
1454.544
0.70
921.6
923.077
0.16
460.8
461.538
0.16
230.4
230.796
0.17
115.2
115.385
0.16
57.6
57.692
0.16
38.4
38.4
0.00

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Desired Rate [kbaud]
Actual Rate [kbaud]
Error [%]
28.8
28.846
0.16
19.2
19.2
0.00
14.4
14.423
0.16
9.6
9.6
0.00
Table 12: Example of common baud rates
High Speed UART signals are powered by the VIO voltage domain.
1.5.4 PCM/I2S –Audio interfaces
JODY-W1 series modules provide two bi-directional 4-wire digital audio interfaces that can be used
for digital voice/audio communication
4
with external digital audio devices like an audio codec. The
PCM interface supports:
•Master or slave mode with up to 1024 kHz clock rate.
•8 kHz or 16 kHz sample rate.
•PCM sample width size of 8 bit or 16 bit.
•Short frame and long frame synchronization.
•Burst mode at up to 24 MHz to reduce host processor load.
The I2S interface supports:
•Master (1.536 MHz or 2.4 MHz) or slave (any frequency up to 3.072 MHz is supported) mode.
•Channel word length: 16bit.
Name
I/O
Description
Remarks
PCM_CLK
I/O
PCM clock
Output if Master, Input if Slave
Alternate function: I2S clock
PCM_SYNC
I/O
PCM frame sync
Output if Master, Input if Slave
Alternate function: I2S word select
PCM_IN
I
PCM data out
Alternate function: I2S data out
PCM_OUT
O
PCM data in
Alternate function: I2S data in
I2S_CLK
I/O
I2S clock
Reserved for additional I2S interface. Do not connect.
The I2S interface shares the pins with the PCM interface. Use the PCM
pins to connect an I2S interface for Bluetooth audio
I2S_WS
I/O
I2S word select
I2S_DI
I
I2S data in
I2S_DO
O
I2S data out
Table 13: PCM digital audio signal description
☞The PCM pins of JODY-W1 series modules can be configured to either PCM or I2S operation mode
through HCI commands. See also PCM/I2S audio interface configuration.
The PCM and I2S signals are powered by the VIO voltage domain.
4
The two physical interfaces are mutually exclusive and cannot work simultaneously.

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1.5.5 LTE Coexistence UART
The module supports an auxiliary UART for coexistence with other mobile radio technologies.
5
Name
I/O
Description
Remarks
LTE_COEX_TX
O
WCI-2 UART TX signal
Connect to MWS device RX
LTE_COEX_RX
I
WCI-2 UART RX signal
Connect to MWS device TX
Table 14 : Auxiliary UART signal description
The signals shown in Table 14 are powered by the VIO voltage domain.
1.5.6 Low Power Oscillator
It is mandatory to connect an external low-frequency clock to the LPO_IN pin. This clock is used for
low-power mode timing and a few other functions. The external LPO must meet the requirements
listed in Table 16.
Name
I/O
Description
Remarks
LPO_IN
I
32.768 kHz clock input
Failsafe pin
Table 15 : External 32.768 kHz sleep clock signal description
The LPO_IN pin is a failsafe input, clock signal that can be applied to the pin when the module is not
powered provided that the requirements in Table 16 are fulfilled.
Parameter
LPO clock
Unit
Nominal input frequency
32.768
kHz
Frequency accuracy
±250
ppm
Duty cycle
30 –70
%
Input signal accuracy
200 –3300
mV, pkpk
Signal type
Square-wave or Sine-wave
-
Input impedance6
> 100
kΩ
< 5
pF
Clock jitter (during startup)
< 10,000
ppm
Table 16: External 32.768 kHz sleep clock specification
1.6 Antenna interfaces
1.6.1 Wi-Fi and Bluetooth antennas
JODY-W1 modules provide different antenna configurations based on the selected product variant:
•JODY-W163/-W164/-W174 provide two pins for dual-band Wi-Fi and Bluetooth shared
connectivity (ANT0 and ANT1), where RSDB operation is supported on a single antenna pin
(ANT1).
•JODY-W167 provides three pins for dual-band Wi-Fi operation (ANT0 and ANT1) and dedicated
Bluetooth connectivity (ANT2).
5
Not supported in current firmware.
6
When power is applied or switched off.

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The following recommendations apply while developing an antenna interface for the JODY-W1 series
module:
•Where possible, consider integrating the u-blox reference design in the end product to minimize
the effort on the certification process. See JODY-W1 antenna reference design [12] for a full list
of available reference designs.
•The ANT0, ANT1 and ANT2 pins have a nominal characteristic impedance of 50 and must be
connected to the external antennas through a 50 transmission line to allow proper RF
transmission and reception.
•Good isolation must be provided between the various antennas in the system. Special care should
be taken to maximize isolation between antennas operating in the same or nearby bands.
For information about how to properly design circuits compliant with these requirements, see also
Antenna interfaces.
1.6.2 Approved antenna designs
JODY-W1 series modules come with a pre-certified design that can be used to save costs and time
during the certification process. To minimize this effort, the customer is required to implement
antenna layout according to u-blox reference designs. Reference design source files can be provided
on request by u-blox.
The designer integrating a u-blox reference design into an end-product is solely responsible for the
Unintentional Emissions levels produced by the end-product. See also Regulatory compliance.
For Wi-Fi and Bluetooth operation, the module has been tested and approved for use with the
antennas listed in the JODY-W1 series data sheet [2]. The module may be integrated with other
antennas and in this case the designer should refer to the Regulatory compliance information that
describes the certification options available to customers. For more information, also see the
JODY-W1 antenna reference design [12].
1.7 Other remarks
1.7.1 Unused pins
JODY-W1 modules have pins reserved for future use (NC) that must be left unconnected on the
application board.