Ublox SARA-R4 Series Quick setup guide

SARA-R4 series
Size-optimized LTE Cat M1 / NB1 modules
System Integration Manual
Abstract
This document describes the features and the system integration of
SARA-R4 series cellular modules.
These modules are a complete, cost efficient and performance
optimized multi-band LTE Cat M1 / NB1 solution in the compact
SARA form factor.
www.u-blox.com
UBX-16029218 - R06

SARA-R4 series - System Integration Manual
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Document Information
Title
SARA-R4 series
Subtitle
Size-optimized LTE Cat M1 / NB1 modules
Document type
System Integration Manual
Document number
UBX-16029218
Revision and date
R06
30-Oct-2017
Disclosure restriction
Product Status
Corresponding content status
Functional Sample
Draft
For functional testing. Revised and supplementary data will be published later.
In Development /
Prototype
Objective Specification
Target values. Revised and supplementary data will be published later.
Engineering Sample
Advance Information
Data based on early testing. Revised and supplementary data will be published later.
Initial Production
Early Prod. Information
Data from product verification. Revised and supplementary data may be published later.
Mass Production /
End of Life
Production Information
Final product specification.
This document applies to the following products:
Name
Type number
Firmware version
PCN reference
Product Status
SARA-R404M
SARA-R404M-00B-00
K0.0.00.00.07.06
UBX-17047084
Initial Production
SARA-R410M
SARA-R410M-01B-00
L0.0.00.00.02.03
UBX-17051617
Initial Production
SARA-R410M-02B-00
L0.0.00.00.03
UBX-17051388
Functional Sample
u-blox reserves all rights to this document and the information contained herein. Products, names, logos and designs described herein may in
whole or in part be subject to intellectual property rights. Reproduction, use, modification or disclosure to third parties of this document or
any part thereof without the express permission of u-blox is strictly prohibited.
The information contained herein is provided “as is” and u-blox assumes no liability for the use of the information. No warranty, either
express or implied, is given, including but not limited, with respect to the accuracy, correctness, reliability and fitness for a particular purpose
of the information. This document may be revised by u-blox at any time. For most recent documents, visit www.u-blox.com.
Copyright © 2017, u-blox AG
u-blox is a registered trademark of u-blox Holding AG in the EU and other countries.. Microsoft and Windows are either registered
trademarks or trademarks of Microsoft Corporation in the United States and/or other countries. All other registered trademarks or
trademarks mentioned in this document are property of their respective owners.

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Preface
u-blox Technical Documentation
As part of our commitment to customer support, u-blox maintains an extensive volume of technical
documentation for our products. In addition to our product-specific technical data sheets, the following manuals
are available to assist u-blox customers in product design and development.
AT Commands Manual: This document provides the description of the AT commands supported by the
u-blox cellular modules.
System Integration Manual: This document provides the description of u-blox cellular modules’ system
from the hardware and the software point of view, it provides hardware design guidelines for the optimal
integration of the cellular modules in the application device and it provides information on how to set up
production and final product tests on application devices integrating the cellular modules.
Application Note: These documents provide guidelines and information on specific hardware and/or
software topics on u-blox cellular modules. See Related documents for a list of Application Notes related to
your Cellular Module.
How to use this Manual
The SARA-R4 series System Integration Manual provides the necessary information to successfully design and
configure the u-blox cellular modules.
This manual has a modular structure. It is not necessary to read it from the beginning to the end.
The following symbols are used to highlight important information within the manual:
An index finger points out key information pertaining to module integration and performance.
A warning symbol indicates actions that could negatively impact or damage the module.
Questions
If you have any questions about u-blox Cellular Integration:
Read this manual carefully.
Contact our information service on the homepage http://www.u-blox.com/
Technical Support
Worldwide Web
Our website (http://www.u-blox.com/) is a rich pool of information. Product information, technical documents
can be accessed 24h a day.
By E-mail
Contact the closest Technical Support office by email. Use our service pool email addresses rather than any
personal email address of our staff. This makes sure that your request is processed as soon as possible. You will
find the contact details at the end of the document.
Helpful Information when Contacting Technical Support
When contacting Technical Support, have the following information ready:
Module type (SARA-R404M) and firmware version
Module configuration
Clear description of your question or the problem
A short description of the application
Your complete contact details

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Contents
Preface ................................................................................................................................3
Contents..............................................................................................................................4
1System description.......................................................................................................7
1.1 Overview .............................................................................................................................................. 7
1.2 Architecture.......................................................................................................................................... 9
1.3 Pin-out ............................................................................................................................................... 10
1.4 Operating modes................................................................................................................................ 14
1.5 Supply interfaces ................................................................................................................................ 16
1.5.1 Module supply input (VCC) ......................................................................................................... 16
1.5.2 Generic digital interfaces supply output (V_INT)........................................................................... 18
1.6 System function interfaces.................................................................................................................. 19
1.6.1 Module power-on ....................................................................................................................... 19
1.6.2 Module power-off ....................................................................................................................... 20
1.6.3 Module reset ............................................................................................................................... 21
1.7 Antenna interface............................................................................................................................... 22
1.7.1 Antenna RF interface (ANT) ......................................................................................................... 22
1.7.2 Antenna detection interface (ANT_DET) ...................................................................................... 23
1.8 SIM interface ...................................................................................................................................... 23
1.8.1 SIM interface ............................................................................................................................... 23
1.8.2 SIM detection interface ............................................................................................................... 23
1.9 Data communication interfaces .......................................................................................................... 24
1.9.1 UART interface ............................................................................................................................ 24
1.9.2 USB interface............................................................................................................................... 26
1.9.3 SPI interface ................................................................................................................................ 26
1.9.4 SDIO interface ............................................................................................................................. 27
1.9.5 DDC (I2C) interface ...................................................................................................................... 27
1.10 Audio.............................................................................................................................................. 27
1.11 General Purpose Input/Output ........................................................................................................ 28
1.12 Reserved pins (RSVD) ...................................................................................................................... 28
1.13 System features............................................................................................................................... 29
1.13.1 Network indication ...................................................................................................................... 29
1.13.2 Antenna supervisor ..................................................................................................................... 29
1.13.3 Dual stack IPv4/IPv6 ..................................................................................................................... 29
1.13.4 TCP/IP and UDP/IP ....................................................................................................................... 29
1.13.5 FTP .............................................................................................................................................. 29
1.13.6 HTTP ........................................................................................................................................... 30
1.13.7 Firmware update Over AT (FOAT) ................................................................................................ 30
1.13.8 Firmware update Over The Air (uFOTA) ....................................................................................... 30
1.13.9 Power saving ............................................................................................................................... 30

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2Design-in.....................................................................................................................34
2.1 Overview ............................................................................................................................................ 34
2.2 Supply interfaces ................................................................................................................................ 35
2.2.1 Module supply (VCC) .................................................................................................................. 35
2.2.2 Generic digital interfaces supply output (V_INT)........................................................................... 46
2.3 System functions interfaces ................................................................................................................ 47
2.3.1 Module power-on (PWR_ON) ...................................................................................................... 47
2.3.2 Module reset (RESET_N) .............................................................................................................. 48
2.4 Antenna interface............................................................................................................................... 49
2.4.1 Antenna RF interface (ANT) ......................................................................................................... 49
2.4.2 Antenna detection interface (ANT_DET) ...................................................................................... 56
2.5 SIM interface ...................................................................................................................................... 59
2.5.1 Guidelines for SIM circuit design.................................................................................................. 59
2.5.2 Guidelines for SIM layout design ................................................................................................. 63
2.6 Data communication interfaces .......................................................................................................... 64
2.6.1 UART interface ............................................................................................................................ 64
2.6.2 USB interface............................................................................................................................... 69
2.6.3 SPI interface ................................................................................................................................ 71
2.6.4 SDIO interface ............................................................................................................................. 71
2.6.5 DDC (I2C) interface ...................................................................................................................... 71
2.7 Audio ................................................................................................................................................. 71
2.8 General Purpose Input/Output ............................................................................................................ 72
2.9 Reserved pins (RSVD) .......................................................................................................................... 72
2.10 Module placement .......................................................................................................................... 73
2.11 Module footprint and paste mask ................................................................................................... 74
2.12 Thermal guidelines .......................................................................................................................... 75
2.13 Schematic for SARA-R4 series module integration........................................................................... 76
2.13.1 Schematic for SARA-R4 series modules........................................................................................ 76
2.14 Design-in checklist .......................................................................................................................... 77
2.14.1 Schematic checklist ..................................................................................................................... 77
2.14.2 Layout checklist ........................................................................................................................... 78
2.14.3 Antenna checklist ........................................................................................................................ 78
3Handling and soldering .............................................................................................79
3.1 Packaging, shipping, storage and moisture preconditioning ............................................................... 79
3.2 Handling............................................................................................................................................. 79
3.3 Soldering ............................................................................................................................................ 80
3.3.1 Soldering paste............................................................................................................................ 80
3.3.2 Reflow soldering ......................................................................................................................... 80
3.3.3 Optical inspection........................................................................................................................ 81
3.3.4Cleaning...................................................................................................................................... 81
3.3.5 Repeated reflow soldering........................................................................................................... 82
3.3.6 Wave soldering............................................................................................................................ 82
3.3.7 Hand soldering ............................................................................................................................ 82

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3.3.8 Rework........................................................................................................................................ 82
3.3.9 Conformal coating ...................................................................................................................... 82
3.3.10 Casting........................................................................................................................................ 82
3.3.11 Grounding metal covers .............................................................................................................. 82
3.3.12 Use of ultrasonic processes.......................................................................................................... 82
4Approvals....................................................................................................................83
4.1 Product certification approval overview............................................................................................... 83
4.2 US Federal Communications Commission notice................................................................................. 84
4.2.1 Safety warnings review the structure ........................................................................................... 84
4.2.2 Declaration of Conformity ........................................................................................................... 84
4.2.3 Modifications .............................................................................................................................. 85
4.3 Innovation, Science and Economic Development Canada notice ......................................................... 85
4.3.1 Declaration of Conformity ........................................................................................................... 85
4.3.2 Modifications .............................................................................................................................. 86
5Product testing ...........................................................................................................88
5.1 u-blox in-series production test........................................................................................................... 88
5.2 Test parameters for OEM manufacturer .............................................................................................. 89
5.2.1 “Go/No go” tests for integrated devices...................................................................................... 89
5.2.2 RF functional tests ....................................................................................................................... 89
Appendix ..........................................................................................................................91
AMigration between SARA modules...........................................................................91
A.1 Overview ............................................................................................................................................ 91
A.2 Pin-out comparison between SARA-G3, SARA-U2, SARA-R4 and SARA-N2 modules .......................... 93
BGlossary ......................................................................................................................98
Related documents.........................................................................................................100
Revision history..............................................................................................................101
Contact............................................................................................................................102

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1System description
1.1 Overview
The SARA-R4 series comprises LTE Cat M1 / NB1 multi-mode modules in the miniature SARA LGA form-factor
(26.0 x 16.0 mm, 96-pin), that allows an easy integration in compact designs and a seamless drop-in migration
from u-blox cellular module families.
SARA-R4 series modules are form-factor compatible with u-blox LISA, LARA and TOBY cellular module families
and are pin-to-pin compatible with u-blox SARA-N, SARA-G and SARA-U cellular module families. This facilitates
migration from the u-blox NB-IoT, GSM/GPRS, CDMA, UMTS/HSPA and other LTE modules, maximizes customers
investments, simplifies logistics, and enables very short time-to-market.
The modules are ideal for LPWA applications with low to medium data throughput rates, as well as devices that
require long battery lifetimes, such as connected health, smart metering, smart cities and wearables.
SARA-R4 series includes the following modules:
SARA-R404M single-band modules designed primarily to operate in North America on Verizon network
SARA-R410M-01B quad-band modules designed primarily to operate in North America on AT&T network
SARA-R410M-02B multi-band modules, with software-based bands’ configurability for worldwide operation
LTE Cat M1 supports vehicular handover capability and delivers the technology necessary to enable the use of
the modules in applications such as vehicle, asset and people tracking where mobility is a pre-requisite. Other
applications where the module is well suited include and are not limited to: smart home, security systems,
industrial monitoring and control.
SARA-R4 series modules support data communication up to 375 kb/s over an extended operating temperature
range of –40 to +85 °C, with low power consumption, and with coverage enhancement for deeper range into
buildings and basements (and underground with NB1). The modules will also support Voice over LTE Cat M1.
The flexibility extends further through dynamic mode selection as M1-only/preferred or NB1-only/preferred.
Table 1 summarizes the main features and interfaces of SARA-R4 series modules.
Model
Region
Bands
Positioning
Interfaces
Audio
Features
Grade
3GPP Release Baseline
3GPP LTE category
LTE FDD Bands
GNSS via modem
AssistNow Software
CellLocate®
UART
USB 2.0
SPI
SDIO
DDC (I2C)
GPIOs
Analog audio
Digital audio
Power Saving Mode
eDRX
Antenna supervisor
Embedded TCP/UDP stack
Embedded HTTP, FTP
Dual stack IPv4/IPv6
FW update over the air (FOTA)
Standard
Professional
Automotive
SARA-R404M
USA
13
M1
13
○
○
○
●
●
○
○
○
●
○
●
○
●
●
●
●
●
SARA-R410M-01B
N. America
13
M1
2,4
5,12
○
○
○
●
●
○
○
○
●
○
●
○
●
●
●
●
●
SARA-R410M-02B
Global
13
M1
NB1
*
●
●
●
●
●
○
○
●
●
○
●
●
●
●
●
●
●
* = Bands 1, 2, 3, 4, 5, 8, 12, 13, 17, 18, 19, 20, 25, 26, 28 (and band 39 in M1-only) ●= supported by all FW versions ○= supported by future FW versions
Table 1: SARA-R4 series main features summary

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Table 2 reports a summary of cellular radio access technologies characteristics and features of the modules.
Item
SARA-R404M
SARA-R410M-01B
SARA-R410M-02B
Protocol stack
3GPP Release 13
LTE Cat M1 Half-Duplex
3GPP Release 13
LTE Cat M1 Half-Duplex
3GPP Release 13
LTE Cat M1 / NB1 Half-Duplex
Operating bands
FDD Band 13 (750 MHz)
FDD Band 12 (700 MHz)
FDD Band 5 (850 MHz)
FDD Band 4 (1700 MHz)
FDD Band 2 (1900 MHz)
FDD Band 12 (700 MHz)
FDD Band 17 (700 MHz)
FDD Band 28 (700 MHz)
FDD Band 13 (700 MHz)
FDD Band 20 (800 MHz)
FDD Band 26 (850 MHz)
FDD Band 5 (850 MHz)
FDD Band 19 (850 MHz)
FDD Band 8 (900 MHz)
FDD Band 4 (1700 MHz)
FDD Band 3 (1800 MHz)
FDD Band 2 (1900 MHz)
FDD Band 25 (1900 MHz)
TDD Band 39 (1900 MHz)1
FDD Band 1 (2100 MHz)
Power class
Power Class 3 (23 dBm)
Power Class 3 (23 dBm)
Power Class 3 (23 dBm)
Data rate
LTE category M1:
up to 375 kb/s UL
up to 375 kb/s DL
LTE category M1:
up to 375 kb/s UL
up to 375 kb/s DL
LTE category M1:
up to 375 kb/s UL
up to 375 kb/s DL
LTE category NB1:
up to 62.5 kb/s UL
up to 27.2 kb/s DL
Table 2: SARA-R4 series LTE Cat M1 / NB1 characteristics summary
1
Supported in LTE category M1 only

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1.2 Architecture
Figure 1 summarizes the internal architecture of SARA-R4 series modules.
Memory
V_INT
RF
transceiver
Cellular
BaseBand
Processor
ANT
VCC (Supply)
USB
DDC (I2C)
SIM card detection
SIM
UART
Power-On
Reset
GPIOs
Antenna detection
Switch
PA
19.2 MHz
Power
Management
Filter
SDIO
SPI / Digital Audio
Figure 1: SARA-R4 series modules simplified block diagram

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1.3 Pin-out
Table 3 lists the pin-out of the SARA-R4 series modules, with pins grouped by function.
Function
Pin Name
Pin No
I/O
Description
Remarks
Power
VCC
51, 52, 53
I
Module supply input
VCC supply circuit affects the RF performance and
compliance of the device integrating the module with
applicable required certification schemes.
See section 1.5.1 for functional description / requirements.
See section 2.2.1 for external circuit design-in.
GND
1, 3, 5, 14,
20-22, 30, 32,
43, 50, 54, 55,
57-61, 63-96
N/A
Ground
GND pins are internally connected each other.
External ground connection affects the RF and thermal
performance of the device.
See section 1.5.1 for functional description.
See section 2.2.1 for external circuit design-in.
V_INT
4
O
Generic digital
interfaces supply
output
V_INT = 1.8 V (typical) generated by internal regulator
when the module is switched on, outside the low power
PSM deep sleep mode.
Test-Point for diagnostic access is recommended.
See section 1.5.2 for functional description.
See section 2.2.2 for external circuit design-in.
System
PWR_ON
15
I
Power-on input
Internal 200 kpull-up resistor.
Test-Point for diagnostic access is recommended.
See section 1.6.1 for functional description.
See section 2.3.1 for external circuit design-in.
RESET_N
18
I
External reset input
Internal 37 kpull-up resistor.
Test-Point for diagnostic access is recommended.
See section 1.6.3 for functional description.
See section 2.3.2 for external circuit design-in.
Antenna
ANT
56
I/O
Primary antenna
Main Tx / Rx antenna interface.
50 nominal characteristic impedance.
Antenna circuit affects the RF performance and application
device compliance with required certification schemes.
See section 1.7 for functional description / requirements.
See section 2.4 for external circuit design-in.
ANT_DET
62
I
Antenna detection
ADC for antenna presence detection function
See section 1.7.2 for functional description.
See section 2.4.2 for external circuit design-in.
SIM
VSIM
41
O
SIM supply output
VSIM = 1.8 V / 3 V output as per the connected SIM type.
See section 1.8 for functional description.
See section 2.5 for external circuit design-in.
SIM_IO
39
I/O
SIM data
Data input/output for 1.8 V / 3 V SIM
Internal 4.7 kpull-up to VSIM.
See section 1.8 for functional description.
See section 2.5 for external circuit design-in.
SIM_CLK
38
O
SIM clock
4.8 MHz clock output for 1.8 V / 3 V SIM
See section 1.8 for functional description.
See section 2.5 for external circuit design-in.
SIM_RST
40
O
SIM reset
Reset output for 1.8 V / 3 V SIM
See section 1.8 for functional description.
See section 2.5 for external circuit design-in.

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Function
Pin Name
Pin No
I/O
Description
Remarks
UART
RXD
13
O
UART data output
1.8 V output, Circuit 104 (RXD) in ITU-T V.24,
for AT commands, data communication, FOAT.
See section 1.9.1 for functional description.
See section 2.6.1 for external circuit design-in.
TXD
12
I
UART data input
1.8 V input, Circuit 103 (TXD) in ITU-T V.24,
for AT commands, data communication, FOAT.
Internal active pull-up to V_INT.
See section 1.9.1 for functional description.
See section 2.6.1 for external circuit design-in.
CTS
11
O
UART clear to send
output
1.8 V output, Circuit 106 (CTS) in ITU-T V.24.
Not supported by “00”, “01” and “02” product versions.
See section 1.9.1 for functional description.
See section 2.6.1 for external circuit design-in.
RTS
10
I
UART ready to send
input
1.8 V input, Circuit 105 (RTS) in ITU-T V.24.
Internal active pull-up to V_INT.
Not supported by “00”, “01” and “02” product versions.
See section 1.9.1 for functional description.
See section 2.6.1 for external circuit design-in.
DSR
6
O
UART data set ready
output
1.8 V, Circuit 107 in ITU-T V.24.
See section 1.9.1 for functional description.
See section 2.6.1 for external circuit design-in.
RI
7
O
UART ring indicator
output
1.8 V, Circuit 125 in ITU-T V.24.
See section 1.9.1 for functional description.
See section 2.6.1 for external circuit design-in.
DTR
9
I
UART data terminal
ready input
1.8 V, Circuit 108/2 in ITU-T V.24.
Internal active pull-up to V_INT.
See section 1.9.1 for functional description.
See section 2.6.1 for external circuit design-in.
DCD
8
O
UART data carrier
detect output
1.8 V, Circuit 109 in ITU-T V.24.
See section 1.9.1 for functional description.
See section 2.6.1 for external circuit design-in.
USB
VUSB_DET
17
I
USB detect input
VBUS (5 V typical) USB supply generated by the host must
be connected to this input pin to enable the USB interface.
Test-Point for diagnostic / FW update access is recommended
See section 1.9.2 for functional description.
See section 2.6.2 for external circuit design-in.
USB_D-
28
I/O
USB Data Line D-
USB interface for AT commands, data communication,
FOAT, FW update by u-blox dedicated tool and diagnostic.
90 nominal differential impedance (Z0)
30 nominal common mode impedance (ZCM)
Pull-up or pull-down resistors and external series resistors as
required by the USB 2.0 specifications [4] are part of the
USB pin driver and need not be provided externally.
Test-Point for diagnostic / FW update access is recommended.
See section 1.9.2 for functional description.
See section 2.6.2 for external circuit design-in.
USB_D+
29
I/O
USB Data Line D+
USB interface for AT commands, data communication,
FOAT, FW update by u-blox dedicated tool and diagnostic.
90 nominal differential impedance (Z0)
30 nominal common mode impedance (ZCM)
Pull-up or pull-down resistors and external series resistors as
required by the USB 2.0 specifications [4] are part of the
USB pin driver and need not be provided externally.
Test-Point for diagnostic / FW update access is recommended.
See section 1.9.2 for functional description.
See section 2.6.2 for external circuit design-in.

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Function
Pin Name
Pin No
I/O
Description
Remarks
SPI
I2S_WA /
SPI_MOSI
34
O
SPI MOSI
SPI Master Output Slave Input, alternatively configurable as
I2S word alignment
Not supported by “00”, “01” and “02” product versions.
See section 1.9.3 for functional description.
See section 2.6.3 for external circuit design-in.
I2S_RXD /
SPI_MISO
37
I
SPI MISO
SPI Master Input Slave Output, alternatively configurable as
I2S receive data
Not supported by “00”, “01” and “02” product versions.
See section 1.9.3 for functional description.
See section 2.6.3 for external circuit design-in.
I2S_CLK /
SPI_CLK
36
O
SPI clock
SPI clock, alternatively configurable as
I2S clock
Not supported by “00”, “01” and “02” product versions.
See section 1.9.3 for functional description.
See section 2.6.3 for external circuit design-in.
I2S_TXD /
SPI_CS
35
O
SPI Chip Select
SPI Chip Select, alternatively configurable as
I2S transmit data
Not supported by “00”, “01” and “02” product versions.
See section 1.9.3 for functional description.
See section 2.6.3 for external circuit design-in.
SDIO
SDIO_D0
47
I/O
SDIO serial data [0]
Not supported by “00”, “01” and “02” product versions.
See section 1.9.4 for functional description.
See section 2.6.4 for external circuit design-in.
SDIO_D1
49
I/O
SDIO serial data [1]
Not supported by “00”, “01” and “02” product versions.
See section 1.9.4 for functional description.
See section 2.6.4 for external circuit design-in.
SDIO_D2
44
I/O
SDIO serial data [2]
Not supported by “00”, “01” and “02” product versions.
See section 1.9.4 for functional description.
See section 2.6.4 for external circuit design-in.
SDIO_D3
48
I/O
SDIO serial data [3]
Not supported by “00”, “01” and “02” product versions.
See section 1.9.4 for functional description.
See section 2.6.4 for external circuit design-in.
SDIO_CLK
45
O
SDIO serial clock
Not supported by “00”, “01” and “02” product versions.
See section 1.9.4 for functional description.
See section 2.6.4 for external circuit design-in.
SDIO_CMD
46
I/O
SDIO command
Not supported by “00”, “01” and “02” product versions.
See section 1.9.4 for functional description.
See section 2.6.4 for external circuit design-in.
DDC
SCL
27
O
I2C bus clock line
1.8 V open drain, for communication with I2C-slave devices.
Internal pull-up to V_INT: external pull-up is not required.
Not supported by “00” and “01” product versions.
See section 1.9.5 for functional description.
See section 2.6.5 for external circuit design-in.
SDA
26
I/O
I2C bus data line
1.8 V open drain, for communication with I2C-slave devices.
Internal pull-up to V_INT: external pull-up is not required.
Not supported by “00” and “01” product versions.
See section 1.9.5 for functional description.
See section 2.6.5 for external circuit design-in.

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Function
Pin Name
Pin No
I/O
Description
Remarks
Audio
I2S_TXD /
SPI_CS
35
O
I2S transmit data
I2S transmit data, alternatively configurable as
SPI Chip Select
Not supported by “00”, “01” and “02” product versions.
See section 1.10 for functional description.
See section 2.7 for external circuit design-in.
I2S_RXD /
SPI_MISO
37
I
I2S receive data
I2S receive data, alternatively configurable as
SPI Master Input Slave Output
Not supported by “00”, “01” and “02” product versions.
See section 1.10 for functional description.
See section 2.7 for external circuit design-in.
I2S_CLK /
SPI_CLK
36
I/O
I2S clock
I2S clock, alternatively configurable as
SPI clock
Not supported by “00”, “01” and “02” product versions.
See section 1.10 for functional description.
See section 2.7 for external circuit design-in.
I2S_WA /
SPI_MOSI
34
I/O
I2S word alignment
I2S word alignment, alternatively configurable as
SPI Master Output Slave Input
Not supported by “00”, “01” and “02” product versions.
See section 1.10 for functional description.
See section 2.7 for external circuit design-in.
GPIO
GPIO1
16
I/O
GPIO
1.8 V GPIO with alternatively configurable functions.
See section 1.11 for functional description.
See section 2.8 for external circuit design-in.
GPIO2
23
I/O
GPIO
1.8 V GPIO with alternatively configurable functions.
See section 1.11 for functional description.
See section 2.8 for external circuit design-in.
GPIO3
24
I/O
GPIO
1.8 V GPIO with alternatively configurable functions.
See section 1.11 for functional description.
See section 2.8 for external circuit design-in.
GPIO4
25
I/O
GPIO
1.8 V GPIO with alternatively configurable functions.
See section 1.11 for functional description.
See section 2.8 for external circuit design-in.
GPIO5
42
I/O
GPIO
1.8 V GPIO with alternatively configurable functions.
See section 1.11 for functional description.
See section 2.8 for external circuit design-in.
GPIO6
19
I/O
GPIO
1.8 V GPIO with alternatively configurable functions.
See section 1.11 for functional description.
See section 2.8 for external circuit design-in.
Reserved
RSVD
33
N/A
Reserved pin
This pin can be connected to GND.
See sections 1.12 and 2.9
RSVD
2, 31
N/A
Reserved pin
Leave unconnected.
See sections 1.12 and 2.9
Table 3: SARA-R4 series module pin definition, grouped by function

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1.4 Operating modes
SARA-R4 series modules have several operating modes. The operating modes are defined in Table 4 and
described in detail in Table 5, providing general guidelines for operation.
General Status
Operating Mode
Definition
Power-down
Not-Powered Mode
VCC supply not present or below operating range: module is switched off.
Power-Off Mode
VCC supply within operating range and module is switched off.
Normal Operation
Deep-Sleep Mode
RTC runs with 32 kHz reference internally generated.
Active Mode
Module processor core runs with 19.2 MHz reference generated by the internal oscillator
Connected Mode
RF Tx/Rx data connection enabled and processor core runs with 19.2 MHz reference.
Table 4: SARA-R4 series modules operating modes definition
Mode
Description
Transition between operating modes
Not-Powered
Module is switched off.
Application interfaces are not accessible.
When VCC supply is removed, the modules enter not-powered mode.
When in not-powered mode, the module can enter power-off mode
applying VCC supply (see 1.6.1).
Power-Off
Module is switched off: normal shutdown by an
appropriate power-off event (see 1.6.2).
Application interfaces are not accessible.
The modules enter power-off mode from active mode when the host
processor implements a proper switch-off procedure, by sending the
AT+CPWROFF command or by using the PWR_ON pin (see 1.6.2).
When in power-off mode, the modules can be switched on by the host
processor using the PWR_ON input pin (see 1.6.1).
When in power-off mode, the modules enter not-powered mode by
removing VCC supply.
Deep-Sleep
Only the internal 32 kHz reference is active.
The RF section and the application interfaces are
temporarily disabled and switched off: the
module is temporarily not ready to communicate
with an external device by means of the
application interfaces as configured to reduce
the current consumption.
The module enters the low power deep sleep
mode (entering the Power Saving Mode defined
in 3GPP Rel.13) whenever possible, if power
saving configuration is enabled by AT+CPSMS
command (see SARA-R4 series AT Commands
Manual [2]), reducing current consumption (see
1.13.9).
Power saving configuration is not enabled by
default; it can be enabled by AT+CPSMS (see
the SARA-R4 series AT Commands Manual [2]).
The modules automatically switch from the active mode to low power
deep sleep mode whenever possible, upon expiration of “Active
Timer”, entering in the Power Saving Mode defined in 3GPP Rel.13, if
power saving configuration is enabled (see 1.13.9 and the SARA-R4
series AT Commands Manual [2], AT+CPSMS command).
When in low power deep sleep mode, the module switches on to the
active mode upon expiration of “Periodic Update Timer” according to
the Power Saving Mode defined in 3GPP Rel.13 (see 1.13.9 and the
SARA-R4 series AT Commands Manual [2], AT+CPSMS command), or it
can be switched on to the active mode by the host processor using the
PWR_ON input pin (see section 1.6.1).
Active
Module is switched on with application
interfaces enabled or not suspended: the
module is ready to communicate with an
external device by means of the application
interfaces unless power saving configuration is
enabled by AT+CPSMS (see SARA-R4 series AT
Commands Manual [2]).
The modules enter active mode from power-off mode when the host
processor implements a proper switch-on procedure by using the
PWR_ON pin (see 1.6.1).
The modules enter active mode from low power deep sleep mode
upon expiration of “Periodic Update Timer” (see 1.13.9), or when the
host processor implements a proper switch-on procedure by using the
PWR_ON pin (see 1.6.1).
The modules enter power-off mode from active mode when the host
processor implements a proper switch-off procedure (see 1.6.2).
The modules automatically switch from active to low power deep sleep
mode whenever possible, if power saving is enabled (see 1.13.9).
The module switches from active to connected-mode when a RF Tx/Rx
data connection is initiated or when RF Tx/Rx activity is required due to
a connection previously initiated.
The module switches from connected to active mode when a RF Tx/Rx
data connection is terminated or suspended.

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Mode
Description
Transition between operating modes
Connected
RF Tx/Rx data connection is in progress.
The module is prepared to accept data signals
from an external device.
When a data connection is initiated, the module enters connected
mode from active mode.
Connected-mode is suspended if Tx/Rx data is not in progress. In such
cases the module automatically switches from connected to active
mode and then, if power saving configuration is enabled by the
AT+CPSMS command, the module automatically switches to low
power deep sleep mode whenever possible. Vice-versa, the module
wakes up from low power deep sleep mode to active mode and then
connected mode if RF Tx/Rx activity is necessary.
When a data connection is terminated, the module returns to the
active-mode.
Table 5: SARA-R4 series modules operating modes description
Figure 2 describes the transition between the different operating modes.
If power saving is enabled,
and Active Timer is expired
•Upon expiration of the
Periodic Update Timer
•Using PWR_ON pin
Incoming/outgoing data
or other dedicated device
network communication
No RF Tx/Rx in progress,
Communication dropped
Remove VCC
Switch ON:
•PWR_ON
Not
powered
Power off
ActiveConnected Deep Sleep
Switch OFF:
•AT+CPWROFF
•PWR_ON
Apply VCC
Figure 2: SARA-R4 series modules operating modes transitions

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1.5 Supply interfaces
1.5.1 Module supply input (VCC)
The modules must be supplied via the three VCC pins that represent the module power supply input.
During operation, the current drawn by the SARA-R4 series modules through the VCC pins can vary by several
orders of magnitude, depending on the operating mode and state (as described in sections 1.5.1.2, 1.5.1.3 and
1.5.1.4).
It is important that the supply source is able to support the average current consumption occurring during a LTE
transmission at maximum RF power level.
1.5.1.1 VCC supply requirements
Table 6 summarizes the requirements for the VCC modules supply. See section 2.2.1 for suggestions to properly
design a VCC supply circuit compliant with the requirements listed in Table 6.
The supply circuit affects the RF compliance of the device integrating SARA-R4 series modules
with applicable required certification schemes as well as antenna circuit design. Compliance is
guaranteed if the requirements summarized in the Table 6 are fulfilled.
Item
Requirement
Remark
VCC nominal voltage
Within VCC normal operating range:
3.20 V min. / 4.20 V max
RF performance is guaranteed when VCC voltage is inside
the normal operating range limits.
RF performance may be affected when VCC voltage is
outside the normal operating range limits, though the
module is still fully functional until the VCC voltage is
inside the extended operating range limits.
VCC voltage during
normal operation
Within VCC extended operating range:
3.00 V min. / 4.30 V max
VCC voltage must be above the extended operating range
minimum limit to switch-on the module.
The module may switch-off when the VCC voltage drops
below the extended operating range minimum limit.
Operation above VCC extended operating range is not
recommended and may affect device reliability.
VCC average current
Support with adequate margin the highest averaged
VCC current consumption value in connected-mode
conditions specified in SARA-R4 Data Sheet [1]
The maximum average current consumption can be
greater than the specified value according to the actual
antenna mismatching, temperature and supply voltage.
Section 1.5.1.2 describes current consumption profiles in
connected-mode.
VCC peak current
Support with adequate margin the highest peak VCC
current consumption value in Tx connected-mode
conditions specified in SARA-R4 Data Sheet [1]
The maximum peak Tx current consumption can be
greater than the specified value according to the actual
antenna mismatching, temperature and supply voltage.
Section 1.5.1.2 describes current consumption profiles in
connected-mode.
VCC voltage ripple
during LTE Tx
Noise in the supply pins has to be minimized
High supply voltage ripple values during RF transmissions
in connected-mode directly affect the RF compliance with
the applicable certification schemes.
Table 6: Summary of VCC modules supply requirements

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1.5.1.2 VCC current consumption in connected-mode
During an LTE Category M1 connection, the SARA-R4 series modules transmit and receive in half duplex mode.
The current consumption depends on output RF power, which is always regulated by the network (the current
base station) sending power control commands to the module. These power control commands are logically
divided into a slot of 0.5 ms (time length of one Resource Block), thus the rate of power change can reach a
maximum rate of 2 kHz.
Figure 3 shows an example of SARA-R4 modules’ current consumption profile versus time in connected-mode:
transmission is enabled for one sub-frame (1 ms) according to LTE Category M1 half duplex connected-mode.
Detailed current consumption values can be found in SARA-R4 series Data Sheet [1].
Time
[ms]
Current [mA]
Current consumption value
depends on TX power and
actual antenna load
1 Slot
1 Resource Block
(0.5 ms) 1 LTE Radio Frame
(10 ms)
0
300
200
100
500
400
Figure 3: VCC current consumption profile versus time during LTE Cat M1 half duplex connection
1.5.1.3 VCC current consumption in low power deep sleep mode (power saving enabled)
The power saving configuration is by default disabled, but it can be enabled using the AT+CPSMS command (see
SARA-R4 series AT Commands Manual [2] and section 1.13.9).
When power saving is enabled, the module automatically enters the PSM low power deep sleep mode whenever
possible, reducing current consumption down to a steady value in the µA range: only the RTC runs with internal
32 kHz reference clock frequency.
Detailed current consumption values can be found in SARA-R4 series Data Sheet [1].
Due to RTC running during PSM mode, the Cal-RC turns on the chrystal every ~10 s to calibrate the RC
oscillator, as a consequence, a very low spike in current consumption will be observed.

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1.5.1.4 VCC current consumption in active mode (power saving disabled)
The active mode is the state where the module is switched on and ready to communicate with an external device
by means of the application interfaces (as the USB or the UART serial interface). The module processor core is
active, and the 19.2 MHz reference clock frequency is used.
If power saving configuration is disabled, as it is by default (see SARA-R4 series AT Commands Manual [2],
+CPSMS AT command for details), the module does not automatically enter the PSM low power deep sleep
mode whenever possible: the module remains in active mode. Otherwise, if the power saving configuration is
enabled, the module enters PSM low power deep sleep mode whenever possible (see section 1.13.9).
Figure 4 illustrates a typical example of the module current consumption profile when the module is in active
mode. In such case, the module is registered with the network and, while active-mode is maintained, the
receiver is periodically activated to monitor the paging channel for paging block reception.
Detailed current consumption values can be found in SARA-R4 series Data Sheet [1].
ACTIVE MODE
Paging period
Time [s]
Current [mA]
Time [ms]
Current [mA]
RX
Enabled
0
100
0
100
Figure 4: VCC current consumption profile with power saving disabled and module registered with the network: active-mode is
always held and the receiver is periodically activated to monitor the paging channel for paging block reception
1.5.2 Generic digital interfaces supply output (V_INT)
The V_INT output pin of the SARA-R4 series modules is generated by the module internal power management
circuitry when the module is switched on and it is not in the deep sleep power saving mode.
The typical operating voltage is 1.8 V, whereas the current capability is specified in the SARA-R4 series Data
Sheet [1]. The V_INT voltage domain can be used in place of an external discrete regulator as a reference
voltage rail for external components.

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1.6 System function interfaces
1.6.1 Module power-on
When the SARA-R4 series modules are in the not-powered mode (i.e. the VCC module supply is not applied),
they can be switched on as follows:
Rising edge on the VCC input pins to a valid voltage level, and then a low logic level has to be held at the
PWR_ON input pin for a valid time.
When the SARA-R4 series modules are in the power-off mode (i.e. switched off) or in the PSM low power mode,
with a valid VCC supply applied, they can be switched on as follows:
Low pulse on the PWR_ON pin for a valid time period
The PWR_ON input pin is equipped with an internal active pull-up resistor. Detailed electrical characteristics with
voltages and timings are described in SARA-R4 series Data Sheet [1].
Figure 5 shows the module switch-on sequence from the not-powered mode, describing the following phases:
The external power supply is applied to the VCC module pins
The PWR_ON pin is held low for a valid time
All the generic digital pins of the module are tri-stated until the switch-on of their supply source (V_INT).
The internal reset signal is held low: the baseband core and all the digital pins are held in the reset state.
When the internal reset signal is released, any digital pin is set in a proper sequence from the reset state to
the default operational configured state. The duration of this pins’ configuration phase differs within generic
digital interfaces and the USB interface due to host / device enumeration timings (see section 1.9.2).
The module is fully ready to operate after all interfaces are configured.
VCC
PWR_ON
RESET_N
V_INT
Internal Reset
System State
BB Pads State
Internal Reset →Operational Operational
Internal
Reset
OFF
ON
Tristate / Floating
Start of interface
configuration
Module interfaces
are configured
Start-up
event
~4.5 s
0 s
Figure 5: SARA-R4 series switch-on sequence description
The Internal Reset signal is not available on a module pin, but the host application can monitor the V_INT
pin to sense the start of the SARA-R4 series module switch-on sequence.
Before the switch-on of the generic digital interface supply source (V_INT) of the module, no voltage
driven by an external application should be applied to any generic digital interface of the module.
Before the SARA-R4 series module is fully ready to operate, the host application processor should not
send any AT command over the AT communication interfaces (USB, UART) of the module.
The duration of the SARA-R4 series modules’ switch-on routine can vary depending on the application /
network settings and the concurrent module activities.

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1.6.2 Module power-off
SARA-R4 series can be properly switched off by:
AT+CPWROFF command (see SARA-R4 series AT Commands Manual [2]). The current parameter settings are
saved in the module’s non-volatile memory and a proper network detach is performed.
Low pulse on the PWR_ON pin for a valid time period (see SARA-R4 series Data Sheet [1]).
An abrupt under-voltage shutdown occurs on SARA-R4 series modules when the VCC module supply is
removed. If this occurs, it is not possible to perform the storing of the current parameter settings in the module’s
non-volatile memory or to perform the proper network detach.
It is highly recommended to avoid an abrupt removal of the VCC supply during SARA-R4 series modules
normal operations.
An abrupt hardware shutdown occurs on SARA-R4 series modules when a low level is applied on RESET_N pin.
In this case, the current parameter settings are not saved in the module’s non-volatile memory and a proper
network detach is not performed.
It is highly recommended to avoid an abrupt hardware shutdown of the module by forcing a low level on
the RESET_N input pin during module normal operation: the RESET_N line should be set low only if reset
or shutdown via AT commands fails or if the module does not reply to a specific AT command after a time
period longer than the one defined in the SARA-R4 series AT Commands Manual [2].
Figure 6 describes the SARA-R4 series modules switch-off sequence started by means of the AT+CPWROFF
command, allowing storage of current parameter settings in the module’s non-volatile memory and a proper
network detach, with the following phases:
When the +CPWROFF AT command is sent, the module starts the switch-off routine.
The module replies OK on the AT interface: the switch-off routine is in progress.
At the end of the switch-off routine, all the digital pins are tri-stated and all the internal voltage regulators
are turned off, including the generic digital interfaces supply (V_INT).
Then, the module remains in switch-off mode as long as a switch on event does not occur (e.g. applying a
proper low level to PWR_ON), and enters not-powered mode if the supply is removed from the VCC pins.
VCC
PWR_ON
RESET_N
V_INT
Internal Reset
System State
BB Pads State Operational
OFF
Tristate / Floating
ON
Operational →Tristate
AT+CPWROFF
sent to the module
OK
replied by the module
VCC can be
removed
Figure 6: SARA-R4 series switch-off sequence by means of AT+CPWROFF command
The Internal Reset signal is not available on a module pin, but it is recommended to monitor the V_INT
pin to sense the end of the switch-off sequence: VCC supply can be removed only after V_INT goes low.
The duration of each phase in the SARA-R4 series modules’ switch-off routines can largely vary depending
on the application / network settings and the concurrent module activities.