Ublox SARA-N210 Quick setup guide

SARA-N2 series
Power-optimized NB-IoT (LTE Cat NB1) modules
System Integration Manual
Abstract
This document describes the features and the system integration of the SARA-N2 series NB-IoT
modules. These modules are a complete and cost efficient solution offering single-band and
dual-band data transmission for the Internet of Things technology in the compact SARA form factor.
www.u-blox.com
UBX-17005143 - R06

SARA-N2 series - System Integration Manual
UBX-17005143 - R06 Page 2 of 82
Document Information
Title
SARA-N2 series
Subtitle
Power-optimized NB-IoT (LTE Cat NB1) modules
Document type
System Integration Manual
Document number
UBX-17005143
Revision and date
R06
30-Nov-2018
Disclosure Restriction
Product status
Corresponding content status
Functional Sample
Draft
For functional testing. Revised and supplementary data will be published later.
In Development /
Prototype
Objective Specification
Target values. Revised and supplementary data will be published later.
Engineering Sample
Advance Information
Data based on early testing. Revised and supplementary data will be published later.
Initial Production
Early Production Information
Data from product verification. Revised and supplementary data may be published later.
Mass Production /
End of Life
Production Information
Document contains the final product specification.
This document applies to the following products:
Product name
Type number
Modem version
Application version
PCN reference
Product status
SARA-N200
SARA-N200-02B-00
06.57
A07.03
UBX-18005015
End of Life
SARA-N200-02B-01
06.57
A09.06
UBX-18048558
Mass Production
SARA-N201
SARA-N201-02B-00
06.57
A07.03
UBX-18005015
End of Life
SARA-N201-02B-01
06.57
A08.05
UBX-18023224
Mass Production
SARA-N210
SARA-N210-02B-00
06.57
A07.03
UBX-18005015
End of Life
SARA-N210-02B-01
06.57
A09.06
UBX-18048558
Mass Production
SARA-N211
SARA-N211-02X-00
06.57
A07.03
UBX-18005015
End of Life
SARA-N211-02X-01
06.57
A09.06
UBX-18048558
Mass Production
SARA-N280
SARA-N280-02B-00
06.57
A07.03
UBX-18005015
End of Life
SARA-N280-02B-01
06.57
A09.06
UBX-18048558
Mass Production
u-blox or third parties may hold intellectual property rights in the products, names, logos and designs included in this document.
Copying, reproduction, modification or disclosure to third parties of this document or any part thereof is only permitted with the
express written permission of u-blox.
The information contained herein is provided “as is” and u-blox assumes no liability for its use. No warranty, either express or
implied, is given, including but not limited to, with respect to the accuracy, correctness, reliability and fitness for a particular
purpose of the information. This document may be revised by u-blox at any time without notice. For the most recent documents,
visit www.u-blox.com.
Copyright © u-blox AG.

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Contents
Document Information................................................................................................................................ 2
Contents ..........................................................................................................................................................3
1System description...............................................................................................................................6
1.1 Overview........................................................................................................................................................ 6
1.2 Architecture ................................................................................................................................................. 7
1.3 Pin-out ...........................................................................................................................................................8
1.4 Operating modes....................................................................................................................................... 10
1.5 Supply interfaces ....................................................................................................................................... 11
1.5.1 Module supply input (VCC) .............................................................................................................. 11
1.5.2 Generic digital interfaces supply output (V_INT)....................................................................... 13
1.6 System function interfaces .................................................................................................................... 14
1.6.1 Module power-on .............................................................................................................................. 14
1.6.2 Module power-off.............................................................................................................................. 15
1.6.3 Module reset ...................................................................................................................................... 15
1.7 Antenna interface ..................................................................................................................................... 16
1.7.1 Antenna RF interface (ANT)........................................................................................................... 16
1.7.2 Antenna detection interface (ANT_DET)......................................................................................17
1.8 SIM interface...............................................................................................................................................17
1.9 Serial interfaces .........................................................................................................................................17
1.9.1 Asynchronous serial interface (UART) ..........................................................................................17
1.9.2 Secondary asynchronous serial interface (Secondary UART)................................................. 19
1.9.3 DDC (I2C) interface............................................................................................................................ 19
1.10 General Purpose Input/Output (GPIO) ..................................................................................................20
1.11 Reserved pins (RSVD) ..............................................................................................................................20
2Design-in................................................................................................................................................. 21
2.1 Overview.......................................................................................................................................................21
2.2 Supply interfaces ......................................................................................................................................22
2.2.1 Module supply (VCC)........................................................................................................................22
2.2.2 Interface supply (V_INT).................................................................................................................. 31
2.3 System functions interfaces ..................................................................................................................32
2.3.1 Module reset (RESET_N).................................................................................................................32
2.4 Antenna interface .....................................................................................................................................33
2.4.1 Antenna RF interface (ANT)...........................................................................................................33
2.4.2 Antenna detection interface (ANT_DET).....................................................................................40

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2.5 SIM interface..............................................................................................................................................43
2.6 Serial interfaces ........................................................................................................................................46
2.6.1 Asynchronous serial interface (UART) .........................................................................................46
2.6.2 Secondary asynchronous serial interface (Secondary UART).................................................48
2.6.3 DDC (I2C) interface............................................................................................................................49
2.7 General Purpose Input/Output (GPIO) ..................................................................................................49
2.8 Reserved pins (RSVD) ..............................................................................................................................49
2.9 Module placement ....................................................................................................................................50
2.10 Module footprint and paste mask ......................................................................................................... 51
2.11 SARA-N211 integration in devices intended for use in potentially explosive atmospheres.......52
2.11.1 General guidelines ............................................................................................................................52
2.11.2 Guidelines for VCC supply circuit design .....................................................................................54
2.11.3 Guidelines for antenna RF interface design................................................................................55
2.12 Schematic for SARA-N2 series module integration ..........................................................................56
2.13 Design-in checklist....................................................................................................................................57
2.13.1 Schematic checklist.........................................................................................................................57
2.13.2 Layout checklist................................................................................................................................57
2.13.3 Antenna checklist.............................................................................................................................58
3Handling and soldering ..................................................................................................................... 59
3.1 Packaging, shipping, storage and moisture preconditioning ..........................................................59
3.2 Handling ......................................................................................................................................................59
3.3 Soldering .....................................................................................................................................................60
3.3.1 Soldering paste .................................................................................................................................60
3.3.2 Reflow soldering................................................................................................................................60
3.3.3 Optical inspection............................................................................................................................. 61
3.3.4 Cleaning .............................................................................................................................................. 61
3.3.5 Repeated reflow soldering ..............................................................................................................62
3.3.6 Wave soldering ..................................................................................................................................62
3.3.7 Hand soldering ..................................................................................................................................62
3.3.8 Rework ................................................................................................................................................62
3.3.9 Conformal coating ............................................................................................................................62
3.3.10 Casting................................................................................................................................................63
3.3.11 Grounding metal covers ..................................................................................................................63
3.3.12 Use of ultrasonic processes ...........................................................................................................63
4Approvals............................................................................................................................................... 64
4.1 Approvals overview ...................................................................................................................................64

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4.2 European Conformance CE mark ..........................................................................................................65
4.3 ATEX conformance...................................................................................................................................66
4.4 Chinese conformance ..............................................................................................................................67
4.5 Taiwanese conformance .........................................................................................................................67
5Product testing ................................................................................................................................... 68
5.1 u-blox in-series production test .............................................................................................................68
5.2 Test parameters for OEM manufacturer.............................................................................................68
5.2.1 “Go/No go” tests for integrated devices ......................................................................................69
5.2.2 RF functional tests...........................................................................................................................69
Appendix ........................................................................................................................................................ 71
AMigration between SARA modules................................................................................................ 71
A.1 Overview.......................................................................................................................................................71
A.2 Pin-out comparison between SARA-G3, SARA-U2, SARA-R4 and SARA-N2 modules..............73
A.3 Schematic for SARA-G3 /-U2 /-R4 /-N2 modules integration..........................................................78
BGlossary ..................................................................................................................................................79
Related documents .................................................................................................................................... 81
Revision history........................................................................................................................................... 81
Contact.......................................................................................................................................................... 82

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1System description
1.1 Overview
SARA-N2 series modules provide a Narrow Band Internet of Things (NB-IoT) solution in the miniature
SARA LGA form factor (26.0 x 16.0 mm, 96-pin). The modules offer IoT data communication over an
extended operating temperature range of –40 to +85 °C, with extremely low power consumption.
The SARA-N2 series includes four variants that support single-band communication over the LTE
bands 5, 8, 20 and 28, plus a dual-band variant designed to operate in the frequency range of the LTE
bands 8 and 20.
SARA-N2 series modules are ideally suited to battery-powered IoT applications characterized by
occasional communications of small amounts of data.
SARA-N2 series modules are the optimal choice for IoT devices designed to operate in locations with
very limited coverage and requiring low energy consumption to permit a very long operating life with
the primary batteries. Examples of applications include and are not limited to: smart grids, smart
metering, telematics, street lighting, environmental monitoring and control, security and asset
tracking.
Table 1 describes a summary of interfaces and features provided by SARA-N2 series modules.
Model
Region
Bands
Positioning
Interfaces
Features
Grade
3GPP Release Baseline
3GPP Category
NB-IoT bands
GNSS via modem
AssistNow Software
CellLocate®
UART
USB 2.0
SPI
DDC (I2C)
GPIO
Antenna supervisor
Power Save Mode
eDRX
Deep sleep mode
Embedded UDP stack
CoAP
FW update over AT (FOAT)
FW update over the air (FOTA)
Standard
Professional
Automotive
SARA-N200
Europe
APAC
13
NB1
8
2
●
●
●
●
●
●
●
●
●
SARA-N201
APAC
13
NB1
5
2
●
●
●
●
●
●
●
●
●
SARA-N210
Europe
13
NB1
20
2
●
●
●
●
●
●
●
●
●
SARA-N211
Europe
13
NB1
8,20
2
●
●
●
●
●
●
●
●
●
SARA-N280
South America
APAC
13
NB1
28
2
●
●
●
●
●
●
●
●
●
Table 1: SARA-N2 series characteristics summary

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Table 2 summarizes cellular radio access technology characteristics of SARA-N2 series modules.
Item
SARA-N200
SARA-N201
SARA-N210
SARA-N211
SARA-N280
NB-IoT protocol stack
3GPP Release 13
3GPP Release 13
3GPP Release 13
3GPP Release 13
3GPP Release 13
Operating band
Band 8 (900 MHz)
Band 5 (850 MHz)
Band 20 (800 MHz)
Band 8 (900 MHz),
Band 20 (800 MHz)
Band 28 (700 MHz)
Deployment mode
In-Band
Guard-Band
Standalone
In-Band
Guard-Band
Standalone
In-Band
Guard-Band
Standalone
In-Band
Guard-Band
Standalone
In-Band
Guard-Band
Standalone
Power Class
Class 3 (23 dBm)
Class 3 (23 dBm)
Class 3 (23 dBm)
Class 3 (23 dBm)
Class 3 (23 dBm)
Data rate
LTE category NB1:
Up to 31.25 kb/s UL
Up to 27.2 kb/s DL
LTE category NB1:
Up to 31.25 kb/s UL
Up to 27.2 kb/s DL
LTE category NB1:
Up to 31.25 kb/s UL
Up to 27.2 kb/s DL
LTE category NB1:
Up to 31.25 kb/s UL
Up to 27.2 kb/s DL
LTE category NB1:
Up to 31.25 kb/s UL
Up to 27.2 kb/s DL
Table 2: SARA-N2 series NB-IoT characteristics summary
1.2 Architecture
Figure 1 summarizes the architecture of SARA-N2 series modules, describing the internal blocks of
the modules, consisting of the RF, Baseband and Power Management main sections, and the available
interfaces.
Memory
V_INT
38.4 MHz 32.768 kHz
RF
Transceiver
Power
Management
Baseband
ANT SAW
Filter
Switch
PA
VCC (Supply)
DDC (I2C)
UART
SIM
Secondary UART
RESET_N
GPIO
Antenna detection
Figure 1: SARA-N2 series modules block diagram
The RF section is composed of the following main elements:
LTE Power Amplifier, which amplifies the signals modulated by the RF transceiver
RF switches, which connect the antenna input/output pin (ANT) of the module to the suitable
RX/TX path
RX low-loss SAW filters
38.4 MHz crystal oscillator for the clock reference in active-mode and connected-mode
The Baseband and Power Management section is composed of the following main elements:
Baseband processor
Flash memory
Voltage regulators to derive all the system supply voltages from the module supply VCC
Circuit for the RTC clock reference in low power deep-sleep

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1.3 Pin-out
Table 3 lists the pin-out of the SARA-N2 series modules, with pins grouped by function.
Function
Pin Name
Pin No
I/O
Description
Remarks
Power
VCC
51, 52, 53
I
Module supply
input
All VCC pins must be connected to external supply.
VCC supply circuit affects the RF performance and
compliance of the device integrating the module with
applicable required certification schemes.
See section 1.5.1 for description and requirements.
See section 2.2.1 for external circuit design-in.
GND
1, 3, 5, 14, 20-22,
30, 32, 43, 50, 54,
55, 57-61, 63-96
N/A
Ground
GND pins are internally connected to each other.
External ground connection affects the RF and thermal
performance of the device.
V_INT
4
O
Generic Digital
Interfaces supply
output
V_INT = 1.8 V (typical) supply output, generated by
internal linear LDO regulator when the radio is on.
Provide a test point on this pin for diagnostic purpose.
See section 1.5.2 for functional description.
See section 2.2.2 for external circuit design-in.
System
RESET_N
18
I
External reset
input
Internal 78 kpull-up to VCC.
Provide a test point on this pin for diagnostic purpose.
See section 1.6.3 for functional description.
See section 2.3.1 for external circuit design-in.
Antenna
ANT
56
I/O
RF input/output
for antenna
50 nominal characteristic impedance.
Antenna circuit affects the RF performance and
compliance of the device integrating the module with
applicable required certification schemes.
See section 1.7 for description and requirements.
See section 2.4 for external circuit design-in.
ANT_DET
62
I
Input for antenna
detection
ANT_DET not supported by "02" product versions.
ADC input for antenna detection function.
See section 1.7.2 for functional description.
See section 2.4.2 for external circuit design-in.
SIM
VSIM
41
O
SIM supply output
VSIM = 1.80 V (typical).
See section 1.8 for functional description.
See section 2.5 for external circuit design-in.
SIM_IO
39
I/O
SIM data
Internal 4.7 kpull-up to VSIM.
See section 1.8 for functional description.
See section 2.5 for external circuit design-in.
SIM_CLK
38
O
SIM clock
Clock for external SIM, operating at VSIM voltage level.
See section 1.8 for functional description.
See section 2.5 for external circuit design-in.
SIM_RST
40
O
SIM reset
Reset for external SIM, operating at VSIM voltage level.
See section 1.8 for functional description.
See section 2.5 for external circuit design-in.

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Function
Pin Name
Pin No
I/O
Description
Remarks
UART
RXD
13
O
UART data output
Circuit 104 (RXD) in ITU-T V.24, for AT command and
data, FOAT and FW upgrade via dedicated tool.
It operates at VCC voltage level.
Provide a test point on this pin for diagnostic purpose.
See section 1.9.1 for functional description.
See section 2.6.1 for external circuit design-in.
TXD
12
I
UART data input
Circuit 103 (TXD) in ITU-T V.24, for AT command and data,
FOAT and FW upgrade via dedicated tool.
No internal pull-up / pull-down.
Provide a test point on this pin for diagnostic purpose.
See section 1.9.1 for functional description.
See section 2.6.1 for external circuit design-in.
CTS
11
O
UART clear to send
output
HW flow control output signal (Circuit 106 in ITU-T V.24)
is not supported by "02" product versions.
The pin can be configured as described in section 1.10.
The pin operates at VCC voltage level.
See section 1.9.1 for functional description.
See section 2.6.1 for external circuit design-in.
RTS
10
I
UART ready to
send input
HW flow control input signal (Circuit 105 in ITU-T V.24) is
not supported by "02" product versions.
Internal active pull-up to VCC.
See section 1.9.1 for functional description.
See section 2.6.1 for external circuit design-in.
DDC
SCL
27
O
I2C bus clock line
I2C interface is not supported by "02" product versions.
1.8 V open drain, without internal pull-up.
The pin operates at V_INT voltage level.
See section 1.9.3 for functional description.
See section 2.6.3 for external circuit design-in.
SDA
26
I/O
I2C bus data line
I2C interface is not supported by "02" product versions.
1.8 V open drain, without internal pull-up.
The pin operates at V_INT voltage level.
See section 1.9.3 for functional description.
See section 2.6.3 for external circuit design-in.
GPIO
GPIO1
16
I/O
GPIO
1.8 V secondary UART data output, for diagnostic
purpose.
The pin operates at V_INT voltage level.
Provide a test point on this pin for diagnostic purpose.
See sections 1.9.2 and 1.10 for functional description.
See sections 2.6.2 and 2.7 for external circuit design-in.
GPIO2
24
I/O
GPIO
GPIO2 function is not supported by "02" product versions.
The pin operates at V_INT voltage level.
See section 1.10 for functional description.
See section 2.7 for external circuit design-in.
Reserved
RSVD
33
N/A
RESERVED pin
This pin can be connected to GND.
See sections 1.11 and 2.8.
RSVD
2, 6-9, 15, 17,19, 23,
25, 28, 29, 31, 34-
37, 42, 44-49
N/A
RESERVED pin
Leave unconnected.
See sections 1.11 and 2.8.
Table 3: SARA-N2 series modules pin definition, grouped by function

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1.4 Operating modes
SARA-N2 series modules have several operating modes. The operating modes defined in Table 4 and
described in detail in Table 5 provide general guidelines for operation.
Figure 2 describes the transition between the different operating modes.
General Status
Operating Mode
Definition
Power-down
Not-Powered Mode
VCC supply not present or below operating range: module is switched off.
Normal operation
Deep-sleep mode
Module processor runs with internal 32 kHz reference; lowest current consumption
Active-Mode
Module processor runs with internal 38.4 MHz reference.
Connected-Mode
Module processor runs with internal 38.4 MHz reference; data
transmission/reception or signaling activity with the network enabled.
Table 4: Module operating modes definition
Mode
Description
Transition between operating modes
Not-Powered
Module is switched off.
Application interfaces are not accessible.
When VCC supply is removed, the module enters not-powered
mode.
When in not-powered mode, the modules can be switched on
applying VCC supply (see section 2.2.1) so that the module
switches from not-powered to active-mode.
Active
Module is switched on with application
interfaces enabled or not suspended: the
module is ready to communicate with an
external device by means of the application
interfaces.
The module enters active mode from not-powered mode by
applying VCC supply (see section 2.2.1).
Then, the module automatically switches from active to
deep-sleep mode whenever possible or switches to connected
mode in case there is any data to transmit or receive.
Deep-sleep
Only the internal 32 kHz reference is active;
the RF section is completely disabled. This is
the lowest current consumption mode.
The UART interface is still completely
functional and the module can accept and
respond to any AT command.
All the other interfaces are disabled. If a
trace is active on the secondary UART, it is
automatically suspended when the module
enters this mode.
In this mode the module is not able to
receive any down-link message or data
from the network. To do so, the module
must be in the active or connected mode.
The module automatically enters deep-
sleep mode whenever possible after a
network dependent time of inactivity.
The module automatically switches from active mode to deep-
sleep mode whenever possible.
The module wakes up from deep-sleep to active mode in the
following events:
Automatic periodic monitoring of the paging channel for
the paging block reception and periodic tracking area
update (TAU) according to network conditions
A send-data request is issued to the module using the
related commands (for more details, see the SARA-N2
series AT Commands Manual [3] and the u-blox NB-IoT
Application Development Guide [4]).
Connected
The module is transmitting/receiving data
to/from the network.
Both internal references at 32 kHz and
38.4 MHz are active.
When a data connection is initiated, the module enters
connected mode from active mode.
Connected-mode is suspended if Tx/Rx data is not in progress.
In such cases the module automatically switches from
connected to active mode and then the module automatically
switches to deep sleep mode whenever possible. Vice-versa, the
module wakes up re-entering connected mode upon resume of
RF Tx/Rx activity.
When a data connection is terminated, the module returns to
the active-mode and then the module automatically switches to
deep sleep mode whenever possible.
Table 5: Module operating modes description

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Switch ON:
•Apply VCC
If there is no activity for
a defined time interval
•Network paging
•New up-link message request
from the Application Processor
Up-linlk transmission, reception
of network signalling indications
or downlink data reception
No RF Tx/Rx in progress
Not
powered
ActiveConnected Deep-sleep
Switch OFF:
•Remove VCC
Figure 2: Operating modes transitions
1.5 Supply interfaces
1.5.1 Module supply input (VCC)
The modules must be supplied via all the three VCC pins that represent the module power supply
input.
The VCC pins are internally connected to the RF power amplifier and to the integrated Power
Management Unit: all supply voltages needed by the module are generated from the VCC supply by
integrated voltage regulators, including V_INT (digital interfaces supply) and VSIM (SIM card supply).
During operation, the current drawn by the SARA-N2 series modules through the VCC pins can vary
by several orders of magnitude. This ranges from the high peak of current consumption during data
transmission at maximum power level in connected mode, to the low current consumption during
deep-sleep mode (as described in section 1.5.1.2).
1.5.1.1 VCC supply requirements
Table 6 summarizes the requirements for the VCC module supply. See section 2.2.1 for all the
suggestions to properly design a VCC supply circuit compliant to the requirements listed in Table 6.
⚠VCC supply circuit design may affect the RF compliance of the device integrating SARA-N2 series
modules with applicable required certification schemes. Compliance is not guaranteed if the VCC
requirements summarized in the Table 6 are not fulfilled.

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Item
Requirement
Remark
VCC nominal voltage
Within VCC normal operating range:
3.1 V min. / 4.0 V max
The module cannot be switched on if VCC voltage
value is below the normal operating range minimum
limit.
Ensure that the input voltage at VCC pins is above
the minimum limit of the normal operating range
for at least more than 3 s after the module
switch-on.
VCC voltage during
normal operation
Within VCC extended operating range:
2.75 V min. / 4.2 V max
The module may switch off when VCC voltage drops
below the extended operating range minimum limit.
Operation above extended operating range limit is
not recommended and may affect device reliability.
When operating below the normal operating range
minimum limit, the internal PA may not be able to
transmit at the network-required power level.
VCC average current
Support with margin the highest averaged VCC
current consumption value in connected mode
specified in SARA-N2 series Data Sheet [1].
The maximum average current consumption can be
greater than the specified value according to the
actual antenna mismatching, temperature and
supply voltage.
VCC voltage ripple
Noise in the supply has to be minimized
High supply voltage ripple values during RF
transmissions in connected-mode directly affect
the RF compliance with applicable certification
schemes.
Table 6: Summary of VCC supply requirements
☞For the additional specific requirements applicable to the integration of SARA-N211 modules in
devices intended for use in potentially explosive atmospheres, see section 2.11.
1.5.1.2 VCC current consumption profile
Figure 3 shows an example of the module VCC current consumption profile starting from the switch-
on event, followed by different phases and operating modes:
Network registration and context activation procedure
Transmission of an up-link datagram
RRC connection release and related signaling operations
Cyclic paging reception
Deep sleep mode
Timings in the figure are purely indicative since these may significantly change depending on the
network signaling activity. The current consumption peaks occur when the module is in the connected
(transmitting) mode and the value of these peaks is strictly dependent on the transmitted power,
which is regulated by the network. See the electrical specification section in the SARA-N2 series Data
Sheet [1] for more details about the current consumption values in the different modes and the
influence of the transmitting power level.

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A proper power supply circuit for SARA-N2 series modules must be able to withstand the current
values present during the data transmission at maximum power, even though NB-IoT systems should
be designed to keep the module in deep-sleep mode for most of the time, with an extremely low
current consumption in the range of few microamps.
Current [mA]
20
0
150
100
50
0
510 15 20 25 30 4035 Time [s]
Registration and
context activation
RRC connection release
(signaling operations)
Up-link
data
45 50 6055
Cyclic paging reception Deep Sleep
25
0
65 70 8075 85 90 100950
Figure 3: Example of module current consumption from the switch-on event up to deep-sleep mode
1.5.2 Generic digital interfaces supply output (V_INT)
The same 1.8 V voltage domain used internally to supply the generic digital interfaces (GDI) of
SARA-N2 series modules is also available on the V_INT supply output pin, as described in Figure 4.
The internal regulator that generates the V_INT supply is a low drop out (LDO) converter that is
directly supplied from the VCC main supply input of the module.
The V_INT supply output provides internal short circuit protection to limit start-up current and
protect the load to short circuits.
The V_INT voltage regulator output is disabled (i.e. 0 V) when the module is switched off, while it can
be used to monitor the operating mode when the module is switched on:
When the radio is off, the voltage level is kept low (i.e. 0 V)
When the radio is on, the voltage level is maintained high (i.e. 1.8 V)
☞Provide a test point connected to the V_INT pin for diagnostic purpose.
Baseband
Processor
51
VCC
52
VCC
53
VCC
4
V_INT
LDO Digital I/O
Interfaces
Power
Management
SARA-N2 series
Figure 4: SARA-N2 series interfaces supply output (V_INT) simplified block diagram

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1.6 System function interfaces
1.6.1 Module power-on
1.6.1.1 Switch-on events
When the SARA-N2 series modules are in the not-powered mode (i.e. switched off with the VCC
module supply not applied), they can be switched on by:
Rising edge on the VCC supply input to a valid voltage value for module supply, starting from a
voltage value lower than 1.8 V, so that the module switches on applying a proper VCC supply within
the normal operating range. (See SARA-N2 series Data Sheet [1].)
Alternately, the RESET_N pin can be held low during the VCCrising edge, so that the module
switches on by releasing the RESET_N pin when the VCCvoltage stabilizes at its nominal value
within the normal range.
1.6.1.2 Switch-on sequence from not-powered mode
Figure 5 shows the modules power-on sequence from the not-powered mode, describing the following
phases:
The external supply is applied to the VCC module supply inputs, representing the start-up event.
The RESET_N line rises suddenly to high logic level due to internal pull-up to VCC.
The V_INT generic digital interfaces supply output is enabled by the integrated power
management unit.
The RXD UART data output pin also rises to the high logic level, at VCC voltage value
A greeting message is sent on the RXD pin (for more details see SARA-N2 series AT Commands
Manual [3]). From now on the module is fully operational and the UART interface is functional
VCC
RESET_N
V_INT
HIGH when radio is ON
LOW when radio is OFF
RXD
System State
OFF
ON
0 s
~3.5 s
Module is
operational
Start-up
event
Greeting text
Figure 5: SARA-N2 series power-on sequence from not-powered mode
☞No voltage driven by an external application should be applied to the UART interface of the module
before applying the VCC supply, to avoid latch-up of circuits and allow a proper boot of the module.
☞No voltage driven by an external application should be applied to any generic digital interface of
the module (GPIOs, I2C interface) before the switch-on of the generic digital interface supply
source of the module (V_INT), to avoid latch-up of circuits and allow a proper boot of the module.

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1.6.2 Module power-off
The SARA-N2 series modules can be switched off by:
Removal of the VCC supply supply; the voltage drops below the operating range minimum limit
☞It is highly recommended to avoid an abrupt removal of the VCC supply during module normal
operation: the VCC supply should be removed only when the V_INT supply output is switched off
by the module.
1.6.3 Module reset
SARA-N2 series modules can be properly reset (rebooted) by:
AT command (see the SARA-N2 series AT Commands Manual [3] for more details).
This command causes an “internal” or “software” reset of the module, which is an asynchronous reset
of the module baseband processor. The current parameter settings are saved in the module’s non-
volatile memory and a proper network detach is performed: this is the proper way to reset the
modules.
An abrupt hardware reset occurs on SARA-N2 series modules when a low level is applied on the
RESET_N input pin for a specific time period. In this case, the current parameter settings are not
saved in the module’s non-volatile memory and a proper network detach is not performed.
As described in Figure 6, the RESET_N input pin is equipped with an internal active pull-up to the VCC
supply.
Baseband Processor
18
RESET_N
SARA-N2 series
VCC
Reset
~78 k
Figure 6: SARA-N2 series RESET_N input equivalent circuit description
☞For more electrical characteristics details see the SARA-N2 series Data Sheet [1].
☞It is highly recommended to avoid an abrupt hardware reset of the module by forcing a low level on
the RESET_N input pin during module normal operation: the RESET_N line should be set low only
if reset via AT command fails if the module does not provide a reply to a specific AT command after
a time period longer than the one defined in the SARA-N2 series AT Commands Manual [3].
☞Provide a test point connected to the RESET_N pin for diagnostic purpose.

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1.7 Antenna interface
1.7.1 Antenna RF interface (ANT)
The ANT pin of SARA-N2 series modules represents the RF input/output for the cellular RF signals
reception and transmission. The ANT pin has a nominal characteristic impedance of 50 and must
be connected to the antenna through a 50 transmission line for proper RF signals reception and
transmission.
1.7.1.1 Antenna RF interface requirements
Table 7 summarizes the requirements for the antenna RF interface (ANT). See section 2.4.1 for
suggestions to properly design an antenna circuit compliant to these requirements.
⚠The antenna circuit affects the RF compliance of the device integrating SARA-N2 series module
with applicable required certification schemes.
Item
Requirements
Remarks
Impedance
50 nominal characteristic impedance
The nominal characteristic impedance of the
antenna RF connection must match the ANT pin
50 impedance.
Frequency range
See the SARA-N2 series Data Sheet [1]
The required frequency range of the antenna
depends on the operating bands supported by the
cellular module.
Return Loss
S11 < -10 dB (VSWR < 2:1) recommended
S11 < -6 dB (VSWR < 3:1) acceptable
The Return loss or the S11, as the VSWR, refers to the
amount of reflected power, measuring how well the
RF antenna connection matches the 50 
impedance.
The impedance of the antenna RF termination must
match as much as possible the 50 impedance of
the ANT pin over the operating frequency range,
reducing as much as possible the amount of
reflected power.
Efficiency
> -1.5 dB ( > 70%) recommended
> -3.0 dB ( > 50%) acceptable
The radiation efficiency is the ratio of the radiated
power to the power delivered to antenna input: the
efficiency is a measure of how well an antenna
receives or transmits.
The efficiency needs to be enough high over the
operating frequency range to comply with the Over-
The-Air radiated performance requirements, as
Total Radiated Power and Total Isotropic Sensitivity,
specified by certification schemes
Maximum Gain
See section 4.2 for maximum gain limits
The power gain of an antenna is the radiation
efficiency multiplied by the directivity: the maximum
gain describes how much power is transmitted in the
direction of peak radiation to that of an isotropic
source.
The maximum gain of the antenna connected to
ANT pin must not exceed the values stated in
section 4.2 to comply with regulatory agencies
radiation exposure limits.
Input power
> 0.5 W peak
The antenna connected to ANT pin must support the
maximum power transmitted by the modules.
Table 7: Summary of antenna RF interface (ANT) requirements
☞For the additional specific requirements applicable to the integration of SARA-N211 modules in
devices intended for use in potentially explosive atmospheres, see section 2.11.

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1.7.2 Antenna detection interface (ANT_DET)
☞Antenna detection interface is not supported in the "02" version of the product.
The ANT_DET pin is an Analog to Digital Converter (ADC) input used to sense the antenna presence
evaluating the resistance from the ANT pin to GND by means of an external antenna detection circuit
implemented on the application board. This optional functionality can be managed by dedicated AT
command (for more details see the SARA-N2 series AT Commands Manual [3]).
1.8 SIM interface
SARA-N2 series modules provide a high-speed SIM/ME interface working at 1.8 V, which is available
to connect an external SIM / UICC.
The VSIM supply output provides internal short circuit protection to limit start-up current and protect
the external SIM / UICC to short circuits.
1.9 Serial interfaces
SARA-N2 series modules provide the following serial communication interfaces:
UART interface: 5-wire unbalanced asynchronous serial interface, operating at VCC voltage level
(~3.6 V), supporting (see 1.9.1):
oAT command
oFW upgrades by means of the FOAT feature
oFW upgrades by means of the dedicated tool
Auxiliary UART interface: 2-wire unbalanced asynchronous serial interface, operating at V_INT
level (1.8 V), supporting (see 1.9.2):
oTrace log capture (diagnostic purpose)
DDC interface
1
: I2C-bus compatible interface, operating at V_INT level (1.8 V), supporting (see
1.9.3):
oCommunication with external chips and sensors
oCommunication with external u-blox GNSS chips / modules
1.9.1 Asynchronous serial interface (UART)
1.9.1.1 UART features
The UART interface is a 5-wire unbalanced asynchronous serial interface, supporting:
AT command
FW upgrades by means of the FOAT feature
FW upgrades by means of the dedicated tool
The main characteristics of the interface are the following:
Serial port with RS-232 functionality working at the VCC voltage domain (0 V for low data bit or
ON state and ~3.6 V, i.e. VCC, for high data bit or OFF state)
Data lines (RXD as module data output, TXD as module data input)
Hardware flow control lines (CTS as module output, RTS as module input)
Default baud rate: 9600 b/s (4800, 57600 and 115200 b/s baud rates are also supported)
Fixed frame format: 8N1 (8 data bits, No parity, 1 stop bit)
1
Not supported on “02” product version

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The CTS output line can be configured as RING indicator, to signal an incoming message received by
the module or an URC event, or as Network status indicator (for more details see section 1.10 and the
SARA-N2 series AT Commands Manual [3], +URING, +UGPIOC AT commands).
☞Hardware flow control lines CTS and RTS are not supported by "02" product versions.
The UART interface provides RS-232 functionality conforming to the ITU-T V.24 Recommendation
(more details available in ITU Recommendation [5]): SARA-N2 series modules are designed to operate
as a cellular modem, which represents the Data Circuit-terminating Equipment (DCE) according to
ITU-T V.24 Recommendation [5]. The application processor connected to the module through the
UART interface represents the Data Terminal Equipment (DTE).
☞The signal names of the SARA-N2 series modules’ UART interface conform to the ITU-T V.24
Recommendation [5]: e.g. the TXD line represents the data transmitted by the DTE (application
processor data line output) and received by the DCE (module data line input).
Figure 7 describes the 8N1 frame format, which is the default configuration with fixed baud rate.
D0 D1 D2 D3 D4 D5 D6 D7
Start of 1-Byte
transfer
Start Bit
(Always 0)
Possible Start of
next transfer
Stop Bit
(Always 1)
t
bit
= 1/(Baudrate)
Normal Transfer, 8N1
Figure 7: Description of UART default frame format (8N1) with fixed baud rate
1.9.1.2 UART signal behavior
At the module switch-on, before the UART interface initialization (as described in the power-on
sequence reported in Figure 5), each pin is first tri-stated and then is set to its related internal reset
state. At the end of the boot sequence, the UART interface is initialized and the UART interface is
enabled as AT commands interface.
The configuration and the behavior of the UART signals after the boot sequence are described below.
See section 1.4 for definition and description of module operating modes referred to in this section.
RXD signal behavior
The module data output line (RXD) is set by default to the OFF state (high level) at UART initialization.
The greeting message is sent on the RXD line after the completion of the boot sequence to indicate
the completion of the UART interface initialization.
The module holds RXD in the OFF state until the module does not transmit some data.
TXD signal behavior
The module data input line (TXD) is assumed to be controlled by the external host once UART is
initialized.
There is no internal pull-up / pull-down inside the module on the TXD input.

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1.9.1.3 UART and deep sleep mode
To limit the current consumption, SARA-N2 modules automatically enter deep-sleep mode whenever
possible, that is if there is no data to transmit or receive. When in deep-sleep mode the UART interface
is still completely functional and the module can accept and respond to any AT command. All the other
interfaces are disabled.
The application processor should go in standby (or lowest power consumption mode) as soon as the
SARA-N2 module enters the deep-sleep mode and there is no more data to be transmitted.
At any time the DTE can request the module to send data using the related commands (for more
details, see the SARA-N2 series AT Commands Manual [3] and the u-blox NB-IoT Application
Development Guide [4]); these commands automatically force the module to exit the deep-sleep
mode.
1.9.2 Secondary asynchronous serial interface (Secondary UART)
The secondary auxiliary UART interface is a 2-wire unbalanced asynchronous serial interface,
providing:
Trace diagnostic log delivered by the module
The main characteristics of the secondary auxiliary UART interface are:
Serial port with RS-232 functionality working at the V_INT voltage domain (0 V for low data bit or
ON state and 1.8 V, i.e. V_INT, for high data bit or OFF state)
Data line (GPIO1 as module data output)
No flow control
Fixed baud rate: 921600 b/s
Fixed frame format: 8N1 (8 data bits, no parity, 1 stop bit)
☞Provide a test point connected to the GPIO1 pin for diagnostic purpose.
☞The trace diagnostic log is temporarily stopped when the module is in deep-sleep mode.
1.9.3 DDC (I2C) interface
☞DDC (I2C) interface is not supported in the "02" version of the product.
The SDA and SCL pins represent an I2C bus compatible Display Data Channel (DDC) interface,
operating at the V_INT voltage level (1.8 V).

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1.10 General Purpose Input/Output (GPIO)
SARA-N2 series modules provide the following pins:
GPIO1 pin, working at the V_INT (1.8 V) voltage domain, supporting the Secondary UART data
output functionality (see section 1.9.2 and Table 8)
GPIO2 pin, working at the V_INT (1.8 V) voltage domain, not supported by "02" product versions
CTS pin, working at the VCC (3.6 V typical) voltage domain, supporting the Network status
indication and the RING indicator functionality (see section 1.9.1 and Table 8)
For more details about how the pins can be configured, see SARA-N2 series AT Commands
Manual [3], +UGPIOC, +URING AT commands.
☞Provide a test point connected to the GPIO1 pin for diagnostic purpose.
Function
Description
Default GPIO
Configurable GPIOs
Network status indication
Network status: registered home network,
registered roaming, data transmission, no
service
--
CTS
RING indicator
Indicates an incoming message received by the
module or an URC event
--
CTS
Secondary UART
Secondary UART data output for diagnostic
purpose, to capture diagnostic logs delivered
by the module
GPIO1
GPIO1
Pin disabled
Tri-state with an internal active pull-down
enabled
CTS
CTS
Table 8: GPIO custom functions configuration
1.11 Reserved pins (RSVD)
SARA-N2 series modules have pins reserved for future use, marked as RSVD.
All the RSVD pins are to be left unconnected on the application board, except for the RSVD pin number
33 that can be externally connected to ground.