Ublox TOBY-L4 Series Quick setup guide

TOBY-L4 series
LTE Advanced (Cat 6) modules
with 3G and 2G fallback
System Integration Manual
Abstract
This document describes the features and the system integration of
TOBY-L4 series multi-mode cellular modules.
The modules are a complete and cost efficient LTE-FDD, LTE-TDD,
DC-HSPA+, (E)GPRS multi-mode and multi-band solution with uCPU
embedded Linux programming capability. The modules offer up to
301.5 Mb/s download and up to 51.0 Mb/s upload data rates with
Category 6 LTE-Advanced carrier aggregation technology in the
compact TOBY form factor.
www.u-blox.com
UBX-16024839 - R04

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Document Information
Title
TOBY-L4 series
Subtitle
LTE Advanced (Cat 6) modules
with 3G and 2G fallback
Document type
System Integration Manual
Document number
UBX-16024839
Revision, date
R04
08-Feb-2018
Disclosure restriction
Product Status
Corresponding content status
Functional Sample
Draft
For functional testing. Revised and supplementary data will be published later.
In Development /
Prototype
Objective Specification
Target values. Revised and supplementary data will be published later.
Engineering Sample
Advance Information
Data based on early testing. Revised and supplementary data will be published later.
Initial Production
Early Prod. Information
Data from product verification. Revised and supplementary data may be published later.
Mass Production /
End of Life
Production Information
Final product specification.
This document applies to the following products:
Name
Type number
Modem version
Application version
PCN reference
Product status
TOBY-L4006
TOBY-L4006-00A-00
TBD
TBD
TBD
Functional Sample
TOBY-L4006-50A-00
40.24
A00.02
UBX-18007908
Engineering Sample
TOBY-L4106
TOBY-L4106-00A-00
TBD
TBD
TBD
Functional Sample
TOBY-L4106-50A-00
40.24
A00.02
UBX-18007908
Engineering Sample
TOBY-L4206
TOBY-L4206-00A-00
TBD
TBD
TBD
Functional Sample
TOBY-L4206-50A-00
TBD
TBD
TBD
Functional Sample
TOBY-L4906
TOBY-L4906-00A-00
TBD
TBD
TBD
Functional Sample
TOBY-L4906-50A-00
40.19
A00.02
UBX-17058711
Engineering Sample
u-blox reserves all rights to this document and the information contained herein. Products, names, logos and designs described herein may in
whole or in part be subject to intellectual property rights. Reproduction, use, modification or disclosure to third parties of this document or
any part thereof without the express permission of u-blox is strictly prohibited.
The information contained herein is provided “as is” and u-blox assumes no liability for the use of the information. No warranty, either
express or implied, is given, including but not limited, with respect to the accuracy, correctness, reliability and fitness for a particular purpose
of the information. This document may be revised by u-blox at any time. For most recent documents, please visit www.u-blox.com.
Copyright © 2018, u-blox AG
u-blox®is a registered trademark of u-blox Holding AG in the EU and other countries. Microsoft and Windows are either registered
trademarks or trademarks of Microsoft Corporation in the United States and/or other countries. All other registered trademarks or
trademarks mentioned in this document are property of their respective owners.

TOBY-L4 series - System Integration Manual
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Preface
u-blox Technical Documentation
As part of our commitment to customer support, u-blox maintains an extensive volume of technical
documentation for our products. In addition to our product-specific technical data sheets, the following manuals
are available to assist u-blox customers in product design and development.
AT Commands Manual: This document provides the description of the AT commands supported by the
u-blox cellular modules.
System Integration Manual: This document provides the description of u-blox cellular modules’ system
from the hardware and the software point of view, it provides hardware design guidelines for the optimal
integration of the cellular modules in the application device and it provides information on how to set up
production and final product tests on application devices integrating the cellular modules.
Application Note: These documents provide guidelines and information on specific hardware and/or
software topics on u-blox cellular modules. See Related documents for a list of Application Notes related to
your Cellular Module.
How to use this Manual
The TOBY-L4 series System Integration Manual provides the necessary information to successfully design and
configure the u-blox cellular modules.
This manual has a modular structure. It is not necessary to read it from the beginning to the end.
The following symbols are used to highlight important information within the manual:
An index finger points out key information pertaining to module integration and performance.
A warning symbol indicates actions that could negatively impact or damage the module.
Questions
If you have any questions about u-blox Cellular Integration:
Read this manual carefully.
Contact our information service on the homepage http://www.u-blox.com/
Technical Support
Worldwide Web
Our website (http://www.u-blox.com/) is a rich pool of information. Product information, technical documents
can be accessed 24h a day.
By E-mail
Contact the closest Technical Support office by email. Use our service pool email addresses rather than any
personal email address of our staff. This makes sure that your request is processed as soon as possible. You will
find the contact details at the end of the document.
Helpful Information when Contacting Technical Support
When contacting Technical Support, have the following information ready:
Module type (TOBY-L4106) and firmware version
Module configuration
Clear description of your question or the problem
A short description of the application
Your complete contact details

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Contents
Preface ................................................................................................................................3
Contents..............................................................................................................................4
1System description.......................................................................................................7
1.1 Overview .............................................................................................................................................. 7
1.2 Architecture........................................................................................................................................ 10
1.3 Pin-out ............................................................................................................................................... 12
1.4 Operating modes................................................................................................................................ 20
1.5 Supply interfaces ................................................................................................................................ 22
1.5.1 Module supply input (VCC) ......................................................................................................... 22
1.5.2 RTC back-up supply (V_BCKP) ..................................................................................................... 30
1.5.3 Generic digital interfaces supply output (V_INT)........................................................................... 30
1.6 System function interfaces.................................................................................................................. 31
1.6.1 Module power-on ....................................................................................................................... 31
1.6.2 Module power-off ....................................................................................................................... 33
1.6.3 Module reset ............................................................................................................................... 35
1.6.4 Module / host configuration selection ......................................................................................... 35
1.7 Antenna interfaces ............................................................................................................................. 36
1.7.1 Antenna RF interfaces (ANT1 / ANT2) .......................................................................................... 36
1.7.2 Antenna detection interface (ANT_DET) ...................................................................................... 38
1.8 SIM interfaces..................................................................................................................................... 38
1.8.1 SIM interfaces.............................................................................................................................. 38
1.8.2 SIM detection interface ............................................................................................................... 38
1.9 Data communication interfaces .......................................................................................................... 39
1.9.1 USB interface............................................................................................................................... 40
1.9.2 UART interfaces........................................................................................................................... 41
1.9.3 SPI interfaces............................................................................................................................... 44
1.9.4 DDC (I2C) interfaces..................................................................................................................... 45
1.9.5 SDIO interface ............................................................................................................................. 45
1.9.6 RGMII interface ........................................................................................................................... 46
1.10 eMMC interface.............................................................................................................................. 47
1.11 Audio interfaces.............................................................................................................................. 48
1.11.1 Analog audio interfaces............................................................................................................... 48
1.11.2 Digital audio interface ................................................................................................................. 49
1.12 ADC interfaces................................................................................................................................ 50
1.13 General Purpose Input/Output ........................................................................................................ 50
1.14 Reserved pins (RSVD) ...................................................................................................................... 51
2Design-in.....................................................................................................................52
2.1 Overview ............................................................................................................................................ 52
2.2 Supply interfaces ................................................................................................................................ 53

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2.2.1 Module supply (VCC) .................................................................................................................. 53
2.2.2 RTC back-up supply (V_BCKP) ..................................................................................................... 66
2.2.3 Generic digital interfaces supply output (V_INT)........................................................................... 67
2.3 System functions interfaces ................................................................................................................ 68
2.3.1 Module power-on (PWR_ON) ...................................................................................................... 68
2.3.2 Module reset (RESET_N) .............................................................................................................. 69
2.3.3 Module / host configuration selection ......................................................................................... 70
2.4 Antenna interface............................................................................................................................... 71
2.4.1 Antenna RF interfaces (ANT1 / ANT2) .......................................................................................... 71
2.4.2 Antenna detection interface (ANT_DET) ...................................................................................... 77
2.5 SIM interfaces..................................................................................................................................... 79
2.5.1 Guidelines for SIM circuit design.................................................................................................. 79
2.5.2 Guidelines for SIM layout design ................................................................................................. 85
2.6 Data communication interfaces .......................................................................................................... 86
2.6.1 USB interface............................................................................................................................... 86
2.6.2 UART interfaces........................................................................................................................... 89
2.6.3 SPI interfaces............................................................................................................................... 93
2.6.4 DDC (I2C) interfaces..................................................................................................................... 94
2.6.5 SDIO interface ............................................................................................................................. 98
2.6.6 RGMII interface ......................................................................................................................... 100
2.7 eMMC interface ............................................................................................................................... 101
2.8 Audio interface................................................................................................................................. 102
2.8.1 Analog audio interface .............................................................................................................. 102
2.8.2 Digital audio interface ............................................................................................................... 111
2.9 ADC interfaces ................................................................................................................................. 113
2.10 General Purpose Input/Output ...................................................................................................... 114
2.11 Reserved pins (RSVD) .................................................................................................................... 115
2.12 Module placement ........................................................................................................................ 115
2.13 Module footprint and paste mask ................................................................................................. 116
2.14 Thermal guidelines ........................................................................................................................ 117
2.15 Design-in checklist ........................................................................................................................ 118
2.15.1 Schematic checklist ................................................................................................................... 118
2.15.2 Layout checklist ......................................................................................................................... 119
2.15.3 Antenna checklist ...................................................................................................................... 119
3Handling and soldering ...........................................................................................120
3.1 Packaging, shipping, storage and moisture preconditioning ............................................................. 120
3.2 Handling........................................................................................................................................... 120
3.3 Soldering .......................................................................................................................................... 121
3.3.1 Soldering paste.......................................................................................................................... 121
3.3.2 Reflow soldering ....................................................................................................................... 121
3.3.3 Optical inspection...................................................................................................................... 122
3.3.4 Cleaning.................................................................................................................................... 122
3.3.5 Repeated reflow soldering......................................................................................................... 123

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3.3.6 Wave soldering.......................................................................................................................... 123
3.3.7 Hand soldering .......................................................................................................................... 123
3.3.8 Rework...................................................................................................................................... 123
3.3.9 Conformal coating .................................................................................................................... 123
3.3.10 Casting...................................................................................................................................... 123
3.3.11 Grounding metal covers ............................................................................................................ 123
3.3.12 Use of ultrasonic processes........................................................................................................ 123
4Approvals..................................................................................................................124
4.1 Product certification approval overview............................................................................................. 124
4.2 US Federal Communications Commission notice............................................................................... 125
4.2.1 Safety warnings review the structure ......................................................................................... 125
4.2.2 Declaration of conformity.......................................................................................................... 125
4.2.3 Modifications ............................................................................................................................ 126
4.3 Innovation, Science and Economic Development Canada notice ....................................................... 127
4.3.1 Declaration of Conformity ......................................................................................................... 127
4.3.2 Modifications ............................................................................................................................ 128
4.4 European Conformance CE mark...................................................................................................... 130
4.5 Chinese CCC and SRRC certifications ............................................................................................... 131
5Product testing .........................................................................................................132
5.1 u-blox in-series production test......................................................................................................... 132
5.2 Test parameters for OEM manufacturers........................................................................................... 133
5.2.1 “Go/No go” tests for integrated devices.................................................................................... 133
5.2.2 RF functional tests ..................................................................................................................... 133
Appendix ........................................................................................................................135
AMigration between TOBY-L2 and TOBY-L4 ............................................................135
A.1 Overview .......................................................................................................................................... 135
A.2 Pin-out comparison between TOBY-L2 and TOBY-L4 ........................................................................ 137
BGlossary ....................................................................................................................139
Related documents.........................................................................................................141
Revision history..............................................................................................................142
Contact............................................................................................................................143

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1System description
1.1 Overview
The TOBY-L4 series modules support multi-band LTE-FDD, LTE-TDD, DC-HSPA+, and (E)GPRS radio access
technologies (see Table 1) in the very small TOBY 248-pin LGA form-factor (35.6 x 24.8 mm), which is easy to
integrate in compact designs.
TOBY-L4 series modules are form-factor compatible with the other u-blox cellular module families (including
SARA, LISA, LARA, and TOBY form-factors): this allows customers to take maximum advantage of their hardware
and software investments, and provides very short time-to-market.
With LTE-Advanced carrier aggregation category 6 data rates up to 301.5 Mbit/s (downlink) / 51.0 Mbit/s
(uplink), the modules are ideal for applications requiring the highest data-rates and high-speed internet access.
Reduced cost variants supporting LTE Cat 4 or LTE Cat 1 will be available for lower speed or “pure” telematics
devices.
TOBY-L4 series include the following LTE Cat 6 modules with 3G and 2G fallback:
TOBY-L4006 modules, mainly designed for operation in North America
TOBY-L4106 modules, mainly designed for operation in Europe
TOBY-L4206 modules, mainly designed for operation in Asia-Pacific and South America
TOBY-L4906 modules, mainly designed for operation in China
TOBY-L4 series modules include the following product versions:
The “00” product versions, integrating the u-blox uCPU on-chip processor to allow customers to run their
dedicated applications on an embedded Linux distribution based on Yocto, with RIL-Core connectivity APIs
The “50” product versions, which can be controlled by an external application processor through standard
and u-blox proprietary AT commands described in the u-blox AT Commands Manual [2]
TOBY-L4 series modules are the ideal product for the development of all kinds of automotive devices, such as
smart antennas and in-dash telematics / infotainment devices, supporting a comprehensive set of HW interfaces
(including RGMII/RMII for Ethernet and analog audio) over a very extended temperature range that allow the
establishment of an emergency call up to +95 °C, complemented by a set of state-of-the art security features.
TOBY-L4 series modules are also the perfect choice for consumer fixed-wireless terminals, mobile routers and
gateways, applications requiring video streaming and many other industrial (M2M) applications.
TOBY-L4 series modules are manufactured in ISO/TS 16949 certified sites, with the highest production standards
and the highest quality and reliability. Each module is fully tested and inspected during production. The modules
are qualified according to the automotive requirements as for systems installed in vehicles.

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Table 1 summarizes the main features and interfaces of the TOBY-L4 series modules.
Model
Region
Bands
Interfaces
Features
Grade
LTE FDD bands
LTE TDD bands
UMTS FDD bands
GSM bands
UART
USB 2.0 device/host*
USB 3.0 device**
SPI
RGMII / RMII
eMMC
SDIO
DDC (I2C)
SIM
GPIO
ADC
Antenna supervisor
CA / MIMO / Rx Diversity
Analog audio
Digital Audio
uCPU for customer applications
GNSS via modem
Wi-Fi via modem
Network indication
Jamming detection
Embedded TCP/UDP stack
Embedded HTTP, FTP, SSL
FOTA
Dual stack IPv4/IPv6
Standard
Professional
Automotive
TOBY-L4006-00
North
America
2,4,5
7,12
13,29
2
4,5
850
1900
4
1
1
2
1
1
1
2
2
14
2
●
●
●
●
●
●
●
●
●
●
●
●
●
TOBY-L4006-50
North
America
2,4,5
7,12
13,29
2
4,5
850
1900
1
1
2
9
●
●
●
●
●
●
●
TOBY-L4106-00
EMEA
1,3
7,8
20
38
1,8
900
1800
4
1
1
2
1
1
1
2
2
14
2
●
●
●
●
●
●
●
●
●
●
●
●
●
TOBY-L4106-50
EMEA
1,3
7,8
20
38
1,8
900
1800
1
1
2
9
●
●
●
●
●
●
●
TOBY-L4206-00
APAC,
South
America
1,3,5
7,8,9
19,28
1
5,8
Quad
4
1
1
2
1
1
1
2
2
14
2
●
●
●
●
●
●
●
●
●
●
●
●
●
TOBY-L4206-50
APAC,
South
America
1,3,5
7,8,9
19,28
1
5,8
Quad
1
1
2
9
●
●
●
●
●
●
●
TOBY-L4906-00
China
1,3
39
40,41
1,8
900
1800
4
1
1
2
1
1
1
2
2
14
2
●
●
●
●
●
●
●
●
●
●
●
●
●
TOBY-L4906-50
China
1,3
39
40,41
1,8
900
1800
1
1
2
9
●
●
●
●
●
●
●
* USB 2.0 host role not supported by the "50" product versions
** USB 3.0 interface supported by future firmware versions
Table 1: TOBY-L4 series main features summary

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TOBY-L4 series modules provide multi-band 4G / 3G / 2G multi-mode radio access technologies, based on the
3GPP Release 10 protocol stack, with the main characteristics summarized in Table 2 and Table 3.
LTE
3G
2G
LTE-Advanced Carrier Aggregation
Frequency Division Duplex (LTE FDD)
Time Division Duplex (LTE TDD)
Down-Link CA / MIMO / Rx diversity
Dual-Cell High Speed Packet Access
Frequency Division Duplex (UMTS FDD)
Down-Link Rx diversity
Enhanced Data rate GSM Evolution (EDGE)
Time Division Multiple Access (TDMA)
DL Advanced Rx Performance Phase 1
LTE FDD Power Class
Class 3 (23 dBm)
LTE TDD Power Class
Class 3 (23 dBm)
UMTS FDD Power Class
Class 3 (24 dBm)
GMSK Power Class
Class 4 (33 dBm) for GSM/E-GSM bands
Class 1 (30 dBm) for DCS/PCS bands
8-PSK Power Class
Class E2 (27 dBm) for GSM/E-GSM bands
Class E2 (26 dBm) for DCS/PCS bands
Data rate
LTE category 6:
up to 301.5 Mbit/s DL
up to 51.0 Mbit/s UL
Data rate
FDD UE categories:
DL cat.24, up to 42.2 Mbit/s
UL cat.6, up to 5.76 Mbit/s
Data rate
GPRS multi-slot class 33, CS1-CS4:
up to 107.0 kbit/s DL
up to 85.6 kbit/s UL
EDGE multi-slot class 33, MCS1-MCS9
up to 296.0 kbit/s DL
up to 236.8 kbit/s UL
Table 2: TOBY-L4 series LTE, 3G and 2G characteristics summary
Module
Region
LTE FDD bands
LTE TDD bands
LTE CA
UMTS FDD bands
GSM bands
TOBY-L4006
North America
12 (700 MHz)
17 (700 MHz)
29 (700 MHz)
13 (750 MHz)
5 (850 MHz)
4 (1700 MHz)
2 (1900 MHz)
7 (2600 MHz)
4 + 17
2 + 13
2 + 17
2 + 29
4 + 5
4 + 4
4 + 13
4 + 29
5 (850 MHz)
4 (1700 MHz)
2 (1900 MHz)
GSM 850
PCS 1900
TOBY-L4106
EMEA,
APAC
20 (800 MHz)
8 (900 MHz)
3 (1800 MHz)
1 (2100 MHz)
7 (2600 MHz)
38 (2600 MHz)
3 + 20
7 + 20
3 + 3
3 + 7
8 (900 MHz)
1 (2100 MHz)
E-GSM 900
DCS 1800
TOBY-L4206
APAC,
South America
28 (750 MHz)
19 (850 MHz)
5 (850 MHz)
8 (900 MHz)
9 (1800 MHz)
3 (1800 MHz)
1 (2100 MHz)
7 (2600 MHz)
3 + 28
3 + 7
7 + 28
3 + 3
1 + 8
3 + 19
1 + 19
5 (850 MHz)
8 (900 MHz)
1 (2100 MHz)
GSM 850
E-GSM 900
DCS 1800
PCS 1900
TOBY-L4906
China
3 (1800 MHz)
1 (2100 MHz)
39 (1900 MHz)
40 (2300 MHz)
41 (2500 MHz)
3 + 3
40 + 40
41 + 41
39 + 41
8 (900 MHz)1
1 (2100 MHz)
E-GSM 900
DCS 1800
Table 3: TOBY-L4 series supported bands
2
and Carrier Aggregation combinations summary
1
Down-Link Rx diversity not supported on this band
2
TOBY-L4 series modules support all the E-UTRA channel bandwidths for each operating band according to 3GPP TS 36.521-1 [13].

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1.2 Architecture
Figure 1 summarizes the internal architecture of the TOBY-L4 series modules.
Cellular
Base-band
Processor
Memory
Power Management Unit
26 MHz
32.768 kHz
ANT1
RF
Transceiver
ANT2
V_INT (I/O)
V_BCKP (RTC)
VCC (Supply)
2 x SIM
USB 2.0 / 3.0
2 x ADC
Power on
External reset
PAs
LNAs Filters
Filters
Duplexer
Filters
PAs
LNAs Filters
Filters
Duplexer
Filters
LNAs FiltersFilters
LNAs FiltersFilters
Switch
Switch
2 x DDC (I2C)
SDIO
4 x UART
Analog audio
Antenna detection
Host Select
2 x SPI
RGMII
eMCC
2 x Digital audio (I2S)
GPIOs
Figure 1: TOBY-L4 series modules simplified block diagram
TOBY-L4 series modules internally consist of the RF, Baseband and Power Management sections described herein
with more details than the simplified block diagrams of Figure 1.
RF section
The RF section is composed of an RF transceiver, PAs, LNAs, crystal oscillator, filters, duplexers and RF switches.
The Tx signal is pre-amplified by the RF transceiver, then output to the primary antenna input/output port
(ANT1) of the module via power amplifier (PA), SAW band pass filters band, specific duplexer and antenna
switch.
Dual receiving paths are implemented according to Carrier Aggregation, MIMO, and Receiver Diversity radio
technologies supported by the modules as LTE category 6 and HSDPA category 24 User Equipments: incoming
signals are received through the primary (ANT1) and the secondary (ANT2) antenna input ports which are
connected to the RF transceiver via specific antenna switch, diplexer, duplexer, LNA, SAW band pass filters.
RF transceiver performs modulation, up-conversion of the baseband I/O signals for Tx, down-conversion and
demodulation of the dual RF signals for Rx. The RF transceiver contains:
Single chain high linearity receivers with integrated LNAs for multi-band multi-mode CA operation,
Highly linear RF demodulator / modulator capable GMSK, 8-PSK, QPSK, 16-QAM, 64-QAM
RF synthesizer,
VCO.
Power Amplifiers (PA) amplify the Tx signal modulated by the RF transceiver
RF switches connect the primary (ANT1) and secondary (ANT2) antenna ports to the suitable Tx / Rx path
SAW duplexers and band pass filters separate the Tx and Rx signal paths and provide RF filtering
26 MHz voltage-controlled temperature-controlled crystal oscillator (VC-TCXO) generates the clock reference
in active mode or connected mode.

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Baseband and power management section
The Baseband and Power Management section is composed of the following main elements:
A mixed signal ASIC, which integrates
oMicroprocessor for control functions
oDSP core for cellular Layer 1 and digital processing of Rx and Tx signal paths
oMemory interface controller
oDedicated peripheral blocks for control of the USB, SIM and generic digital interfaces
oInterfaces to the RF transceiver ASIC
Memory system, which includes NAND flash and LPDDR2 RAM
Voltage regulators to derive all the subsystem supply voltages from the module supply input VCC
Voltage source for external use: V_INT
Hardware power on
Hardware reset
Low power idle mode support
32.768 kHz crystal oscillator to provide the clock reference in the low power idle mode, which can be set by
enabling the power saving configuration.

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1.3 Pin-out
Table 4 lists the pin-out of the TOBY-L4 series modules, with pins grouped by function.
Function
Pin Name
Pin No
I/O
Description
Remarks
Power
VCC
70,71,72
I
Module supply input
VCC supply circuit affects the RF performance and
compliance of the device integrating the module with
applicable required certification schemes.
See section 1.5.1 for functional description / requirements.
See section 2.2.1 for external circuit design-in.
GND
2, 30, 32, 44,
46, 69, 73, 74,
76, 78, 79, 80,
82, 83, 85, 86,
88-90, 92-
152, 209, 219,
226, 229, 232,
235, 238, 241
N/A
Ground
GND pins are internally connected each other.
External ground connection affects the RF and thermal
performance of the device.
See section 1.5.1 for functional description.
See section 2.2.1 for external circuit design-in.
V_BCKP
3
I/O
RTC back-up supply
If the VCC voltage is below the operating range, the RTC
block can be externally supplied through the V_BCKP pin.
See section 1.5.2 for functional description.
See section 2.2.2 for external circuit design-in.
V_INT
5
O
Generic digital
interfaces supply
output
V_INT = 1.8 V (typical) generated by internal DC/DC
regulator when the module is switched on.
Test-Point for diagnostic access is recommended.
See section 1.5.3 for functional description.
See section 2.2.3 for external circuit design-in.
System
PWR_ON
20
I
Power-on input
Internal 35 kpull-up resistor to internal 1.3 V supply rail.
Test-Point for diagnostic access is recommended.
See section 1.6.1 for functional description.
See section 2.3.1 for external circuit design-in.
RESET_N
23
I
External reset input
Internal 100 kpull-up resistor to V_INT.
Test-Point for diagnostic access is recommended.
See section 1.6.3 for functional description.
See section 2.3.2 for external circuit design-in.
HOST_SELECT0
26
I/O /
I
GPIO /
External Interrupt
1.8 V GPIO or External Interrupt configurable by uCPU API.
See sections 1.6.4, 1.13 for functional description.
See sections 2.3.3, 2.10 for external circuit design-in.
HOST_SELECT1
62
I/O /
I
GPIO /
External Interrupt
1.8 V GPIO or External Interrupt configurable by uCPU API.
See sections 1.6.4, 1.13 for functional description.
See sections 2.3.3, 2.10 for external circuit design-in.
Antennas
ANT1
81
I/O
Primary antenna
Main Tx / Rx antenna interface.
50 nominal characteristic impedance.
Antenna circuit affects the RF performance and application
device compliance with required certification schemes.
See section 1.7.1 for functional description / requirements.
See section 2.4 for external circuit design-in.
ANT2
87
I
Secondary antenna
Rx only for Down-Link CA, MIMO and Rx diversity.
50 nominal characteristic impedance.
Antenna circuit affects the RF performance and application
device compliance with required certification schemes.
See section 1.7.1 for functional description / requirements.
See section 2.4 for external circuit design-in.
ANT_DET
75
I
Antenna detection
ADC for antenna presence detection function.
See section 1.7.2 for functional description.
See section 2.4.2 for external circuit design-in.

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Function
Pin Name
Pin No
I/O
Description
Remarks
SIM0
VSIM
59
O
SIM0 supply output
VSIM = 1.8 V / 3 V output as per the connected SIM type.
See section 1.8 for functional description.
See section 2.5 for external circuit design-in.
SIM_IO
57
I/O
SIM0 data
Data input/output for 1.8 V / 3 V SIM.
Internal 4.7 kpull-up to VSIM.
See section 1.8 for functional description.
See section 2.5 for external circuit design-in.
SIM_CLK
56
O
SIM0 clock
3.9 MHz clock output for 1.8 V / 3 V SIM.
See section 1.8 for functional description.
See section 2.5 for external circuit design-in.
SIM_RST
58
O
SIM0 reset
Reset output for 1.8 V / 3 V SIM.
See section 1.8 for functional description.
See section 2.5 for external circuit design-in.
SIM1
VSIM1
172
O
SIM1 supply output
VSIM1 = 1.8 V / 3 V output as per the connected SIM type.
See section 1.8 for functional description.
See section 2.5 for external circuit design-in.
SIM1_IO
178
I/O
SIM1 data
Data input/output for 1.8 V / 3 V SIM.
Internal 4.7 kpull-up to VSIM1.
See section 1.8 for functional description.
See section 2.5 for external circuit design-in.
SIM1_CLK
182
O
SIM1 clock
3.9 MHz clock output for 1.8 V / 3 V SIM.
See section 1.8 for functional description.
See section 2.5 for external circuit design-in.
SIM1_RST
177
O
SIM1 reset
Reset output for 1.8 V / 3 V SIM.
See section 1.8 for functional description.
See section 2.5 for external circuit design-in.
USB
VUSB_DET
4
I
USB detect input
VBUS (5 V typical) generated by the host must be connected
to this pin to enable the module USB device interface.
Test-Point for diagnostic / FW update access is
recommended.
See section 1.9.1 for functional description.
See section 2.6.1 for external circuit design-in.
USB_D–
27
I/O
USB High-Speed 2.0
diff. transceiver (–)
90 nominal differential impedance (Z0).
30 nominal common mode impedance (ZCM).
Pull-up or pull-down resistors and external series resistors as
required by the USB 2.0 specifications [3] are part of the
USB pin driver and need not be provided externally.
Test-Point for diagnostic / FW update access is recommended.
See section 1.9.1 for functional description.
See section 2.6.1 for external circuit design-in.
USB_D+
28
I/O
USB High-Speed 2.0
diff. transceiver (+)
90 nominal differential impedance (Z0).
30 nominal common mode impedance (ZCM).
Pull-up or pull-down resistors and external series resistors as
required by the USB 2.0 specifications [3] are part of the
USB pin driver and need not be provided externally.
Test-Point for diagnostic / FW update access is recommended.
See section 1.9.1 for functional description.
See section 2.6.1 for external circuit design-in.
USB_ID
168
I
USB device
identification
Pin for ID resistance measurement.
See section 1.9.1 for functional description.
See section 2.6.1 for external circuit design-in.

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Function
Pin Name
Pin No
I/O
Description
Remarks
USB_SSTX+
175
O
USB Super-Speed 3.0
diff. transmitter (+)
90 nominal differential characteristic impedance.
Internal series 100 nF capacitor for AC coupling.
Compliant with USB Revision 3.0 specification [4].
See section 1.9.1 for functional description.
See section 2.6.1 for external circuit design-in.
USB_SSTX–
176
O
USB Super-Speed 3.0
diff. transmitter (–)
90 nominal differential characteristic impedance.
Internal series 100 nF capacitor for AC coupling.
Compliant with USB Revision 3.0 specification [4].
See section 1.9.1 for functional description.
See section 2.6.1 for external circuit design-in.
USB_SSRX+
170
I
USB Super-Speed 3.0
diff. receiver (+)
90 nominal differential characteristic impedance.
Compliant with USB Revision 3.0 specification [4].
See section 1.9.1 for functional description.
See section 2.6.1 for external circuit design-in.
USB_SSRX–
171
I
USB Super-Speed 3.0
diff. receiver (–)
90 nominal differential characteristic impedance.
Compliant with USB Revision 3.0 specification [4].
See section 1.9.1 for functional description.
See section 2.6.1 for external circuit design-in.
UART0
RXD
17
O
UART0 data output
1.8 V output, Circuit 104 (RXD) in ITU-T V.24.
Test-Point for diagnostic access recommended.
See section 1.9.2 for functional description.
See section 2.6.2 for external circuit design-in.
TXD
16
I
UART0 data input
1.8 V input, Circuit 103 (TXD) in ITU-T V.24.
Internal active pull-up to V_INT.
Test-Point for diagnostic access recommended.
See section 1.9.2 for functional description.
See section 2.6.2 for external circuit design-in.
CTS
15
O
UART0 clear to send
output
1.8 V output, Circuit 106 (CTS) in ITU-T V.24.
See section 1.9.2 for functional description.
See section 2.6.2 for external circuit design-in.
RTS
14
I
UART0 ready to
send input
1.8 V input, Circuit 105 (RTS) in ITU-T V.24.
Internal active pull-up to V_INT.
See section 1.9.2 for functional description.
See section 2.6.2 for external circuit design-in.
DSR
10
I/O /
I
GPIO /
External Interrupt
1.8 V GPIO or External Interrupt configurable by uCPU API.
See sections 1.9.2, 1.13 for functional description.
See sections 2.6.1, 2.10 for external circuit design-in.
RI
11
O /
I/O /
I
UART0 ring indicator /
GPIO /
External Interrupt
1.8 V output, Circuit 125 (RI) in ITU-T V.24.
Configurable as GPIO or External Interrupt.
See sections 1.9.2, 1.13 for functional description.
See sections 2.6.1, 2.10 for external circuit design-in.
DTR
13
I/O /
I
GPIO /
External Interrupt
1.8 V GPIO or External Interrupt configurable by uCPU API.
See sections 1.9.2, 1.13 for functional description.
See sections 2.6.1, 2.10 for external circuit design-in.
DCD
12
I/O /
I
GPIO /
External Interrupt
1.8 V GPIO or External Interrupt configurable by uCPU API.
See sections 1.9.2, 1.13 for functional description.
See sections 2.6.1, 2.10 for external circuit design-in.

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Function
Pin Name
Pin No
I/O
Description
Remarks
UART1
RXD1
160
O /
O
UART1 data output /
SPI1 MOSI
1.8 V output, Circuit 104 (RXD) in ITU-T V.24,
alternatively configurable as SPI1 MOSI by uCPU API.
See section 1.9.2 / 1.9.3 for functional description.
See section 2.6.2 / 2.6.3 for external circuit design-in.
TXD1
159
I /
I
UART1 data input /
SPI1 MISO
1.8 V input, Circuit 103 (TXD) in ITU-T V.24,
alternatively configurable as SPI1 MISO by uCPU API.
Internal pull-up to V_INT enabled when UART1 data input.
See section 1.9.2 / 1.9.3 for functional description.
See section 2.6.2 / 2.6.3 for external circuit design-in.
CTS1
195
O /
O
UART1 CTS output /
SPI1 Chip Select
1.8 V output, Circuit 106 (CTS) in ITU-T V.24,
alternatively configurable as SPI1 Chip Select by uCPU API.
See section 1.9.2 / 1.9.3 for functional description.
See section 2.6.2 / 2.6.3 for external circuit design-in.
RTS1
193
I /
O
UART1 RTS input /
SPI1 Clock
1.8 V input, Circuit 105 (RTS) in ITU-T V.24,
alternatively configurable as SPI1 Clock by uCPU API.
Internal pull-up to V_INT enabled when UART1 RTS input.
See section 1.9.2 / 1.9.3 for functional description.
See section 2.6.2 / 2.6.3 for external circuit design-in.
UART2
RXD2
162
O
UART2 data output
1.8 V output, Circuit 104 (RXD) in ITU-T V.24.
See section 1.9.2 for functional description.
See section 2.6.2 for external circuit design-in.
TXD2
161
I
UART2 data input
1.8 V input, Circuit 103 (TXD) in ITU-T V.24.
Internal active pull-up to V_INT.
See section 1.9.2 for functional description.
See section 2.6.2 for external circuit design-in.
UART3
RXD3
19
O
UART3 data output
1.8 V output, Circuit 104 (RXD) in ITU-T V.24.
See section 1.9.2 for functional description.
See section 2.6.2 for external circuit design-in.
TXD3
18
I
UART3 data input
1.8 V input, Circuit 103 (TXD) in ITU-T V.24.
Internal active pull-up to V_INT.
See section 1.9.2 for functional description.
See section 2.6.2 for external circuit design-in.
SPI0
SPI_MOSI
174
O
SPI0 Master Output
Slave Input
1.8 V, SPI0 data output.
See section 1.9.3 for functional description.
See section 2.6.3 for external circuit design-in.
SPI_MISO
169
I
SPI0 Master Input
Slave Output
1.8 V, SPI0 data input.
See section 1.9.3 for functional description.
See section 2.6.3 for external circuit design-in.
SPI_SCLK
179
O
SPI0 Shift Clock
1.8 V, SPI0 clock.
See section 1.9.3 for functional description.
See section 2.6.3 for external circuit design-in.
SPI_CS
173
O
SPI0 Chip Select 0
1.8 V, SPI0 chip select 0.
See section 1.9.3 for functional description.
See section 2.6.3 for external circuit design-in.
I2C0
SCL
54
O
I2C0 clock
1.8 V open drain.
External pull-up required.
See section 1.9.4 for functional description.
See section 2.6.4 for external circuit design-in.
SDA
55
I/O
I2C0 data
1.8 V open drain.
External pull-up required.
See section 1.9.4 for functional description.
See section 2.6.4 for external circuit design-in.

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Function
Pin Name
Pin No
I/O
Description
Remarks
I2C1
SCL1
54
O
I2C1 clock
1.8 V open drain.
External pull-up required.
See section 1.9.4 for functional description.
See section 2.6.4 for external circuit design-in.
SDA1
55
I/O
I2C1 data
1.8 V open drain.
External pull-up required.
See section 1.9.4 for functional description.
See section 2.6.4 for external circuit design-in.
SDIO
SDIO_D0
66
I/O
SDIO serial data [0]
SDIO interface for communication with Wi-Fi / Bluetooth.
See section 1.9.5 for functional description.
See section 2.6.5 for external circuit design-in.
SDIO_D1
68
I/O
SDIO serial data [1]
SDIO interface for communication with Wi-Fi / Bluetooth.
See section 1.9.5 for functional description.
See section 2.6.5 for external circuit design-in.
SDIO_D2
63
I/O
SDIO serial data [2]
SDIO interface for communication with Wi-Fi / Bluetooth.
See section 1.9.5 for functional description.
See section 2.6.5 for external circuit design-in.
SDIO_D3
67
I/O
SDIO serial data [3]
SDIO interface for communication with Wi-Fi / Bluetooth.
See section 1.9.5 for functional description.
See section 2.6.5 for external circuit design-in.
SDIO_CLK
64
O
SDIO serial clock
SDIO interface for communication with Wi-Fi / Bluetooth.
See section 1.9.5 for functional description.
See section 2.6.5 for external circuit design-in.
SDIO_CMD
65
I/O
SDIO command
SDIO interface for communication with Wi-Fi / Bluetooth.
See section 1.9.5 for functional description.
See section 2.6.5 for external circuit design-in.
Ethernet
V_ETH
221
O
Ethernet Interface
supply output
Ethernet (RGMII / RMII) interface supply output.
See section 1.9.6 for functional description.
See section 2.6.6 for external circuit design-in.
ETH_TX_CLK
29
O
Ethernet
Transmission Clock
RGMII: Transmit reference clock (TXC).
RMII: Reference clock (REF_CLK).
See section 1.9.6 for functional description.
See section 2.6.6 for external circuit design-in.
ETH_TX_CTL
33
O
Ethernet Transmit
Control
RGMII: Control signal for the transmit data (TXEN on TXC
rising edge; TXEN xor TXER on TXC falling edge).
RMII: Control signal for the transmit data (TX_EN).
See section 1.9.6 for functional description.
See section 2.6.6 for external circuit design-in.
ETH_TXD0
37
O
Ethernet Transmit
Data [0]
RGMII: Tx data bit 0 / 4 on TXC rising / falling edges.
RMII: Tx data bit 0 in sync with REF_CLK.
See section 1.9.6 for functional description.
See section 2.6.6 for external circuit design-in.
ETH_TXD1
36
O
Ethernet Transmit
Data [1]
RGMII: Tx data bit 1 / 5 on TXC rising / falling edges.
RMII: Tx data bit 1 in sync with REF_CLK.
See section 1.9.6 for functional description.
See section 2.6.6 for external circuit design-in.
ETH_TXD2
35
O
Ethernet Transmit
Data [2]
RGMII: Tx data bit 2 / 6 on TXC rising / falling edges.
RMII: Not used.
See section 1.9.6 for functional description.
See section 2.6.6 for external circuit design-in.
ETH_TXD3
34
O
Ethernet Transmit
Data [3]
RGMII: Tx data bit 3 / 7 on TXC rising / falling edges.
RMII: Not used.
See section 1.9.6 for functional description.
See section 2.6.6 for external circuit design-in.

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Function
Pin Name
Pin No
I/O
Description
Remarks
ETH_RX_CLK
43
I
Ethernet Receive
Clock
RGMII: Receive reference clock (RXC).
RMII: Not used.
See section 1.9.6 for functional description.
See section 2.6.6 for external circuit design-in.
ETH_RX_CTL
42
I
Ethernet Receive
Control
RGMII: Control signal for receive data (RXDV on RXC rising
edge; RXDV xor RXER on RXC falling edge).
RMII: Control signal for receive data, contains carrier sense
(CRS) and data valid (RX_DV) information.
See section 1.9.6 for functional description.
See section 2.6.6 for external circuit design-in.
ETH_RXD0
38
I
Ethernet Receive
Data [0]
RGMII: Rx data bit 0 / 4 on RXC rising / falling edges.
RMII: Rx data bit 0 in sync with REF_CLK.
See section 1.9.6 for functional description.
See section 2.6.6 for external circuit design-in.
ETH_RXD1
39
I
Ethernet Receive
Data [1]
RGMII: Rx data bit 1 / 5 on RXC rising / falling edges.
RMII: Rx data bit 1 in sync with REF_CLK.
See section 1.9.6 for functional description.
See section 2.6.6 for external circuit design-in.
ETH_RXD2
40
I
Ethernet Receive
Data [2]
RGMII: Rx data bit 2 / 6 on RXC rising / falling edges.
RMII: Not used.
See section 1.9.6 for functional description.
See section 2.6.6 for external circuit design-in.
ETH_RXD3
41
I
Ethernet Receive
Data [3]
RGMII: Rx data bit 3 / 7 on RXC rising / falling edges.
RMII: Not used.
See section 1.9.6 for functional description.
See section 2.6.6 for external circuit design-in.
ETH_INTR
220
I
Ethernet Interrupt
Input
Input for the detection of an interrupt event in the PHY.
See section 1.9.6 for functional description.
See section 2.6.6 for external circuit design-in.
ETH_MDIO
222
I/O
Ethernet
Management Data
Input Output
Ethernet management data input / output.
See section 1.9.6 for functional description.
See section 2.6.6 for external circuit design-in.
ETH_MDC
223
O
Ethernet
Management Data
Clock
Ethernet management data clock output.
See section 1.9.6 for functional description.
See section 2.6.6 for external circuit design-in.
eMMC
V_MMC
210
O
Multi-Media Card
Interface supply
output
Embedded Multi-Media / SD Card memory supply.
See section 1.10 for functional description.
See section 2.7 for external circuit design-in.
MMC_D0
214
I/O
Multi-Media Card
Data [0]
Embedded Multi-Media / SD Card memory data [0].
See section 1.10 for functional description.
See section 2.7 for external circuit design-in.
MMC_D1
212
I/O
Multi-Media Card
Data [1]
Embedded Multi-Media / SD Card memory data [1].
See section 1.10 for functional description.
See section 2.7 for external circuit design-in.
MMC_D2
217
I/O
Multi-Media Card
Data [2]
Embedded Multi-Media / SD Card memory data [2].
See section 1.10 for functional description.
See section 2.7 for external circuit design-in.
MMC_D3
213
I/O
Multi-Media Card
Data [3]
Embedded Multi-Media / SD Card memory data [3].
See section 1.10 for functional description.
See section 2.7 for external circuit design-in.
MMC_CMD
215
I/O
Multi-Media Card
Command
Embedded Multi-Media / SD Card memory command.
See section 1.10 for functional description.
See section 2.7 for external circuit design-in.
MMC_CLK
216
O
Multi-Media Card
Clock
Embedded Multi-Media / SD Card memory clock.
See section 1.10 for functional description.
See section 2.7 for external circuit design-in.

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Function
Pin Name
Pin No
I/O
Description
Remarks
MMC_RST_N
211
O
Multi-Media Card
Reset
Embedded Multi-Media / SD Card memory reset.
See section 1.10 for functional description.
See section 2.7 for external circuit design-in.
MMC_CD_N
218
I
Multi-Media Card
Detect
Embedded Multi-Media / SD Card detect.
See section 1.10 for functional description.
See section 2.7 for external circuit design-in.
I2S0
I2S_TXD
51
O
I2S0 transmit data
I2S transmit data output.
See sections 1.11 for functional description.
See sections 2.8 for external circuit design-in.
I2S_RXD
53
I
I2S0 receive data
I2S receive data input.
See sections 1.11 for functional description.
See sections 2.8 for external circuit design-in.
I2S_CLK
52
I/O
I2S0 clock
I2S serial clock.
See sections 1.11 for functional description.
See sections 2.8 for external circuit design-in.
I2S_WA
50
I/O
I2S0 word alignment
I2S word alignment.
See sections 1.11 for functional description.
See sections 2.8 for external circuit design-in.
I2S1
I2S1_TXD
206
O
I2S1 transmit data
I2S transmit data output.
See sections 1.11 for functional description.
See sections 2.8 for external circuit design-in.
I2S1_RXD
207
I
I2S1 receive data
I2S receive data input.
See sections 1.11 for functional description.
See sections 2.8 for external circuit design-in.
I2S1_CLK
208
I/O
I2S1 clock
I2S serial clock.
See sections 1.11 for functional description.
See sections 2.8 for external circuit design-in.
I2S1_WA
205
I/O
I2S1 word alignment
I2S word alignment.
See sections 1.11 for functional description.
See sections 2.8 for external circuit design-in.
Analog
audio
MIC_BIAS
231
O
Microphone supply
output
Supply output for external microphones.
See sections 1.11 for functional description.
See sections 2.8 for external circuit design-in.
MIC_GND
230
I
Microphone analog
reference
Local ground for the external microphone.
See sections 1.11 for functional description.
See sections 2.8 for external circuit design-in.
MIC1_P
237
I
MIC1 differential
analog audio input (+)
MIC1 differential analog audio signal input (positive).
See sections 1.11 for functional description.
See sections 2.8 for external circuit design-in.
MIC1_N
236
I
MIC1 differential
analog audio input (–)
MIC1 differential analog audio signal input (negative).
See sections 1.11 for functional description.
See sections 2.8 for external circuit design-in.
MIC2_P
234
I
MIC2 differential
analog audio input (+)
MIC2 differential analog audio signal input (positive).
See sections 1.11 for functional description.
See sections 2.8 for external circuit design-in.
MIC2_N
233
I
MIC2 differential
analog audio input (–)
MIC2 differential analog audio signal input (negative).
See sections 1.11 for functional description.
See sections 2.8 for external circuit design-in.

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Function
Pin Name
Pin No
I/O
Description
Remarks
SPK_P
227
O
Differential analog
audio output (+)
Differential analog audio signal output (positive).
See sections 1.11 for functional description.
See sections 2.8 for external circuit design-in.
SPK_N
228
O
Differential analog
audio output (–)
Differential analog audio signal output (negative).
See sections 1.11 for functional description.
See sections 2.8 for external circuit design-in.
ADC
ADC1
240
I
ADC input
See section 1.12 for functional description.
See section 2.9 for external circuit design-in.
ADC2
239
I
ADC input
See section 1.12 for functional description.
See section 2.9 for external circuit design-in.
GPIO
GPIO1
21
I/O
GPIO
1.8 V GPIO with alternatively configurable functions.
See section 1.13 for functional description.
See section 2.10 for external circuit design-in.
GPIO2
22
I/O
GPIO
1.8 V GPIO with alternatively configurable functions.
See section 1.13 for functional description.
See section 2.10 for external circuit design-in.
GPIO3
24
I/O
GPIO
1.8 V GPIO with alternatively configurable functions.
Configurable as External Interrupt by uCPU API.
See section 1.13 for functional description.
See section 2.10 for external circuit design-in.
GPIO4
25
I/O
GPIO
1.8 V GPIO with alternatively configurable functions.
Configurable as SPI0 Chip Select 1 by uCPU API.
See sections 1.13, 1.9.3 for functional description.
See sections 2.10, 2.6.3 for external circuit design-in.
GPIO5
60
I/O
GPIO
1.8 V GPIO with alternatively configurable functions.
See section 1.13 for functional description.
See section 2.10 for external circuit design-in.
GPIO6
61
I/O
GPIO
1.8 V GPIO with alternatively configurable functions.
See section 1.13 for functional description.
See section 2.10 for external circuit design-in.
GPIO7
248
I/O
GPIO
1.8 V GPIO with alternatively configurable functions.
See section 1.13 for functional description.
See section 2.10 for external circuit design-in.
GPIO8
247
I/O
GPIO
1.8 V GPIO with alternatively configurable functions.
See section 1.13 for functional description.
See section 2.10 for external circuit design-in.
Reserved
RSVD
6
N/A
Reserved pin
This pin must be connected to ground.
See sections 1.14 and 2.11
RSVD
1, 7-9, 31, 45,
47-49, 77, 84,
91, 153-158,
163-167, 180,
181, 183-192,
194, 196-202,
224, 225, 242,
243, 244-246
N/A
Reserved pin
Leave unconnected.
See sections 1.14 and 2.11
Table 4: TOBY-L4 series module pin definition, grouped by function

TOBY-L4 series - System Integration Manual
UBX-16024839 - R04 System description
Page 20 of 143
1.4 Operating modes
TOBY-L4 series modules have several operating modes. The operating modes are defined in Table 5 and
described in detail in Table 6, providing general guidelines for operation.
General Status
Operating Mode
Definition
Power-down
Not-powered mode
VCC supply not present or below operating range: module is switched off.
Power-off mode
VCC supply within operating range and module is switched off.
Normal Operation
Idle mode
Module processor core runs with 32 kHz reference generated by the internal oscillator.
Active mode
Module processor core runs with 26 MHz reference generated by the internal oscillator.
Connected mode
RF Tx/Rx data connection enabled and processor core runs with 26 MHz reference.
Table 5: TOBY-L4 series modules operating modes definition
Mode
Description
Transition between operating modes
Not-powered
Module is switched off.
Application interfaces are not accessible.
When VCC supply is removed, the modules enter not-powered mode.
When in not-powered mode, the modules do not switch on by
applying VCC supply, or by using the PWR_ON pin.
When in not-powered mode, the modules go to power-off mode by
applying VCC supply.
Power-off
Module is switched off: normal shutdown by an
appropriate power-off event (see 1.6.2).
Application interfaces are not accessible.
When the modules are switched off by an appropriate power-off event
(see 1.6.2), the modules enter power-off mode from active mode.
When in power-off mode, the modules can be switched on by means
of the PWR_ON pin (see 1.6.1).
When in power-off mode, the modules enter not-powered mode by
removing VCC supply.
Idle
Module is switched on with application
interfaces temporarily disabled or suspended to
reduce the current consumption (see 1.5.1.5)
due to power saving configuration enabled by
AT+UPSV command or uCPU API
The modules automatically switch from the active mode to low power
idle mode whenever possible if power saving is enabled.
The modules wake up from low power idle mode to active mode due
to any necessary network related activity, external wake-up through
the operating interfaces, or wake-up by means of dedicated uCPU API.
Active
Module is switched on with application
interfaces enabled or not suspended: the
module is ready to communicate with an
external device by means of the application
interfaces unless power saving configuration is
enabled by AT+UPSV command or uCPU API.
When the modules are switched on by an appropriate power-on event
(see 1.6.1), the module enter active mode from power-off mode.
If power saving configuration is enabled by the AT+UPSV command or
uCPU API, the module automatically switches from active to idle mode
whenever possible and the module wakes up from idle to active mode
in the events listed above (see idle mode to active mode transition
description above).
When a RF Tx/Rx data or voice connection is initiated or when RF Tx/Rx
is required due to a connection previously initiated, the module
switches from active to connected mode.
Connected
RF Tx/Rx data connection is in progress.
The module is prepared to accept data signals
from an external device unless power saving
configuration is enabled by AT+UPSV command
or uCPU API.
When a data or voice connection is initiated, the module enters
connected mode from active mode.
Connected mode is suspended if Tx/Rx data or voice is not in progress.
In such case, the module automatically switches from connected to
active mode and then, if power saving configuration is enabled by the
AT+UPSV command or uCPU API, the module automatically switches
to idle mode whenever possible. Vice-versa, the module wakes up from
idle to active mode and then connected mode if RF Tx/Rx is necessary.
When a data connection is terminated, the module returns to the
active mode.
Table 6: TOBY-L4 series modules operating modes descriptions