Xerox CX PRINT SERVER 560 User manual

Xerox 560 Computer
Reference Manual
90 30 76A

'xerox Corporation
/701 South Aviation Boulevard
lEI Segundo, California 90245
_213679-4511
©1974, Xerox Corporation
XEROX
Xerox 560 Computer
Reierence iVianuai
FIRST EDITION
90 30 76A
January 1974
Price: $7.25
Printed in U.S.A.

ii
RELATED PUBLICATIONS
Publication No.
Xerox Symbol/LN, OPS Reference Manua I
90 1790
Xerox Meta-Symbol/LN, OPS Reference Manua I
90 09 52
Xerox Macro-Symbol/LN, OPS Reference Manual
90 1578
Manual Content Codes: BP - batch processing, LN - language, OPS - operations, RP -remote processing,
RT - real-time, SM -system management, TS - time-sharing, UT - utilities.
/,LL SPECIFICATIONS SUBJECT TO CHANGE VI/ITHOUT NOTICE

CONTENTS
1. XEROX
560 COMPUTER SYSTEM
Hardware Error Trap
43
Instruction Exception Trap
44
Introduction
1 Power
On Trap
44
General Characteristics
1 Power Off Trap 44
Standard and Optional Features
3 Processor
Detected Fault Flag 44
General- Purpose Features
3 Register
Altered Bit 45
Time-Sharing Features
4
Real- Time Features
5
Multiuse Features
6
Multiprocessor Features
6
Multiprocessor Interlock
6 3.
INSTRUCTION REPERTOIRE 47
Multiport Memory System 7
Manual Partitioning Capability
7
Load/Store Instructions 49
Multiprocessor Control Function 7
Analyze/Interpret Instructions 57
Shared Input/Output
7
Fixed-Point Arithmetic Instructions
59
Comparison Instructions
66
Logical Instructions 69
Shift Instructions
70
2.
SYSTEM ORGANIZATION
8
Floating-Point Shift
72
Conversion Instructions
73
Processor Clusters 8
Floating-Point Arithmetic Instructions
74
System Control Processor 8
Floating-Point Numbers
75
Bas ic Processor 8
Floating-Point Add and Subtract
76
General Registers 8
Floating-Point Multiply and Divide
78
Memory Control Storage 11
Condition Codes for Floating-Point
Computer Modes 11
Instructions
78
Information Format 12
Decimal Instructions
80
Information Boundaries
13
Packed DecimaI Numbers 81
Instruction Register 13
Zoned Decimal Numbers
81
Main Memory
14
Decimal Accumulator 81
A A _______
I 1 __ ~ L ,4 Decimai
instruction format ~I
IVIO;::IIIVIY Villi
Maintainability and Performance 16
Illegal Digit and Sign Detection 81
Virtual and Real Memory 17 Overflow Detection 82
Types of Addressing 19 Decimal Instruction Nomenclature 82
Memory Address Control
26 Condition Code Settings 82
Program Status Words 28 Byte-String Instructions 86
Centralized Interrupts
.30
Push-Down Instructions (Non-Privileged)
96
States of an Interrupt Level
30
Stack Pointer Doubleword (SPD) 96
Dialogue Between the Basic Processor and Push-Down Condition Code Settings
97
the Interrupt System During an Push-Down Instructions (Privi leged) 101
Interrupt-Entering Sequence 32 Status Stack Pointer Doubleword
101
Dialogue During an Interrupt-Exiting Execute/Branch Instructions 106
Sequence
32 Nonallowed Operation Trap During
Physical
Organization
32
Execution of Branch Instruction 106
Interrupt Groups 32 Call Instructions 109
Control of the Interrupt System 35 Control Instructions 109
SingI e- Instruction Interrupts 36 Loading
the Memory Map
114
Trap System
36
Memory Write Protection Locks 116
Trap Entry
Sequence
36 Interruption of MMC 117
Trap Addressing
36
Memory Access Traps by MMC Instruction __ 117
Trap
Condition Code 39 Read Direct, Internal Basic Processor
Nonallowed Operation Trap
39
Control (Mode 0) 120
Push-Down Stack Limit Trap 41
Read Direct, Interrupt Control (Mode 1) __ 121
Fixed-Point Overflow Trap 41 Read Direct (Mode 9) 123
Floating-Point Arithmetic Fault Trap 42 Write Direct, Internal Basic Processor
Decimal
Arithmetic Fault Trap
42 Control (Mode 0) 123
Watchdog Timer Runout Trap
43
Input/Output Instructions 127
Programmed Trap
43
Overa" Characteristics
127
Call Instruction Trap
43 I/O Status Information 127
iii

4. INPUT/OUTPUT OPERATIO NS 142
AGURES
External DIO Interface
142 1. A Xerox 560
Computer System 9
Multiplexor Input/Output Processor (MIOP)
Devi ce Controllers
142 2.
The Basic Processor 10
Rotating Memory Processor (RMP) 143
Input/Output Processor (lOP) Fundamentals __ 143
3.
Information Boundaries 13
Command List 143
Operational IOCD
143
4. Main Memory 15
Control IOCD
146
I/o Operation Phases 148
5. Addressing Logic 18
Preparation Phase 148
Initiation Phase 148 6.
Index Displacement Alignment (Real and
Fetching Phase 148 Virtual Addressing Modes)
21
Execution Phase 149
Termination Phase
151 7.
Generation of Actual Addresses Indirect,
Virtual Addressing 22
5. OPERATIONAL CONTROL
152 8.
Index Displacement Alignment (Real-
Extended Addressing)
23
ExternaI Control Subsystem 152
Central ized System Control
152 9.
Generation of Effective Virtual Address
Control Console Devices
152
(Indirect Real-Extended Addressing)
24
Control Commands 153
Operator Control Commands 153 10. Operational States of an Interrupt Level
31
Diagnostic Control Commands 156
Maintenance Control Commands 158 1l. Interrupt Priority Chain
34
System Control Panel 161
Operating Procedures and Information ___
164
12.
Typical 28-Word Portion of Memory Stack
for PSS and P LS 102
6. SYSTEM CONFIGURATION CONTROL 167 13. Formats of I/o Instructions 128
Configuration Control Panel (CCP) 167
14. Bootstrap Loader 155
15.
APPENDIXES
System Control Panel 162
16.
Chassis Physical Configuration
168
A. REFERENC E TABLES
173
17. Sample Rows of CCP Switches 168
Standard Symbols and Codes
173
Standard Character Sets 173
Control Codes
173
Special Code Properties 173
Standard 8-Bit Computer Codes (EBCDIC) ___ 174
Standard 7-Bit Communication Codes TABLES
(ANSCII) 174
Standard Symbol-Code Correspondences
175
l.
Basic Processor Operating Modes and
Hexadecimal Arithmetic
179 Addressing Cases
25
Addition Table 179
Multiplication Table
179
2. Interrupt Locations
33
Table of Powers of SixteenlO 180
Table of Powers of Ten16 180
3.
Summary of Trap Locations
37
Hexadecimal-Decimal Integer Conversion
Table
181
4. TCC Setting for Instruction Exception
Hexadecimal-Decimal Fraction Conversion
Trap X'4D'
44
Table
187
Table of Powers of Two
191
5. Registers Changed at Time of a Trap Due to
Mathematica I Constants
191
an Operand Access 45
B. GLOSSARY OF SYMBOLIC TERMS
192
6. ANALYZE Table for Operation Codes
57
C.
FAULT STATUS REGISTERS
195
7.
Floating-Point Number Representation
76
iv

8.
Condition Code Settings for Floating-Point
19. Status Response Bits for AIO Instruction 135
Instructions
79
20. I/o Address (AIO Response) 135
9. Status Word 0 119
2l. Event Messages 153
10.
Status Word 1 119
22. Diagnostic Control (P-Mode) Commands
___ 157
11. Read Direct Mode 9 Status Word 123
23. Bit Assignments and Description, Processor
12. Chassis Type Assignments 124 Control Word, Register
Q30 (X'1 E') ___ 165
13. Description of I/o Instructions 128
24. Bit Assignments, Address Compare
Register Q31 (X'1F') 166
14. I/o Status Information (Register R) 130
25.
Functions of Processor Cluster Confi gurat ion
15. Device Status Byte (Register R or Ru1)
Control Panel Row
169
(SIO, no, and HIO only) 131
26. Functions of Memory Unit Configuration
16. Operational Status Byte (Register Ru1) 132 Control Panel Row
170
17. Status Response Bits for I/o Instructions 133 C-l.
Fault Status Registers 195
18. lOP Status Byte 134
C-2. Memory Unit Status Register 196
v

1. XEROX 560 COMPUTER SYSTEM
INTRODUCTION
The Xerox 560 general-purpose, digital, computer system
accommodates a
variety of scientific, business, real-time,
and ti me-shari ng appIi cat ions. A system incIudes system
control, basic processor, I/O processor, and main memory
(up
to 256K words) with two ports. Each major system
element performs asynchronously with respect to other
elements.
The basic system
can be readi Iy expanded. Memory access
paths can be increased from the basic two ports to a maxi-
mum of six ports. Input/output capability can be increased
by adding more
input/output processors (lOPs), device con-
trollers, and peripheral devices.
The basic processor (BP) has an extensi ve instruction set
that includes floating-point, byte-string, and decimal
instructions.
The multiaccess memory units, with
interleaving, afford a
high level of system performance. Main memory
can be
expanded in
16K word increments to a maximum of 256K
words. Address
interleaving may be performed between
memory units of like
size. The number of ports to each
memory unit can be expanded to allow independent ac-
cess to memory by up to six II processor clusters" (i. e. ,
functional groups).
Processor clusters are the grouping of two or more functions
(such as a basic processor,
an I/O processor, and inter-
faces) on a common bus. Clustering permits processors to
share common faci Iities, e. g., buses and memory inter-
faces. Therefore, the hardware is Iess redundant, hence
less complex, resulting in more reliability at a lower cost.
There
are multiple combinations of functional groups from
which
to select.
Existing Sigma 5-9 programs may be run on the system. The
upward
compatibility of the comprehensive, modular soft-
ware (assemblers, compi lers, mathematical and uti lity rou-
tines, and application packages) eliminates reprogramming.
Features
have been incorporated in this design to enhance
overall system reliability, maintainability, and availability.
Centralized switches for system repartitioning may permit
faulty units, or
an entire subsystem, to be isolated for diag-
nosis or repair while the primary system continues operation.
Parity checking is performed on each byte of information
for most system interfaces and internal control signals. Most
fai led instructions
are automatically retried, and uninter-
rupted processing continues. The only apparent effect may
be an entry in the error log. In the event an error is irre-
coverabl e, there are error storage registers that return com-
plete data on the fault and the status of the system at
that point.
GENERAL CHARACTERISTICS
The following system features and characteristics permit
efficient operation in general-purpose, multiprocessor,
time-sharing, real-time, and multiuse environments:
• Word-oriented memory (32-bit word plus parity bit
per byte) that can be addressed and altered as byte
(8-bit), halfword (2-byte), word (4-byte), and double-
word (8-byte) quantities.
•
•
•
•
•
•
•
•
•
Memory expandable to 256K words (K = 1024) in mod-
ular units of
16K words each.
Indirect addressing with or without postindexing.
Displacement
index registers, automatically self-
adjusting for all data sizes.
Immediate operand instructions for
greater storage
efficiency and increased speed.
Four blocks of
16 general-purpose registers for address-
ing, indexing, and accumulating. Multiple registers
permit rapid
context switching.
Hardware memory mapping, which
virtually eliminates
memory fragmentation and provides dynamic program
relocation.
AA ____ ... ______ ___ J.. __ L~ __ L __ _ ~ ~_L ___ ___ .-.I ! __ r ______ L~ __ _
n .... II.v., ............ "'= !-'.V."' .... IIVII 'VI ;'1;"""" ,",II,", II11V111,UIIUII
security and protection.
Memory write
protection within memory units to prevent
inadvertent destruction of critical areas of memory from
any processor cluster.
Watchdog timer to assure nonstop operation.
Real-time priority
interrupt system with automatic iden-
tification and priority assignment, fast response time,
and 14 internal and up to 48 external levels that can
be individually armed, enabled, and triggered by
program
control.
• Instructionswith long execution times can be interrupted.
• Automatic traps for error or fault conditions, with
masking
capability and maximum recoverability, under
program
control.
• Power fail-safe for automatic shutdown and resumption
of processing in
event of power fai lure.
• Multiple interval timers with a choice of resolutions
for independent ti
me bases.
• Privileged instruction logic for program integrity in
multiuse environments.
Xerox 560 Computer System

• Extensive instruction set that includes:
• Byte, halfword, word, and doubleword operations.
• Use of all memory-referencing instructions for
register-to-register operations, with or without
indirect addressing and postindexing, and within
normal instruction format.
• Multiple register operations.
• Fixed-point integer arithmetic operations in half-
word, word, and doubleword modes.
• Immediate operand instructions.
• Floating-point hardware operations in short and
long formats with significance, zero, and normal-
ization control and checking, all under full pro-
gram control.
• Full complement of logical operations (AND, OR,
exclusive OR).
• Comparison
operations, including compare between
limits (with Iimits in memory or in registers).
• Call instructions that permit up to 64 dynamically
variable, user-defined instructions, and allow a
program
access to operating system functions with-
out operating system intervention.
• Decimal hardware operations, including arith-
metic, edit, and pack/unpack.
• Byte-string instructions.
• Push-down stack operations (hardware imple-
mented) of single or multiple words, with auto-
matic Iimit checking, for dynamic space alloca-
tion, subroutine communication, and recursive
routine capabi lity.
• Automatic conversion operations, including binary/
BCD and any other weighted-number systems.
• Analyze instruction that facilitates effective
address computation.
• Interpret instruction that increases speed of inter-
pretive programs.
• Shift operations (left and right) of word or double-
word, including logical, circular, arithmetic,
searching shift, and floating-point modes.
• Built-in reliability and maintainability features that
include:
• Extensive error logging. When a fault is detected,
system status and fault information are available
for program retrieval and logging for subsequent
analysis.
2
General Characteristics
• Full parity checking on all data and addresses
communicated in
either direction on buses between
memory units and processors, providing fault de-
tection and location capability to permit the
operating system or diagnostic program to quickly
determine a faulty unit.
• Address stop feature that permits operator or main-
tenance personnel to:
Stop on
any instruction address.
Stop on
any memory reference address.
Stop when
any word in a selected page of
memory is
referenced.
• Traps that provide for detection of a variety of
fault conditions, designed to enable a high degree
of system recoverab iiity.
• Partitioning features that enable system reconfig-
uration via a centralized Configuration Control
Panel. Units may be partitioned from the system
by
selectively disabling them from buses (assuming
other system facilities can handle the additional
load). Thus, faulty units, processors, devices, or
an alternate system can be isolated from the oper-
ational system to enable diagnosis or repair whi Ie
the primary system continues operation.
• Independently operating I/O system with the following
features:
• Direct input/output (READ DIRECT, WRITE DIRECT
instructions) for transfer of 32-bit words between
the specified general register and an external de-
vice; a 16-bit address is transferred for selection
and control purposes; and each transfer is under
direct program control.
• Up to five independent I/O processor clusters (re-
stricted only by the maximum number of 6 ports).
• Multiplexor I/O processors (MIOPs) (up to 3 per
I/O cluster), each providing for simultaneous op-
eration of up to 16 devices per processor.
• Data chaining for gather-read and scatter-write
operati ons.
• Command chaining for multiple record operations.
• Write lock protect feature within memory unit
for positive
protection from all processors storing
into memory.
• Comprehensive modular software that is program com-
patible with Sigma 5-9 computers:
• Expands in
capabi Iity and speed as system grows.
•
Operating system: Control Program-Five (CP-V).

• Language processors and utilities and applications
software for both commercial and scientific users.
• Peripheral equipment includes:
• Card equipment: Reading speeds up to 1500 cards
per minute; punching speed of 100 cards per min-
ute; intermixed binary and EBCDIC card codes.
• Line printers: Fully buffered with speeds up to
1250 lines per minute; 132 print positions with
character sets containing 64 or 95 characters.
• Magnetic tape units: 9-track systems, single or
dual density (1600 or 800/1600 BPI), industry-
compatible; high-speed, automatic loading units
operating
at 125 inches per second with trans-
fer rates up to 200,000 bytes per second; and
at 75 inches per second with transfer rates up
to 120,000 bytes per second.
• Rapid Access Data (RAD) and disk files: RAD
capacity of 2.9 million bytes, with a transfer
rate of 750,000 bytes per second; disk capa-
cities in increments of 86 mi Ilion bytes (format-
ted) per unit with a transfer rate of 806,000 bytes
per second, and in increments of 49 million bytes
per unit with a transfer rate of 312,500 bytes
per second.
• Keyboard printers: 10 characters per second.
• Data communications equipment: Complete line
of character-oriented, message-oriented, and
procedure-oriented equipment to connect remote
user terminals (including remote batch) to the
computer center via common carrier lines and
local terminals directly.
STANDARD AND OPTIONAL FEATURES
A basic system has the following standard features:
• A basic processor (BP) that includes:
• Full instruction set
• Memory map with access protection
• Register blocks (4)
• Multiplexor Input/Output Processor (MIOP) with:
• 16 subchannels
• 1- or 4-byte interface
• Input/Output Adapter
• Two memory units that include:
• Dual port access
~ Memory write lock protection
• A system control processor that incIudes:
• Real-time clocks (4)
• Internal interrupts (14)
• Power fail-safe detection
• External Direct Input/Output Interface (DIO)
• External Control Subsystem
(ECS)
• System Control Panel (SCP)
• Configuration Control Panel (CCP)
• Local and remote assist facility
• Error detecti on faciIiti es
• Diagnostics
A system may have the following optional features:
• BP options:
• Up to 48 external priority interrupts (in groups
of 12)
• Memory options:
• Memory expansion up to 256K words
• Up to 4 additional access ports (in sets of 2).
• Input/ Output options:
•
Multiple I/O cluster/.
• Up to 3 additional MIOPs, each with 16 sub-
channels, per cI uster.
• One Input/Output Adapter (for one MIOP)
per cluster.
• One Rotating Memory Processor (RMP) per
cluster.
GENERAL-PURPOSE FEATURES
General-purpose computing applications are characterized
by emphasis on computation and internal data handling.
tThe
aggregate of processor clusters is restricted by the max-
imum memory port limitation of 6.
Standard and Optional Features/General-Purpose Features 3

Many operations are performed in floating-point format
and on strings of characters. Other typical characteristics
include decimal arithmetic operations, binary to decimal
number conversion (for printing or display), and high sys-
tem i nput/ output transfer rates.
General-purpose features are described in the following
paragraphs.
Floating-Point Hardware. Both short (32-bit) and long
(64-bit) formats are available in the floating-point in-
structions. Under program control, the user may select
optional zero checking, normalization, floating-point
rounding and significance checking. Significance check-
ing permits use of short floating-point format for high pro-
cessing speed and storage economy and of long floating-
point format when loss of significance is detected.
Decimal Arithmetic Hardware. Decimal arithmetic instruc-
tions operate on up to 31 digits plus sign. This instruction
set includes pack/unpack instructions for converting to/from
the packed format of two digits per byte, and a generalized
edit instruction for zero suppression, check protection, and
formatting, with punctuation to display or print it.
Indirect Addressing. Indirect addressing faci litates table
linkages and permits keeping data sections of a program
separate from procedure sections for ease of maintenance.
Displacement Indexing. Indexing by means of a IIfloating
li
displacement permits accessing a desired unit of data with-
out considering its size. The index registers automatically
align themselves appropriately; thus, the same index reg-
ister may be used on arrays with different data sizes. For
example, in a matrix multiplication of any array of full
word, single-precision, fixed-point numbers, the results
may be stored in a second array as double-precision num-
bers, using the same index quantity for both arrays. If an
index register contains the value of k, then the user always
accesses the kth element, whether it is a byte, halfword,
word, or doubleword. Incrementing by various quantities
according ro daro size is nor required; instead, increment-
ing is always by units in a continuous array table regardless
of the size of data element used.
Instruction Set. More than 100 major instructions permit
short, highly optimized programs to be written. These are
rapidly assembled and minimize both program space and
execution time.
Translate Instruction. The Translate instruction permits
rapid translation between any two 8-bit codes; thus, data
from a variety of input sources can be handled and re-
converted easi iy for output.
Conversion Instructions. Two generalized conversion in-
structions provide for bidirectional conversions between
internal binary and any other weighted number system,
including BCD.
4 Time-Sharing Features
Call Instructions. These four instructions permit handling
up to 64 user-defined subroutines, as if they were built-in
machine instructions. Call instructions also gain access to
specified operating system services without requiring its
intervention.
Interpret Instruction. The Interpret instruction simplifies
and speeds interpretive operations such as compilation, thus
reducing space and time requirements for compilers and
other interpretive systems.
Four-Bit Condition Code. Checking results is simplified by
automatically providing information on almost every instruc-
tion execution, including indicators for overflow, under-
flow, zero, minus, and plus, as appropriate, without
requiring an extra instruction execution.
Direct Input/Output (DIO). Direct input/output faci li-
tates in-line program control of asynchronous or special-
purpose devices. This feature permits information to be
transmitted directly to or from general-purpose registers.
Multi lexor Input/Out ut Processor (MIOP). Once initia-
lized, I 0 processors operate independently of the basic
processor, freeing it to provide faster response to system
needs. An MIOP requires minimal interaction with the
basic processor. I/O command doublewords permit both
command chaining and data chaining without intervening
basic processor control. I/o equipment speeds range from
slow rates involving human interaction (teletypewriter, for
example) to transfer rates of rotating memory devices of
over 750,000 bytes per second. Peripheral controllers at-
tached to an MIOP may be operated simultaneously.
Rotating Memory Processor (RMP). An RMP supports up to
15 disk drives, one at a time, permitting large capacity,
high transfer rate files. Dual access (between 2 RMPs) op-
tion is available.
TIME -SHARING FEATURES
Time-shari ng is the abi Ii ty of a system to share its totaI
resources among many users at the same time. Each user
may be performing a different task, requiring a different
share of the available resources. Some users may be on-
line in an interactive, IIconversational
li
mode with the
basic processor while other users may be entering work to
be processed that requires only final output.
Time-sharing features are described in the following
paragraphs.
Rapid Context Saving. When changing from one user to
another, the operating environment can be switched quickly
and easily. Stack-manipulating instructions permit storing
in a push-down stack of 1 to 16 general-purpose registers by
a single instruction. Stack status is updated
automatically
and information in the stack can be retrieved when needed

(also, by a single instruction). The current program status
words, which
contain the entire description of the current
user's environment and mode of operation, may be stored
anywhere in memory, and new program status words may be
loaded,
all with a single instruction.
Multiple Register Blocks. The availability of four blocks
of 16
general-purpose registers improves response time by
reducing
the need to store and load register blocks. A
distinct block may be assigned for different functions as
needed; the program status words
automatically select the
applicable register block.
User Protection. The
slave mode feature restricts each user
to his own set of instructions while reserving to the operat-
ing system certain "privileged" (master mode) instructions
that could destroy another user's program if used incor-
rectly. Also, a memory access -protection feature pre-
vents a user from accessi ng any storage areas other than
those assigned to him. It permits him to access certain areas
for reading only, such as those containing public subrou-
tines, while preventing him from
reading, writing, or ac-
cessing instructions in areas set aside for other users.
Storage Management. Main memory
is expandable to 256K
(K = 1024) words. To make efficient use of available mem-
ory,
the memory map hardware permits storing a user's pro-
gram in fragments as sma II as a page of 512 words, wherever
space is available; yet all fragments appear as a single,
contiguously addressable block of storage at execution time.
The memory map also automatically handles dynamic pro-
gram relocation so that the program appears to be stored in
n dnnrlrlrt"l v.i0}' 0t ~X~ClJt!0!",! t!!'!'!e, e'!e!"! th0~gh it !'!'!cy cc-
tually be stored in a different set of locations each time it
is brought into memory. The memory map provides the
abiIity to locate any 128K-word virtual program in the basic
processor's logical addressing space. Thus, the system can
always address a virtual memory of 128K words regardless
of physical memory
size.
Input/Output Capability. Time-sharing input/output re-
quirements are handled by the same general-purpose input/
output capabi Iiti es described under II Genera I-Purpose
Features".
Nonstop
Operation. A "watchdog" timer assures that the
system continues to operate even in case of halts or delays
due to fai lure of special I/O devices. Multiple real-time
clocks with varying resolutions permit independent time
bases for
flexible allocation of time slices to each user.
Reliability,
Maintainability, Availability. Since time-
sharing systems have many on-line users needing immediate
system response, "downtime"
defeats time sharing's primary
purpose. Pool i
ng of resources along wi th fl exi bl e recon-
figuration control ensures a high level of continuous avail-
ability. Configuration controls are provided to switch the
load from one
unit to another in the event of a failure with
no loss of functional
capability, only capacity. In addi-
tion, a nonworking subset of the total system may be
logically isolated (partitioned) so that maintenance may
proceed on
the subset while the remainder of the system
continues
to operate.
To minimize the effect of transient errors, automatic retry
of failed instructions is performed.
REAL-TIME FEATURES
Real-time applications are characterized by a need for:
(1) hardware that provides quick response to an external
environment;
(2) speed that is sufficient to keep up with
the real-time process itself; (3) input/output flexibility to
handle a wide variety of data types at different speeds;
and (4) reliabi lity features to minimize irreplaceable lost
time.
Multilevel, Priority Interrupt System. The real-time-
ori ented system provides rapid response to external interrupt
levels. Each interrupt is
automatically identified and res-
ponded to according to its priority. For further flexibi lity,
each level can be individually disarmed (to discontinue in-
put acceptance) and disabled (to defer responses). Use of
the disarm/disable feature makes programmed dynamic re-
assignment of priorities quick and easy, even while a real-
ti me process is in progress.
Programs involving interrupts from specially designed equip-
ment often require checkout before the equipment is actually
avai lable. To permit simulating this special equipment, any
external interrupt level can be "triggered" by the basic
processor through
execution of a single instruction. This
capability is also useful in establishing a modified hierarchy
of responses. For
example, in responding to a high-priority
interrupt, after the urgent processing is completed, it may
be desirable to assign a lower priority to the remaining por-
tion so that the interrupt routine is free to respond to other
critical stimul i. The interrupt routine can accomplish this
by triggering a
lower-priority level, which processes the
remaining data only after other interrupts have been handled.
READ DIRECT and WRITE DIRECT instructions (described in
Chapter 3) allow the program to completely interrogate,
preserve, and a I ter the condition of the interrupt system at
any time and to restore that system at a later time.
Nonstop
Operation. When connected to special devices
(on a ready/resume basis), the basic processor may be ex-
cessively delayed if the specific device does not respond
quickly. As in the time-sharing environment, the built-in
watchdog timer assures that the basic processor cannot be
delayed for an excessive length of time.
Real-Time Clocks. Many
real-time functions must be timed
to
occur at specific instants. Other timing information isalso
needed -for example, elapsed time since a given event, or
the
current time of day. The computer system can contain
up to four real-time clocks with varying degrees of resolu-
tion to meet these needs. These clocks a I so a II ow easy hand-
ling of separate time bases and relative time priorities.
Real-Time Features 5

Rapid Context Switching. When responding to a new set of
interrupt-initiated circumstances, a computer system must
preserve
the current operating environment, for continuance
later, whi Ie setting up the new environment. This changing
of environments must be done quickly, with a minimum of
II overhead
ll
time costs. Anyone of the four blocks of
general-purpose arithmetic registers can, if desired, be as-
signed to a specific environment. All relevant information
about the current environment (instruction address, current
general register block, memory-protection key, etc.) is
kept in
the program status words. A single instruction
stores
the current program status words anywhere in memory
and loads new ones from memory
to establish a new en-
vironment, which includes information identifying a new
block of
general-purpose registers. Thus, the system's
operating environment can be preserved and changed com-
pletely through the execution of a single instruction.
Memory Protection. Both foreground
(real-time) and back-
ground can run concurrently in the system because a fore-
ground program is protected against destruction by an un-
checked background program. Under operating system
control, the memory access-protection feature prevents
accessing memory for specified combinations of reading,
writing, and instruction acquisition.
Variable Precision Arithmetic. Much of the data encoun-
tered in real-time systems are 16 bits or less. To process
this
data efficiently, both halfword and fullword arithmetic
operations are provided. For extended precision, double-
word arithmetic operations are also included.
Direct Input/Output. For handling asynchronous I/O, a
32-bitword can be transferred direct!y between any genera!-
purpose register and external devices.
Reliability, Maintainability, Availability. The capabil-
ities described in the section, II Time-Sharing Features
ll
apply equally to the real-time environment.
MULTIUSE FEATURES
As implemented in this system, IImultiuse
ll
combines two or
more
application areas. The real-time application is the
most difficult general computing task because of its severe
requirements. Similarly,
another difficult multiuse task is
a time-sharing
application that includes one or more real-
time processes. Because the system is designed on a real-
time base, it is qualified for a mixture of applications in a
multiuse environment. Many hardware features
that prove
valuable for Certain application areas are equally USeful in
others, although in different ways. This multiple capa-
bility makes the system particularly effective in multi-
use applications.
The major multiuse features are described in the follow-
i ng paragraphs.
6 Multiuse Features/Multiprocessor Features
Priority Interrupt System. In a multiuse environment, many
elements
operate simulatneously and asynchronously. Thus,
an efficient priority interrupt system is essential. It allows
the computer system to respond quickly, and in proper or-
der, to the many demands made on it, with attendant im-
provements in resource efficiency.
Quick Response. The many features that combine to pro-
duce a quick-response system (multiple register blocks,
rapid
context saving, multiple push-pull operations) benefit
all users because more of the system's resources are readi Iy
avai lable at any instant.
Memory Protection. The memory protection features
protect
each user from every other user and guarantee the integrity
of programs essential to
critical real-time applications.
Input/Output. Because of the wide range of capacities and
speeds,
the I/O system simultaneously satisfies the needs of
many
different application areas economically, both in
terms of equipment and programming.
Instruction Set. The comprehensive instruction
set provides
the computational and data-handling capabilities required
for widely differing
application areasi therefore, each user's
program length and running time is minimized, and the
throughput is maximized.
MULTIPROCESSOR FEATURES
System design readily permits expansion to shared memory
in a multiprocessor system. The system
can contain a com-
bination of functional clusters, each of which in turn may
contain multiple processors. The total number of clusters
is restricted to the maximum port limitation of six. All
pro-
cessors ina system may share common memory.
The following paragraphs describe
the major multiprocessor
features of the system,
MULTIPROCESSOR INTERLOCK
In a multiprocessor system, the basic processors often need
exclusive control of a system resource. This resource may
be a region of memory, a
particular peripheral device, or,
in some
cases, a specific software process. There isa special
instruction
to provide this required multiprocessor interlock.
This special instruction,
LOAD AND SET, unconditionally
sets a
11111 bit inthe sign position of the referenced memory
location during the restore cycle of the memory operation.
If this bit had been previously set by another processor, the
interlock is said to be IIset" and the testing program pro-
ceeds to another task. On the other hand, if the sign bit
of
the tested location is a zero, the resource is allocated
to the testing processor, and simultaneously the interlock
is set for any other processor.

MULTIPORT MEMORY SYSTEM
The system has growth capabi Ii ty of up to 6 ports per
memory unit. A memory unit may contain 16K or32K words.
This architecture allows flexibility in growth patterns
and provides high memory bandwidth, essential to multi-
processor systems.
MANUAL PARTITIONING CAPABILITY
Manual partitioning capability is afforded for all system
units. Thus, besides the primary advantage of increased
throughput, a secondary advantage of a multiprocessor
system is the "fail-soft" abiIity. Given a duplicate unit,
any unit can be partitioned by selectively disabling it from
the system buses. Depending on the type of fai ling unit,
the system wi II be operable, with some degree of degraded
performance. An alternate processor bus with dual system
capabilities can be provided.
MULTIPROCESSOR CONTROL FUNCTION
A multiprocessor control function is provided on all multi-
processor systems. This function provides these basic features:
1. Control of the External Direct Input/Output bus (Ex-
ternal DIO), used for controlling system maintenance
and special purpose units such as analog to digital
converters.
2. Central control of system partitioning.
3. Centralized interrupt system, providing capability for
the operating system to use interrupts to schedule tasks
independently of the number of basic processors pres-
ent in a system.
4. Processor to processor communication via processor
buses.
SHARED INPUT/OUTPUT
In a multiprocessor system, any basic processor may direct
I/o actions to any I/O processor. Specifically, any basic
processor can issue an SIO, no, TDV, or HIO instruc-
tion to begin, test, or stop any I/O process. However,
the "end-action
ll
sequence of the I/O process is directed
to one of the basic processors in the system by the System
Control Processor. This feature (accomplished by setting
a pair of configuration control switches) allows dedicating
I/o end-action tasks to a single processor and avoids con-
flict resolution problems.
Multiprocessor Features 7

2. SYSTEM ORGANIZATION
The elements of this computer system include a basic
processor
(BP), input/output processors (lOPs), memory, I/o
device controllers, and devices (see Figure 1). The pro-
cessors and interfaces clustered into functional groups, in-
terconnected via buses and controlled from a Configuration
Control Panel and a System Control Processor. Elements
within a processor cluster share an access path for intra-
cluster communications. Thus, the total computer system can
be viewed functionally as a group of program-controlled
processor clusters communicating with each other and a
common memory. Each processor
cluster operates asyn-
chronously and semi-independently, automatically over-
lapping the operation of elements within as well as the
operation of other processor clusters for greater speed (when
circumstances permit).
PROCESSOR CLUSTERS
Processors (basic processor and MIOP, for example) are
grouped functionally along with a Memory Interface (MI)
and a Processor Interface (PI) into a processor cluster. El-
ements within a processor cluster share an access path (the
cluster bus) to the Memory Interface, which connects to the
memory system via a memory bus. The Memory Interface
resolves contention problems and controls use of the cluster
bus by the elements in the cluster.
A processor communicates with processors in other processor
clusters through the Processor
Interface, which connects di-
rectly to a processor bus. Via the processor bus, any pro-
cessor can communicate with or control any other processor
anywhere in the system configuration.
Note: Although two processor buses are provided, a Pro-
cessor
Interface can be connected to one or the
other of the processor buses, but not to both at the
same
time.
Within a basic processor-MIOP processor cluster, the basic
processor primari
Iy performs overa II controI and data reduc-
tion tasks whereas the MIOP performs the task associated
with the exchange of digital information between main
memory
and selected peripheral devices. The MIOP com-
municates with device controllers via the I/o bus, which
connects to the Controller Interface (CI).
SYSTEM CONTROL PROCESSOR
The System Control Processor performs these primary func-
tions in the overall system:
1• System
control.
2. External Control Subsystem.
8 System
Organization
3. Internal and external interrupt processing.
4. External and certain internal direct I/o (DIO) control.
It provides these major interfaces with other parts of the
system:
1. System console interface.
2. System controI bus interface.
3. Processor bus interface.
4. InternaI and externa I interrupt interfaces.
5. External and certain internaI DIO interfaces.
6. System clock interface.
In addition to these major interfaces it provides paths for
other signals including system reset, 1.024 MHz clock,
power on/power off trap requests, and external real-time
clocks.
Figure 1 shows the interconnection of a System Control Pro-
cessor to processor clusters via a processor bus as well as
in-
terconnection to the system console, external Direct Input/
Output (DIO), and external interrupts.
BASIC PROCESSOR
This section describes the organization and operation of the
basic processor in terms of instruction and data formats, in-
formation processing, and program control. The basic pro-
cessor comprises a fast memory and an arithmetic and control
unit as functionally shown in Figure 2.
Note: Functionally associated with the basic processor bUT
physically located elsewhere are a memory map,
memory
access protection codes, and memory write
protection codes. Memory control storage for the
memory map
and access codes is located in the Mem-
ory
Interface, and the memory control storage for
the write protection codes (write locks) is located
in the memory. These functions are described in
"Memory System", later in this chapter.
GENERAL REGISTERS
A fast (integrated circuit) memory consisting of ninety-six
32-bit registers is used within the basic processor. A group
of 24 registers is referred to as a register block; thus, a
basic processor contains four register
blocks. A 2-bit con-
trol field (called a register block pointer) in the program
status words
(PSWs) selects the register block currently

System
Control
Console
System
Control
Processor
Memory
UnH Memory
Unit
~~ss;- - - - ---,
r
I
I Cluster (Basic) 1
I I I
I I
Memory I
I Interface
I
I
I
I
I
I
Processor
Interface
I
I
I
Processor IBus #1 I
I I
I I
I I
Memory
Unit
~~-;:- --- -,
Cluster (I/O)
Memory
Interface
Processor
Interface
r---
____ I ~
I I ~
rocessoq BUS 1fT T"2
.--1---,
System I
Control I
Processor I
L_[_J
r- --,
1 System I
I Control I
LC~o~J
External Interrupts
Basic
Processor
MIOP
I I ~
·u
I
I
I
I
I
I
I
I
I
Remote Terminal Console Inputs
DIO
Bus
Communications
.-------1 Interface
90 30 76A-l (1/74)
Line
Adapter
Line
Adapter
Comm.
Lines
Comm.
Lines
Device
Controller
Device
Controller
Dual Access Option
o
~
Device
Controller
Figure 1. A Xerox 560 Computer System
RMP
MIOP
Basic Processor 9

FAST MEMORY
ARITHMETIC AND CONTROL UNIT
GENERAL REGISTER BLOCK (TYPICAL)
INSTRUCTION REGISTER
0~1 ______________ ~
1
:::::::::::::.:.:.:::. ~:~:~:~:~:~:~:~:~:~:~:) .. ~:.'~.:~:.~ .. :~ .. :~.:~: .. ~: .. ::.~.:~:. . .............. .
I
··············· ............ : .. -:.:-:.: .. -:.:-......... ........................ .:.:.:- ......... ,
~~~~~~~~~~~:~~;:~:;:; ~:~:~:~:~:;~~;~~~~~~~~r~~~~~:;:~:;:::::::::::::: ·t~:~r~~~~~
I
~:-:·:·:·:·:·:·:·:·:·: .-:::::::::::::::::::::::.: .. :::::.:.:.:.:.:.:.:.:-:.:.:.:.:. ::::::::::::::::::::::::::. :::::::::::::::1
2 {:rrr::r ::::::)~.: ................. :. ::::)):::::::nc:::::::::::::::::::::::::::.:::::: ::::::rt~:l
3
(:: ::.:.:.::::::::: .. :.:.:::..... .:.:.:.:.:.:.:.. >f>~{:: ::::::::::: :.:.:.:-::::::: :::::;:::: : .. ::: .. : .. :': .. ' .. :.::.' .. :': .. :~.:: .. ' .. ::: .. : .. : ... '.:: .. :: .. 1
I Jf;~;~;;;; Itf}~}::::: ............... :.:.:.:.: .. ,:.:: .. - ... - ...... ::::::;::::::::: ~
4 1::I:::::~::::::I::::::::::::::r::r:::::j:: :::::::;:::;::::::f::t::::::::::::::; :::::::::::::::::::::::::::::::::::1
5 1::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::1 .::::):r::::::=::::::::::::::::·: ,::::::::::::::I:I:t::tl
8~1 ______________ ~
9 ..... 1 ________ ......
1O~1 ______________ ~
11 I"-- ________________ ~
12 ~I ________________ ~
13 ~I ________ ~
14 ~I _________ .....
15
16 Jl
----------------------
171 ~ __________ ......
18 I~ ________________ __
19 IL... ________ ....
20 ..... 1 ________ ......
21 ..... 1 ________ _
Index
Registers
o Indirect Access Flag
o
III 1111 I Operation Code Field
1 7
DID General Register Designator
8 11
ITIJ Index Register Designator
12 14
Reference Address Field
111111111 11111111 III
15 31
....... -- ....
Memory
1
31-digit
Decimal
Accumu-
lator
Reserved
PROGRAM STATUS WORDS
OJ]] Condition Code
o 3
I/O Processors I
I I
I
Read/Write Direct
1 •
Interrupts
Mopping
• •
.Access Protection.
ITO Floating-point Mode Control
5 7
o Master/Slave Mode Control
8
DMemory Map Control
9
[JJ Arithmetic Trap Masks
1011
Instruction
,..,...'T"'"T""'T'"T..,....,~'T"'"T""'I""T"'T'"'T..,....I""""I Address
Id IIIIIIIIIII" III or
15 31 Extended
[ill Write Key
32 35
[ill Interrupt Inhibits
37 39
OJ Register Block Pointer
5859
oRegister AI tered
60
Displacement
o Mode Altered Control
61
L---..I :: --=---=----=------,1 ~I _--------'
Figure 2. The Basic Processor
10 Basic Processor

available to a program. The register block pointer can be
changed when the basic processor is in the master mode or
the master-protected mode. Only the first 16 general reg-
isters of a register block may be used by programs; the last
eigh
tare reserved.
Each of the first 16 general registers in a register block is
identified by a 4-bit code in the range 00002 through 11112
(0 through 15 in decimal notation, or XIO
I through XIF I in
hexadecimal notation). Any of these 16 registers can be
used as a fixed-point temporary data storage location, or
to contain control information such as a data address, count,
pointer, etc. General registers 1 through 7 can be used
as index registers
and registers 12 through 15 can be used
as a
decimal accumulator capable of containing a decimal
number of 31 digits plus sign. Registers 12 through 15 are
always used when a decimal instruction is executed.
MEMORY CONTROL STORAGE
The memory control storage for the memory map and the
associated memory access protection codes are contained
in the Memory Interface (MI). Memory control storage for
the
4-bit write locks are contained in the memory units.
Memory control storage can be modified when the basic
processor is in the master mode or the master-protected
mode.
MEMORY MAP
Two terms are essential in understanding the memory map-
ping concept: actual (i .e., absolute or real) address and
virtuaI address.
An actual address is used within the memory unit (memory
address registers)
to access a specific, physical memory lo-
cation for storage or retrieval of information as required by
the
execution sequence of an instruction. Actual addresses
are fixed and are dependent on the wired-in hardware.
A virtual address refers to a logical location as required by
an individuaI program. Like an actual address, a virtual
address may designate a location that contains a program
instruction, an element of data, a data address (indirect
address), or it may also be an explicit quantity. Normally,
virtua I addresses are derived from programmer-supplied
labels through
an assembly (or compi lation) process followed
by a loading process. Virtual addresses may also be com-
puted during a program IS execution. Virtual addresses in-
clude all instruction addresses, indirect addresses, and
addresses used as counts within a stored program, as well as
those instructions computed by
the program. (See "Virtual
and Real Memory", later in this chapter.)
Memory mapping transforms virtual addresses as seen by the
individual program into actual addresses as seen by the
memory system. Thus, when the memory map is in effect,
any program can be broken into 512-word pages and dy-
namically relocated throughout memory in whatever pages
of space are available.
When the memory map is not in effect, all virtual address
values above 1510 are used by the memory as actual ad-
dresses. Virtual addresses 0 through 15 are alwayst used by
the basic processor as general register addresses rather than
as memory addresses. For example, if an instruction uses
virtual address 5 to address the location where a result is
to be stored, the basic processor stores that result in gen-
eral register 5 in the current register block instead of in
memory
location 5.
When the basic processor is operating with the memory map
in
effect, virtual addresses 0 through 15 are still used as
general register addresses. Virtual addresses above 15 are
transformed into actual addresses by replacing the high-
order portion of the virtual address with a value obtained
from the memory map. (The memory map address replace-
ment process is described in "Memory Address Control ",
later in this chapter.)
MEMORY ACCESS PROTECTION
When the basic processor is operating with the memory map
in
the slave mode or the master-protected mode, the access
protection codes determine whether the program may access
instructions from, read from, or write into specific regions
of the virtual address continuum (virtual memory). If the
slave mode or master-protected mode program attempts to
access a protected region of virtual memory, a trap occurs
(see "Memory Address Control ", "Virtual and Real Mem-
ory", and "Trap System", later in this chapter).
MEMORY WRITE PROTECTION
The memory write-protection feature operates independently
of access protection and the memory map. The 4-bit write
lock operates in conjunction with a 4-bit field, called the
write key, in bits 32-35 of the Program Status Words (PSWs).
The lock and the key determine whether any program may
alter any word of main memory. The write key can be
changed when the basic processor is in the master mode or
the master-protected mode. (The functions of the write
lock and key are described in "Memory Address Control II,
later in this chapter.)
COMPUTER MODES
The basic processor operates in one of three modes: master,
master-protected, or slave. The operation mode is deter-
mined by the setting of three bits (bits 8, 9, and 61) of the
Program Status Words (PSWs). (See IIProgram Status Words",
later in this chapter.) Additionally, the basic processor
operates in a mapped mode or an unmapped mode.
tExcept for the READ DIRECT (RD)/WRITE DIRECT (WD) in-
structionswhich can read from and store into these locations.
Basic Processor 11

MASTER MODE
The master/slave control bit (bit 8 of the PSWs) must con-
tain a zero for the basic processor to operate in master
mode. In th is mode the basic processor can perform a II of
its control functions and can modify any part of the system.
The restrictions upon the basic processor1s operations in this
mode are those imposed by the write locks on certain pro-
tected parts of memory. It is assumed that there is a res-
ident operating system (operating in the master mode) that
controls and supports the operation of other programs (which
may be in the master, master-protected, or slave mode).
MASTER-PROTECTED MODE
The master-protected mode of operation provides additional
protection for programs that operate in the master mode. The
master-protected mode occurs when the basic processor is
operating in the master mode with the memory map in effect
and the mode altered control bit (bit 61 of the PSWs) is on.
In this mode the memory protection violation trap occurs
(location XI 40
I,
with CC4 = 1), as it does in all mapped
slave programs, if a program makes a reference to a virtual
page to which access is prohibited by the current setting of
the access protecti on codes.
SLAVE MODE
The slave mode of operation is the problem-solving mode
of the basic processor. In this mode, access protection
codes apply to the slave mode program if mapping is in ef-
fect, and all IIprivileged II operations are prohibited. Priv-
ileged operations are those relating to input/output and to
changes in the fundamental control state of the basic pro-
cessor. All privileged operations are performed in the
master or master-protected mode by a group of privileged
instructions. Any attempt by a program to execute a priv-
ileged instruction whi Ie the basic processor is in the slave
mode results in a trap. The master/slave mode control bit
(bit 8 of the PSWs) can be changed when the basic processor
is in the master or master-protected mode. Nevertheless,
a s!aVe mode program can gain direct access to certai!1 ex-
ecutive program operations by means of CALL instructions.
- The operations avai lable through CALL instructions are es-
tablished by the resident operating system.
MAPPED MODE
Although the memory map is located in the Memory Inter-
face (MI), it functions as part of the basic processor. The
basic processor communicates with memory through the MI.
Mapping is effective for all the words of real memory, and
is invoked when bit 9 (MM) of the PSWs contains a one.
Memory mapping generates real page addresse:s from vir-tual
addresses. The memory map can be loaded with either
11-bit real page addresses or 8-bit real page addresses by
meansofthe MOVE MEMORY CONTROL (MMC) privileged
instruction (see Chapter 3, "Control Instructions "). Eleven-
bit real page addresses are always provided for in the map,
thus if 8-bit real page addresses are generated, the three
12 Basic Processor
high-order bits contain zeros. The memory map always maps
17-bit virtual addresses into 20-bit real addresses (see
IIMemory Address Control II, later in this chapter for a dis-
cussion of how the map is used).
UNMAPPED MODE
When the basic processor is operating in the unmapped mode,
there is a direct one-to-one relationship between the effec-
tive virtual address of each instruction and the actual ad-
dress used to access main memory. (See II Rea I Addressing
ll
,
later in this chapter.)
INFORMATION FORMAT
Nomenclature associated with digital information within the
computer system is based on functional and/or physical at-
tributes. A "word" may be either a 32-bit instruction word
or a 32-bit data word.
The bit positions of a word are numbered from 0 through 31
as follows:
A word
can be divided into two 16-bit parts (halfwords) in
wh
ich the bit positions are numbered from 0 through 15 as
follows:
A word can also be divided into four 8-bit parts (bytes) in
which the bit positions are numbered 0 through 7 as follows:
Two words
can be combined to form a 64-bit element (a
doubleword) in which the bit positions are numbered 0
through 63 as follows:
I : Least Signif~cant word: I
n " " "I~ ~ '" '" ~ " " ,,1« " " ,,:« " '" "I" ,; ,. ,,' ~ " " "1M,, " "
In fixed-point binary arithmetic each element of information
represents nurneiical data as a signed integer (bit 0 repre-
sents the sign, remaining bits represent the magnitude, and
the binary point is assumed to be just to the right of the
least significant or righi-most bit). Negative va lues are
represented in two1s complement form. Other formats re-
quired for floating-point and decimal instructions are de-
scribed in Chapter 3.

INFORMATION BOUNDARIES
Basic processor instructions assume that bytes, halfwords,
and doublewords
are located in main memory according to
the following boundary
conventions:
1. A byte is located in bit positions 0 through 7, 8
through 15,
16 through 23, and 24 through 31 of a
word.
Doubleword
Word (even address) Word (odd address)
Halfword 0 Halfword 1 Halfword 0 Halfword 1
Byte
O! Byte 1 Byte 2!Byte 3 Byte 0!Byte 1 Byte 2!Byte 3
2. A halfword is located in bit positions 0 through 15 and
16 through 31 of a word.
3. A doubleword is located such that bit positions 0 through
31 are contained within an even-numbered word, and
bit positions 32 through 63 are contained within the
next consecutive word (which is odd-numbered).
Figure 3 illustrates these boundaries.
Doubleword
Word (even address) Word (odd address)
Halfword 0 Halfword 1 Halfword 0 Halfword 1
Byte
O! Byte 1 Byte 2!Byte 3 Byte 0!Byte 1 Byte 2!Byte 3
Figure
3. Information Boundaries
INSTRUCTION REGISTER
The instruction register contains the instruction the basic
processor is currently executing. The format and fields of
the two general types of instructions (memory reference and
immediate operand) are described below. Specific formats
for
each instruction are given in Chapter 3.
MEMORY REFERENCE INSTRUCTIONS
Instructions that make reference to an operand in main mem-
ory may
have the following format:
Bits Description
o
1-7
Indirect addressing. One level of indirect ad-
dressing is performed only if this bit position con-
tains a one.
Operation code. This 7-bit field contains the code
that designates the operation to be performed. See
the inside front and back covers for complete list-
ings of operation codes.
8-11 R field. For most instructions this 4-bit field des-
ignates one of the first 16 general registers of the
current register block as an operand source, result
destination, or both.
12-14 X field. This 3-bit field designates one of general
registers 1-7 of the current register block as an
Bits Description
12-14 index register. If X contains zero, indexing will
(cont.) not be performed; hence register 0 cannot be used
as
an index register. (See "Address Modification
Example: Indexing (Real and Virtual Addressing) ",
later in this chapter for a description of the
indexing process.)
15-31 Reference address. Th is 17 -b it fi eId norma II y con-
tains the reference address of the instruction oper-
and. The reference address is translated into an
effective virtual address in accordance with the
addressing type (real, real extended, or virtual)
and the address modification required (direct!
indirect or indexing). (See "Memory Reference
Addresses"
later in this chapter.)
IMMEDIATE OPERAND INSTRUCTIONS
Immediate operand type instructions are particularly effi-
cient because the required operand is contained within the
instruction word. Hence, memory reference, indirect ad-
dressing, and indexing are not required.
Bits
o
Description
Bit position 0 must
be coded with a zero. If it
contains a one, the instruction is interpreted as be-
ing nonexistent. (See "Trap System ", later in this
chapter. )
Bas ic Processor 13

Bits
1-7
8-11
12-31
Description
Operation code. This 7-bit field contains the code
that designates the operation to be performed.
When the basic processor encounters any immedi-
ate operand operation, it interprets bits 12-31 of
the instruction word as an operand. These are the
immediate operand operation codes:
Operation
Code
X' 02
1
X' 21
1
X' 22
1
X' 23
1
Instruction
Name
Load
Conditions
and Floating Con-
trol Immediate
Add Immediate
Compare Immediate
Load
Immediate
Multiply Immediate
Mnemonic
LCFI
AI
CI
LI
MI
R field. This 4-bit field designates one of the
first 16 general registers in the current general
register block. The register may contain another
operand and/or be designated as the register in
which the results of the operation are to be
stored or accumula ted.
Operand. This 20-bit field contains the immedi-
ate operand. Negative numbers are represented
in two1s complement form. For arithmetic opera-
tions bit 12 (the sign bit) is extended by duplica-
tion to the left through bit position 0 to form a
32-bit operand.
The byte-string instructions (described in Chapter 3) are
simi lar to immediate-operand instructions in that they can-
not be modified by indexing. Nevertheless, the operand
field of byte-string instructions contains either a byte
address displacement or a byte address that is a virtual ad-
dress subject to modification by the memory map. If a
byte-string instruction has a one in bit position zero, the
basic processor treats it as a nonexistent instruction (see
"Trap System ", later in this chapter).
MAIN MEMORY
The memory system comprises memory units, memory inter-
faces (MIs), and memory buses. Figure 4 illustrates the re-
lationships among these components.
The primary technology for main memory is magnetic core.
The maximum physical storage is 256Kwords. Memory units
can be interleaved on a two-way interleave basis. Each
memory
unit is provided with a set of starting address
switches on the Configuration Control Panel (see Chapter 6)
together with a two-position switch that selects one of two
14
Main Memory
possible
clock and power sources. Memory units may con-
tain two, four, or six ports, which have a fixed priority
order for the resolution of contention problems.
The following sections describe the organization and opera-
tion of the memory system. Also described are the various
modes
and types of addressing, including indexing.
MEMORY UNIT
Main memory is divided physically and logically into one
to eight module assemblies called memory units. Because
the memory unit is a logical component that contains all the
functions available in the entire memory, the minimum mem-
ory
is one memory unit. The minimum storage capacity per
memory
unit is 16K words; the maximum is 32K words. A
memory
location stores a word of 36 bits; the first 32 bits are
information and the last 4 are byte parity bits (the latter
being unavai lable to the program). Each memory unit com-
prises a specific storage capacity, drive and sense circuits,
a set of operational registers (address, data, and status), a
set of write lock control registers for 32K words of memory,
and a timing and control unit.
CORE MEMORY MODULES
Core memory modules (CMMs) provide a storage facility of
standard modules (see Figure 4).
MEMORY DRIVER
The memory driver in each memory unit performs all memory
operations except storage (provided for by the CMMs) and
the few operations performed by the ports. The major func-
tions of the memory driver are:
1• Store address word.
2. Store data-in and data-out words during memory
cycles.
3. Store write locks in special memory (other than CMMs).
4. Perform parity generation and checking on address and
memory bus data words, and on core memory module
words.
5. Generate and store status words.
6. Control and time all transfers of address words, data
words, status words, write locks, and write key among
the ports, CMM, and the storage registers.
7. Control and time a!! data, parity, and. control signals
issued to the memory bus.
8. Accept one of two or more simultaneous memory re-
quests on the basis of port positional priority and other
priority status information such as "high priority" and
"memory reserved".