Xerox Sigma 6 User manual

• Xerox SIGMA 6 Computer
Reference Manual
.~I ...

XEROX SIGMA 6 INSTRUCTIONS
Mnemonic Code In$truction
Nome
Page Mnemonic Code Instruction
Nome
~
LOAD
STORE
FLOATING-POINT ARITHMETIC (!!I!!ionol)
LI
22
Load Immediate 32
FAS 3D Floating Add Short
51
LB
72
Load Byte
32
FAL
10
Floating Add Long
51
LH
52 Load Hallward 32
FSS
3C
Floating Subtract Short
51
L':I 32
Load Ward
32
FSL
IC Floating Subtract
Long
52
LD
12
Load Doubleword 32
FMS
3F
Floating Multiply Short 52
LCH
5,0.
Load Complement Hallward
33
FML
IF
Floating Multiply Long
52
LAH
5B
Load Absolute Hallward 33
FDS
3E
Floating Divide Shart 52
LCW
3,0.
Load Complement Word
33 FDl
IE
Floating Divide Long
52
LAW
3B
Load Absolute Word
33
LCD
1,0.
Load Complement Doubleward 33
DECIMAL
LAD
IB
Load Absolute Doubleword 34
LS
4,0.
Load Selective
34
DL
7E
Decimal Load
56
LM
2,0. Load Multiple
35
DST
7F
Decimal Store
56
LCFI
02
Load Conditions and Floating Control Immediate
35
DA
79 Decimal Add 57
LCF
70
Load Condition. and Floating Control
35
OS
78 Decimal Subtract 57
XW
46 Exchange
Word
36
OM
7B
Decimal Multiply 57
STB
75
Store Byt.
36
DO
7A
Decima I Oi vide 58
STH
55 Store Hallward
36
DC
70
Decimal Compar. 58
STW
35
Store Word
36
DSA
7C
Decimal Shift Aritlvnetic 58
STD
15
Store Doubleword
36
PACk 76
Pock Decimal Digits 59
STS
47
Store Selective
36
UNPk
77 Unpack Decimal Digits 59
STM
2B
Store Multiple 37
STCF
74
Store Condition. and Floating ConlJol
37
BYTE STRING
ANALYZE / INTERPRET
MIS
61
Move Byte String 61
ANLZ
.. Analyze
37
CBS 60
Compare Byte String 62
INT
6B
Interpret
31
TBS
.1
Translate Byte String 63
HBS 40 Tran.late and Test Byte String 63
FIXED-POINT ARITHMETIC
EBS
63 Edit Byte String
64
AI
20
Add Immediate 39
PUSH DOWN
AH
50
Add Hallward
39
AW 30 Add
Word
40
PSW
09
Push Word
69
AD
10
Add Doub leward 40
PLW 08 Pull
Word
69
SH
58 Subtract Hallward 40
PSM
OB
Push Mu hiple
70
SW
38 Subtract
Word
40
PLM OA
Pull Multiple 70
SO
18
Subtract Doubleward
41
MSP
13
Modify Stock Pointer
71
MI
23
Multiply Immediate
41
MH
57 Multiply Hallward
41
MW
37
Multiply Word
42
EXECUTE/BRANC H
DH
56 Divide Hallward 42
OW
36
Divide Word
42
EXU
67
Execut.
73
AWM 66
Add Word 10 Memory
43 BeS
69
Branch on Condition. Set
73
MTB
73
Modify and Test Byte
43
BeR 68 Branch on Conditions Reset
73
MTH
53 Modily and Te.t Hallward 43
BIR 65
Branch on Incrementing Regist.r
73
MTW
33
Mod ily and T e.t Word
44
BDR
64
Branch on Decrementing Regist.r
7.
BAL
6A Branch and
Link
74
COMPARISON
CI
21
Compore Immediat. 44
CALL
CB
71
Compore Byte
44
CALI 04
Calli
CH
51
Compare Halfword 45 n
CW
31
Compare Word
45
CAL2
05 Call 2 n
CD
II
Compare Doubleward 45
CAL3 06 Call 3 n
CS
45
Compare Selective 45 CAL. 07
Call.
n
CLR
39 Compare with Limits in Register 46
CLM
19
Con:'pore with Limits in Memory
46 CONTROL (prIvileged)
LOGICAL
LPSD OE
Load Program Slotu. Doubleward
73
XPSD OF
Exchange Program Status Doubleword
73
OR
49
OR Word
46
LRP 2F
Load Regilter Pointer 75
EOR
48
Exclu.ive OR Ward
46 MIN:. 6F Move
10 Memory Control 75
AND
4B
AND Word
46
WAIT 2E
Wait
77
RD 6C
Rood Direct 'II
SHIFT
WD
60 Write Direct
'II
S
25
Shilt
.7 INPUT/OUTPUT (prIvileged)
SF
24
Shift Floating
...
SIO 4C
Start Input/Output 83
CONVERSION HIO
4F
Halt Input/ Output
86
TlO
.0 Test Input/Output 86
CVA
29
Convert by Addition
49 TDV 4E Telt Device 87
CVS 28
Convert by Subtroc.tion 50 AIO
6E
Acknowledge Input/Output Interrupt
87

Xerox SIGMA 6 Computer
Reference Manual
90 17 138
June 1971
© 1970. 1971. Xerox Corporation
XEROX
File No.: 1X13
XL47, Rev. 0
Printed in U.S.A.

ii
REVISION
This publication is a revision of the Xerox SIGMA 6 Computer Reference Manual, 90 17 13A, and describes the
new SIGMA 6 Computer System features. Changes to the previous manual
are indicated by a vertical line in the
margin of the
affected page.
RELATm PUBLICATIONS
Xerox Sigma Glossary of Computer Terminology
Xerox Meta-Symbol/LN,OPS Reference Manual
Xerox
Symbol/lN,OPS Reference Manual
Xerox Macro-Symbol/LN,OPS Reference Manual
Publication No.
90 09 57
900952
90 1790
90 1578
Manual Type Codes: SP -batch processing, LN -language, OPS -operations, RBP -remote batch processing,
RT - real-time, SM -system management, 15 -time-sharing, UT -utilities.
All SPECIFICATIONS SUBJECT TO CHANGE WITHOUT NOTICE

CONTENTS
1. SIGMA 6 SYSTEM
Introduction 1
General Characteristics 1
Standard and Optional Features 4
Real-Time Features 4
General-Purpose Features 5
Time-Sharing Features 6
Multiuse Features 6
2. SIGMA 6 SYSTEM ORGANIZATION 8
Information Format 8
Core Memory 8
Dedicated Memory Locations 8
Information Boundaries 8
Computer Modes 9
Master Mode 9
Slave Mode 9
CPU Fast Memory 9
Central Processing Unit 10
General Registers and Register Block Pointer_ 11
Memory Control Storage 11
Memory Map and Acc.ess Protection 11
Instruction Format 11
Immediate Operand 12
Memory Reference Addresses 12
Memory Address Control 14
Memory Map and Access Protection 14
Memory Write Locks 15
Program Status Doubleword 17
Interrupt System 18
Internal Interrupts 18
External Interrupts 20
States of an Interrupt Level 20
Control of the Interrupt System 21
Time of Interrupt Occurrences 21
Singl e-Instruction Interrupts 22
Trap System 22
Nonallowed Operation Trap 22 4.
Unimplemented Instruction Trap '24
Push-Down Stack Limit Trap 25
Fixed-Point Overflow Trap 25
Floating-Point Arithmetic Fault Trap 26
Decimal Arithmetic Fault Trap 26
Watchdog Timer Runout Trap 26
Call Instruction Traps 27
3. INSTRUCTION REPERTOIRE
28
5.
Load/Store Instructions __________ 31
Anal yze/Interpret Instructions 37
Fixed-Point Arithmetic Instructions 39
Comparison Instructions 44
Logical Instructions 46
Sh ift Instructions 47
Floating-Point Shift 48
Conversion Instructions
49
Floating-Point Arith'metic Instructions 50
Floating-Point Numbers 50
Unimplemented Floating-Point Instructions __ 52
Floating-Point Add and Subtract 52
Floating-Point Multiply and Divide 52
Condition Codes for floating-Potnt
Instructions ____________ 53
Decimal Instructions
54
Packed Decimal Numbers 55
Zoned Decimal Numbers 55
Decimal Accumulator 55
Decimal Instruction Format 55
Illegal Digit and Sign Detection 55
Overflow Detection 55
Decimal Instruction Nomenclature 56
Condition Code Settings 56
Byte-String Instructions 60
Push-Down Instructions 67
Stack Pointer Doubleword 68
Push-Down Condition Code Settings 68
Execute/Branch Instructions 72
Ca II Instructions 74
Control Instructions 75
Program Status Doubleword 75
Loadi ng the Memory Map 78
Loadi ng the Access Protection Controls 78
Loadi ng the Memory Wri te Protection Locks __ 79
Interruption of MMC 79
Read Direct Internal Computer Control
(Mode 0) ___________ 80
Write Direct Internal Computer Control
(Mode 0) 81
Write Direct, Interrupt Control (Mode 1) ___ 81
Input/Output Instructions 82
I/O Address 82
I/O Unit Address Assignment 82
I/O Status Response 82
Status Information for SIO 83
INPUT/OUTPUT OPERATIO NS
89
lOP Command Doublewords 90
Order
90
Memory Byte Address
91
Flags
91
Byte Count 92
OPERATOR CONTROLS 93
Processor Control Panel 93
POWER
93
CPU RESET/CLEAR
93
I/O RESET
94
LOAD 94
UNIT
ADDRESS
94
SYSTEM RESET/CLEAR
94
NORMAL MODE 94
RUN
94
WAIT
94
iii

INTERRUPT
94
B.
REFERENCE DIAGRAMS 119
PROGRAM STATUS DOUBLEWORD 94
INSERT
94 Notes on Basic SIGMA 6 Instruction Execution
INSTR
ADDR
95
Cycle 1.
ADDR STOP 95 Basic SIGMA 6 Instruction
Execution Cycle __ 1
SE LECT ADDRESS
96 Floati
ng-Point Instruction Execution 122
STORE 96
Floating-Point Multiplication and Division __ 122
DISPLAY 96
Floating-Point Addition and Subtraction ___ 123
DATA
96 Floating-Point Shift 124
COMPUTE 96 Edit Byte String Instruction
Execution
125
CON TROL MODE
97
MEMORY FAULT
97
C.
SIGMA 6 INSTRUCTIONS (MNEMONICS)
126
ALARM
97
AUDIO
97
D.
INSTRUCTION TIMING
128
WATCHDOG TIMER
97
INTERLEAVE SELECT
97
PARITY ERROR MODE
97
PHASES
98
FIGURES
RE GISTER SELECT
98
SIGMA 6 Computer System
SENSE
98
v
CLOCK MODE
98
1.
A Typical SIGMA 6 System 2
Loading
Operation
98
Load Procedure
98
2. Information Boundaries 9
Load
Operation Details
99
INDEX 135
3.
SIGMA 6 Central Processing Unit
10
4.
Index Displacement Alignment 14
APPENDIXES
5.
Generati on of Actua I Memory Addresses
16
A.
REFERENCE TABLES
100
6.
Typical Interrupt Priority Chain
~
XDS Standard Symbols and Codes 100 7.
Operational States of an In~errupt Level
XDS Standard Character Sets 100
Control Codes 100 Processor Control Panel 93
8.
Special Code Properties 100
XDS Standard 8-Bit Computer Codes
(EBCDIC)
101
XDS Standard 7-Bit Communication Codes
TABLES
(ANSCII)
101
XDS Standard Symbol-Code Correspondences __ 102
1.
SIGMA 6 Dedicated Memory Locations 'l
Hexadecimal Arithmetic 106
2.
SIGMA 6 Interrupt Locations 19
Addition Table
106
3.
Summary of SIGMA 6 Trap System 23
Multiplication Table 106
4.
Glossary of Symbolic Terms 30
Table of Powers of Sixteenl0
107
5.
ANALYZE Table for SIGMA 6 Operation Codes_
38
Table of Powers of Ten16
107
6.
Floating-Point Number Representation
51
Hexadecimal-Decimal Integer Conversion 7.
Condition Code Settings for Floating-Point
Table 108 Instructions 53
Hexadecimal-Decimal Fraction Conversion
8.
Status Bits for I/O Instructions
84
Table 114 9.
Program Status Doubleword Display 95
Table of Powers of Two 118
D-1. Basic Instruction Timing 129
Mathematical Constants 118
D-2.
Additional Instruction Timing 133
iv

· 6 Computer
Sigma

1. SIGMA 6 SYSTEM
INTRODUCTION
The SIGMA 6 computer system can concurrently process
operations for business,
engineering/scientific, and general-
purpose applications. The basic system consists of a central
processor, 32, 768 words of memory, and independent, multi-
plexed I/O capability. It is easily expandable by adding
memory units,
input/output processors, and peripheral de-
vices. Figure 1 shows a typical SIGMA 6 system.
A SIGMA 6 system consists of the following majorelements:
• A memory consisting of up to four magnetic
core storage
units.
• A central processor unit {CPU} that addresses core mem-
ory, fetches and stores information, performs arithmetic
and logical operations, sequences and controls instruc-
tion
execution, and controls the exchange of information
between core memory and
other elements of the system.
• An i nput/ outputsystem cor.trolled by one or more i nput/
output processors {lOPs}, each providing data transfer
between core memory and peripheral
devices. The lOPs
have separate access to core memory which are inde-
pendent of the CPU. They operate asynchronously
and simultaneously with the CPU.
GENERAL CHARACTERISTICS
A SIGMA 6 computer system has features and operating
characteristics that permit efficient functioni ng in real-
time, general-purpose, time-sharing, and multiuse computing
environments:
• Word-oriented memory {32-bit word plus parity bit}
which
can be addressed and altered as byte (8-bit),
halfword {2-byte}, word {4-byte}, and doubleword
(8-byte) quantities.
• Full parity checking for both CPU/memory and input/
output operations.
•
•
•
•
Memory expandable from 32,768 to 131,072 words
{131 ,072to524,288bytes} in incrementsof 16,384 words.
Direct addressing of
the entire core memory, within the
primary instruction word and without the need for base
registers, indirect addressing, or indexing.
Indirect addressing, with or without postindexing.
Displacement index registers, automatically self-
adjusting for all data sizes.
Immediate addressing' of operands, for
greater storage
efficiency and increased speed.
• Sixteen general-purpose registers, expandable (in
blocks of 16) to 512 to
reduce transfer of data into and
out of registers in a multiuse environment.
• Hardware memory mapping, which obviates the problem
of memory fragmentation and provides dynamic program
relocation.
•
Selective memory access protection with four modes for
system and information security and
protection.
• Selective memory-write protection.
• Watchdog timer, assuring nonstop operation.
• Real-time priority interrupt system with automatic iden-
tification and priority assignment, fast response time,
and up to 235 levels
that can be individually armed,
enabled, and triggered by program control.
• Interruptibi Iity of long instructions,
guarantee i ng fast
response
to interrupts.
• Automatic traps, for error conditions and for simulation
of optional instructions not physically implemented, all
under program control.
• Power fai
I-safe, for automatic, safe shutdown in the
event of a power failure.
• Multiple interval timers, with a
choice of resolutions
for independent time bases.
• Privileged instruction logic {master/slave modes}, for
concurrent, time-shared operation.
• Complete instruction set including:
• Byte, halfword, word, and doubleword operations.
• Use of all memory-referencing instructions for
register-to-register operations, with or without
indirect addressing and postindexing, and within
the normal instruction format.
• Multiple register operations.
•
•
•
•
Fixed-point arithmetic operations in halfword,
word, and doubleword modes.
Optional floating-point hardware operations, in
short and long formats, with
significance, zero,
and normalization control and checking, all under
program control.
Full complement of logical operations {AND, OR,
exclusive OR}.
Comparison operations, including compare between
limits {with limits in memory or in registers}.
SIGMA 6 System

CENTRAL PROCESSOR UNIT
(CPU)
Standard Features:
• Decimal arithmetic unit
• Memory mop
• Access protection
• Memory write protection
• Two register blocks
• Power fail-safe
•
Two reol-time clacks
• External interface (direct
VOl
Optional Features:
• Two additional real-time clacks
• 30 additional register blocks
• Floating-pointarithmetic
• External priarity interrupt system
(up to
224 levels)
MEMl :: ----- - -- r=- --=- ~:-eM-:1- uNiT - - -1
Standard Features: I Standard Features: I
32,768 words
Two ports (multiocess)
Two-way interleaving
Four-way interleaving
Parity checking
Optional Features:
• Four additional ports
• Memory system expandable by
adding up to three additional
32K memory units
I 16,384 or I
I 32,768 words I
I •
Two ports (multiaccess) I
• Two-way interleaving
I • Four-woy interleaving I
I • Parity checking I
I Optional Features: I
I • Four odditional ports :
L--.---T'""""'-----'
: I
: I
'-- ___ .== . .::.:=.~.=.=.=.=== .. ==.= . .:.r ..............•.....................•...•...•....••........•.•....••.•.•. !
...- _____ -..1. ____ :..'_--. -------------------.
MUlTIPLEXING INPUT/OUTPUT r- MIOP EXPANsION OPTION- -, r
l -
-smcroRi~puT/OUTPUT-1
PROCESSOR (MIOP) (ONE PER MIOP) I PROCESSOR (SlOP) I
Standard Features: Standard Features: I Stondard Features: I
• One group of eight subchonnels One group of eight subchannels I Single-byte interface I
• Single-byte interface • Single-byte interface I Four-byte interface I
• Four-byte interface I I
Optianal Features:
Two additional groups of eight
subchannels
Accommodates:
One device controller
per subchonnel
I
r;:--1--, r.:-.J.._:j
I
SDIENVGICLEE UNIT I IMULTI~UNIT I
I
··· DEVICE I
~~~O'!:!:E.!J IE£!'I~~L!RJ
I I
_..l-:::-1 I r-----,
[1/
0
~V~ J r -t 1/0 DEVICE I
I '- ____ ..J
I
L fiiO DEViCE 1
., (Up to I
~~e~~J
Optional Features: I Accommodates: I
I • 32 device control/en I
Two additional groups aF eight
subchonnels
Accommodates:
• One device contraller
per subchannel
L __
,
_____ , __
I I
r.-
J
--:1 r.--1-~
I SINGLE UNIT I I MULTI-UNIT I
I DEVICE I. • '1 DEVICE I
I CONTROLLERJ I CONTROLLER I
I..-
T
-- L..;.-T- .....
I I
Ii/O~VlC~ . ~ rVODEvlcE]
L.. ____ " I L~ __
I .
L .- Vo DeVICE!
-I (Up 10 :
Ll~de~ces) J
L--r-------J
I
I
I
I
~------,
I I
r-J.--, r-J--,
I DEVICE I I DEVICE I
ICONTROlLERI' •
'ICONTROLLERI
L_,---i L_,_-J
I I
r--L-,~_J-:1
~O ~~~ lYO ~~~
--------------Standard-$PMd peripheral devices ------------ ..... pl 1- High-speed peripheral devices -I
Note: Standard units and pracessan are shown enclosed with solid barder lines. Optional units, processors, device contrallen,
-- and devices are enclosed with clashed barder lines. Standard and optional features within a unit or processor are as listed.
Figure 1. A Typical SIGMA 6 System
2 General Characteristics

• Call instructions permitting up to 64 dynamically
variable, user-defined instructions, and permitting
a program to gain access to operating system func-
tions without operating system intervention.
• Decimal hardware operations, including arith-
metic, edit, and pack/unpack.
• Push-down stack operations (hardware imple-
mented) of single or multiple words, with auto-
matic limitchecking, for dynamic space allocation,
subroutine communication, and recursive routine
capabi Iity.
• Automatic conversion operations, including binary/
BCD and any other weighted-number systems.
• An analyze instruction, for facilitating effective
address computation.
• An interpret instruction, for increased speed of
interpretive programs.
• Shift operations (left and right) or word or double-
word, including logical, circular, arithmetic, and
floating-point modes.
• Independently operating input/output system with the
following features:
• Direct input/output of a full word, without the
use of a channel.
• Up to eight input/output processors (lOPs).
• Multiplexor input/output processors (MIOPs) for
simultaneous operation of up to 24 devices per
lOP.
• MIOP expansion option for simultaneous operation
of up to 24additional devices, and includes conflict-
resolving circuitry that allows it to share a memory
bus with an MIOP.
• Selector input/output processors (SlOPs) (8 or 32
bits wide}for data transfer rates approaching 4 mi I-
Iion bytes per second.
• Up to 32 device controllers can be connected to
each SlOP.
• Both data and command chaining, for gather-read
and scatter-write operations.
• Up to 32,000 output control signals and input test
signals.
• External interface feature that:
• Provides an exter-nal interface for the attachment of
external equipment to a SIGMA 6 computer via the
Direct I/O system (Write Direct/Read Direct).
• Allows the transfer of a 32-bit data word between
an affected register and an external devi ce. In add i-
tion, a 16-bit address is transferred for selection and
control purposes. Each transfer is under direct
program control.
• Is used for the attachment of external units to the
direct I/O interface. External units may be Xerox
external interrupts, Xerox system interface units,
or nonstandard special equipment.
• Comprehensive complement of modular software:
• Expands in capabi Iity and speed as system grows.
• Basic system programming support: "Stand-Alone"
Systems and Basic Control Monitor (BCM).
•
Operating systems: Real-time Batch Monitor
(RBM), Batch Processing Monitor (BPM), Batch
Time-Sharing Monitor
(BTM), Universal Time-
Sharing System (UTS), and Xerox Operating Sys-
tem (XOS). When larger computing capacity is
required, UTS and XOS users can expand to the
Xerox SIGMA 9 Computer.
• Language processors that include: FORTRAN IV -H,
Extended Xerox FORTRAN IV, Xerox ANS COBOL,
BASIC, FLAG, Symbol, Macro-Symbol, Meta-
Symbol; also, utilities and applications software
for both commercial and scientific users, e. g. ,
Data Management System (DMS), General ized
Sort and Merge, Manage, 1401 Simulator, Func-
tional Mathematical Programming System (FMPS),
FMPS Matrix Generator/Report Writer (GAMMA3),
Simulation Language (SL-l), General Purpose Dis-
crete Simulation package (GPDS), Circuit
Analysis Systems (CIRC-AC, CIRC-DC), etc.
• Standard and special-purpose peripheral equipment
includes:
• Rapid Access Data (RAD) fi les: Capacities to
6.2 million bytes per unit; transfer rates to 3 -mil-
lion bytes per second; average access times from
17 mi lIiseconds.
• Magnetic tape units: 7-track and 9-track sys-
tems, IBM-compatible; high-speed units operate
at 150 inches per second wi th transfer rates up
to 120,000 bytes per second; and other units
operate at 37.5 inches per second with transfer
rates up to 20,800 bytes per second and at 75 inches
per second with transfer rates up to 60,000 bytes
per second.
• Displays: Graphic display has standard character
generator, vector generator, and close-ups, as
well as Iight pen and
alphanumeric/function key-
board with a display rate of up to 100,000 charac-
ters per second.
General Characteristics 3

• Card equipment: Reading speeds of up to 1500 cards
perminute; punching speeds of up to 300cards per
minute; intermixedbinary and EBCDIC card codes.
• Line printers: Fully buffered, with speeds of up
to 1500 lines per minute; 132 print positions with
64 characters.
• Keyboard/printers: Ten characters per second;
also available with integral paper tape reader
(20 characters per second) and punch (10 charac-
ters per second).
• Paper tape equipment: Readers with speeds of up
to 300 characters per second; punches with speeds
of up to 120 characters per second.
• Graph plotters: Digital incremental, providing
drift-free plotting in two axes in up to 300 steps
per second at speeds from 30 mm to 3 inches per
second.
• Data communications equipment: A complete line
of character- and message-oriented equipment to
connect remote user terminals to the computer sys-
tem via common carrier lines and local terminals
directly.
STANDARD AND OPTIONAL FEATURES
A basic SIGMA 6 system has the following standard
features:
• A CPU that includes:
• Decimal
arithmetic unit
• Memory map with
access protection
• Memory write protection
• Watchdog timer
• Two register blocks
•
Two real-time clocks
• Power fa
ii-safe
• Memory
parity interrupt
•
Input/output interrupt
• Control
pane I interrupt
• External
interface (Direct I/O)
• 32,768 words of main memory with two ports
• Multiplexor Input/Output Processor with eight sub-
channels and 4-byte interface feature.
4 Standard and OptionaI/Rea 1- Ti me Features
A SIGMA 6 system may have the following optional features: I
• Two additional real-time clocks
• Up to 30 additional register blocks
• Floating-point arithmetic unit
• Up to 224 external priority interrupts
• Up to four additional memory ports
• Up to three additional Multiplexor I/O Processors
(MIOPs)
• Up to two additional groups of eight multiplexor sub-
channels with each MIOP
• MIOP expansion option for each MIOP with 4-byte
interface and one group of eight subchannels
• Selector Input/Output Processor (SlOP) with 4-byte
interface
REAL-TIME FEATURES
Real-time appl ications are characterized by a need for hard-
ware that provides quick response to an external environment,
enough speed to keep up with the real-time process and suf-
ficient input/output flexibility to handle a variety of data
types at varying speeds. The SIGMA 6 system includes pro-
visions for the following real-time computing features.
Multi level, True Priority Interrupt System. The real-time
oriented SIGMA 6 system provides for quick response to in-
terrupts bymeans of up to 224 external interrupt levels. The
source of each interrupt is automatically identified and re-
sponded to according to its priority. For further flexibility
each level can be individually disarmed (to discontinue ac-
cepting inputs to it) and disabled (to defer responding to it).
Use of the disarm/disable feature makes programmed dynam;c
reassignment of priorities quick and easy, even while a real-
time process is in progress. In establishing a configuration for
the system, each group of 16 interrupt levels can have its
priority assigned in different ways in order to meet the spe-
cific needs of the problem; the way in which interrupt levels
are programmed is not affected by the priority assignment.
Programs that deal with interrupts from specially designed
equipment sometimes must be checked out before that
equipment is actually available. To permit simulating this
special equipment, any SIGMA 6 interrupt level can be
triggered by the CPU itself through exec uti on of a si ngle
instruction. This capability is also useful in establishing a
hierarchy of responses. For example, in responding to a
high-priority interrupt, after the urgent processing is com-
pleted, it may be desirable to assign a lower priority to the
remaining porti on in order to respond to other criti ca I i nter-
rupt levels. The interrupt routine can accomplish this by I
triggering a lower-priority level, which processes the re-
maining data only after other interrupts have been handled.

Nonstop Operation. When connected to special devices
(on a ready-resume basis), the computer can sometimes
become
excessively delayed if the special device does not
respond quickly. A built-in watchdog timer assures that
the SIGMA 6 computer cannot be delayed for an exces-
sive length of time.
Real-Time Clocks. Many
real-time functions must be timed
to occur at specific instants. Other timing information is
also needed - elapsed time since a given event, for example,
or the current time of day. SIGMA 6 can contain two (or
four)
real-time clocks with varying degrees of resolution
(1/60 second or V8 mi lIisecond, for example) to meet these
needs. These clocks also allow easy handling of separate
time bases and relative time priorities.
Rapid Context Switching. When responding to a new set of
interrupt-initiated circumstances, a computer system must
preserve
the current operating environment, for continuance
later, whi Ie setting up the new environment. This changing
of environments must be done quickly, with a minimum of
II overhead II costs in time. In SIGMA 6, each one of up to
32 blocks of general-purpose arithmetic registers can, if
desired, be assigned to a specific environment. All rele-
vant information about the current environment (instruction
address,
current generaI regi s"er block, memory-protection
key, etc.) is kept in a 64-bit program status doubleword
(PSD). A
single instruction stores the current PSD any-
where in memory and loads a new one from memory to es-
tablish a new environment, which includes information
identifying a new block of general-purpose registers. A
SIGMA 6 system
can thus preserve and change its operating
environment completely through the execution of a single
instruction.
Simultaneous
I/O Channel Operation. The use of a multi-
plexor input/output processor (MIOP) or MIOP expansion
option permits up
to 24 channels with standard-speed de-
vices to operate concurrently; the addition of more MIOPs
increases this throughput.
High-Speed Channel Operation. The use of the selector
input/output processor (SlOP) permits very high-speed data
transfer -up to one 32-bit word per memory cycle. To
meet special needs, data size can be 8 or 32 bits wide.
Memory
Protection. Both foreground (real-time) and back-
ground programs can be run concurrently ina SIGMA 6
system,
because a foreground program is protected against
destruction by on unchecked background program. Mem-
ory write-protection guarantees that protected areas of
memory can be written into only under predefined con-
ditions. Under operating system control, the memory
access-protection feature also prevents accessing of mem-
ory for
specified combinations of reading, writing, and
instruction
acquisition.
Variable Precision Arithmetic. Much data encountered in
real-time systems are 16 bits or less. To permit this length
of
data to be processed efficiently, SIGMA 6 provides half-
word arithmetic operations in addition to fullword oper-
ations. Doubleword arithmetic operations (for extended
precision) are also included.
Direct Data Input/Output. For handl ing asynchronous I/O,
a 32-bit word can be transferred directly to or from a
general-purpose register, so that an I/O channel need not
be
occupied with relatively infrequent transmissions.
Interleave/Overlap. To increase processing speeds, mem-
ory banks
overlap cycles automatically wherever possible.
Core memory addresses
can be interleaved modul0-2 or
modul0-4 on a bank basis to increase the probability of
overlapping.
GENERAL -PURPOSE FEATURES
General-purpose computing applications are characterized
primari Iy by an emphasis on computation and internal data
handling. Many operations are performed in floating-point
format and on strings of characters. Other typical charac-
teristics include decimal arithmetic operations, the need to
convert binary numbers into decimal (for printing or display),
and considerable input/output at standard speeds. The
SIGMA 6 system
includes the following general-purpose
computer features.
Floating-Point Hardware (optional). Floating-point in-
structions are avai lable in both short (32-bit) and long
(64-bit) formats. Under program control, the user can
select optional zero checking, normalization, and signifi-
cance checking (which causes the computer to trap when a
post opera.tion
shift of more than two hexadecimal places
occurs in the fraction of a floating-point number). The
significance checki ng feature permits the use of the short
floating-point format (for high processing speed and storage
economy)
and the use of the ·Iong format when loss of
significance is detected.
Decimal Arithmetic Hardware. Decimal arithmetic instruc-
tions operate on up to 31 digits plus sign. This instruction
set also includes pack/unpack instructions (for converting to/
from the packed format of two digits per byte) and a general-
ized edit instruction (for zero suppression, check protection,
and formatting byte information with punctuation to displc:y
or print it).
Indirect Addressing. This feature provides for simple table
linkages and permits the user to keep data sections of
his program
separate from procedure sections for ease of
maintenance.
Displacement Indexing. The technique of indexing by
means of a IIfloating
li
displacement permits the user to
access the desired unit of data without the need to con-
sider its size. The index registers automatically align
themselves appropriately; thus, the same index register
can be used on arrays with different data sizes. For ex-
omple, in a matrix multiplication of any array of fullword,
single-precision, fixed-point numbers, the results can be
stored in a second
array as double-precision numbers, using
the same index quantity for both arrays. If an index regis-
ter contains the value of k, then the user always accesses
the kth
element, whether it is a byte, halfword, word, or
doublaword. Incrementing by various quantities according
to data size is not required; instead, incrementing is always
General-Purpose Features 5

by units in a continuous array table no matter which size
of data element is used.
Powerful Instruction Set. The availability of more than
100 major instructions results in programs that are short,
rapidly assembled, and quickly executed.
Translate Instruction. This instruction permits rapid trans-
lation between any two 8-bit codes (such as EBCDIC to
ANSCII); thus data from a variety of input sources can be
easi Iy handled and reconverted for output.
Conversion Instructions. Two generalized conversion in-
structions provide for bidirectional conversions between
internal binary and any other weighted number system,
including BCD.
Call Instructions. Four instructions permit handling up to
64 user-defined subroutines (as if they were built-in
machine instructions) and gaining access to specified oper-
ating system services without requiring its intervention.
Interpret Instruction. This instruction simplifies and speeds
interpretive operations such as compi Iing, thus reducing the
space and time requirements for compilers.
Four-Bit Condition Code. This feature simplifies the
checking of results by automatically providing information
on almost every instruction execution (including indicators
for overflow, underflow, zero, minus, and plus, as appro-
priate) without requiring an extra instruction execution.
TIME -SHARING FEATURES
Time-sharing is the abi lity of a computer system to share
its resources among many users at the same time. Each
user may perform a different task that requires a different
share of the avai lable resources and, in many instances,
each may be on-line in an interactive ("conversational")
mode with the computer. Other users may enter work to be
batch processed. The SIGMA 6 system provides for the fol-
lowing time-sharing computer features.
Rapid Context Saving. When changing from one user to
another, the operating environment can be switched quickly
and easi Iy. Stack-manipulating instructions permit from
one to 16 general-purpose registers to be stored in a push-
down stack by a single instruction -with automatic updating
of stack status information -and to be retrieved (again, by
a single instruction) when needed. The current program
status doubleword (which contains the entire description of
the current user's environment and mode of operation) can
be stored anywhere in memory and a new program status
doubleword loaded, all with a single instruction.
Multiple Register Blocks. The optional avai lability of up
to 32 blocks of 16 general-purpose registersfurther improves
response time by reducing
the need to store and load regis-
ter blocks. As needed, ea~h user can be assigned a distinct
block; the program status doubleword automatically points
to the currently appl icable register block.
6 Time-Sharing/Multiuse Features
User Protection. The slave mode of operation restricts each
user to his own set of instructions while reserving to the
operating system those instructions that could, if used in- ~
correctly, destroy another user's prog:am. A memory acce~
protection system prevents any user from accessing storage
areas other than those assigned to him. This access protec-
tion permits the user to access certain areas for reading only,
such as those containing public subroutines, whi Ie preventing
him from reading, writing, or accessing instructions in areas
set aside for other users.
Storage Management. SIGMA 6 memories
are available in I'
seven sizes (from 32,768 to 131,072 words) to provide the ca-
pacity needed, while assuring potential for expansion. To
assure efficient use of available memory, the memory map
hardware permits storing a user's program in fragments (as
small as 512 words) wherever space is available; yet, all
fragments appear as a single, contiguous block of storage at
execution time. The memory map also automatically and
dynamically handles program relocation, so that the pro-
gram appears to be stored in a standard way at execution
time (even though it may actually be stored in a different
set of locations each time it is brought into memory). The
memory map for the full-sized SIGMA 6 memory is provided
no matter how sma II the actua I memory may be. Th us, the
system can always address a virtual memory of 131,072 words
regardless of physical memory size.
Input/Output Capability. Sigma 6 can control up to eight I
input/output processors (of two types) in various combi-
nations. Each multiplexor I/O processor or MIOP expansiort-"
option can have up to 24 standard-speed I/O channels op-
erating simu Itaneously; selector I/O processors can have any
one of up to 32 high-speed I/O devices operating on each
processor. The I/O processors operate semi-independently
of the central processor, leaving it free to provide faster
response to overall system needs.
Nonstop Operation. A watchdog timer assures that the
system continues to operate even if certain special I/O
capabilities are used with special devices that can cause
delays or halts if they fail. Multiple real-time clocks with
varying resolutions permit establishing several independent
time bases, thus allowing flexible allocation of time slices
to each user.
MULTIUSE FEATURES
As implemented in the SIGMA 6 system, II multiuse II com-
bines two or more computer applicati on areas. The most
difficult computing problems are associated with real-time
applications. Simi larly, the most difficult multiuse prob-
lems are associated with time-sharing applications that
include one or more real-time processes. SIGMA 6 sys-
tem design is especially suited for a mixture of applica-
tions in a multiuse environment. Many of the hardware
features
that are required for specific application areas
are equally useful in others, although in different ways.

This multiple capabi lity makes SIGMA 6 particularly effec-
tiv.", for multiuse applications. The major SIGMA 6 multiuse
computer
features are:
Priority Interrupt. In a multiuse environment, many ele-
ments operate asynchronously. Thus, a true pri ority i n-
terrupt system is essential. It allows the computer system
to respond quickly {and in proper order} to the many de-
mands made on it, without the high overhead cost of
compl icated programming, lengthy execution time, and
extensive storage allocations.
Quick Response. The many features that combine to pro-
duce a quick-response system -multiple register blocks,
quick context saving, push-pull operations - benefit all
users because more of the computer's resources are avail-
able for useful work.
Memory Protection.
The memory protection features protect
each user from every other user and also guarantee the
integrity of programs that are essential to critical real-time
applications.
Input/Output. Because of its wide range of capacities
and speeds (with and without channels), the SIGMA 6
I/O system simultaneously satisfies the needs of many
different application areas economically, both in terms of
equipment and of programming.
Instruction
Set. The large SIGMA 6 instruction set pro-
vides the computational and data-handling capabilities
required for widely differing application areas; therefore,
each user's program length (thus running time) is decreased
and the speed of obtaining results is increased.
Multiuse Features 7

2. SIGMA 6 SYSTEM ORGANIZATION
The primary el ements in a basic SIGMA 6 system - a centrai
processor, core memory, and input/output processor - are
all designed around a central, double bus structure.
Each primary element of the system operates asynchronously
and semi
-independently, automatically overlapping the op-
eration of the other elements (when circumstances permit)
for
greater speed. The basic configuration can be expanded
merely by increasing the number of core memory units
(up
to four), increasing the number of buses (up to six),
increasing the number of input/output processors (up to
eight), or by increasing the number of central processors.
INFORMATION FORMAT
The basic element of SIGMA 6 information is a 32-bit word,
in which
the bit positions are numbered from 0 through 31,
as follows:
A SIGMA 6 word can be divided into two 16-bit parts
(called halfwords) in which the bit positions are numbered
from 0 through 15, as follows:
A SIGMA 6 word can also be divided into four 8-bit parts
(called bytes) in which the bit positions are numbered from
othrough 7, as follows:
Byte 0 Byte 1 Byte 2 Byte 3
Two SIGMA 6 words can be combined to form a 64-bit
element (called a doubleword) in which the bit positions
are numbered from 0 through 63, as follows:
I : least si9ni~cant ward: I
32 33 34 35136 37 38 39 40 41 42 43144 45 46 47 48 49 50 5d52 53 54 55 56 57 58 59160 61 62 63
Four bits of information can be expressed as a single hexa-
decimal digit. A byte can be expressed as a 2-digit hexa-
decimal number, a halfword as a 4-digit hexadecimal
number, a word as an 8-digit hexadecimal number, and a
doubleword as a
16-digit hexadecimal number. In this
reference manual, a hexadecimal number is displayed as
a string
of hexadecimal digits enclosed by single quotation
marks and preceded by the letter II X". For example, the
binary number 01011010 is expressed hexadecimally as
X' 5A',
8 51 GMA 6 System Organization
CORE MEMOR't'
SIGMA 6 core memory systems use a 32-bit word (four 8-bit
bytes) plus a parity bit as the basic unit of information, All
of memory is directly addressable by the CPU (except for
memory
locations 0 through 15)and by the lOPs. The SIGMA6
addressing capabi lity accommodates a maximum memory size
of 131, 072 words (524,288 bytes). Core memory is modular
and is available in increments of 16, 384 words (65,536 bytes),
The main memory for SIGMA 6 is physically organized as a
group
of "units", A memory unit is the smallest, logically
complete part of the system. It is the smallest port that
can be logically isolated from the rest of the memory sys-
tem. A memory unit may consist of up to two physical
memory banks. Each memory bank
operates independently
and asynchronously with respect to each other. 128K words
of main memory is comprised of four memory units. The
memory is word,
halfword, and byte addressable for both
reading and writing. Each memory unit has a set of "ports"
that are common to both banks within the unit; that is,
all ports in a
given memory unit give access to the bonks
within that unit. The basic system is provided with two
ports,
expandable to six.
The memory system has
2-way interleaving capabi lity within
a unit and 4-way interleaving between two adjacent units.
Interleaving increases the probabi lity that a processor can
gain access to a given memory bonk without encountering
interference from other processors: A multiple bonk system
increases the probability that successive memory accesses
may be overlapped. In combination, these two features
provide the SIGMA 6 system with effective memory cycle
times of a fraction of the individual bonk cycle times.
DEDICATED MEMORY LDCATIONS
Memory locations 0 through 319 are reserved by standard
XDS software for dedicated purposes as shown in Table 1.
INFORMATION BOUNDARIES
SIGMA 6 instructions assume that bytes, halfwords, and
doublewords are located in storage according to the
following boundary
conventions:
1. A byte is located in bit positions 0 through 7, 8
through 15, 16 through 23,
or 24 through 31 of a word.
2. A halfword is
located in bit positions 0 through 15 or
16 through
31 of a word.
3. A doubleword is located such that bits 0 through 31 of
the doubleword are contained within an even-numbered
word, and bits 32 through 63 of the same doubleword
must
be contained within the next consecutive (odd-
numbered) word.
The various information
boundaries are illustrated in Figure 2.

i Doubleword Doubleword I
I I
I •
.
I Word
(even address) Word (odd address) Word
(even address) Word (odd address) I
! I
i Halfword 0 Halfword 1 Halfword 0 Halfword 1 Halfword 0 Hal fword 1 Halfword 0 Halfword 1 i
I I
: Byte 01 Byte 1 Byte
21 Byte 3 Byte 0 1Byte 1 Byte
2/ Byte 3 Byte 0 / Byte 1 Byte
2\ Byte 3 Byte 01Byte 1 Byte
2[ Byte 3!
Figure 2. Information Boundaries
Table
1. SIGMA 6 Dedicated Memory Locations
Location
Decimal Hexadecimal Function
0 0 Addresses of
general registers
15
F
16
10 Reserved for future use
31
1F
32 20
Cpu/Iop communication
33
21
34
22 Program stored by LOAD
switch on the processor panel
41 29
42 2A First record read from
peri-
phera device during a load
63 3F operation
64 40
Traps (see Table 3)
79
4F
80
50
Override interrupt levels
t
87
57
88 58
Counter interrupt level/
91 5B
92 5C
Input/output interrupt level/
93 5D
94
5E
Reserved for future uset
95
5F
96
60
External interrupt level/
319
13F
tSee Table 2
COMPUTER MODES
The SIGMA 6 computer operates in either the master mode
or
the slave mode. The mode of operation is determined
by the state of the master/slave mode control bit in the
arithmetic and control unit.
MASTER MODE
The master mode is the basic operating mode of the
computer. In this mode, all SIGMA 6 instructions are
permissible. It is assumed that there is a resident execu-
tive program (operating in the master mode) that controls
and supports the other programs operating in the master
or slave mode.
SLAVE MODE
The slave mode is the problelT)-solving mode of the com-
puter. In this mode, "privileged" instructions are pro-
hibited. Privileged instructions are those relating to input/
output and to changes in the basic control state of the com-
puter. All privileged instructions are performed in the
master mode only. Any attempt by a program to execute a
privileged instruction while the computer is in the slave
mode results in a return of control to the resident execu-
tive program.
The
master/slave mode control bit can be changed only
when the computer is in the master mode; thus, a slave pro-
gram cannot directly change the computer mode from slave
to master. However, the slave program can gain direct
access to certain executive program operations by means
of
call instructions. The operations available through
call instructions are established by the resident execu-
tive program.
CPU FAST MEMORY
Several high-speed integrated circuit memories may be
used in the SIGMA 6 CPU. These memories are cap-
able of delivering information to (or receiving informa-
tion from) the arithmetic and control unit simultaneously
with the operation of core memory. These memories
are not accessible to any other unit in a SIGMA 6
system.
Computer
Modes/CPU Fast Memory 9

CENTRAL PROCESSING UNIT
This section describes the organization and operation of
the SIGMA 6 central processing unit in terms of informa-
tion processing and program control, instruction and data
CPU fAST MEMORY
GENERAL REGISTER BLOCK (nPiCALI
o I .... ________ ~
1~:n~:n~§I~&~m~@~@~@~Th~~@~%~~@~@~ru~w~M~a~
2 1:~~:::::fII:J:~:lJlI:l:jiI:Il~:~:~::II:1I::ililil:::lilmI1lljIIlllll\llllllItm!ililti::1
3 lil!!:i!!!i:[!I[ttlllIililili!il@ttilIi!illi:it}!ttitl:1!~@!IMI1!@!!i!i!Ii!i!{fi!1
4 1?:::Iffl:::l:::Ijljl!i!ill:iImt:1:::I1~iI::fliJi::~l:lIllIlllIIiIi}}tIIl
Index
~ Registers
5 1:}I:::i::t:::~l::ii~::iiiii:i~iililiiil!ill:l\l\llliIlili~il:~i~i~\1!1:1\~\1lI1l1l1ltjll:l:llj:ltttl:l:tlt::1
formats, indirect addressing and indexing, memory mapping
and protection, overflow and trap conditions, and inter-
rupt control. Basically, the SIGMA 6 CPU consists of
a fast memory
and an arithmetic and control unit (see
Figure 3).
ARITHMETIC AND CONTROL UNIT
INSTRUCTION REGISTER
oIndirect Address Flag
o
III I III I Operation Code Field
I 7
ITTIJ General Register Designator
8 11
ITIJ Index Register Designator
12 ,.
Reference Address Field
11111111111111111111 I
6 1:::t:!!I:t:I:I:Iiili!11!il!lljlIll\illllllllilttIi:lilIJliti!tI::1il!:::!Illl!tl!lH
7 f))))))):))))!)!!i~!:r!I:l)ijl)l)!)~!)ljl)~I!!!lj~~IIjjjljljj!j!j!j)))))jI)I!lj:)))I1)!1!Iijj)~1!~~))liI)j)lI!J
15 31 .• To/From
..... ~--...-jt~ Core Memory I
I.. •To/From
a
9
10
11
12
13
14
15
~
I
]
~------------------~ ~
~------------------~3' ~
MEMORY CONTROL STORAGE
Memory Map
I- 256 a-bit page addresses ---t
Memory Access Protection
III1I111I1111 ~ ~--+-I""-'-II"""'-II
I--- 256 2-bit access codes ~
Memory Write Protection
II1II1III1I11 ~~~II~III
l----256 2-bit write locks ---I
31-digit
Decimal
Accumu-
lator
-
I
I/O Processors I
• Read/Write
Direct I
__ Interrupts
Priority Interrupt System Write Direct
PROGRAM STATUS DOUBLEWORD
rrrn Condition Code
o 3
ITTI Flooting-point Mode Control
S 7
oMaster/Slave Mode Control
oMemory Map Control
9
OJ Arithmetic Trap Masks
10 \I
Instructian Address
111111111111111111
IS 31
OJ Write Key
343S
OTI Interrupt Inhibits
37 39
III III Register Block Pointer
ss 59
Figure 3. SIGMA 6 Central Processing Unit
10 Central Processing Unit
--

GENERAL REGISTERS AND REGISTER BLOCK POINTER
A register block is a high-speed memory consisting of six-
teen 32-bit words contained in the basic SIGMA 6 CPU for
general-purpose register usage. A SIGMA 6 contains two
such
register blocks (expandable to 32), and a 5-bit control
field (called the register block pointer) in the arithmetic
and control unit selects the block currently available to
a program. The 16 general registers selected by the
register block pointer are referred to as the current register
'block. The register block pointer can be changed only
when the computer is in the master mode; thus, a slave
program cannot change the register block pointer.
Each general register in a current register block is identified
by a 4-bit code in the range 0000 through 1111 (0 through 15
in decimal, or X'O' through X'F' in hexadecimcl notation).
Any general register can be used as a fixed-point accumu-
lator, floating-point accumulator, temporary storage, or can
contain control information such as a data address, count,
pointer, etc. Any (or all) of general registers 1 through 7
can be used as index registers. Registers 12 through 15 are
used as a decimal accumulator that is capable of containing
31 decimal digits plus sign. The use of registers 12 through 15
is automatic when a decimal instruction is executed; how-
ever, these registers may be used for other purposes by in-
structions not in the decimal instruction set.
MEMORY CONTROL STORAGE
Three high-speed integrated-circuit memories are avai 1-
able for storage of a memory map, a set of memory access-
protection codes, and a set of memory write-protection
codes, all of which can be changed only when the computer
is in the master mode.
MEMORY MAP AND ACCESS PROTECTION
The memory map feature includes high-speed memories for
both
the memory map and the access-protection codes. Use
of the map is determined by the state of the memory map
control
bit in the arithmetic and control unit.
Memory Map. Two terms are essential to a proper under-
standing of the memory mapping concept: virtual address
(Jnd actua I address.
A
virtual address is a value used by a machine-level pro-
gram to designate the location of an instruction, the loca-
tion of an element of data, the location of a data address
(indirect address), or to designate an explicit quantity,
such as a count. Normally, virtual addresses are derived
from programmer-supplied labels through an assembly (or
compi
lation) process followed by a loading process. Virtual
addresses
maya Iso be computed during a program's execu-
tion. Thus, virtual addresses include all instruction ad-
dresses, data addresses, indirect addresses, and addresses
used as counts within a
s~ored program, as well as those
addresses computed by
the program.
An actual address is a value used by the CPU t:. access mem-
ory for storage or retrieval of information, as required b>, tl1e
execution sequence of an instruction. Thus, actual addresses
designate wired-in hardware storage locations.
When the memory map is not in effect in a SIGMA 6 com-
puter, as determined by the memory map control bit, all
virtual address values above 15 are used by the CPU as ac-
tual addresses. Virtual addresses in the range 0 through 15
are always used by the CPU as general register addresses
rather than as core memory addresses. Thus, for example,
if an instruction uses a virtual address of 5 as the address
where a result is to be stored, the result is stored in general
register 5 in the current register block instead of in core
memory location 5.
When the computer is operating with the memory map, vir-
tual addresses in the range 0 through 15 are sti II used as
general register addresses. However, all virtual addresses
above 15 are transformed into actual addresses, by replacing
the high-order portion of the virtual address with a value ob-
tained from the memory map. The memory map replacement
process is descri bed in the secti on II MemoryAddress Control" .
Memory
Access Protection. When the computer is oper-
ati ng in the slave mode with the memory map, the access-
protection codes determine whether or not the program may
access instructions from, read from, or write into specific
regions of the virtual address continuum (virtual memory).
If the slave program attempts to access a region of virtual
memory that is so protected, program control is returned to
the executive program. (The access-protection codes are
described in the section "Memory Address Control".)
MEMORY WRITE PROTECTION
The memory write-protection feature operates independently
of the memory map and access protection. The memory
write-protection feature includes the high-speed memory
for
the memory write locks. These locks operate in con-
junction with a 2-bit field, called the write key, in the
arithmetic and control unit. The locks and the key de-
termine whether or not the program (slave or master) may
alter the contents of specific regions of core memory as
accessed by actual addresses. The write key can be changed
only when the computer is in the master mode; thus the cur-
rent write key cannot be changed by a slave program. (The
functions
of the locks and key are described in the section
"Memory Address Control".)
INSTRUCTION FORMAT
The normal SIGMA 6 memory-addressing instruction has the
following format:
* This
bit position indicates whether or not in-
direct addressing is to be performed. Indirect
addressing is performed (one level only) if this
Instruction Format 11

bit position contains a 1, and is not performed
if this
bit position contains a 0.
Operation This 7-bit field contains the code that desig-
nates the operation to be performed.
R This
4-bit field designates any of the 16 regis-
ters of the current register block as an operand
source, result destination, or both.
x
Reference
address
This
3-bit field designates anyone of registers
1-7 of the current register block as an index
register. X =0 designates no indexing; hence,
register ° cannot be used as an index register.
This 17-bit field contains the initial virtual ad-
dress of the instruction operand. Although the
contents of this field is always, in itself, a word
address, the reference address field allows any
word, doubleword, left halfword, or leftmost
byte within a word in memory to be directly
addressed. Halfword and byte operations re-
quire additional address bits for halfwords and
bytes that do not begin on a word boundary.
Thus,
to address the second halfword of a word,
the X fi~ld of the instruction must designate a
register that contains a 1 in its low-order bit
position. To address bytes 1, 2, or 3 of a word,
the X field of the instruction must designate a
register that contains 01, 10, or 11, respec-
tively, in its two low-order bit positions. See
II Indexing and Index Registers" for a more com-
plete description of the SIGMA 6 indexing
process.
Some SIGMA 6 instructions are ofthe immediate-addressing
type. The format of these instructions provides for an
operand within the instruction word itself, as shown below.
The functions of the Operation and Rfields are identical to
those
of the normal instruction format.
°
Operand
This bit position is shown coded with a 0 be-
cause indirect addressing cannot be used with
this
type of instruction. If indirect addressing
is
attempted, the computer treats the instruc-
tion as a nonexistent instruction.
This field contains an operand that is 20 bits in
I ength, with negative numbers represented in
two's-complement form.
There are several methods by which an instruction word
may
specify the source of an operand or the destination of
a result. These methods are explained below.
IMMEDIATE OPERAND
The operation code of an i'mmediate operand instruction
speci
fi es that an operand is to be found in the operand
field (bit positions 12-31) of the instruction word itself,
12 Instruction Format
and not in a general register or core memory location. The
operand
field of this type of instruction cannot be modified
by
indexing. The following SIGMA 6. instructions are of
the immediate operand type:
Instruction
Name
Mnemonic Page
load Immediate
LI
29
load Conditions and Floating
LCFI 32
Control Immediate
Add Immediate AI 36
Mul tipl y Immediate
MI
38
Compare Immediate CI
41
The byte string instructions are similar to those of the
. immediate operand type in that they cannot be modified
by
indexing. However, the operand field of these in-
structions contains a byte address displacement (or a byte
address) that is a virtual address subject to modification by
the memory map. If an immediate or byte string instruction
is indirectl y addressed, it is treated as a nonexistent instruc-
tion by the computer.
MEMORY REFERENCE ADDRESSES
Core memory locations °through 15 are not accessible to
the programm~r because memory addresses °through 15 are
reserved as register designators for "register-to-register"
operations. Thus, an instruction can treat any register of
the current register block as if it were a location in core
memory. Furthermore, the register block can be used to
hold
an instruction (or a series of up to 16 instructions) for
execution just as jf the instruction (or instructions) were in
core memory. The only restriction upon the use of the
register block for instruction storage is:
If an instruction accessed from a general register uses
the R field of the instruction word to designate the
next higher-numbered register and execution of the
instruction would alter the contents of the register so
designated, the contents of that register should not be
used as
the next instruction in sequence because the
operation of the instruction in the affected register
would be unpredictable.
In the maximum core memory configuration (131,072 words),
memory addresses
II
wrap
around" with address °(general
register 0) being the next consecutive memory address after
XI1FFFFI(131,071). Core memory location 16 follows gen-
eral register 15 as the next location in ascending sequence.
Direct Reference Address. If neither indirect addressing
nor
indexing is called for by the instruction, the reference
address field of the instruction is a direct reference address.
Indirect Reference Address. If indirect addressing is called
forbythe instruction (a 1 in bit position 0 of the instruction
word), the
reference address field is used to access a word
location that contains the direct reference address in bit