Xerox CX PRINT SERVER 550 User manual

Xerox 550 Computer
Reference Manual
90 30 77A

Xerox Corporation
701 South Aviation Boulevard
EI Segundo, California 90245
213 679-4511
Xerox 550 Computer
Reference Manual
FIRST EDITION
90 30 77A
February 1974
Price: $6.50
XEROX
Printed In ~.S.A.

ii
RELATED PUBLICATIONS
Title
Publication No.
Xerox Symbol/LN,OPS Reference Manual
90 1790
Xerox Meta-Symbol/LN,OPS Reference Manual
900952
Xerox Macro-Symbol/LN,OPS Reference Manual 90
1578
Manual Content Codes; BP - batch processing, LN - language, OPS - operations, RP -remote processing,
RT - real-time, SM -system management, TS - time-sharing, UT - utilities.

CONTENTS
l. XEROX 550 COMPUTER SYSTEM
Instruction Exception Trap
43
Power On Trap 44
Introduct ion 1 Power
Off Trap 44
General Characteristics
1 Processor
Detected FauIt Flag 44
Standard and Opti ona I Features
3 Register
Altered Bit 45
Genera 1- Purpose Features 3
Time-Sharing Features
4
Rea
1- Time Features 5
Multiuse Features
6
3. INSTRUCTION REPERTOIRE 46
Multiprocessor Features
6
Multiprocessor Interlock
6
Load/Store Instructions 48
Multiport Memory System 7
LI
49
Manual Partitioning Capability
7
LB
49
Multiprocessor Control Function 7
LH
49
Shared Input/Output
7
LW
49
LD
50
LCH
50
LAH
50
2. SYSTEM ORGANIZATION
8
LCW
51
LAW
51
Processor CI us ters 8
LCD
51
System Control Processor 8
LAD
52
Basic Processor 8
LAS
52
General Registers 8
LS
53
Memory Control Storage
11
LM
53
Computer Modes
11
LCFI
53
Information Format 12
LCF
54
Information Boundaries 13
LVAW
54
Instruction Register 13 XW
54
Main Memory 14
STB
54
Memory Unit
14
STH
55
Maintainability and Performance
16 STW
55
Virtual and Real Memory 17
STD
55
Types of Addressing 19
STS
55
Memory Address Control 26
STM
55
Program Status Words 28 STCF
56
Centra I ized Interrupts 30
Ana Iyze/Interpret Instructions
56
States of an Interrupt Level
30
ANLZ
56
Dialogue Between the Basic Processor and
INT
58
the Interrupt System During an Interrupt-
Fixed-Point Arithmetic Instructions
58
Entering Sequence
32 AI
59
Dialogue During an Interrupt-Exiting AH
59
Sequence
32
AW
60
Physical Organization
32 AD
60
Interrupt Groups
32
SH
61
Control of the Interrupt System 35 SW
61
Single-Instruction Interrupts 36 SD
61
Trap System
36 MI
62
Trap Entry Sequence
36
MH
62
Trap Addressing 36 MW
63
Trap Condition Code
39
DH
63
Nonallowed Operation Trap 39 DW
63
Push-Down Stack Limit Trap
40
AWM
64
Fixed-Point Overflow Trap
41
MTB
64
Floating-Point Arithmetic Fault Trap
42
MTH
64
Watchdog Timer Runout Trap
42
MTW
65
Programmed Trap
43
Comparison Instructions
65
CALL Instruction Trap
43 CI
66
Hardware Error Trap
43 CB
66
iii

CH
CW
CD
CS
CLR
CLM
Logical Instructions
OR
EOR
AND
Shift Instructions
S
Floating-Point Shift
SF
Conversion Instructions
CVA
CVS
Floating-Point Arithmetic Instructions
Floating-Point Numbers
Floating-Point
Add and Subtract
Floating-Point Multiply and Divide
Condition Codes for Floating-Point
Instructions
FAS
FAL
FSS
FSL
FMS
FML
FDS
FDL
Push-Down Instructions (Non-Privileged)
Stack Pointer Doubleword (SPD)
Push-Down Condition Code Settings
PSW
PLW
PSM
PLM
MSP
Push-Down Instructions (Privileged)
Status Stack Pointer Doubleword
PSS
PLS
I='VOl""II ... 'O /1l ... ,...,It"'l_~ 1_,..J. .... _ ... : __ r
_"" ..... "'1_/ Loll"""."", • .llloJlIIV ....... ,VII.)
Nonallowed Operation Trap During
Execution of Branch Instruction
EXU
BCS
BCR
BIR
BDR
BAL
CALL Instructions
CAll
CAL2
CAL3
CAL4
Control Instructions
Program Status
Words
LPSD
XPSD
LRP
Mly",C
iv
66
67
67
67
67
68
68
68
68
69
69
69
71
71
72
73
73
73
74
75
77
77
77
77
78
78
79
79
79
79
79
79
80
81
81
82
83
83
84
84
87
88
00
UI'
90
90
91
91
91
91
92
92
92
92
92
93
93
93
93
94
96
97
Loading the Memory Map 98
LMAP 98
LMAPRE 98
Loading the Access Protection Controls 98
Memory Write Protection
Locks 99
LLOCKS 99
LLOCKSE 99
Interrupti
on of MMC 100
Memory Access Traps by MMC Instruction __ 100
LRA 100
LMS 101
WAIT 103
RD 103
Read Direct, Internal Basic Processor
Control (Mode 0) 104
Read Direct, Interrupt Control (Mode 1} __ 105
Read Direct (Mode 9) 105
WD 1W
Write Direct, Internal Basic Processor
Control (Mode 0) 108
Write Direct, Interrupt Control (Mode
1} __ 109
Input/Output Instructions 110
Overall Characteristics 110
I/O Status Information 110
SIO 118
no 119
TDV 120
HIO 121
RIO 122
POLP 122
POLR 122
AIO 123
4. INPUT/OUTPUT OPERATIONS 125
External DIO Interface 125
Multiplexor Input/Output Processor (MIOP) __ 125
Device Controllers 125
Input/Output Processor (lOP) Fundamentals
__ 126
Command List 126
Operational IOCD 126
1/0 Operati on Phases 131
Preparation Phase 131
Initiation Phase 131
Fetching Phase 131
Executi on Phase 132
Termination Phase 134
5. OPERATIONAL CONTROL
135
External Control Subsystem ________ 135
CentraIized System Control 135
Controi Console Devices 135
Control Commands 136
Operator Control Commands 136
ZCI 137
ZcSSW 137
ZCSS# 137
ZCLDN###lf ___________ 137

ZCRSY
138 Standard 7-Bit Communication Codes
(ANSCII)_ 156
ZCRBP
138
Standard Symbol-Code Correspondences
157
ZCRIO
138 Hexadecimal Arithmetic
161
ZCHLT
138
Addition Table
161
ZCRUN
139 Multiplication Table
161
Diagnostic Control Commands
139
Table of Powers of SixteenlO
162
pc
139 Table of
Powers of Ten16 162
/
139 Hexadecimal-Decimal Integer Conversion
+
139
Table
163
139 Hexadecimal-Decimal Fraction Conversion
M
139 Table
169
L
140
Table of Powers of Two
173
R
140
Mathematical Constants 173
I 140
RUB OUT
140
B.
GLOSSARY OF SYMBOLIC TERMS
174
S
140
G
141 C.
FAULT STATUS REGISTERS
177
X
141
Maintenance Control Commands 141
ZC
CLK
141
J6'
142
ZcC##
142
ZCE##
142
ZCKIL
142
FIGURES
ZCMMO
142
ZC MM1 143
l. A Xerox 550 Computer System
9
ZC
MM2 143
ZC MM3
143
2. The Bas ic Processor
10
ZC MM4
143
ZC MM5 143
3. Information Boundaries
13
ZC MM6
143
ZC MM7
144
4.
Main Memory
15
ZCMM8 144
ZC MM9
144 5. Addressing Logic
18
L~MMA
i44
ZCLDS####
144
6. Index Displacement AI ignment (Real and
ZCLDT
144 Vi rtua I Addressing Modes)
21
ZCT
144
System Control Panel 144
7. Generation of ActuaI Addresses Indirect,
Operating Procedures and Information
147
Virtual Addressing
22
8.
Index Displacement Alignment (Real-
Extended Addressing) 23
6. SYSTEM CONFIGURATION CONTROL 150
9. Generation of Effective Virtual Address
Configuration Control Panel
(CCP)
150 (Indirect Real-Extended Addressing) 24
10. OperationaI States of an Interrupt Level 31
1l. Interrupt Priority Chain 34
12. Typical 28-Word Portion of Memory Stack
for PSS and P LS
86
APPENDIXES
13. Formats of I/O Instructions 111
A. REFERENCE TABLES 155
14. Bootstrap Loader 138
Standard
Symbo Is and Codes 155 15. System Control Panel 145
Standard Character Sets 155
Control Codes
155 16. Chassis Physical Configuration 151
Special Code Properties
155
Standard 8-Bit Computer Codes (EBCDIC) 156 17. Sample
Rows of CCP Switches
151
v

TABLES
15.
Device Status Byte (Register Ror Ru1)
(510, no, and HIO only) 114
1. Basic Processor
Operating Modes and
Addressing Cases 25 16.
Operational Status Byte (Register Ru 1) 115
2. Interrupt Locations 33
17.
Status Response Bits for I/O Instructions 116
3.
Summary of Trap Locations
37
18. lOP Status Byte 117
4.
TCC Setting for Instruction Exception Trap X'4D~
44
19.
Status Response Bits for AIO Instruction 118
5.
Registers Changed at Time of a Trap Due to an
20.
I/O Address (AIO Response) 118
Operand Access
45
21.
Event Messages 136
6.
ANALYZE Table for Operation Codes 56
22. Diagnostic Control (P-Mode) Commands 140
7.
Floating-Point Number Representation 75
23. Bit Assignments and Description, Processor
8.
Condition Code Settings for Floating-Point Control Word, Register Q30 (X'l E') 148
Instructions
78
24.
Bit Assignments, Address Compare Register
9.
Status Word 0 102 Q31 (X1'F') 149
10.
Status Word 1 103
25.
Functions of Processor Cluster Configuration
Control Panel
Row 152
11.
Read Direct Mode 9 Status Word 105
26. Functions of Memory Unit Configuration
12.
Chassis Type Assignments 106 Control Panel Row 153
13.
Description of I/o Instructions 111
C-1. Fault Status Registers 177
14.
I/o Status Information (Register R)
113
C-2. Memory Unit Status Register 178
vi

1. XEROX 550 COMPUTER SYSTEM
INTRODUCTION
The Xerox 550 general-purpose, digital, computer system
accommodates a
variety of scientific, business, real-time,
and time-sharing applications. A system includes system
control, basic processor, I/O processor, and main memory
(up
to 256K words) with two ports. Each major system
element performs asynchronously
wi th respect to other
elements.
The basic system
can be readi Iy expanded. Memory access
paths can be increased from the basic two ports to a maxi-
mum of six ports. Input/output capabi Iity can be increased
by adding more
input/output processors (lOPs), device con-
trollers, and peripheral devices.
The basic processor (BP) has an extensive instruction set
that includes floating-point instructions.
The multiaccess memory units, with
interleaving, afford a
high level of system performance. Main memory
can be
expanded in
16K word increments to a maxi mum of 256K
words. Address
interleaving may be performed between
memory units of like
size. The number of ports to each
memory unit can be expanded to allow independent ac-
cess to memory by up to six "processor clusters" (i.e.,
functional groups).
Processor clusters are the grouping of two or more functions
{such as a basic processor,
an I/O processor, and inter-
faces} on a common bus. Clustering permits processors to
share common faci Ii ties, e. g., buses and memory i nter-
faces. Therefore, the hardware is Iess redundant, hence
less complex, resulting in more reliabi lity at a lower cost.
There
are multiple combinations of functional groups from
which to
select.
Existing Sigma 5-9 programs may be run on the system.
The upward compati
bi Iity of the comprehensi ve, mod-
ular software (assemblers, compilers, mathematical and
utility routines, and application packages) eliminates
reprogramming.
Features have been incorporated in this design
to enhance
overall system reliability, maintainability, and availability.
Centralized switches for system repartitioning may permit
faulty units, or
an entire subsystem, to be isolated for diag-
nosis or repair whi Ie the primary system continues operation.
Parity checking is performed on each byte of information
for most system interfaces and internal control signals. Most
failed instructions are automatically retried, and uninter-
rupted processing continues. The only apparent effect may
be an entry in the error log. In the event an error is irre-
coverable, there are error storage registers that return com-
plete data on the fault and the status of the system at
that point.
GENERAL CHARACTERISTICS
The following system features and characteristics permit
efficient operation in general-purpose, multiprocessor,
time-sharing,
real-time, and multiuse environments:
• Word-oriented memory (32-bit word plus parity bit
per byte) that can be addressed and altered as byte
(8-bit), halfword (2-byte), word (4-byte), and double-
word (8-byte) quantities.
• Memory expandable to 256K words (K == 1024) in mod-
ular units of
16K words each.
• Indirect addressing with or without postindexing.
• Displacement index registers, automatically self-
adjusting for all data sizes.
• Immediate operand instructions for greater storage
efficiency and increased speed.
• Four blocks of 16 general-purpose registers for address-
ing, indexing, and accumulating. Multiple registers
permit rapid
context switching.
• Hardware memory mapping, which virtually eliminates
memory fragmentation and provides dynamic program
relocation.
• Memory access protection for system aOO informaTion
security
and protection.
• Memory write protection within memory units to prevent
inadvertent destruction of critical areas of memory from
any processor cluster.
• Watchdog timer to assure nonstop operation.
• Real-time priority interrupt system with automatic iden-
tification and priority assignment, fast response time,
and 14 internal and up to 48 external levels that can
be individually armed, enabled, and triggered by
program
control.
• Instructionswith long execution times can be interrupted.
• Automatic traps for error or fault conditions, with
masking
capability and maximum recoverability, under
program
control.
• Power fail-safe for automatic shutdown and resumption
of processing in
event of power fai lure.
• Multiple interval timers with a choice of resolutions
for independent ti
me bases.
• Privileged instruction logic for program integrity in
multiuse environments.
Xerox 550 Computer System

• Extensive instruction set that includes:
• Byte, halfword, word, and doubleword operations.
• Use of all memory-referencing instructions for
register-to-register operations, with or without
indirect addressing and postindexing, and within
normal instruction format.
• Multiple register operations.
• Fixed-point integer arithmetic operations in half-
word, word,· and doubleword modes.
• Immediate operand instructions.
• Floating-point hardware operations in short and
long formats with significance, zero, and normal-
ization control and checking, all under full pro-
gram control.
• Full complement of logical operations (AND, OR,
exclusive OR).
• Comparison
operations, includingcompare between
limits (with limits in memory or in registers).
• Call instructions that permit up to 64 dynamically
variable, user-defined instructions, and allow a
program
access to operating system functions with-
out operating system intervention.
• Push-down stack operations (hardware imple-
mented) of single or multiple words, with auto-
matic limit checking, for dynamic space alloca-
tion, subroutine communication, and recursive
routine
capabi Iity.
• Automatic conversion operations, including binary/
BCD and any other weighted-number systems.
• Analyze instruction that facilitates effective
address computation.
• Interpret instruction that increases speed of inter-
pretive programs.
• Shift operations (left and right) of word or double-
word, including logical, circular, arithmetic,
searching shift, and floating-point modes.
• Built-in reliability and maintainability features that
include:
• Extensive error logging. When a fault is detected,
system status and fault information ale available
for program retrieval and logging for subsequent
analysis.
• Full parity checking on all data and addresses
communicated in
either direction on buses be-
tween memory units and processors, providing fault
2 General Characteristics
detection and location capability to permit the
operati ng system or diagnostic program to quickly
determine a faulty unit.
• Address stop feature that permits operator or main-
tenance personnel to:
Stop on
any instruction address.
Stop on
any memory reference address.
Stop when
any word in a selected page of
memory is
referenced.
• Traps that provide for detection of a variety of
fault conditions, designed to enable a high degree
of system recoverabi Iity.
• Partitioning features that enable system recon-
figuration via a centralized Configuration Con-
trol Panel. Units may be partitioned from the
system by selectively disabling them from buses
(assuming
other system facilities can handle the
additional load). Thus, faulty units, processors,
devices, or an alternate system can be isolated
from the operational system to enable diagnosis
or
repair while the primary system continues
operation.
• Independently operating I/o system with the following
features:
• Direct input/output (READ DIRECT, W.UTE DIRECT
instructions) for transfer of 32-bit words between
the specified general register and an external de-
vice; a 16-bit address is transferred for selection
and control purposes; and each transfer is under
direct program control.
• Up to five independent I/O processor clusters (re-
stricted only by the maximum number of 6 ports).
• Multiplexor I/O processors (MIOPs) (up to 3 per
I/O ciuster), each providing for simuitaneous op-
eration of up to 16 devices per processor.
• Data chaining for gather-read and scatter-write
operati ons.
• Command chaining for multiple record operations.
• Write lock protect feature within memory unit
for positive
protection from all processors storing
into memory.
.. Comprehensive modular software that is program com-
patible with Sigma 5-9 computers:
• Expands in capability and speed as system grows.
• Operati ng system: Control Program Real-Time
(CP-R).

• Language processors and utilities and applications
software for both commercial and sci entific users.
• Peripheral equipment includes:
• Card equipment: Reading speeds up to 1500 cards
per minute; punching speed of 100 cards per min-
ute; intermixed binary and EBCDIC card codes.
• Line printers: Fully buffered with speeds up to
1250 lines per minute; 132 print positions with
character sets containing 64 or 95 characters.
• Magnetic tape units: 9-track systems, single or
dual density (1600 or 800/1600 BPI), industry-
compatible; high-speed, automatic loading units
operating at 125 inches per second with trans-
fer rates up to 200,000 bytes per second; and
at 75 inches per second wi th transfer rates up
to 120,000 bytes per second.
• Rapid Access Data (RAD) and disk files: RAD
capacity of 2.9 million bytes, with a transfer
rate of 750,000 bytes per second; disk capa-
cities in increments of 49 million bytes per unit
wi th a transfer rate of 312,500 bytes per second.
• Keyboard printers: 10 characters per second.
• Data communications equipment: Complete line
of character-oriented, message-oriented, and
procedure-oriented equipment to connect remote
user terminals (including remote batch) to the
computer center via common carrier lines and
local terminals directly.
STANDARD AND OPTIONAL FEATURES
A basic system has the following standard features:
• A basic processor (BP) that includes:
• Full instruction set
• Memory map with access protection
• Register blocks (4)
• Multiplexor Input/Output Processor (MIOP) with:
• 16 subchannels
• 1- or 4-byte interface
• Input/Output Adapter
• Memory unit that includes:
• DuaI port access
• Memory write lock protection
• A system control processor
that includes:
• Real-time clocks
(4)
• Internal interrupts (14)
• Power
fail-safe detection
• External Control Subsystem
(ECS)
• System Control Panel (SCP)
• Configuration Control Panel (CCP)
• Local and remote assist
facility
• Error
detecti on faciIities
• Diagnostics
A system may have the following optional features:
• System Control Processor options:
•
• Up to 48 external priority interrupts (in groups
of 12)
• External Direct Input/Output interface (010)
Memory options:
• Up to 4 additional access ports (in sets of 2).
• Input/Output options:
• Multiple I/O clusterst•
• Up to 3 additional MIOPs, each with 16 sub-
channeIs, per cluster.
• One Input/Output Adapter (for one MIOP)
per cluster.
GENERAL-PURPOSE FEATURES
General-purpose computing applications are characterized
by emphasis on computation and internal data handling.
tThe aggregate of processor clusters is restricted by the max-
imum memory port limitation of 6.
Standard and Optional Features/General-Purpose Features 3

Many operations are performed in floating-point format.
Other typical characteristics include high system input/
output transfer rates.
General-purpose features are described in the following
paragraphs.
Floating-Point Hardware. Both short (32-bit) and long
(64-bit) formats are avai lable in the floating-point in-
structions. Under program control, the user may select
optional zero checking, normalization, floating-point
rounding and significance checking. Significance check-
ing permits use of short floating-point format for high pro-
cessing speed and storage economy and of long floating-
point format when loss of significance is detected.
Indirect Addressing. Indirect addressing facilitates table
linkages and permits keeping data sections of a program
separate from procedure sections for ease of maintenance.
Displacement Indexing. Indexing by means of a IIfloat-
ing
ll
displacement permits accessing a desired unit of
data without considering its size. The index registers
automatically align themselves appropriately; thus, the
same index register may be used on arrays with different
data sizes. For example, in a matrix multiplication of
any array of full word, single-precision, fixed-point
numbers, the results may be stored in a second array as
double-precision numbers, using the same index quantity
for both arrays. If an index register contains the value
of k, then the user always accesses the kth element,
whether it is a byte, halfword, word, or doubleword.
Incrementing by various quantities according to data size
is not required; instead, incrementing is always by units
in a
continuous array table regardless of the size of data
element used.
Instruction Set. The instructions permit short, highly
optimized programs to be written. These are rapidly
assembled and minimize both program space and execu-
tion time.
Conversion Instructions. Two generalized conversion in-
structions provide for bidirectional conversions between
internal binary and any other weighted number system,
including BCD.
Call Instructions. These four instructions permit handling
up
to 64 user-defined subroutines, as if they were bui It-in
machine instructions. Call instructions also gain access to
specified operating system services without requiring its
intervention.
4 Time-Shari ng Features
Interpret Instruction. The Interpret instruction simplifies
and speeds interpretive operations such as compilation, thus
reducing space and time requirements for compilers and
other interpretive systems.
Four-Bit
Condition Code. Checking results is simpl ified by
automatically providing information on almost every instruc-
tion execution, including indicators for overflow, under-
flow, zero, minus, and plus, as appropriate, without
requiring an extra instruction execution.
Direct Input/Output (DIO). Direct input/output facili-
tates in-line program control of asynchronous or special-
purpose devices. This feature permits information to be
transmitted directly to or from general-purpose registers.
Multiplexor In ut/Output Processor (MIOP). Once in-
itialized, I 0 processors operate independently of the
basic processor, freeing it to provide faster response to
system needs. An MIOP requires minimal interaction
with the basic processor. I/O command doublewords per-
mit both command chaining and data chaining without
intervening basic processor cO:ltrol. I/o equipment speeds
range from slow rates involving human interaction (tele-
typewriter, for example) to transfer rates of rotating mem-
ory
devices of over 750, 000 bytes per second. Peri-
pheral controllers attached to an MIOP may be operated
simultaneously.
TIME-SHARING FEATURES
Time-sharing is the ability of a system to share its total
resources among many users at the same time. Each user
may
be performing a different task, requiring a different
share of the available resources. Some users may be on-
line in an interactive, IIconversationalli mode with the
basic processor whiie other users may be entering work to
be processed that requires only final output.
Time-sharing features are described in the following
paragraphs.
Rapid Context Saving. When changing from one user to
another, the operating environment can be switched quickly
and easiIy. Stack-manipulating instructions permit storing
in a push-down
stack of 1 to 16 general-purpose registers by
(1 single instruction, Stack status is updated automat!ca!!y
and information in the stack can be retrieved when needed
(also, by a single instruction). The current program status
words, which
contain the entire description of the current
user's environment and mode of operation, may be stored
anywhere in memory, and new program status words may be
loaded, all with a single instruction.

Multiple Register Blocks. The availability of four blocks
of 16
general-purpose registers improves response time by
reducing
the need to store and load register blocks. A
distinct block may be assigned for different functions as
needed;
the program status words automatically select the
applicable register block.
User Protection. The slave mode feature restricts each user
to his own set of instructions while reserving to the operat-
ing system certain "privileged" (master mode) instructions
that could destroy another user's program if used incor-
rectly. Also, a memory access - protection feature pre-
vents a user from accessi ng any storage areas other than
those assigned to him. It permits him to access certain areas
for reading only, such as those containing publ ic subrou-
tines, whi Ie preventing him from
reading, writing, or ac-
cessing instructions in areas set aside for other users.
Storage Management. Main memory is
expandable to 256K
(K = 1024) words. To make efficient use of available mem-
ory,
the memory map hardware permits storing a user's pro-
gram in fragments as sma II as a page of 512 words, wherever
space is available; yet all fragments appear as a single,
contiguously addressable block of storage at execution time.
The memory map also automatically handles dynamic pro-
gram relocation so that the program appears to be stored in
a standard way
at execution time, even though it may ac-
tually be stored in a different set of locations each time it
is brought into memory. The memory map provides the
ability to locate any 128K-word virtual program in the basic
processor's logical addressing
space. Thus, the system can
always address a virtual memory of 128K words regardless
of physical memory
size.
Input/Output Capability. Time-sharing input/output re-
quirements are handled by the same general-purpose input/
output capabi lities described under" General-Purpose
Features".
Nonstop operation. A "watchdog" timer assures that the
system continues to operate even in case of halts or de-
lays due to failure of special I/O devices. Multiple
real-time clocks with varying resolutions permit indepen-
dent time bases for flexible allocation of time slices to
each user.
Reliability,
Maintainability, Availability. Since time-
sharing systems have many on-line users needing immediate
system response, "downtime"
defeats time sharing's primary
purpose. Pooling of resources
along with flexible recon-
figuration control ensures a high level of continuous avai 1-
abi lity. Configuration controls are provided to switch the
load from one unit to another in the event of a failure with
no loss of functional
capabi lity, only capacity. In addi-
tion, a nonworking subset of the total system may be
logically isolated (partitioned) so that maintenance may
proceed on the subset whi Ie
the remainder of the system
continues to
operate.
To minimize the effect of transient errors, automatic retry
of failed instructions is performed.
REAL-TIME FEATURES
Real-time applications are characterized by a need for:
(1) hardware that provides quick response to an external
environment; (2) speed that is sufficient to keep up with
the real-time process itself; (3) input/output flexibility to
handle a wide variety of data types at different speeds;
and (4) reliability features to minimize irreplaceable lost
time.
Multilevel, Priority Interrupt System. The real-time-
oriented system provides rapid response to external interrupt
levels. Each interrupt is automatically identified and res-
ponded to according to its priority. For further flexibility,
each level can be individually disarmed (to discontinue in-
put acceptance) and disabled (to defer responses). Use of
the disarm/disable feature makes programmed dynamic re-
assignment of priorities quick and easy, even while a real-
time process is in progress.
Programs involving interrupts from
specially designed equip-
ment often require checkout before the equipment is actually
available. To permit simulating this special equipment, any
external interrupt level can be "triggered" by the basic
processor through
execution of a single instruction. This
capability is also useful in establishing a modified hierarchy
cf !"esp~!"!ses. F~!" ex!:!!'!'!p!e, ;~ !"e5p0l"!di l"!2 to (1 hi2h-pri(")rity
interrupt, after the urgent processing is completed, it may
be
desirable to assign a lower priority to the remaining por-
tion so that the interrupt routine is free to respond to other
critical stimuli. The interrupt routine can accomplish this
by triggering a
lower-priority level, which processes the
remaining data only after other interrupts have been handled.
READ DIRECT and WRITE DIRECT instructions (described in
Chapter 3) allow the program to completely interrogate,
preserve, and alter the condition of the interrupt system at
any time and to restore that system at a later time.
Nonst
Operation. When connected to special devices
(on a ready resume basis), the basic processor may be ex-
cessively delayed if the specific device does not respond
quickly. As in the time-sharing environment, the built-in
watchdog timer assures that the basic processor cannot be
delayed for an excessive length of time.
Real-Time Clocks. Many
real-time functions must be timed
to occur at specific instants. Other timing information isalso
needed -for example, elapsed time since a given event, or
the current time of day. The computer system can contain
up to four real-time clocks with varying degrees of resolu-
tion to meet these needs. These clocks also allow easy hand-
ling of separate time bases and relative time priorities.
Real-Time Features 5

Rapid Context Switching. When responding to a new set of
interrupt-initiated circumstances, a computer system must
preserve the current operating environment, for continuance
later, while setting up the new environment. This changing
of environments must be done quickly, with a minimum of
II overhead" time costs. Anyone of the four blocks of
generar-purpose arithmetic registers can, if desired, be as-
signed to a specific environment. All relevant information
about the current environment (instruction address, current
general register block, memory-protection key, etc.) is
kept in the program status words. A single instruction
stores the current program status words anywhere in memory
and loads new ones from memory to establish a new en-
vironment, which includes information identifying a new
block of general-purpose registers. Thus, the system's
operating environment can be preserved and changed com-
pletely through the execution of a single instruction.
Memory Protection. Both foreground (real-time) and back-
ground can run concurrently in the system because a fore-
ground program is protected against destruction by an un-
checked background program. Under operating system
control, the memory access-protection feature prevents
accessing memory for specified combinations of reading,
writing, and instruction acquisition.
Variable Precision Arithmetic. Much of the data encoun-
tered in real-time systems are 16 bits or less. To process
this data efficiently, both halfword and fullword arithmetic
operations are provided. For extended precision, double-
word arithmetic operations are also included.
Direct Input/Output. For handling asynchronous I/O, a
32-bi t word can be transferred di rectly between any genera 1-
purpose register and external devices.
Reliability, Maintainability, Availability. The capabil-
ities described in the section, .. Time-Sharing Features"
apply equally to the real-time environment.
MULTIUSE FEATURES
As implemented in this system, IImultiuse" combines two or
more application areas. The real-time application is the
most difficult general computing task because of its severe
requirements. Similarly, another difficult multiuse task is
a time-sharing application that includes one or more real-
time processes. Because the system is designed on a real-
time base, it is qualified for a mixture of applications in a
multiuse environment. Many hardware features that prove
valuable for certain application areas are equally useful in
others, although in different ways. This multiple capa-
bi Iity makes the system particularly effective in multi-
use applications.
The major multiuse features are described in the follow-
i
ng paragraphs.
6 Muitiuse Features/Multiprocessor Features
Priority Interrupt System. In a multiuse environment, many
elements operate simulatneously and asynchronously. Thus,
an efficient priority interrupt system is essential. It allows
the computer system to respond quickly, and in proper or-
der, to the many demands made on it, with attendant im-
provements in resource efficiency.
Quick Response. The many features that combine to pro-
duce a quick-response system (multiple register blocks,
rapid context saving, multiple push-pull operations) benefit
a II users because more of the system's resources are readily
available at any instant.
Memory Protection. The memory protecti on features protect
each user from every other user and guarantee the integrity
of programs essential to critical real-time applications.
Input/Output. Because of the wide range of capacities and
speeds, the I/O system simultaneously satisfies the needs of
many different appl ication areas economically, both in
terms of equipment and programming.
Instruction Set. The comprehensive instruction set provides
the computational and data-handling capabilities required
for widely differing application areas; therefore, each user's
program length and running time is minimized, and the
throughput is maximized.
MULTIPROCESSOR FEATURES
System design readi Iy permits expansion to shared memory
in a multiprocessor system. The system can contain a com-
bination of functional clusters, each of which in turn may
contain multiple processors. The total number of clusters
is restricted to the maximum port limitation of six. All pro-
cessors ina system may share common memory.
The following paragraphs describe the major multiprocessor
features of the system.
MULTIPROCESSOR INTERLOCK
In a multiprocessor system, the basic processors often need
exclusive control of a system resource. This resource may
be a region of memory, a particular peripheral device, or,
in some cases, a specific software process. There isa special
instruction to provide this required multiprocessor interlock.
This special instruction, LOAD AND SET, unconditionally
sets a Ill" bit inthe sign position of the referenced memory
location during the restore cycle of the memory operation.
If this bit had been previously set by another processor, the
interlock is said to be "set" and the testing program pro-
ceeds to another task. On the other hand, if the sign bit
of the tested location is a zero, the resource is allocated
to the testing processor, and simultaneously the interlock
is set for any other processor.

MULTIPORT MEMORY SYSTEM
The system has growth capabi Iity of up to 6 ports per
memory unit. A memory unit may contain 16K or 32K words.
This architecture allows flexibility in growth patterns
and provides high memory bandwidth, essential to multi-
processor systems.
MANUAL PARTITIONING CAPABILITY
Manual partitioning capability is afforded for all system
units. Thus, besides the primary advantage of increased
throughput, a secondary advantage of a multiprocessor
system is the "fail-soft" ability. Given a duplicate unit,
any unit can be partitioned by selectively disabling it from
the system buses. Depending on the type of failing unit,
the system will be operable, with some degree of degraded
performance. An alternate processor bus with dual system
capabilities can be provided.
MULTIPROCESSOR CONTROL FUNCTION
A multiprocessor control function is provided on all multi-
processorsystems. This function provides these basic features:
1. Control of the External Direct Input/Output bus (Ex-
ternal 010), used for controlling system maintenance
and special purpose units such as analog to digital
converters.
2. Central control of system partitioning.
3. Centralized interrupt system, providing capability for
the operating system to use interrupts to schedule tasks
independently of the number of basic processors pres-
ent ina system.
4. Processor to processor communication via processor
buses.
SHARED INPUT/OUTPUT
In a multiprocessor system, any basic processor may direct
I/O actions to any I/O processor. Specifically, any basic
processor can issue an SIO, TIO, TOY, or HIO instruc-
tion to begin, test, or stop any I/O process. However,
the II end-action" sequence of the I/O process is directed
to one of the basic processors in the system by the System
Control Processor. This feature (accomplished by setting
a pair of configuration control switches) allows dedicating
I/O end-action tasks to a single processor and avoids con-
flict resolution problems.
Multiprocessor Features 7

2. SYSTEM ORGANIZATION
The elements of this computer system include a basic
processor
(BP), input/output processors (lOPs), memory, I/O
device controllers, and devices (see Figure 1). The pro-
cessors and interfaces clustered into functional groups, in-
terconnected via buses and controlled from a Configuration
Control Panel
and a System Control Processor. Elements
within a processor
cluster share an access path for intra-
cluster communications. Thus, the total computer system can
be viewed functionally as a group of program-controlled
processor clusters communicating with each other and a
common memory. Each processor
cluster operates asyn-
chronously and semi-independently, automatically over-
lapping the operation of elements within as well as the
operation of other processor clustersfor greater speed (when
circumstances
permit).
PROCESSOR CLUSTERS
Processors (basic processor and MIOP, for example) are
grouped functionally along with a Memory Interface (MI)
and a Processor Interface (PI) into a processor cluster. El-
ements
within a processor cluster share an access path (the
cluster bus) to the Memory Interface, which connects to the
memory system via a memory bus. The Memory Interface
resolves contention problems and controls use of the cluster
bus by the elements in the cluster.
A processor communicates with processors in other processor
clusters through the Processor
Interface, which connects di-
rectly to a processor bus. Via the processor bus, any pro-
cessor can communicate with or control any other processor
anywhere
in the system configuration.
Note: Although two processor buses are provided, a Pro-
cessor Interface can be connected to one or the
other of the processor buses, but not to both at the
same
time.
Within a basic processor-MIOP processor cluster, the basic
processor primari
Iy performs overa" control and data reduc-
tion tasks whereas the MIOP performs the task associated
with the exchange of digital information between main
memory
and selected peripheral devices. The MIOP com-
municates with device controllers via the I/o bus, which
connects to the Controller Interface (CI).
SYSTEM CONTROL PROCESSOR
The System Control Processor performs these primary func-
tions in the overall system:
1• System
control.
2. External Control Subsystem.
8 System
Organization
3. Internal and external interrupt processing.
4. External and certain internal direct I/O (DIO) control.
It provides these major interfaces with other parts of the
system:
1. System console interface.
2. System control bus interface.
3. Processor bus interface.
4. Internal and external interrupt interfaces.
5. External and certain internal DIO interfaces.
6. System clock interface.
In addition to these major interfaces it provides paths for
other signals including system reset, 1.024 MHz clock,
power on/power off trap requests, and external real-time
clocks.
Figure 1 shows the interconnection of a System Control Pro-
cessor to processor c I us ters via a processor bus as we II as i n-
terconnection to the system console, external Direct Input/
Output (DIO), and external interrupts.
BASIC PROCESSOR
This section describes the organization and operation of the
basic processor in terms of instruction
and data formats, in-
formation processing, and program control. The basic pro-
cessor comprises a fast memory and an arithmetic and control
unit
as functionally shown in Figure 2.
.hi9Je: Functionally associated with the basic processor but
physically located elsewhere are a memory map,
memory
access protection codes, and memory write
protection codes. Memory control storage for the
memory map and
access codes is located in the Mem-
ory
Interface, and the memory control storage for
the write protection codes (write locks) is located
in the memory. These functions are described in
"Memory System", later in this chapter.
GENERAL REGISTERS
A fast (integrated circuit) memory consisting of ninety-six
32-bit registers is used wi th in the basic processor. A group
of 24 registers is referred to as a register block; thus, a
basic processor contains four register blocks. A 2-bit con-
trol field (called a register block pointer) in the program
status words
(PSWs) selects the register block currently

System
Control
Console
System
Control
Processor
Memory
Urut Memory
Unit
~~ss;;;:--------' r
I Cluster (Basic) I I
I I I
I I I
Memory I I
I Interface I I
I I
I Processor ,Bus #1 I
I I I
I I
I Processor I I
Memory
Unit
Pr"o~;----
Cluster (I/O)
Memory
Interface
Processor
Interface
r---
I Interface I I
____ I~ I I ~
I
~ rocessoq BUS 1fT T]"
"I
I
.-J
r-..L --,
System ,
Control I
Processor I
L_[_J
r- ,..-..,
I System I
I Control I
LC~o~J
Ex ternaI Interrupts
0 ................ "- .... T ......... --.: .......... I r ........ II:' ...... I ..... 1............ 11:'
.,,"" ... ..., .................. _. _ ....... - ...... "'" & ...... -.-
DIO Bus
Communications
.-----1 Interface
Line
Adapter
Line
Adapter
Comm.
Lines
Comm.
Lines
:> I 12
I V Basic I U
Processor
I I
I I
I I
I I
MIOP
: I
o
~
Device
Controller
Device
Controller
I
_ ...J
o
~
I
I
I
Device
Controller
Device
Controller
MIOP
Dual Access Option Dual Access Option
Figure 1. A Xerox 550 Computer System
-,
I
I
I
I
I
Basic Processor 9

FAST MEMORY
ARITHMETIC AND CONTROL UNIT
GENERAL REGISTER BLOCK (TYPICAL)
INSTRUCTION REGISTER
ol~ ______________ ~
1 I.I:::::::.:::::}:=:::······ ':):::::fff::::rrttr::::t:ttt···:::::\::tt::tl
2 1:=:::"::::::::::':: :::::::r:t:::::ttI:::::I:::t:::::::I:::.::I:}::::·::::::::t:':::I:I::i'::::::]
3 1'.::I::::::::::r:::::::=:,: .::::f:::Im:tt:::fIttt::\:t:II:t:::::::!::::'j':·::II!::::::!::1
4 II:::::.:::::--::::::::!:}f::: :tI:·:,:::::::!::=::::::·,!:::!:!:::':::'I:\::I::.:.:!!:.: .. :.:::::: .• : •• !:.::::::.]
7 I i:::.::::i:.:::·''):;:::::.::'::i:::::i:::::::::·:::::::::: ::::?:ff.?::ftt:·::::::::::::f:::D::::ul.
8~1 ______________ ~
9~1 ______________ ~
10~1 ________________ ~
11 ~I ________________ ~
12 ~I ________________ ~
13~1 ________________ ~
14 '-' _________ ~
15
16
17 I~ _________ ......
18 '-I ________________ ~
191 ~ _______________ .....
20 ~I _______________ .....
211 ~ ______________ .....
I I
10 Basic Processor
Index
Registers
o Indirect Access Flag
o
III II II I Operation Code Field
1 7
[]]]J General Register Designator
8 11
ITO Index Register Designator
12 14
Reference Address Field
IIII1111111111111111
15 31
....... -- .....
Memory
•
Reserved
I/O Processors I
• r
I
Read/Write Direct
• r
•
Interrupts
tv\apping
• r
• Access Protecti on •
PROGRAM STATUS WORDS
[[OJ Condition Code
o 3
ITO Floating-point Mode Control
5 7
o Master/Slave Mode Control
8
oMemory Map Control
9
OJ Arithmetic Trap Masks
1011
Instruction
Id IIII I II III II IIII !ddress
15 31 Extended
om Write Key
32 35
[[IJ Interrupt Inhibits
37 39
OJ Register Block Pointer
5859
oRegister Altered
60
o Mode Altered Control
61
Displacement
Figure 2. The Basic Processor

avai lable to a program. The register block pointer can be
changed when the basic processor is in the master mode or
the master-protected mode. Only the first 16 general reg-
isters of a register block may be used by programs; the last
eight are reserved.
Each
of the first 16 general registers in a register block is
identifi ed by a 4-bi t code in the range 0000
2 through 11112
{O through 15 in decimal notation, or X'O' through X'F' in
hexadecimal notation}. Any or" these 16 registers can be
used as a
fixed-point temporary data storage location, or
to contain control information such as a data address, .count,
pointer, etc. General registers 1 through 7 can be used
as
index registers.
MEMORY CONTROL STORAGE
The memory control storage for the memory map and the
associated memory access protection codes are contained
in the Memory Interface (MI). Memory control storage for
the 4-bit write locks are contained in the memory units.
Memory control
storage can be modified when the basic
processor is in the master mode or the master-protected
mode.
MEMORY MAP
Two terms are essential in understanding the memory map-
ping concept: actual (i. e., absolute or real) address and
'!h·t~d 0dd!"ess.
An actual address is used within the memory unit (memory
address registers) to
access a specific, physical memory lo-
cation for storage or retrieval of information as required by
the execution sequence of an instruction. Actual addresses
are fixed and are dependent on the wired-in hardware.
A virtual address refers to a logical location as required by
an individual program. Like an actual address, a virtual
address may designate a location that contains a program
instruction, an
element of data, a data address (indirect
address), or it may also be an explicit quantity. Normally,
virtual addresses are derived from programmer-supplied
labels through an assembly (or compi lation) process followed
by a loading process. Virtual addresses
m~y also be com-
puted during a program's execution. Virtual addresses in-
clude all instruction addresses, indirect addresses, and
addresses used as counts within a stored program, as well as
those instructions computed by
the program. (See "Virtual
and Real Memory", later in this chapter.)
Memory mapping transforms virtual addresses as seen by the
individual program into actual addresses as seen by the
memory system. Thus, when the memory map is in effect,
any program can be broken into 512-word pages and dy-
namically relocated throughout memory in whatever pages
of space are avai lable.
When the memory map is not in effect, all virtual address
values above 1510 are used by the memory as actual ad-
dresses. Virtual addresses 0 through 15 are alwayst used by
the basic processor as general register addresses rather than
as memory
addresses. For example, if an instruction uses
virtual address 5 to address the location where a result is
to
be stored, the basic processor stores that result in gen-
eral register 5 in the current register block instead of in
memory
location 5.
When the basic processor is operating with the memory map
in
effect, virtual addresses 0 through 15 are still used as
general register addresses. Virtual addresses above 15 are
transformed into actual addresses by replacing the high-
order portion of the virtual address with a value obtained
from the memory map. (The memory map address replace-
ment process is described in "Memory Address Control ",
later in this chapter.)
MEMORY ACCESS PROTECTION
When the basic processor is operating with the memory map
in
the slave mode or the master-protected mode, the access
protection codes determine whether the program may access
instructions from, read from, or write into specific regions
of the virtual address continuum (virtual memory). If the
slave mode or master-protected f}1ode program attempts to
access a protected region of virtuaI memory, a trap occurs
(see "Memory Address Control ", "Virtual and Real Mem-
ory", and "Trap System", later in this chapter).
MEMORY WRITE PROTECTION
The memory write-protection feature operates independently
of access protection and the memory map. The 4-bit write
lock operates in conjunction with a 4-bit field, called the
write key, in bits 32-35 of the Program Status Words (PSWs).
The lock and the key de termine whether any program may
alter any word of main memory. The write key can be
changed when the basic processor is in the master mode or
the master-protected mode. (The functions of the write
lock and key are described in "Memory Address Control ",
later in this chapter.)
COMPUTER MODES
The basic processor operates in one of three modes: master,
master-protected, or slave. The operation mode is deter-
mined by the setting of three bits (bits 8, 9, and 61) of the
Program Status Words (PSWs). (See "Program Status Words",
later in this chapter.) Additionally, the basic processor
operates in a mapped mode or an unmapped mode.
tExcept for
the READ DIRECT (RD)/WRITE DIRECT 0/VD) in-
structions which can read from and store into these locations.
Basi c Processor 11

MASTER MODE
The master/slave control bit (bit 8 of the PSWs) must con-
tain a zero for the basic processor to operate in master
mode. In this mode the basic processor can perform all of
its control functions and can modify any part of the system.
The restrictions upon
the basic processor1s operations in this
mode
are those imposed by the write locks on certain pro-
tected parts of memory. It is assumed that there is a res-
ident operating system (operating in the master mode) that
con tro Is and supports the opera ti on of other programs (wh i ch
may be in the master, master-protected, or slave mode).
MASTER-PROTECTED MODE
The master-protected mode of operation provides additional
protection for programs that operate in the master mode. The
master-protected mode occurs when the basic processor is
operating in the master mode with the memory map in effect
and the mode altered control bit (bit 61 of the PSWs)is on.
In this mode the memory protection violation trap occurs
(location X 140
1
, with
CC4 = 1), as it does in all mapped
slave programs, if a program makes a reference to a virtual
page to which access is prohibited by the current setti ng of
the access protection codes.
SLAVE MODE
The slave mode of operation is the problem-solving mode
of the basic processor. In this mode, access protection
codes apply to the slave mode program if mapping is in ef-
fect, and all "privi leged" operations are prohibited. Priv-
ileged operations are those relating to input/output and to
changes in the fundamental control state of the basic pro-
cessor. All privi leged operations are performed in the
master or master-protected mode by a group of privileged
instructions. Any attempt by a program to execute a priv-
i leged instruction whi Ie the basic processor is in the slave
mode results in a trap. The master/sla·:e mode control bit
(bit 8 of the PSWs) can be changed when the basic processor
is in the master or master-protected mode. Nevertheless,
a slave mode program can gain direct access to certain ex-
ecutive program operations by means of CAll instructions.
The operations available through CAll instructions are es-
tablished by the resident operating system.
MAPPED MODE
Although the memory map is located in the Memory Inter-
face (MI), it functions as part of the basic processor. The
basic processor communicates with memory through the MI.
Mapping is effective for all the words of real memory, and
is invoked when bit 9 (MM) of the PSWs contains a one.
Memory mopping generates rea! page addresses from v:rtuc!
addresses. The memory map can be loaded with either
11-bit real page addresses or 8-bit real page addresses by
means
of the MOVE MEMORY CONTROL (MMC) privi leged
instruction (see Chapter 3, "Control Instructions "). Eleven-
bit rea I page addresses are always provided for in the map,
thus
if 8-bit real page addresses are generated, the three
12 Basic Processor
high-order bits contain zeros. The memory map always maps
17-bit virtual addresses into 20-bit real addresses (see
"Memory Address
Control ", later in this chapter for a dis-
cussion of how the map is used).
UNMAPPED MODE
When the basic processor is operating in the unmapped mode,
there is a direct one-to-one relationship between the effec-
tive virtual address of each instruction and the actual ad-
dress used to access main memory. (See "Real Addressing",
later in this chapter.)
INFORMATION FORMAT
Nomenclature associated with digital information within the
computer system is based on functional and/or physical at-
tributes. A "word" may be either a 32-bit instruction word
or a
32-bit data word.
The bit positions of a word are numbered from 0 through 31
as follows:
A word
can be divided into two 16-bit parts (halfwords) in
which the bit positions are numbered from 0 through 15 as
follows:
A word
can also be divided into four 8-bit parts (bytes) in
which the bit positions are numbered 0 through 7 as follows:
Two words can be combined to form a 64-bit element (a
doubleword) in
which the bit positions are numbered 0
through 63 as follows:
In fixed-point binary arithmetic each element of information
represents numerical data as a signed integer (bil 0 repre-
sents the sign, remaining bits represent the magnitude, and
the binary point is assumed to be just to the right of the
least significant or rightmost bit). Negative values are
represented in two1s complement form. Other formats re-
quired for floating-point and decimal instructions are de-
scribed in Chapter 3.

INFORMATION BOUNDARIES
Basic processor instructions assume that bytes, halfwords,
and doublewords are located in main memory according to
the following boundary conventions:
1. A byte is located in bit positions 0 through 7, 8
through 15,
16 through 23, and 24 through 31 of a
word.
Doubleword
Word (even address) Word (odd address)
Halfword 0 Halfword 1 Halfword 0 Halfword 1
Byte 0 IByte 1 Byte 21Byte 3 Byte 0IByte 1 Byte 21Byte 3
2. A halfword is located in bit positions 0 through 15 and
16 through 31 of a word.
3. Adoubleword is located such that bit positions 0 through
31 are contained within an even-numbered word, and
bit positions 32 through 63 are contained within the
next consecutive word (which is odd-numbered).
Figure 3 illustrates these boundaries.
Doubleword
Word (even address) Word (odd address)
Halfword 0 Halfword 1 Halfword 0 Halfword 1
Byte 0 IByte 1 Byte
21Byte 3 Byte 0IByte 1 Byte
21 Byte 3
Figure
3. Information Boundaries
INSTRUCTION REGISTER
processor is currently executing. The format and fields of
the two general types of instructions (memory reference and
immediate operand) are described below. Specific formats
for
each instruction are given in Chapter 3.
MEMORY REFERENCE INSTRUCTIONS
Instructions that make reference to an operand in main mem-
ory may
have the following format:
Bits
o
1-7
8-11
Description
Indirect
addressing. One level of indirect ad-
dressing is performed only if this bit position con-
tains a one.
Operation code. This 7-bit field contains the code
that designates the operation to be performed. See
the inside front and back covers for complete list-
ings of operation codes.
R field. For most instructions this 4-bit field des-
ignates one of the first 16 general registers of the
Bits
8-11
(cont. )
12-14
Description
current register block as an operand source, result
destination, or both.
X field. This 3-bit field designates one of general
registers 1-7 of the current register block as an
index register. If X contains zero, indexing wi II
not be performed; hence register 0 cannot be used
as
an index register. (See "Address Modification
Example: Indexing (Real and Virtual Addressing)",
later in this chapter for a description of the
indexing process. )
15-31 Reference address. This
17-bit field normally con-
tains the reference address of the instruction oper-
and. The reference address is translated into an
effective virtual address in accordance with the
addressing type
(real, real extended, or virtua I)
and the address modification requied (direct/
indirect or indexing). (See "Memory Reference
Addresses"
later in this chapter. )
IMMEDIATE OPERAND INSTRUCTIONS
Immediate operand type instructions are particularly effi-
cient because the required operand is contained within the
Bas ic Processor 13