Xilinx 7 Series User manual

7 Series FPGAs
Configurable Logic Block
User Guide
UG474 (v1.8) September 27, 2016

7 Series FPGAs CLB User Guide www.xilinx.com UG474 (v1.8) September 27, 2016
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Revision History
The following table shows the revision history for this document.
Date Version Revision
03/01/2011 1.0 Xilinx Initial release.
03/28/2011 1.1 Added devices XC7K355T, XC7K420T, and XC7K480T to Table 1-3. Portions of the text
have been revised for clarity.
09/30/2011 1.2 Added last sentence under 7 Series CLB Features. Added Table 1-3 and Table 1-4.
Updated CLB features in Table 1-3. Added first sentence under CLB Arrangement,
added ASMBL Architecture section, and CLB Slices heading. Added last paragraph
under Carry Logic. Added lasts sentence under Using Carry Logic. Added second
sentence under Slice Multiplexer Timing Parameters. Modified Table 5-2, Table 5-4, and
Table 5-5 for clarity. Added Devices Using Stacked Silicon Interconnect (SSI) Technology
section.
01/30/2012 1.3 Revised Table 1-2. Added fifth paragraph under Distributed RAM (Available in SLICEM
Only). Clarified last paragraph under Global Controls GSR and GTS.
11/05/2012 1.4 Changed “uniformity” to “optimized” in last bullet under 7 Series CLB Features.
Changed “unified” to “scalable” in first sentence under Device Resources. Deleted
7A350T device from Table 1-2. Deleted 7V1500T and 7VH290T devices from Table 1-4.
Added reference to 7 Series FPGA Libraries Guide to Distributed RAM (Available in
SLICEM Only), Shift Registers (Available in SLICEM Only), and Flip-Flop Primitives.
Changed “TCEO” to “TCECK” in Figure 5-2 and first bullet under General Timing
Characteristics.

UG474 (v1.8) September 27, 2016 www.xilinx.com 7 Series FPGAs CLB User Guide
08/6/2013 1.5 Added Artix®-7 devices. Updated references to implementation tools.
08/11/2014 1.6 Revised footnotes in Table 1-2 through Table 1-4. Revised polarity from independent to
programmable in Control Signals, page 22. Added Primitive column to Table 2-3 and
removed footnotes. Renamed or made minor revisions to Figure 2-6 through Figure 2-14.
Revised sections Clock – WCLK, page 49, Clock – CLK, page 50, and Clock - C, page 51.
11/17/2014 1.7 Updated Table 1-2 for new Artix 7A15T device.
09/27/2016 1.8 Added Spartan®-7 device family (updated Preface and added Table 1-1). Added
Artix®-7 7A12T and 7A25T devices to Table 1-2.
Date Version Revision

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Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Preface: About This Guide
Guide Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Additional Support Resources. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Chapter 1: Overview
CLB Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
7 Series CLB Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Device Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Recommended Design Flow. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Pinout Planning. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Chapter 2: Functional Details
CLB Arrangement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Slice Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Look-Up Table (LUT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Storage Elements. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Distributed RAM (Available in SLICEM Only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Shift Registers (Available in SLICEM Only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Multiplexers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Carry Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Chapter 3: Design Entry
Design Checklist . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Using the CLB Resources. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Primitives. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Chapter 4: Applications
Distributed RAM Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Shift Register Applications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Carry Logic Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Chapter 5: Timing
CLB General Slice Timing Model and Parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
CLB Slice Multiplexer Timing Model and Parameters. . . . . . . . . . . . . . . . . . . . . . . . 60
CLB Slice Carry-Chain Timing Model and Parameters . . . . . . . . . . . . . . . . . . . . . . . 61
Table of Contents
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CLB Slice Distributed RAM Timing Model and Parameters (Available in SLICEM Only)
63
CLB Slice SRL Shift Register Timing Model and Parameters (Available in SLICEM
Only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Chapter 6: Advanced Topics
Using the Latch Function as Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Interconnect Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Devices Using Stacked Silicon Interconnect (SSI) Technology . . . . . . . . . . . . . . . 73
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Preface
About This Guide
Xilinx® 7 series FPGAs include four FPGA families that are all designed for lowest power
to enable a common design to scale across families for optimal power, performance, and
cost. The Spartan®-7 family is the lowest density with the lowest cost entry point into the
7 series portfolio. The Artix®-7 family is optimized for highest performance-per-watt and
bandwidth-per-watt for cost-sensitive, high-volume applications. The Kintex®-7 family is
an innovative class of FPGAs optimized for the best price-performance. The Virtex®-7
family is optimized for highest system performance and capacity. This guide serves as a
technical reference describing the 7 series FPGAs configurable logic blocks (CLBs).
Usually, logic synthesis assigns the CLB resources without system designer intervention. It
can be advantageous for the designer to understand certain CLB details, including the
varying capabilities of the look-up tables (LUTs), the physical direction of the carry
propagation, the number and distribution of the available flip-flops, and the availability of
the very efficient shift registers. This guide describes these and other features of the CLB in
detail.
This 7 Series FPGAs Configurable Logic Block User Guide, part of an overall set of
documentation on the 7 series FPGAs, is available on the xilinx.com/documentation.
Guide Contents
This manual contains these chapters:
•Chapter 1, Overview, provides basic information needed for the majority of users,
including:
•CLB Overview is targeted at the new user.
•7 Series CLB Features discusses what is new compared with the Spartan®-6 and
Virtex®-6 FPGA families for the experienced user and provides design migration
considerations.
•Device Resources indicates the number of resources per device, and unity
between different 7 series families.
•Recommended Design Flow provides the basics of using CLB resources and lists
key aspects to consider.
•Pinout Planning discusses aspects of CLBs that might affect pin placement for a
design.
•Chapter 2, Functional Details, lists architectural specifics for each CLB feature.
•Chapter 3, Design Entry, provides design entry guidelines and primitives for
instantiation.
•Chapter 4, Applications, provides examples that use the CLB resources in larger
applications.
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Preface: About This Guide
•Chapter 5, Timing, contains timing models and defines CLB timing specifications
from the respective 7 series FPGA data sheet.
•Chapter 6, Advanced Topics, discusses advanced features of the 7 series CLB.
Additional Support Resources
To find additional documentation, see the Xilinx website at:
http://www.xilinx.com/support.html#documentation
To search the Answer Database of silicon, software, and IP questions and answers, or to
create a technical support WebCase, see the Xilinx website at:
www.xilinx.com/support
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Chapter 1
Overview
CLB Overview
The 7 series configurable logic block (CLB) provides advanced, high-performance FPGA
logic:
• Real 6-input look-up table (LUT) technology
• Dual LUT5 (5-input LUT) option
• Distributed Memory and Shift Register Logic capability
• Dedicated high-speed carry logic for arithmetic functions
• Wide multiplexers for efficient utilization
CLBs are the main logic resources for implementing sequential as well as combinatorial
circuits. Each CLB element is connected to a switch matrix for access to the general routing
matrix (shown in Figure 1-1). A CLB element contains a pair of slices.
The LUTs in 7 series FPGAs can be configured as either a 6-input LUT with one output, or
as two 5-input LUTs with separate outputs but common addresses or logic inputs. Each
5-input LUT output can optionally be registered in a flip-flop. Four such 6-input LUTs and
their eight flip-flops as well as multiplexers and arithmetic carry logic form a slice, and two
slices form a CLB. Four flip-flops per slice (one per LUT) can optionally be configured as
latches. In that case, the remaining four flip-flops in that slice must remain unused.
X-Ref Target - Figure 1- 1
Figure 1-1: Arrangement of Slices within the CLB
Switch
Matrix
Slice(1)
COUTCOUT
CINCIN
Slice(0)
CLB
UG474_c1_01_071910
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Chapter 1: Overview
Approximately two-thirds of the slices are SLICEL logic slices and the rest are SLICEM,
which can also use their LUTs as distributed 64-bit RAM or as 32-bit shift registers (SRL32)
or as two SRL16s. Modern synthesis tools take advantage of these highly efficient logic,
arithmetic, and memory features. Expert designers can also instantiate them.
7 Series CLB Features
The 7 series CLB is identical to that in the Virtex®-6 FPGA family. The CLB is very similar
to that of the Spartan®-6 FPGA family with these differences:
• Columnar architecture
• Scales easily to higher densities
• More routing between CLBs
• SLICEL and SLICEM only (no Spartan-6 FPGA SLICEX)
• All slices support carry logic
• More optimized
The common features in the CLB structure simplify design migration from the Spartan-6
and Virtex-6 families to the 7 series devices. The unique floorplan means that location
constraints should be removed before implementing designs originally targeted to earlier
FPGAs. The interconnect routing resources are increased in size, quantity, and flexibility
relative to the Virtex-6 FPGA family, improving the quality of automatic place and route
results.
Device Resources
The CLB resources are scalable across all the 7 series families, providing a common
architecture that improves efficiency, IP implementation, and design migration. The
number of CLBs and the ratio between CLBs and other device resources differentiates the
7 series families. Migration between the 7 series families does not require any design
changes for the CLBs.
Device capacity is often measured in terms of logic cells, which are the logical equivalent of
a classic four-input LUT and a flip-flop. The 7 series FPGA CLB six-input LUT, abundant
flip-flops and latches, carry logic, and the ability to create distributed RAM or shift
registers in the SLICEM, increase the effective capacity. The ratio between the number of
logic cells and 6-input LUTs is 1.6:1.
7 Series FPGA CLB Resources
Table 1-1 through Table 1-4 show the available CLB resources for the Spartan®-7, Artix®-7,
Kintex®-7, and Virtex®-7 FPGAs. Refer to DS180, 7 Series FPGAs Overview for the most
up-to-date information.
Table 1-1: Spartan-7 FPGA CLB Resources
Device Slices(1) SLICEL SLICEM 6-input
LUTs
Distributed RAM
(Kb)
Shift
Register
(Kb)
Flip-Flops
7S6 938(2) 658 280 3,752 70 35 7,504
7S15 2,000 1,400 600 8,000 150 75 16,000
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Device Resources
7S25 3,650 2,400 1,250 14,600 313 157 29,200
7S50 8,150 5,750 2,400 32,600 600 300 65,200
7S75 12,000(2) 8,672 3,328 48,000 832 416 96,000
7S100 16,000 11,600 4,400 64,000 1,100 555 128,000
Notes:
1. Each 7 series FPGA slice contains four LUTs and eight flip-flops; only SLICEMs can use their LUTs as distributed RAM or SRLs.
2. Number of slices corresponding to the number of LUTs and flip-flops supported in the device.
Table 1-1: Spartan-7 FPGA CLB Resources (Cont’d)
Device Slices(1) SLICEL SLICEM 6-input
LUTs
Distributed RAM
(Kb)
Shift
Register
(Kb)
Flip-Flops
Table 1-2: Artix-7 FPGA CLB Resources
Device Slices(1) SLICEL SLICEM 6-input
LUTs
Distributed RAM
(Kb)
Shift
Register
(Kb)
Flip-Flops
7A12T 2,000(2) 1,316 684 8,000 171 86 16,000
7A15T 2,600(2) 1,800 800 10,400 200 100 20,800
7A25T 3,650 2,400 1,250 14,600 313 156 29,200
7A35T 5,200(2) 3,600 1,600 20,800 400 200 41,600
7A50T 8,150 5,750 2,400 32,600 600 300 65,200
7A75T 11,800(2) 8,232 3,568 47,200 892 446 94,400
7A100T 15,850 11,100 4,750 63,400 1,188 594 126,800
7A200T 33,650 22,100 11,550 134,600 2,888 1,444 269,200
Notes:
1. Each 7 series FPGA slice contains four LUTs and eight flip-flops; only SLICEMs can use their LUTs as distributed RAM or SRLs.
2. Number of slices corresponding to the number of LUTs and flip-flops supported in the device.
Table 1-3: Kintex-7 FPGA CLB Resources
Device Slices(1) SLICEL SLICEM 6-input
LUTs
Distributed RAM
(Kb)
Shift
Register
(Kb)
Flip-Flops
7K70T 10,250 6,900 3,350 41,000 838 419 82,000
7K160T 25,350 16,600 8,750 101,400 2,188 1,094 202,800
7K325T 50,950 34,950 16,000 203,800 4,000 2,000 407,600
7K355T 55,650 35,300 20,350 222,600 5,088 2,544 445,200
7K410T 63,550 40,900 22,650 254,200 5,663 2,831 508,400
7K420T 65,150(2) 41,400 23,750 260,600 5,938 2,969 521,200
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Chapter 1: Overview
Recommended Design Flow
CLB resources are inferred for generic design logic and do not require instantiation. Good
HDL design is sufficient. A few items to note:
• CLB flip-flops have either a set or a reset. The designer must not use both set and
reset.
• Flip-flops are abundant. Pipelining should be considered to improve performance.
• Control inputs are shared across a slice or CLB. The number of unique control inputs
required for a design should be minimized. Control inputs include clock, clock enable,
set/reset, and write enable.
• A 6-input LUT can be used as a 32-bit shift register for efficient implementation.
• A 6-input LUT can be used as a 64 x 1 memory for small storage requirements.
• Dedicated carry logic implements arithmetic functions effectively.
These steps indicate the recommended design flow:
7K480T 74,650 47,500 27,150 298,600 6,788 3,394 597,200
Notes:
1. Each 7 series FPGA slice contains four LUTs and eight flip-flops; only SLICEMs can use their LUTs as distributed RAM or SRLs.
2. Number of slices corresponding to the number of LUTs and flip-flops supported in the device.
Table 1-3: Kintex-7 FPGA CLB Resources (Cont’d)
Device Slices(1) SLICEL SLICEM 6-input
LUTs
Distributed RAM
(Kb)
Shift
Register
(Kb)
Flip-Flops
Table 1-4: Virtex-7 FPGA CLB Resources
Device Slices(1) SLICEL SLICEM 6-input
LUTs
Distributed RAM
(Kb)
Shift
Register
(Kb)
Flip-Flops
7V585T 91,050 63,300 27,750 364,200 6,938 3,469 728,400
7V2000T 305,400 219,200 86,200 1,221,600 21,550 10,775 2,443,200
7VX330T 51,000 33,450 17,550 204,000 4,388 2,194 408,000
7VX415T 64,400 38,300 26,100 257,600 6,525 3,263 515,200
7VX485T 75,900 43,200 32,700 303,600 8,175 4,088 607,200
7VX550T 86,600(2) 51,700 34,900 346,400 8,725 4,363 692,800
7VX690T 108,300 64,750 43,550 433,200 10,888 5,444 866,400
7VX980T 153,000 97,650 55,350 612,000 13,838 6,919 1,224,000
7VX1140T 178,000 107,200 70,800 712,000 17,700 8,850 1,424,000
7VH580T 90,700 55,300 35,400 362,800 8,850 4,425 725,600
7VH870T 136,900 83,750 53,150 547,600 13,275 6,638 1,095,200
Notes:
1. Each 7 series FPGA slice contains four LUTs and eight flip-flops; only SLICEMs can use their LUTs as distributed RAM or SRLs.
2. Number of slices corresponding to the number of LUTs and flip-flops supported in the device.
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Pinout Planning
1. Implement the design using preferred methodologies (HDL, IP, etc.).
2. Evaluate utilization reports to determine resources used.
Check to make sure arithmetic logic, distributed RAM, and SRL are used, when
helpful.
3. Consider flip-flop usage.
a. Pipeline for performance
b. Use dedicated flip-flops at the outputs of dedicated resources (block RAM, DSP)
c. Allow shift registers to use SRL (avoid set/resets)
4. Minimize the use of set/resets.
Pinout Planning
Although the use of most resources affects the resulting device pinout, CLB usage has little
effect on pinouts because they are distributed throughout the device. The ASMBL™
architecture provides maximum flexibility with CLBs on both sides of most I/Os.
The best approach is to let the tools choose the I/O locations based on the FPGA
requirements. Results can be adjusted if necessary for board layout considerations. The
timing constraints should be set so that the tools can choose optimal placement for the
design requirements.
Carry logic cascades vertically up a column, so wide arithmetic buses might drive a
vertical orientation to other logic, including I/O.
While most 7 series devices are available in flip-chip packages, taking full advantage of the
distributed I/O in the ASMBL architecture, the smaller devices are available in wire-bond
packages at a lower cost. In these packages, some pins are naturally closer to the I/Os and
special resources than others, so pin placement should be done after the internal logic is
defined.
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Chapter 1: Overview
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Chapter 2
Functional Details
This chapter provides a detailed view of the 7 series FPGAs CLB architecture. These details
can be useful for design optimization and verification, but are not necessary for initiating
a design. This chapter includes:
•CLB Arrangement
Overview of slice locations and features within the CLB
•Slice Description
Complete details of SLICEM and SLICEL
•Look-Up Table (LUT)
Description of the logical function generators
•Storage Elements
Description and controls for the latches and flip-flops
•Distributed RAM (Available in SLICEM Only)
SLICEM ability to use LUTs as writable memory
•Shift Registers (Available in SLICEM Only)
SLICEM ability to use LUTs as shift registers
•Multiplexers
Dedicated gates for combining LUTs into wide functions
•Carry Logic
Dedicated gates and cascading to implement efficient arithmetic functions
CLB Arrangement
The CLBs are arranged in columns in the 7 series FPGAs. The 7 series is the fourth
generation to be based on the unique columnar approach provided by the ASMBL™
architecture.
ASMBL Architecture
Xilinx created the Advanced Silicon Modular Block (ASMBL) architecture to enable FPGA
platforms with varying feature mixes optimized for different application domains.
Through this innovation Xilinx offers a greater selection of devices, enabling customers to
select the FPGA with the right mix of features and capabilities for their specific design.
Figure 2-1 provides a high-level description of the different types of column-based
resources.
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Chapter 2: Functional Details
The ASMBL architecture breaks through traditional design barriers by:
• Eliminating geometric layout constraints such as dependencies between I/O count
and array size.
• Enhancing on-chip power and ground distribution by allowing power and ground to
be placed anywhere on the chip.
• Allowing disparate integrated IP blocks to be scaled independent of each other and
surrounding resources.
SSI Technology
The 7 series FPGAs extend integration even higher by using the unique stacked silicon
interconnect (SSI) technology. SSI technology enables multiple super logic regions (SLRs)
to be combined on a passive interposer layer, to create a single FPGA with more than ten
thousand inter-SLR connections. See Chapter 6, Advanced Topics for additional
information.
CLB Slices
A CLB element contains a pair of slices, and each slice is composed of four 6-input LUTs
and eight storage elements.
• SLICE(0) – slice at the bottom of the CLB and in the left column
• SLICE(1) – slice at the top of the CLB and in the right column
These two slices do not have direct connections to each other, and each slice is organized as
a column. Each slice in a column has an independent carry chain.
X-Ref Target - Figure 2-1
Figure 2-1: ASMBL Architecture
Column
Based
ASMBL
Architecture
Feature Options
Domain A Domain B Domain C
UG474_c2_24_071014
ApplicationsApplicationsApplications
Logic (SLICEL)
Logic (SLICEM)
DSP
Memory
Clock Management Tile
Global Clock
High-performance I/O
High-range I/O
Integrated IP
Mixed Signal
Transceivers
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7 Series FPGAs CLB User Guide www.xilinx.com 17
UG474 (v1.8) September 27, 2016
CLB Arrangement
The Xilinx tools designate slices with these definitions:
• An “X” followed by a number identifies the position of each slice in a pair as well as
the column position of the slice. The “X” number counts slices starting from the
bottom in sequence 0, 1 (the first CLB column); 2, 3 (the second CLB column); etc.
• A “Y” followed by a number identifies a row of slices. The number remains the same
within a CLB, but counts up in sequence from one CLB row to the next CLB row,
starting from the bottom.
Figure 2-2 shows four CLBs located in the bottom-left corner of the die.
CLB/Slice Configurations
Table 2-1 summarizes the logic resources in one CLB. Each SLICEM LUT can be configured
as a look-up table, distributed RAM, or a shift register.
X-Ref Target - Figure 2- 2
Figure 2-2: Row and Column Relationship between CLBs and Slices
Slice1
X1Y1
COUTCOUT
CINCIN
Slice0
X0Y1
CLB
UG474_c2_01_092210
Slice1
X1Y0
COUTCOUT
Slice0
X0Y0
CLB
Slice1
X3Y1
COUTCOUT
CINCIN
Slice0
X2Y1
CLB
Slice1
X3Y0
COUTCOUT
Slice0
X2Y0
CLB
Table 2-1: Logic Resources in One CLB
Slices LUTs Flip-Flops Arithmetic and
Carry Chains Distributed RAM(1) Shift Registers(1)
2 8 16 2 256 bits 128 bits
Notes:
1. SLICEM only, SLICEL does not have distributed RAM or shift registers.
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18 www.xilinx.com 7 Series FPGAs CLB User Guide
UG474 (v1.8) September 27, 2016
Chapter 2: Functional Details
Slice Description
Every slice contains:
• Four logic-function generators (or look-up tables)
• Eight storage elements
• Wide-function multiplexers
• Carry logic
These elements are used by all slices to provide logic, arithmetic, and ROM functions. In
addition, some slices support two additional functions: storing data using distributed
RAM and shifting data with 32-bit registers. Slices that support these additional functions
are called SLICEM; others are called SLICEL. SLICEM (shown in Figure 2-3) represents a
superset of elements and connections found in all slices. SLICEL is shown in Figure 2-4.
Each CLB can contain two SLICEL or a SLICEL and a SLICEM.
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7 Series FPGAs CLB User Guide www.xilinx.com 19
UG474 (v1.8) September 27, 2016
Slice Description
X-Ref Target - Figure 2-3
Figure 2-3: Diagram of SLICEM
A6:A1
D
COUT
D
DX
C
CX
B
BX
A
AX
O6
DI2
O5
DI1
MC31WEN
CK
DI1
MC31WEN
CK
DI1
MC31WEN
CK
DI1
MC31WEN
CK
UG474_c2_02_110510
DX DMUX
D
DQ
C
CQ
CMUX
B
BQ
BMUX
A
AQ
AMUX
Reset Type
D
FF/LAT
INIT1
INIT0
SRHI
SRLO
SR
CE
CK
FF/LAT
INIT1
INIT0
SRHI
SRLO
FF/LAT
INIT1
INIT0
SRHI
SRLO
FF/LAT
INIT1
INIT0
SRHI
SRLO
D
SR
CE
CK
D
SR
CE
CK
D
SR
Q
CE
CK
CIN
0/1
WEN
WE
CK
Sync/Async
FF/LAT
A6:A1
O6
O5
C6:1
CX
D6:1
DI
A6:A1
O6
O5
B6:1
BX
A6:A1
W6:W1
W6:W1
W6:W1
W6:W1
O6
O5
A6:1
AX
SR
CE
CLK
CE Q
CK SR
Q
Q
Q
SRHI
SRLO
INIT1
INIT0
D
CE Q
CK SR
SRHI
SRLO
INIT1
INIT0
D
CE Q
CK SR
SRHI
SRLO
INIT1
INIT0
D
CE Q
CK SR
SRHI
SRLO
INIT1
INIT0
DI2
DI2
DI2
CI
BI
AI
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20 www.xilinx.com 7 Series FPGAs CLB User Guide
UG474 (v1.8) September 27, 2016
Chapter 2: Functional Details
X-Ref Target - Figure 2-4
Figure 2-4: Diagram of SLICEL
A6:A1
D
COUT
D
DX
C
CX
B
BX
A
AX
O6
O5
UG474_c2_03_101210
DX DMUX
D
DQ
C
CQ
CMUX
B
BQ
BMUX
A
AQ
AMUX
Reset Type
D
FF/LAT
INIT1
INIT0
SRHI
SRLO
SR
CE
CK
FF/LAT
INIT1
INIT0
SRHI
SRLO
FF/LAT
INIT1
INIT0
SRHI
SRLO
FF/LAT
INIT1
INIT0
SRHI
SRLO
D
SR
CE
CK
D
SR
CE
CK
D
SR
Q
CE
CK
CIN
0/1
Sync/Async
FF/LAT
A6:A1
O6
O5
C6:1
CX
D6:1
A6:A1
O6
O5
B6:1
BX
A6:A1
O6
O5
A6:1
AX
SR
CE
CLK
CE Q
CK SR
Q
Q
Q
SRHI
SRLO
INIT1
INIT0
D
CE Q
CK SR
SRHI
SRLO
INIT1
INIT0
D
CE Q
CK SR
SRHI
SRLO
INIT1
INIT0
D
CE Q
CK SR
SRHI
SRLO
INIT1
INIT0
Send Feedback