Xilinx ML605 Operation instructions

AXI Interface Based
ML605/SP605 MicroBlaze
Processor Subsystem
Hardware Tutorial
UG669 (v3.0) March 15, 2011

ML605/SP605 Hardware Tutorial www.xilinx.com UG669 (v3.0) March 15, 2011
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Revision History
The following table shows the revision history for this document.
Date Version Revision
10/05/10 1.0 Initial Xilinx release.
12/21/10 2.0 Tutorial procedures have been updated in accordance with ISE® Design Suite:
Embedded Edition, version 12.4.
03/15/11 3.0 Tutorial procedures have been updated in accordance with ISE Design Suite: Embedded
Edition, version 13.1.

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Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Hardware and Software Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Prerequisites . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
System Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Included Files and Systems. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Executing the System. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
System Design Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Hardware Platform Creation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Opening the Project . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Examining the System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Generating the Hardware Platform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Exporting the Base Hardware Platform to SDK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Downloading and Verifying the Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Customizing the Embedded Hardware Platform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Adding IP from the Xilinx IP Catalog. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Adding the Perf_AXI core. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Connecting the Bus Interfaces. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Connecting Ports. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Implementing and Downloading the Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Testing the Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Next Steps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Table of Contents

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UG669 (v3.0) March 15, 2011
AXI Interface Based ML605/SP605
MicroBlaze Processor Subsystem
Hardware Tutorial
Introduction
This tutorial provides the steps required to build and modify the Xilinx® ML605
MicroBlaze™ Processor Subsystem or the Xilinx SP605 MicroBlaze Processor Subsystem.
The tutorial starts with steps in building the basic subsystem. The basic subsystem is then
modified by adding the cores necessary to measure throughput on AXI Central DMA
(AXI_CDMA).
Additional information can be found in UG683, EDK Concepts, Tools, and Techniques.
Readers are encouraged to refer to UG683 during the execution of this tutorial. [Ref 1]
Users should allow approximately three hours to complete this entire tutorial.
Hardware and Software Requirements
The hardware and software requirements to run the basic tutorial are:
• Xilinx ML605 evaluation board or Xilinx SP605 evaluation board
• Two USB Type-A to Mini-B 5-pin cables
• Ethernet cable (straight-through)
• Serial communications utility program (e.g., Windows HyperTerminal or Tera Term)
• ISE® Design Suite: Embedded Edition 13.1 which includes:
• Integrated Software Environment (ISE)
• Embedded Development Kit (EDK
• Software Development Kit (SDK)

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Prerequisites
Prerequisites
Prerequisites required to run the basic tutorial are:
• ML605 MicroBlaze Processor Subsystem:
• Proper hardware setup and software installation, as described in UG668, Getting
Started with the Virtex-6 FPGA ML605 Embedded Kit [Ref 2]
• Familiarity with the ML605 MicroBlaze Processor Subsystem, documented in
DS668, AXI Interface Based ML605 Embedded Kit MicroBlaze Processor Subsystem
Data Sheet [Ref 3]
• SP605 MicroBlaze Processor Subsystem:
• Proper hardware setup and software installation, as described in UG667, Getting
Started with the Spartan-6 FPGA SP605 Embedded Kit [Ref 4]
• Familiarity with the SP605 MicroBlaze Processor Subsystem, documented in
DS667, AXI Interface Based SP605 Embedded Kit MicroBlaze Processor Subsystem Data
Sheet [Ref 5]
• Familiarity with UG683, EDK Concepts, Tools, and Techniques, Chapter 1 (Introduction),
Chapter 3 (Using Xilinx Platform Studio), and Chapter 4 (Working with the Embedded
Platform) [Ref 1]
• General knowledge of FPGAs, digital design concepts, and microprocessors
• Basic familiarity with the ISE Design Suite
• Basic VHDL/Verilog knowledge
System Overview
This tutorial is based on the ML605/SP605 Embedded Kit MicroBlaze Processor
Subsystem. Readers are encouraged to refer to DS668, AXI Interface Based ML605 Embedded
Kit MicroBlaze Processor Subsystem Data Sheet [Ref 3] or DS667, AXI Interface Based SP605
Embedded Kit MicroBlaze Processor Subsystem Data Sheet [Ref 5] during the execution of this
tutorial.

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Included Files and Systems
Included Files and Systems
The Tutorial_Sandbox directory is a working area for this tutorial. It is provided as part
of the ML605 or SP605 Embedded Kit and contains the benchmarking IP cores that are
added to the base MicroBlaze Processor Subsystem to create the benchmarking system.
Figure 1 shows the directory structure for the Tutorial_Sandbox working area.
Note: Although this tutorial starts from the base ML605_System, or base SP605_System as
shown in Figure 1, the Tutorial_Sandbox directory contains the additional files necessary to build
the benchmarking system. To generate a new tutorial sandbox, copy the Tutorial_Sandbox
directory into the working area on the user’s computer.
X-Ref Target - Figure 1
Figure 1: Tutorial Sandbox Directory Structure
ML605_Embedded_Kit/
SP605_Embedded_Kit
Documentation
edkBmmFile_bd.bmm
system.xml
ise_top.bit (containsno bootloop)
system.ucf
SWHW
hw_platform
hw
data
perf_axi_v1_00_a
pcores
BenchmarkDemo.elf
BenchmarkDemo
SDK_Export
Tutorial_Completed ML605_System/
SP605_System
MicroBlaze_ProcessorSubSystem
(XPSProject)
Tutorial_SandBox Benchmark_Demo
UG669_01_021711
board_test_platform SDK_Workspace
board_test_app
benchmark_demo
standalone
ise_top.ucf
ise_proj.xise
ise_proj.gise
ise_top.vhd

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Included Files and Systems
The directory structure of the completed tutorial (Tutorial_Completed) is shown in
Figure 2.
X-Ref Target - Figure 2
Figure 2: Completed Tutorial Directory Structure
ML605_Embedded_Kit/
SP605_Embedded_Kit
Documentation
edkBmmFile_bd.bmm
system.xml
ise_top.bit (containsno bootloop)
system.ucf
SWHW
hw_platform
hw
data
BenchmarkDemo.elf
BenchmarkDemo
SDK_Export
Tutorial_Completed ML605_System/
SP605_System
MicroBlaze_ProcessorSubSystem
(XPSProject)
Tutorial_SandBox Benchmark_Demo
UG669_02_021711
board_test_platform SDK_Workspace
board_test_app
hello_world_0
board_test_platform
hello_world_bsp_0
hw_platform
board_test_app
benchmark_demo
standalone
perf_axi_v1_00_a
pcores
ise_top.ucf
ise_proj.xise
ise_proj.gise
ise_top.vhd

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Executing the System
Executing the System
The ready_for_download directory contains the pre-built bitstream and ELF files for
the ML605 or SP605 MicroBlaze Processor Subsystem. The directory structure of the
ML605_System is shown in DS668, AXI Interface Based ML605 Embedded Kit MicroBlaze
Processor Subsystem Data Sheet [Ref 3]. The directory structure of the SP605_System is
shown in DS667, AXI Interface Based SP605 Embedded Kit MicroBlaze Processor Subsystem
Data Sheet [Ref 5].
The pre-built bitstream and ELF files file are used to verify that the software is properly
installed and that the board is set up correctly. To execute the system using these files,
follow these steps:
1. Connect a USB Type-A to Mini-B 5-pin cable between the ML605 or SP605 USB JTAG
connector and the host computer.
2. Verify that the USB cable is properly connected to the USB UART connection and the
host computer, as described in UG668, Getting Started with the Virtex-6 FPGA ML605
Embedded Development Kit [Ref 2], or UG667, Getting Started with the Spartan-6 FPGA
ML605 Embedded Development Kit [Ref 4].
3. If the board is not already powered on, power on the ML605 board.
4. Open and configure a serial communications terminal utility program with these
settings:
• Baud Rate: 9600
•Data:8 bit
•Parity:None
•Stop:1 bit
• Flow Control: None
Figure 3 shows the serial port setup window.
Note: The Port setting (COM1, COM2, COM3, COM4) can vary based on the system setup
and might be set up differently than shown in Figure 3. It should be set appropriately for the
user’s system.
X-Ref Target - Figure 3
Figure 3: Serial Communications Utility Configuration
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Executing the System
5. Configure and exercise the MicroBlaze Processor Subsystem by launching the Xilinx
Microprocessor Debugger (XMD). Open a command shell with the proper ISE Design
tool and EDK environment settings.
Note: To set environment variables, run the settings32.bat file located in the Xilinx
installation area. At the command prompt, type C:\Xilinx\13.1\ISE_DS\settings32.bat and
press Enter.
6. Execute these commands to download the design and connect to the MicroBlaze
processor:
For ML605:
$ cd ML605_Embedded_Kit/ML605_System/ready_for_download
$ xmd
XMD% fpga -f ise_top_download.bit
Note: This command downloads the hardware bitstream into the FPGA but does not
download the software application.
XMD% connect mb mdm
Note: This command connects to the MicroBlaze debug module.
For SP605:
$ cd SP605_Embedded_Kit/SP605_System/ready_for_download
$ xmd
XMD% fpga -f ise_top_download.bit
Note: This command downloads the hardware bitstream into the FPGA but does not
download the software application.
XMD% connect mb mdm
Note: This command connects to the MicroBlaze debug module.
7. XMD allows low-level visibility into the design. There are several useful XMD
commands to allow for the peeking and poking of registers and memory locations
within the system. For example, writes to and reads from the internal block RAM are
done as follows:
• For ML605:
XMD% mwr 0x62000000 0xDEADBEEF
XMD% mrd 0x62000000
The value 0xDEADBEEF should be returned:
62000000: DEADBEEF
As an example of register access, write to the GPIO register which outputs data to
the 8-bit GPIO LEDs on the ML605 board:
XMD% mwr 0x81420000 0xAA
The value written to this register is now reflected in the GPIO LEDs. The next write
changes the LED display:
XMD% mwr 0x81420000 0x55
Note: A read from this register always returns 0x00000000, as this is an output-only
register.

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Executing the System
Set all of the DIP switches labeled GPIO DIP SW (SW1) to the ON position. Then
read from the GPIO register which inputs data from the DIP switches:
XMD% mrd 0x81440000
The value 0x000000FF should be returned:
81440000: 000000FF
Change the DIP switch settings and verify that the correct value is read from the
GPIO register.
Note: Switch 1 is the most significant bit.
• For SP605:
XMD% mwr 0x4A000000 0xDEADBEEF
XMD% mrd 0x4A000000
The value 0xDEADBEEF should be returned:
4A000000: DEADBEEF
As an example of register access, write to the GPIO register which outputs data to
the 8-bit GPIO LEDs on the SP605 board:
XMD% mwr 0x81420000 0xA
The value written to this register is now reflected in the GPIO LEDs. The next write
changes the LED display:
XMD% mwr 0x81420000 0x5
Note: A read from this register always returns 0x00000000, as this is an output-only
register.
Set all of the DIP switches labeled GPIO DIP SW (SW1) to the ON position. Then
read from the GPIO register which inputs data from the DIP switches:
XMD% mrd 0x81440000
The value 0x0000000F should be returned:
81440000: 0000000F
Change the DIP switch settings and verify that the correct value is read from the
GPIO register.
Note: Switch 1 is the most significant bit.
For more information about XMD and the commands available within XMD, see
UG111, Embedded System Tools Reference Manual, Chapter 10. [Ref 6]
8. To download and execute the test software application, enter these commands at the
XMD command prompt:
XMD% dow board_test_app.elf
XMD% con

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Executing the System
Figure 4 shows the resulting output for ML605 on the serial communication terminal
utility program. Figure 5 shows the resulting output for SP605 on the serial
communication terminal utility program
Note: The LED Test (option 2) loops through the LEDS two times and returns to the menu when
complete. The Ethernet Loopback Test (option 6) takes 30 seconds to complete after displaying
the initial setup message. (The Ethernet Loopback Test hangs if jumpers are not set for GMII.)
The External Memory Test (option 8) takes approximately 25 minutes to complete.
X-Ref Target - Figure 4
Figure 4: Board Test Application Menu for ML605
X-Ref Target - Figure 5
Figure 5: Board Test Application Menu for SP605
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Executing the System
9. Execute the chosen tests and then select 0to exit. Details about the test options can be
found in the UG670, AXI Interface Based ML605/SP605 MicroBlaze Processor Subsystem
Software Tutorial [Ref 7].
10. When software execution is completed, enter these commands:
XMD% stop
XMD% rst
XMD% exit

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System Design Flow
System Design Flow
The design flow for creating the base MicroBlaze Processor Subsystem and modifying the
system to include the benchmarking cores includes these steps:
1. Hardware Platform Creation
2. Exporting the Base Hardware Platform to SDK, page 22
3. Customizing the Embedded Hardware Platform, page 24
4. Implementing and Downloading the Design, page 35
5. Testing the Design, page 35
Allocate approximately 90 minutes for parts 1 and 2. The bulk of this tutorial is within
parts 3 through 5 which takes approximately two hours to complete.
Note: All time estimates are subject to host computer system speed and can vary depending on
how much time is spent executing the software applications.
Hardware Platform Creation
Opening the Project
1. Start ISE.
• On a Windows XP host, select Start All Programs Xilinx ISE Design Suite
13.1 ISE Design Tools Project Navigator.
• On a Linux host, enter ise at a command prompt.
2. If necessary, close out the previous project by selecting File Close Project.
3. In Project Commands, select Open Project...
4. Browse to
ML605_Embedded_Kit/Tutorial_Sandbox/HW
or
SP605_Embedded_Kit/Tutorial_Sandbox/HW
and select ise_proj.xise. Click Open.
5. Under Hierarchy, expand ise_top - STRUCTURE and double click on system_i -
system (system.xmp). This invokes XPS for the XPS subsystem.

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System Design Flow
Examining the System
The System Assembly View (SAV) of the design provides visibility of the MicroBlaze
Processor Subsystem bus interfaces, port connections, and address map.
Note: Refer to UG683, EDK Concepts, Tools, and Techniques for additional details or instructions
for any of the steps outlined in this section of the tutorial. [Ref 1]
Bus Interfaces
1. To examine the bus structure of the MicroBlaze Processor Subsystem, select the
System Assembly View tab and then select the Bus Interfaces tab along the top edge
of the workspace as shown in Figure 6.
For MicroBlaze masters (Instruction Cache (IC), Data Cache (DC), and Data Port (DP)),
both AXI_MM and AXI_Lite interconnects are used. Two Local Memory Buses (LMB)
are used by MicroBlaze to interface to the local BRAM memory for the processor. These
bus interfaces on MicroBlaze are seen by clicking the +to the left of the microblaze_0
component. (See Figure 6).

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System Design Flow
X-Ref Target - Figure 6
Figure 6: Bus Interfaces View of the MicroBlaze Processor Subsystem
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System Design Flow
Ports
2. Select the Ports tab along the top edge of the workspace. By clicking the +to the left of
any of the components, the connections to that component are shown. (See Figure 7.)
Note: The visibility of the port connections for the system are controlled by the Port Filters window
shown in Figure 8. Many of the peripherals have only default port connections to the AXI
interconnect, and these connections are not shown unless Defaults is checked.
X-Ref Target - Figure 7
Figure 7: Ports View of the MicroBlaze Processor Subsystem
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System Design Flow
Addresses
3. Select the Addresses tab along the top edge of the workspace. Click the +to the left of
microblaze_0’s Address Map to expand the address map as shown in Figure 9. This
workspace is used to modify the addresses of peripherals in the system.
X-Ref Target - Figure 8
Figure 8: Port Filters
UG669_08_021711
X-Ref Target - Figure 9
Figure 9: Addresses View of the MicroBlaze Processor Subsystem
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System Design Flow
IP Core Configurations
The IP cores within the system are configured to the required functionality for this
embedded system. The configurations of the IP cores are described in the System
Configuration section of DS668, AXI Interface Based ML605 Embedded Kit MicroBlaze
Processor Subsystem Data Sheet [Ref 3] and DS667, AXI Interface Based SP605 Embedded Kit
MicroBlaze Processor Subsystem Data Sheet [Ref 5].
4. With the Bus Interfaces tab selected in the System Assembly view, right-click on the
IP core of interest, as shown in Figure 10.
X-Ref Target - Figure 10
Figure 10: Menu Option to Configure IP
UG669_10_021611

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System Design Flow
5. Select Configure IP... and the configuration GUI for that core is displayed. Select the
tab to show the particular feature or parameter of interest. Figure 11 shows the
configuration GUI for the Dual_Timer_Counter core.
6. Click Cancel to return to the System Assembly View because no changes are needed to
the cores in the system at this time.
X-Ref Target - Figure 11
Figure 11: Dual Timer Counter - AXI_Timer Configuration GUI
UG669_11_110410