Xilinx ChipScope Pro User manual

User Guide []
UG029 (v14.3) October 16, 2012 []
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ChipScope Pro
Software and Cores
User Guide
UG029 (v14.3) October 16, 2012
This document applies to the following software versions: ISE Design Suite 14.3 through 14.6This document applies to the following software versions: ISE Design Suite 14.3 through 14.6This document applies to the following software versions: ISE Design Suite 14.3 through 14.6This document applies to the following software versions: ISE Design Suite 14.3 through 14.6

ChipScope Pro Software and Cores User Guide www.xilinx.com UG029 (v14.3) October 16, 2012
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Revision History
The following table shows the revision history for this document.
Date Version Revision
4/24/2012 14.1 Updated for 14.1 release. Updates for KC705 board.
7/25/2012 14.2 Updated for 14.2 release. Various corrections plus support for RX Margin Analysis panel.
10/16/2012 14.3 Updated for 14.3 release. Support for IBERT 7 Series GTP and GTZ devices.

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UG029 (v14.3) October 16, 2012
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Chapter 1: Introduction
ChipScope Pro Tools Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
ChipScope Pro Tools Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Using ChipScope Pro Cores in the PlanAhead Tool . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
ChipScope Pro Cores Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
System Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Software Installation and Licensing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Chapter 2: Using the Core Generator Tools
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Using the Xilinx CORE Generator Tool with ChipScope Pro Cores . . . . . . . . . . . 31
Chapter 3: Using the ChipScope Pro Core Inserter
ChipScope Pro Core Inserter Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Using the ChipScope Pro Core Inserter with the PlanAhead Tool . . . . . . . . . . . . 33
Using the ChipScope Pro Core Inserter with ISE Project Navigator . . . . . . . . . . . 33
Using the ChipScope Pro Core Inserter with Command Line Implementation 35
ChipScope Pro Core Inserter Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Chapter 4: Using the ChipScope Pro Analyzer
ChipScope Pro Analyzer Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
ChipScope Pro Analyzer Server Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
ChipScope Pro Analyzer Client Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
ChipScope Pro Analyzer Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
ChipScope Pro ILA Waveform Toolbar Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
ChipScope Pro Analyzer Command Line Options. . . . . . . . . . . . . . . . . . . . . . . . . . . 129
Chapter 5: ChipScope Engine Tcl Interface
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
CSE/Tcl Command Summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
CseJtag Tcl Commands. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
CseFpga Tcl Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178
CseCore Tcl Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192
CseVIO Tcl Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195
CSE/Tcl Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205
Appendix A: ChipScope Pro Tools Troubleshooting Guide
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207
ChipScope Pro Tools Installation Troubleshooting . . . . . . . . . . . . . . . . . . . . . . . . . 208
Xilinx JTAG Programming Cable Troubleshooting . . . . . . . . . . . . . . . . . . . . . . . . . 209

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UG029 (v14.3) October 16, 2012
ChipScope Pro Analyzer Core Troubleshooting. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217
Gathering Information for Xilinx Technical Support . . . . . . . . . . . . . . . . . . . . . . . . 223
Appendix B: References

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UG029 (v14.3) October 16, 2012
Chapter 1
Introduction
ChipScope Pro Tools Overview
As the density of FPGA devices increases, so does the impracticality of attaching test
equipment probes to these devices under test. The ChipScope™ Pro tools integrate key
logic analyzer and other test and measurement hardware components with the target
design inside the supported Xilinx® FPGA devices listed in the ISE® Design Suite Product
Table [See Reference 16, p. 225]. The tools communicate with these components and
provide the designer with a robust logic analyzer solution.
The ChipScope Pro Serial I/O Toolkit provides features and capabilities specific to the
exploration and debug of designs that use the high-speed serial transceiver I/O capability
of FPGAs. The IBERT (internal bit error ratio tester) core and related software provides
access to the high-speed serial transceivers and perform bit error ratio analysis on channels
composed of these transceivers. In this document, the transceivers are called MGTs (multi-
gigabit transceivers). The IBERT core supports the high-speed serial transceivers found in
the Xilinx Virtex®-7, Kintex™-7, Virtex-6, Spartan®-6, and Virtex-5 FPGA devices listed in
the ISE Design Suite Product Table [See Reference 16, p. 225].
ChipScope Pro Tools Description
The following table gives a brief description of the various ChipScope Pro tools and cores.
Table 1-1: ChipScope Pro Tools Description
Tool Description
Xilinx CORE
Generator™ tool
Provides core generation capability for the ICON (integrated
controller), ILA (integrated logic analyzer), VIO, (virtual
input/output), and ATC2 (Agilent trace core) cores targeting all
supported FPGA device families. Also provides core generation
capability for the IBERT v2.0 core targeting the Virtex-7, Kintex-7,
Virtex-6, Spartan-6, and Virtex-5 FPGA families. The Xilinx CORE
Generator tool is part of the Xilinx ISE Design Suite tool installation.
IBERT Core
Generator
Provides full design generation capability for the IBERT v1.0 core
targeting the Virtex-5 devices. You select the MGTs and parameters
governing the design, and the CORE Generator tool uses the ISE
design suite to produce a configuration file.
Core Inserter Automatically inserts the ICON, ILA, and ATC2 cores into your
synthesized design.

6www.xilinx.com ChipScope Pro Software and Cores User Guide
UG029 (v14.3) October 16, 2012
Chapter 1: Introduction
This figure shows a block diagram of a system containing debug cores added using the
ChipScope Pro tools. You can place the ICON, ILA, VIO, and ATC2 cores (collectively
called the ChipScope Pro cores) into your design by generating the cores with the CORE
Generator tool and instantiating them into the HDL source code. You can also insert the
ICON, ILA, and ATC2 cores directly into the synthesized design netlist using the
ChipScope Pro Core Inserter or PlanAhead tools. You then place and route your design
using the ISE implementation tools. Next, download the bitstream into the device under
test and analyze the design with the ChipScope Pro Analyzer tool.
PlanAhead™ Design
Analysis Tool
Automatically inserts the ICON and ILA cores into the design
netlist. For more information on this feature, go to PlanAhead
Design Analysis Tool [See Reference 17, p. 225].
ChipScope Pro
Analyzer Tool
Provides in-system device configuration, as well as trigger setup,
trace display, control, and status for the ICON, ILA,VIO, and IBERT
cores.
ChipScope Engine Tcl
(CSE/Tcl) Scripting
Interface
The scriptable CSE/Tcl command interface makes it possible to
interact with devices in a JTAG (Joint Test Action Group, IEEE
standard) chain from a Tcl shell
(1).
Notes:
1. Tcl stands for Tool Command Language. The CSE/Tcl interface requires the Tcl shell program (called
xtclsh) that is included in the ChipScope Pro and ISE tool installations or in the ActiveTcl 8.4 shell
available from ActiveState [See Reference 24, p. 226].
X-Ref Target - Figure 1-1
Figure 1-1: ChipScope Pro System Block Diagram
Table 1-1: ChipScope Pro Tools Description (Cont’d)
Tool Description
Board-Under-Test
Host Computer with
ChipScope Pro Software
JTAG
Connections
cs_pro_sys_blk_diag
ChipScope
Pro
Target Device Under Test
User
Function
User
Function
User
Function
ILA Pro
ICON Pro
ILA Pro
ILA Pro
Parallel
Cable

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UG029 (v14.3) October 16, 2012
ChipScope Pro Tools Description
ChipScope Pro Analyzer tool supports the following download cables for communication
between your computer and the devices in the JTAG boundary scan chain:
•Platform Cable USB
•Parallel Cable IV
•Digilent USB-to-JTAG cables
•ByteTools Catapult EJ-1 Ethernet-to-JTAG cable
The ChipScope Pro Analyzer tool and cores contain many features that you can use to
verify your logic (Table 1-2). User-selectable data channels range from 1 to 4,096 and the
sample buffer sizes range from 256 to 131,072 samples. You can change the triggers in real
time without affecting your logic. ChipScope Pro Analyzer tool leads you through the
process of modifying triggers and analyzing the captured data.
Table 1-2: ChipScope Pro Logic Debug Features and Benefits
Feature Benefit
1 to 4,096 user-selectable data channels Accurately captures wide data bus
functionality.
User-selectable sample buffers ranging in
size from 256 to 131,072 samples
Large sample size increases accuracy and
probability of capturing infrequent events.
Up to 16 separate trigger ports, each with a
user-selectable width of 1 to 256 channels (for
a total of up to 4096 trigger channels)
Multiple separate trigger ports increase the
flexibility of event detection and reduce the
need for sample storage.
Up to 16 separate match units per trigger
port (up to 16 total match units) for a total of
16 different comparisons per trigger
condition
Multiple match units per trigger ports
increase the flexibility of event detection
while conserving valuable resources.
All data and trigger operations are
synchronous to your clock at rates up to 500
MHz
Capable of high-speed trigger event
detection and data capture.
Trigger conditions implement either a
boolean equation or a trigger sequence of up
to 16 match functions
Can combine up to 16 trigger port match
functions using a boolean equation or a
16-level trigger sequencer.
Data storage qualification condition
implements a boolean equation of up to 16
match functions
Can combine up to 16 trigger port match
functions using a boolean equation to
determine which data samples are captured
and stored in on-chip memory.
Trigger and storage qualification conditions
are in-system changeable without affecting
the user logic
No need to single step or stop a design for
logic analysis.
Easy-to-use graphical interface Guides you through selecting the correct
options.

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UG029 (v14.3) October 16, 2012
Chapter 1: Introduction
Design Flow
The tools design flow (Figure 1-2) merges easily with any standard FPGA design flow that
uses a standard HDL synthesis tool and the ISE implementation tools.
Using ChipScope Pro Cores in the PlanAhead Tool
You can add the ChipScope Pro cores to your design using the PlanAhead tool using one of
two methods:
•HDL instantiation
•Netlist insertion
Up to 15 independent ILA, VIO, or ATC2
cores per device
Can segment logic and test smaller sections
of a large design for greater accuracy.
Multiple trigger settings
Records duration and number of events
along with matches and ranges for greater
accuracy and flexibility.
Downloadable from the Xilinx Web site Tools are easily accessible from the
ChipScope Suite [See Reference 18, p. 225].
Table 1-2: ChipScope Pro Logic Debug Features and Benefits (Cont’d)
Feature Benefit
X-Ref Target - Figure 1-2
Figure 1-2: ChipScope Pro Tools Design Flow
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UG029 (v14.3) October 16, 2012
Using ChipScope Pro Cores in the PlanAhead Tool
The HDL instantiation method is a two-step process that involves:
1. Using the IP Catalog in the PlanAhead tool to select, customize, and generate the
desired ChipScope Pro debug core.
2. Using the HDL Editor in the PlanAhead tool to manually instantiate the IP component
instance into your HDL source.
The HDL instantiation method is a good approach for users who want full control of all IP
core parameters and connections to signals in their HDL design. The downside of HDL
instantiation is that it requires the user to modify their source code. It can also be difficult
to debug a design that is made up of multiple levels of hierarchy because signals of interest
need to be brought to the debug core instance.
The Netlist insertion method is also a two step process that involves:
1. Selecting signals or nets in your design that are interesting for debugging purposes.
2. Specifying how you want these signals to be attached to debug IP cores.
The PlanAhead tool takes care of generating the debug IP core, inserting it into the design
netlist, and connecting it to the nets of interest. A potential drawback to the netlist insertion
method is that the HDL signals you want to debug could be optimized away or obfuscated
during synthesis process. Most signals that are interesting for debug (such as outputs of
registers, block RAM, etc.) are not adversely affected by the synthesis process. However,
one way to ensure signals are preserved for debugging later in the flow is to attach the
MARK_DEBUG attribute or property to signals in your design source (either your HDL or
constraints files). For details about the MARK_DEBUG attribute and other constraints,
refer to the ISE Constraints Guide [See Reference 14, p. 225].
The MARK_DEBUG property has the following benefits:
•Allows targeted debugging of signals in your design source without the overhead of
HDL instantiation method
•Ensures signals to be debugged are preserved in the synthesized netlist
•Is compatible with Xilinx Synthesis Technology (XST) and third party FPGA synthesis
tools such as Synopsys, Synplify Pro, and Mentor Graphics Precision.
For more details on the ChipScope debugging capabilities of the PlanAhead tool, refer to
the PlanAhead User Guide [See Reference 17, p. 225].
Using ChipScope Pro Cores in Embedded Processor and DSP Tool Flows
The cores (ICON, ILA, IBA, VIO, and ATC2) can also be used in the EDK and System
Generator for DSP tool flows for embedded processor and DSP designs, respectively. For
information on how to use the ChipScope Pro cores, see the EDK Platform Studio [See
Reference 15, p. 225] and System Generator for DSP [See Reference 19, p. 225]
documentation.

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Chapter 1: Introduction
ChipScope Pro Cores Description
ICON Core
All the cores use the JTAG boundary scan port to communicate to the host computer via a
JTAG download cable. The ICON core provides a communications path between the JTAG
boundary scan port of the target FPGA and up to 15 ILA, VIO, and/or ATC2 cores (as
shown in Figure 1-1, page 6).
For devices of the Spartan-3, Spartan-3E, Spartan-3A, and Spartan-3A DSP families, the
ICON core uses either the USER1 or USER2 JTAG boundary scan instructions for
communication via the BSCAN primitive. The unused USER1 or USER2 scan chain of the
BSCAN primitive can also be exported for use in your application, if needed.
For all other supported devices, the ICON core uses any one of the USER1, USER2, USER3
or USER4 scan chains available via the BSCAN primitives. It is not necessary to export
unused USER scan chains because each BSCAN primitive implements a single scan chain.
ILA Core
The ILA core is a customizable logic analyzer core that can be used to monitor any internal
signal of your design. Because the ILA core is synchronous to the design being monitored,
all design clock constraints that are applied to your design are also applied to the
components inside the ILA core. The ILA core consists of three major components:
•Trigger input and output logic:
−Trigger input logic detects elaborate trigger events.
−Trigger output logic triggers external test equipment and other logic.
•Data capture logic:
−ILA cores capture and store trace data information using on-chip block RAM
resources.
•Control and status logic:
−Manages the operation of the ILA core.
ILA Trigger Input Logic
The triggering capabilities of the ILA core include many features that are necessary for
detecting elaborate trigger events. These features are described in Table 1-3.
Table 1-3: Trigger Features of the ILA Core
Feature Description
Wide Trigger Ports Each trigger port can be 1 to 256 bits wide.
Multiple Trigger Ports
Each ILA core can have up to 16 trigger ports. The ability to
support multiple trigger ports is necessary in complex systems
where different types of signals or buses must be monitored
using separate match units.
Multiple Match Units per
Trigger Port
Each trigger port can be connected to up to 16 match units. This
feature enables multiple comparisons to be performed on the
trigger port signals.

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UG029 (v14.3) October 16, 2012
ChipScope Pro Cores Description
Boolean Equation Trigger
Condition
The trigger condition can consist of a Boolean AND or OR
equation of up to 16 match unit functions.
Multi-Level Trigger
Sequencer
The trigger condition can consist of a multi-level trigger
sequencer of up to 16 match unit functions.
Boolean Equation Storage
Qualification Condition
The storage qualification condition can consist of a Boolean
AND or OR equation of up to 16 match unit functions.
Choice of Match Unit
Types
The match unit connected to each trigger port can be one of the
following types:
•Basic comparator:
−Performs ‘=’ and ‘<>’ comparisons.
−Compares up to 8 bits per slice in LUT4-basedadevices.
−Compares up to 19 bits per slice in Virtex-5 and Spartan-6
devices.
−Compares up to 20 bits per slice in all other LUT6b-based
devices.
•Basic comparator w/edges:
−Performs ‘=’ and ‘<>’ comparisons.
−Detects high-to-low and low-to-high bit-wise transitions.
−Compares up to 4 bits per slice in LUT4-based devices.
−Compares up to 8 bits per slice in LUT6-based devices.
•Extended comparator:
−Performs ‘=’, ‘<>’, ‘>’, ‘>=’, ‘<‘, and ‘<=’ comparisons.
−Compares up to 2 bits per slice in LUT4-based devices.
−Compares up to 8 bits per slice in LUT6-based devices.
•Extended comparator w/edges:
−Performs ‘=’, ‘<>’, ‘>’, ‘>=’, ‘<‘, and ‘<=’ comparisons.
−Detects high-to-low and low-to-high bit-wise transitions.
−Compares up to 2 bits per slice in LUT4-based devices.
−Compares up to 8 bits per slice in LUT6-based devices.
•Range comparator:
−Performs ‘=’, ‘<>’, ‘>’, ‘>=’, ‘<‘, ‘<=’, ‘in range’, and ‘not in
range’ comparisons.
−Compares up to 1 bit per slice in LUT4-based devices.
−Compares up to 4 bits per slice in LUT6-based devices.
•Range comparator w/edges:
−Performs ‘=’, ‘<>’, ‘>’, ‘>=’, ‘<‘, ‘<=’, ‘in range’, and ‘not in
range’ comparisons.
−Detects high-to-low and low-to-high bit-wise transitions.
−Compares up to 1bit per slice in LUT4-based devices.
−Compares up to 4 bits per slice in LUT6-based devices.
All match units connected to a given trigger port are the same
type.
Table 1-3: Trigger Features of the ILA Core (Cont’d)
Feature Description

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Chapter 1: Introduction
Choice of Match Function
Event Counter
All the match units of a trigger port can be configured with an
event counter, with a selectable size of 1 to 32 bits. This counter
can be configured at runtime to count events in the following
ways:
•Exactly n occurrences
−Matches only when exactly nconsecutive or non-
consecutive events occur
•At least n occurrences
−Matches and stays asserted after n consecutive or
non-consecutive events occur
•At least n consecutive occurrences
−Matches after n consecutive events occur, and stays
asserted until the match function is not satisfied.
Trigger Output Port
The internal trigger condition of the ILA core can be accessed
using the optional trigger output port. This signal can be used as
a trigger for external test equipment by attaching the signal to an
output pin.
However, it can also be used by internal logic as an interrupt, a
trigger, or to cascade multiple ILA cores together.
The trigger output port of the ILA core has a latency of 10 clock
cycles.
The shape (level or pulse) and sense (active-High or
active-Low) of the trigger output can be controlled at run-time.
a. LUT4-based device families are Spartan-3, Spartan-3E, Spartan-3A, Spartan-3A DSP, and Virtex-4
FPGAs (and the variants of these families).
b. LUT6-based device families include Zynq™ -7000 AP SoCs and, Virtex-5, Virtex-6, Spartan-6, Artix™-
7, Kintex-7, and Virtex-7 FPGAs (and the variants of these families).
Table 1-3: Trigger Features of the ILA Core (Cont’d)
Feature Description

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ChipScope Pro Cores Description
Using Multiple Trigger Ports
The ability to monitor different kinds of signals and buses in the design requires the use of
multiple trigger ports. For example, if you are instrumenting an internal system bus in
your design that is made up of control, address, and data signals, then you could assign a
separate trigger port to monitor each signal group (as shown in Figure 1-3).
If you connected all these different signals and buses to a single trigger port, you would
not be able to monitor for individual bit transitions on the CE, WE, and OE signals while
looking for the Address bus to be in a specified range. The flexibility of being able to
choose from different types of match units allows you to customize the ILA cores to your
triggering needs while keeping resource usage to a minimum.
X-Ref Target - Figure 1-3
Figure 1-3: ILA Core Connection Example
Match Unit M0
(Basic w/edges)
Match Unit M1
(Basic w/edges)
Match Unit M2
(Basic)
Match Unit M3
(Basic)
Match Unit M4
(Range)
Match Unit M5
(Basic w/edges)
Trigger
Condition
Storage
Qualification
Condition
Data
Capture
Control
Data
Capture
Memory
TRIG0
TRIG_OUT
TRIG1
TRIG2
TRIG3
ILA Core
Interrupt
Clock
CE, WE, OE
Address
Data
Ext. Trigger
3
24
32
1
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ila_pro_connection_example_070704
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14 www.xilinx.com ChipScope Pro Software and Cores User Guide
UG029 (v14.3) October 16, 2012
Chapter 1: Introduction
Using Trigger and Storage Qualification Conditions
The ILA core implements both trigger and storage qualification condition logic. The
trigger condition is a Boolean or sequential combination of events that is detected by match
unit comparators that are attached to the trigger ports of the core. The trigger condition is
used to mark a distinct point of origin in the data capture window and can be located at the
beginning, the end, or anywhere within the data capture window.
Similarly, the storage qualification condition is also a Boolean combination of events that is
detected by match unit comparators that are subsequently attached to the trigger ports of
the core. However, the storage qualification condition differs from the trigger condition in
that it evaluates trigger port match unit events to decide whether or not to capture and
store each individual data sample. The trigger and storage qualification conditions can be
used together to define when to start the capture process and what data is captured.
In the ILA core example shown in Figure 1-3, page 13, suppose you want to do the
following:
•Trigger on the first memory write cycle (CE = rising edge, WE = 1, OE = 0) to Address
= 0xFF0000;
•Capture only memory read cycles (CE = rising edge, WE = 0, OE = 1) from Address =
0x23AACC where the Data values are between 0x00000000 and 0x1000FFFF;
To implement these conditions successfully, you would need to make sure that both the
TRIG0 and TRIG1 trigger ports each have two match units attached to them: one for the
trigger condition and one for the storage qualification condition. Here is how you would
set up the trigger and storage qualification equations and each individual match unit to
satisfy the conditions above:
•Trigger Condition = M0 && M2, where:
−M0[2:0] = CE, WE, OE = “R10” (where ‘R’ means “rising edge”)
−M2[23:0] = Address = “FF0000”
•Storage Qualification Condition = M1 && M3 && M4, where:
−M1[2:0] = CE, WE, OE = “R01” (where ‘R’ means “rising edge”)
−M3[23:0] = Address = “23AACC”
−M4[31:0] = Data = in the range of 0x00000000 through 0x1000FFFF
The triggering and storage qualification capabilities of the ILA core allow you to locate and
capture exactly the information that you want without wasting valuable on-chip memory
resources.
ILA Trigger Output Logic
The ILA core implements a trigger output port called TRIG_OUT. The TRIG_OUT port is
the output of the trigger condition that is set up at runtime using the ChipScope Pro
Analyzer tool. The shape (level or pulse) and sense (active-High or active-Low) of the
trigger output can also be controlled at run-time. The latency of the TRIG_OUT port
relative to the input trigger ports is 10 clock cycles.
The TRIG_OUT port is very flexible and has many uses. You can connect the TRIG_OUT
port to a device pin in order to trigger external test equipment such as oscilloscopes and
logic analyzers. Connecting the TRIG_OUT port to an interrupt line of an embedded
PowerPC® or MicroBlaze™ processor can be used to cause a software event to occur. You
can also connect the TRIG_OUT port of one core to a trigger input port of another core in
order to expand the trigger and data capture capabilities of your on-chip debug solution.

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UG029 (v14.3) October 16, 2012
ChipScope Pro Cores Description
ILA Data Capture Logic
Each ILA core can capture data using on-chip block RAM resources independently from all
other cores in the design. Each ILA core can also capture data using one of two capture
modes: Window and N samples.
Window Capture Mode
In Window capture mode, the sample buffer can be divided into one or more equal-sized
sample windows. The window capture mode uses a single trigger condition event (i.e., a
Boolean combination of the individual trigger match unit events) to collect enough data to
fill a sample window.
In the case where the depth of the sample windows is a power of 2 up to 131,072 samples,
the trigger position can be set to the beginning of the sample window (trigger first, then
collect), the end of the sample window (collect until the trigger event), or anywhere in
between.
In the other case where the window depth is not a power of 2, the trigger position can only
be set to the beginning of the sample window.
After a sample window has been filled, the trigger condition of the ILA core is
automatically re-armed and continues to monitor for trigger condition events. This process
is repeated until all sample windows of the sample buffer are filled or until you halt the
ILA core.
N Samples Capture Mode
The N Samples capture mode is similar to the Window capture mode except for two major
differences:
•The number of samples per window can be any integer N from 1 to the sample buffer
size minus 1.
•The trigger position must always be at position 0 in the window.
The N sample capture mode is useful for capturing the exact number of samples needed
per trigger without wasting valuable capture storage resources.
Trigger Marks
The data sample in the sample window that coincides with a trigger event is tagged with
a trigger mark. This trigger mark tells the ChipScope Pro Analyzer tool the position of the
trigger within the window. This trigger mark consumes one extra bit per sample in the
sample buffer.
Data Port
The ILA core provides the capability to capture data on a port that is separate from the
trigger ports that are used to perform trigger functions. This feature is useful for limiting
the amount of data to be captured to a relatively small amount because it is not always
useful to capture and view the same information that is used to trigger the core.
However, in many cases it is useful to capture and view the same data that is used to
trigger the core. In this case, you can choose for the data to consist of one or more of the
trigger ports. This feature allows you to conserve resources while providing the flexibility
to choose what trigger information is interesting enough to capture.

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Chapter 1: Introduction
ILA Control and Status Logic
The ILA contains a modest amount of control and status logic that is used to maintain the
normal operation of the core. All logic necessary to properly identify and communicate
with the ILA core is implemented by this control and status logic.
VIO Core
The Virtual Input/Output (VIO) core is a customizable core that can both monitor and
drive internal FPGA signals in real time. Unlike the ILA core, no on- or off-chip RAM is
required. Four kinds of signals are available in a the VIO core:
•Asynchronous inputs:
−These are sampled using the JTAG clock signal that is driven from the JTAG cable.
−The input values are read back periodically and displayed in the ChipScope Pro
Analyzer tool.
•Synchronous inputs:
−These are sampled using the design clock.
−The input values are read back periodically and displayed in the ChipScope Pro
Analyzer tool.
•Asynchronous outputs:
−You define these in the ChipScope Pro Analyzer tool and drive them out of the
core to the surrounding design.
−A logical 1 or 0 value can be defined for individual asynchronous outputs.
•Synchronous outputs:
−You define these in the ChipScope Pro Analyzer tool. They are synchronized to the
design clock and driven out of the core to the surrounding design.
−A logical 1 or 0 can be defined for individual synchronous outputs. Pulse trains of
16 clock cycles worth of 1’s and/or 0’s can also be defined for synchronous
outputs.
Activity Detectors
Every VIO core input has additional cells to capture the presence of transitions on the
input. Because the design clock will most likely be much faster than the sample period of
the ChipScope Pro Analyzer tool, it is possible for the signal being monitored to transition
many times between successive samples. The activity detectors capture this behavior and
the results are displayed along with the value in the ChipScope Pro Analyzer tool.
In the case of a synchronous input, activity cells capable of monitoring for asynchronous
and synchronous events are used. This feature can be used to detect glitches as well as
synchronous transitions on the synchronous input signal.
Pulse Trains
Every VIO synchronous output has the ability to output a static 1, a static 0, or a pulse train
of successive values. A pulse train is a 16-clock cycle sequence of 1's and 0's that drive out
of the core on successive design clock cycles. The pulse train sequence is defined in the
ChipScope Pro Analyzer tool and is executed only one time after it is loaded into the core.

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ChipScope Pro Cores Description
ATC2 Core
The Agilent Trace Core 2 (ATC2) is a customizable debug capture core that is specially
designed to work with the latest generation Agilent logic analyzers. The ATC2 core
provides external Agilent logic analyzers access to internal FPGA design nets (as shown in
Figure 1-4).
ATC2 Core Data Path Description
The data path of the ATC2 core consists of:
•Up to 64 run-time selectable input signal banks that connect to your FPGA design
•Up to 64 output data pins that connect to the probe connectors of the Agilent logic
analyzer
•Optional 2x time-division multiplexing (TDM) available on each output data pin that
can be used to double the width of each individual signal bank from 64 to 128 bits
•Supports both asynchronous timing and synchronous state capture modes
•Supports any valid I/O standard, drive strength, and output slew rate on each output
data pin on an individual pin-by-pin basis
•Supports any Agilent probe connection technology [See Reference 25, p. 226]
The maximum number of data probe points available at runtime is calculated as:
(64 data ports) * (64 bits per data port) * (2x TDM) = 8,192 probe points.
ATC2 Core Data Capture and Run-Time Control
The external Agilent logic analyzer is used to trigger on and capture the data that passes
through the ATC2 core. This allows you to take full advantage of the complex triggering,
deep trace memory, and system-level data correlation features of the Agilent logic analyzer
as well as the increased visibility of internal design nodes provided by the ATC2 core. The
Agilent logic analyzer is also used to control the run-time selection of the active data port
by communicating with the ATC2 core via a JTAG port connection (as shown in
Figure 1-4).
X-Ref Target - Figure 1-4
Figure 1-4: ATC2 Core and System Block Diagram
1 to 32 Banks
1x or 2x TDM
Probe
Connector
ICON Core
ATC2 Core
FPGA
PCB
User
Design
256
256
256 64
256
JTAG Cable
JTAG
Agilent Logic Analyzer
LPT or USB
Probes
UG029_atc2_block_diagram_021610

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Chapter 1: Introduction
IBERT Core
The IBERT core has all the logic to control, monitor, and change transceiver parameters and
perform bit error ratio tests. The IBERT core has three major components:
•BERT Logic
−The BERT logic instantiates the actual transceiver component, and contains the
pattern generators and checkers. A variety of patterns are available, including
simple clock-type patterns, full PRBS (pseudo random bit sequence) patterns, and
framed counter patterns utilizing commas and comma detection.
•Dynamic Reconfiguration Port (DRP) Logic
−Each transceiver has a Dynamic Reconfiguration Port (DRP) on it, so that
transceiver attributes can be changed in system. All attributes and DRP addresses
are readable and writable in the IBERT core. The DRP for each transceiver can be
accessed individually.
•Control and status logic
−Manages the operation of the IBERT core.
IBERT Design Flow
Because the IBERT is a self-contained design, the design flow is very simple. When using
the ChipScope IBERT Core Generator to generate IBERT core designs for Virtex-5 devices,
the design directory and bit file name are specified, options are chosen, and the Generator
runs the entire implementation flow, including bitstream creation, in one step.
The design flow for generating IBERT core designs for Virtex-7, Kintex-7, Virtex-6, and
Spartan-6 devices are very similar except the Xilinx CORE Generator tool is used. The main
difference is that the design directory and device information is specified in the Xilinx
CORE Generator project. In both cases, you are not required to explicitly run any other
Xilinx tool to generate an IBERT core design bit file.
IBERT Feature Descriptions
The features of the IBERT core vary according to the targeted FPGA device architecture.
The MGT features that are supported are as follows:
•IBERT v2.0 for Virtex-5 FPGA GTX Transceivers (Table 1-4, page 20)
−Full PMA control, including differential swing, emphasis, RX Equalization, and
DFE.
−Ability to change line rate at runtime.
−Limited PCS support, including loopback (8b/10b encoding, clock correction, and
channel bonding are not supported).
−40-bit fabric data width (4-byte mode).
•IBERT v2.0 core for Virtex-6 FPGA GTX transceivers (Table 1-5, page 21)
−Full PMA control, including differential swing, emphasis, RX equalization, and
DFE.
−Ability to change line rates at runtime.
−Ability to set reference clock sources at generate time.
−Limited PCS support, including loopback. Pattern encoding, clock correction and
channel bonding are not supported.

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ChipScope Pro Cores Description
•IBERT v2.0 core for Virtex-6 FPGA GTH transceivers (Table 1-6, page 22)
−Full PMA control, including differential swing, emphasis, RX equalization, and
DFE.
−Ability to set reference clock sources at generate time.
−Limited PCS support, including loopback. Pattern encoding, clock correction, and
channel bonding are not supported.
−TX Diff Swing.
−TX Pre-Emphasis and Post-Emphasis.
•IBERT v2.0 core for Spartan-6 FPGA GTP transceivers (Table 1-7, page 23)
−Full PMA control, including differential swing, emphasis, RX equalization, and
DFE.
−Ability to change line rates at runtime.
−Ability to set reference clock sources at generate time.
−Limited PCS support, including loopback. Pattern encoding, clock correction, and
channel bonding are not supported.
−TX Diff Swing.
−TX Pre-Emphasis.
•IBERT v2.02a core for 7 Series FPGA GTX transceivers (Table 1-8, page 24)
−PMA control, including differential swing, and emphasis.
−Ability to change line rates at generate time.
−Ability to set reference clock sources at generate time.
−Limited PCS support, including loopback. Pattern encoding, clock correction, and
channel bonding are not supported.
•IBERT v2.00a and v2.01a core for 7 Series FPGA GTH Transceivers (Table 1-9,
page 25.)
−IBERT v2.00a targets InitialES silicon only.
−IBERT v2.01a targets GeneralES silicon only.
−PMA control, including differential swing, and emphasis.
−Ability to change line rates at generate time.
−Ability to set reference clock sources at generate time.
−Limited PCS support, including loopback. Pattern encoding, clock correction, and
channel bonding are not supported.
•IBERT v2.00a core for 7 Series FPGA GTP Transceivers (Table 1-10, page 26)
−PMA control, including differential swing, and emphasis.
−Ability to change line rates at generate time.
−Ability to set reference clock sources at generate time.
−Limited PCS support, including loopback. Pattern encoding, clock correction, and
channel bonding are not supported.
•IBERT v2.00a core for 7 Series FPGA GTZ transceivers (Table 1-11, page 27)
−PMA control, including differential swing, and emphasis.
−Ability to change line rates at generate time.
−Ability to set reference clock sources at generate time.

20 www.xilinx.com ChipScope Pro Software and Cores User Guide
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Chapter 1: Introduction
−Limited PCS support, including loopback. Pattern encoding, clock correction, and
channel bonding are not supported.
Table 1-4: IBERT v2.0 Core for the Virtex-5 FPGA GTX Transceivers
Feature Description
Multiple GTX
Transceivers Up to eight transceivers can be selected per design.
Pattern Generator
One pattern generator per selected GTX transceiver is used.
PRBS 7-bit, PRBS 15-bit PRBS 23-bit, PRBS 31-bit, Clk 2x, and Clk
10x patterns are available. The desired pattern from that set can
be selected individually for each GTX transceiver at runtime.
Pattern Checker
One pattern checker per selected GTX transceiver is used. The
same pattern set is available as the pattern generator. The pattern
can be chosen for each GTX transceiver at runtime.
Fabric Width The FPGA fabric interface to the GTX_DUAL tile can be either
32- or 40-bits wide and selectable at generate time.
BERT Parameters
Number of bits received in error and total number of words
received are gathered dynamically and read out by the
ChipScope Pro Analyzer tool.
Polarity The polarity of the TX or RX side of each GTX transceiver can be
changed at runtime.
Reset
Each GTX transceiver and its BER counters can be reset
independently. A reset is also available to reset the entire MGT,
including PLLs.
Link and Lock Status Link, DCM, and PLL lock status are gathered for each GTX
transceiver in the core.
DRP Read The contents of the DRP space for each GTX transceiver can be
read independently of all others.
DRP Write The contents of the DRP space for each GTX transceiver can be
changed at runtime, with single-bit granularity.
Ports Read The contents of the registers that monitor the GTX transceiver
ports can be read independently of others.
Ports Write The contents of the registers that control the GTX transceiver's
ports can be changed at runtime.
Status The dynamic status information for the entire core can be read
out of the core at runtime.