Xilinx DPU IP User manual

DPU for Convolutional
Neural Network v1.2
DPU IP Product Guide
PG338 (v1.2) March 26, 2019

DPU IP Product Guide www.xilinx.com 2
PG338 (v1.2) March 26, 2019
Revision History
The following table shows the revision history for this document.
Section Revision Summary
03/26/2019 Version 1.2
Build the PetaLinux Project
Updated descrption.
Build the Demo
Updated figure.
Demo Execution
Updated code.
03/08/2019 Version 1.1
Table 6: Reg_dpu_base_addr
Updated descrption.
Figure 10: DPU Configuration
Updated figure.
Build the PetaLinux Project
Updated code.
Build the Demo
Updated descrption.
03/05/2019 Version 1.1
Chapter 6: Example Design
Added chapter regarding the DPU targeted reference
design.
02/28/2019 Version 1.0
Initial release
N/A
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Table of Contents
Revision History..........................................................................................................................................................................2
IP Facts ....................................................................................................................................................................................5
Introduction .................................................................................................................................................................................5
Chapter 1: Overview ......................................................................................................................................................................6
Introduction .................................................................................................................................................................................6
Development Tools ....................................................................................................................................................................7
Example System with DPU......................................................................................................................................................8
DNNDK ..........................................................................................................................................................................................8
Licensing and Ordering Information ..................................................................................................................................9
Chapter 2: Product Specification ............................................................................................................................................10
Hardware Architecture ...........................................................................................................................................................10
DSP with Enhanced Utilization (DPU_EU) .......................................................................................................................11
Register Space..........................................................................................................................................................................13
Interrupts....................................................................................................................................................................................17
Chapter 3: DPU Configuration .................................................................................................................................................18
Introduction ..............................................................................................................................................................................18
Configuration Options ..........................................................................................................................................................19
DPU Performance on Different Devices .........................................................................................................................22
Performance of Different Models .....................................................................................................................................22
I/O Bandwidth Requirements.............................................................................................................................................23
Chapter 4: Clocking and Resets ..............................................................................................................................................24
Introduction ..............................................................................................................................................................................24
Clock Domain ...........................................................................................................................................................................24
Reference Clock Generation ...............................................................................................................................................25
Reset ............................................................................................................................................................................................27
Chapter 5: Development Flow ................................................................................................................................................28
Customizing and Generating the Core in MPSoC ......................................................................................................28
Chapter 6: Example Design......................................................................................................................................................33
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Table of Contents
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Introduction ..............................................................................................................................................................................33
Hardware Design Flow..........................................................................................................................................................36
Software Design Flow............................................................................................................................................................39
Appendix A: Legal Notices .......................................................................................................................................................43
References .................................................................................................................................................................................43
Please Read: Important Legal Notices ............................................................................................................................43
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IP Facts
Introduction
The Xilinx® Deep Learning Processor Unit (DPU) is
a configurable engine dedicated for convolutional
neural network. The computing parallelism can be
configured according to the selected device and
application. It includes a set of efficiently optimized
instructions. It can support most convolutional
neural networks, such as VGG, ResNet, GoogLeNet,
YOLO, SSD, MobileNet, FPN, etc.
Features
• One slave AX I interface for accessing
configuration and status registers.
•One master interface for accessing instructions.
•Supports configurable AXI master interface with
64 or 128 bits for accessing data.
•Supports individual configuration of each
channel.
•Supports optional interrupt request generation.
•Some highlights of DPU functionality include:
oConfigurable hardware architecture includes:
B512, B800, B1024, B1152, B1600, B2304,
B3136, and B4096
oConfigurable core number up to three
oConvolution and deconvolution
oMax pooling
oReLu and Leaky ReLu
oConcat
oElementwise
oDilation
oReorg
oFully connected layer
oBatch Normalization
oSplit
DPU IP Facts Table
Core Specifics
Supported
Device Family
Zynq®-7000 SoC and
UltraScale+™ MPSoC Family
Supported User
Interfaces Memory-mapped AXI interfaces
Resources See
Chapter 3: DPU
Configuration
Provided with Core
Design Files
Encrypted RTL
Example Design
Verilog
Constraint File
Xilinx Design Constraints (XDC)
Supported
S/W Driver Included in PetaLinux
Tested Design Flows
Design Entry
Vivado® Design Suite
Simulation
N/A
Synthesis
Vivado Synthesis
Support
Provided by Xilinx at the Xilinx Support web page
Notes:
1. Linux OS and driver support information are available from
DPU
TRD or DNNDK.
2. If the requirement is on Zynq-7000 SoC, contact your local
FAE.
3. For the supported versions of the tools, see the Vivado
Design Suite User Guide: Release Notes Installation, and
Licensing (UG973).
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Chapter 1: Overview
Introduction
The Xilinx® Deep Learning Processor Unit (DPU) is a programmable engine dedicated for convolutional
neural network. The unit contains register configure module, data controller module, and convolution
computing module. There is a specialized instruction set for DPU, which enables DPU to work efficiently
for many convolutional neural networks. The deployed convolutional neural network in DPU includes
VGG, ResNet, GoogLeNet, YOLO, SSD, MobileNet, FPN, etc.
The DPU IP can be integrated as a block in the programmable logic (PL) of the selected Zynq®-7000
SoC and Zynq UltraScale™+ MPSoC devices with direct connections to the processing system (PS). To
use DPU, you should prepare the instructions and input image data in the specific memory address that
DPU can access. The DPU operation also requires the application processing unit (APU) to service
interrupts to coordinate data transfer.
The top-level block diagram of DPU is shown in Figure 1.
Host
CPU
RAM
High Speed Data Tube
DPU
High
Performance
Scheduler
Instruction
Fetch Unit Global Memory Pool
Hybrid Computing Array
PE PE PE PE
X22327-022019
Figure 1: Top-Level Block Diagram
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Development Tools
Use the Xilinx Vivado Design Suite to integrate DPU into your own project. Vivado Design Suite 2018.2
or later version is recommended. Previous versions of Vivado can also be supported. For requests,
contact your sales representative.
Device Resources
The DPU logic resource is optimized and scalable across Xilinx UltraScale+ MPSoC and Zynq-7000
devices. For the detailed resource utilization, refer to
Chapter 3: DPU Configuration .
How to Run DPU
The DPU operation depends on the driver which is included in the Xilinx Deep Neural Network
Development Kit (DNNDK) toolchain.
You can download the free developer resources from the Xilinx website:
https://www.xilinx.com/products/design-tools/ai-inference/ai-developer-hub.html#edge
Refer to the DNNDK User Guide (UG1327) to obtain an essential guide on how to run a DPU with
DNNDK tools. The basic development flow is shown in the following figure. First, use Vivado to
generate the bitstream. Then, download the bitstream to the target board and install the DPU driver.
For instructions on how to install the DPU driver and dependent libraries, refer to the DNNDK User
Guide (UG1327).
Hardware Platform
DPU Driver
Lib
API
Vivado
DPU
Example Third Party
bitfile
X22328-022019
Figure 2: Basic Development Flow
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Example System with DPU
The figure below shows an example system block diagram with the Xilinx UltraScale+ MPSoC using a
camera input. DPU is integrated into the system through AXI interconnect to perform deep learning
inference tasks such as image classification, object detection, and semantic segmentation.
DPU
Camera
AXI Interconnect
Controller DDR
ARM R5
DisplayPort
USB3.0
SATA3.1
P CI e Ge n2
GigE
USB2.0
UART
SPI
Quad SPI
NAND
SD
dem os aic gamma Color_
conversion
DMA AXI
Interconnect
AXI
Interconnect
MIPI
CSI2
AXI Interconnect
MIPI
CSI2
X22329-030719
Figure 3: Example System with Integrated DPU
DNNDK
Deep Neural Network Development Kit (DNNDK) is a full-stack deep learning toolchain for inference
with the DPU.
As shown in Figure 4, DNNDK is composed of Deep Compression Tool (DECENT), Deep Neural Network
Compiler (DNNC), Neural Network Runtime (N2Cube), and DPU Profiler.
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DECENT N
2
Cube
DNNC P rof ile r
OS
Hos t CP U DPU
X22330-022019
Figure 4: DNNDK Toolchain
The instructions of DPU are generated offline with DNNDK. Figure 5 illustrates the hierarchy of executing
deep learning applications on the target hardware platform with DPU.
Industry-standard
Libraries Loader
Operating System
Hos t C PU
Deep Learning App
(DPU-accelerated)
P rof ile r Libarary
DPU Driver
DPU
Use r S pac e
Kernel Space
Hardware Platform
X22331-022019
Figure 5: Application Execution Hierarchy
Licensing and Ordering Information
This IP module is provided at no additional cost under the terms of the Xilinx End User License.
Information about this and other IP modules is available at the Xilinx Intellectual Property page. For
information on pricing and availability of other Xilinx IP modules and tools, contact your local Xilinx sales
representative.
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Chapter 2: Product Specification
Hardware Architecture
The detailed hardware architecture of DPU is shown in Figure 6. After start-up, DPU fetches instructions
from the off-chip memory and parses instructions to operate the computing engine. The instructions
are generated by the DNNDK compiler where substantial optimizations have been performed.
To improve the efficiency, abundant on-chip memory in Xilinx® devices is used to buffer the
intermediate data, input, and output data. The data is reused as much as possible to reduce the
memory bandwidth. Deep pipelined design is used for the computing engine. Like other accelerators,
the computational arrays (PE) take full advantage of the fine-grained building blocks, which includes
multiplier, adder, accumulator, etc. in Xilinx devices.
Instruction
Scheduler
CPU (DNNDK)Memory Controller
Bus
Fetcher
Decoder
Dispatcher
On-Chip Buffer
Controller
Data Mover
On-Chip BRAM
BRAM Reader/Writer
Computing
Engine
Conv
Engine
Misc
Engine
PE PE PE
Processing System (PS)
Programmable Logic (PL)
Off-Chip Memory
X22332-022019
Figure 6: DPU Hardware Architecture
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DSP with Enhanced Utilization (DPU_EU)
In the previous DPU version, the general logic and DSP slices work in the same clock domain, though
technically the latter can run at a higher frequency. To enhance the utilization of DSP slices in DPU, the
advanced DPU_EU version was designed.
The EU in “DPU_EU” means enhanced utilization of DSP slices. DSP Double Data Rate (DDR) technique is
used to improve the performance achieved with the device. Therefore, two input clocks for DPU is
needed, one for general logic, and the other for DSP slices. The difference between DPU and DPU_EU is
shown in Figure 7.
All DPU mentioned in this document refer to DPU_EU, unless otherwise specified.
IMG
ram
IMG
ram
WGT
ram
A
D
BB
RES
+
×
DSP48 Slice
A+D
M
clk1x
IMG
ram
IMG
ram
WGT
ram
A
D
B
+
×
DSP48 Slice
A+D
M
clk2x
WGT
ram
RES
0
DLY
RES
1
OUT
0
OUT
1
+
A
DLY
D
DLY
B0
Async
B1
Async
D
Async
A
Async
B
B
SEL
PCIN
P
PCOUT
PCOUT
RES
0
clk1x clk1x
X22333-022019
Figure 7: Difference between DPU and DPU_EU
Port Descriptions
The DPU top-level interfaces are shown in the following figure.
Figure 8: DPU_EU IP Port
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The DPU I/O signals are listed and described in Table 1 .
Table 1: DPU Signal Description
Signal Name Interface Type Width I/O Description
S_AXI
Memory mapped
AXI slave interface
32
I/O
32-bit Memory mapped AXI interface
for registers.
s_axi_aclk
Clock
1
I
AXI clock input for S_AXI
s_axi_aresetn
Reset
1
I
Active-Low reset for S_AXI
dpu_2x_clk
Clock
1
I
Input clock used for DSP unit in DPU.
The frequency is two times of
m_axi_dpu_aclk.
dpu_2x_resetn
Reset
1
I
Active-Low reset for DSP unit
m_axi_dpu_aclk
Clock
1
I
Input clock used for DPU general logic.
m_axi_dpu_aresetn
Reset
1
I
Active-Low reset for DPU general logic
DPUx_M_AXI_INSTR
Memory mapped
AXI master interface
32
I/O
32-bit Memory mapped AXI interface
for instruction of DPU.
DPUx_M_AXI_DATA0
Memory mapped
AXI master interface
128
I/O
128-bit Memory mapped AXI interface
for DPU data fetch.
DPUx_M_AXI_DATA1
Memory mapped
AXI master interface
128
I/O
128-bit Memory mapped AXI interface
for DPU data fetch.
dpu_interrupt
Interrupt
1~3
O
Active-High interrupt output from DPU.
The data width is decided by the DPU
number.
Notes:
1. If only input ports are needed, you can edit the ports in the block diagram and declare at the port
interface level.
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Register Space
The DPU IP implements registers in the programmable logic. Table 2 shows the DPU IP registers. These
registers are accessible from the host CPU through the S_AXI interface.
Reg_dpu_reset
The reg_dpu_reset register controls the resets of all DPU cores integrated in the DPU IP. The lower three
bits of this register control the reset of up to three DPU cores respectively. All the reset signals are
active-High. The details of reg_dpu_reset is shown in Table 2.
Table 2: Reg_dpu_reset
Register Address
Offset
Width Type Description
Reg_dpu_reset
0x004
32
R/W
[0] – reset of DPU core 0
[1] – reset of DPU core 1
[2] – reset of DPU core 2
Reg_dpu_isr
The reg_dpu_isr register represents the interrupt status of all DPU cores integrated in the DPU IP. The
lower three bits of this register shows the interrupt status of up to three DPU cores respectively. The
details of reg_dpu_irq is shown in Table 3.
Table 3: Reg_dpu_isr
Register Address
Offset
Width Type Description
Reg_dpu_isr
0x608
32
R
[0] – interrupt status of DPU core 0
[1] – interrupt status of DPU core 1
[2] – interrupt status of DPU core 2
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Reg_dpu_start
The reg_dpu_start register is the start signal for DPU core. There is one start register for each DPU core.
The details of reg_dpu_start is shown in Table 4.
Table 4: Reg_dpu_start
Register Address
Offset
Width Type Description
Reg_dpu0_start
0x220
32
R/W
Control the start-up of DPU core0.
Reg_dpu1_start
0x320
32
R/W
Control the start-up of DPU core1.
Reg_dpu2_start
0x420
32
R/W
Control the start-up of DPU core2.
BReg_dpu_instr_addr
The reg_dpu_instr_addr register is used to indicate the instruction address of DPU core. There are three
registers which are reg_dpu0_instr_addr, reg_dpu1_instr_addr, and reg_dpu2_instr_addr. The details of
reg_dpu_instr_addr are shown in Table 5.
Table 5: Reg_dpu_instr_addr
Register Address
Offset
Width Type Description
Reg_dpu0_instr_addr
0x20c
32
R/W
[0] –The instruction start address in
external memory for DPU core0.
Reg_dpu1_instr_addr
0x30c
32
R/W
[0] –The instruction start address in
external memory for DPU core1.
Reg_dpu2_instr_addr
0x40c
32
R/W
[0] –The instruction start address in
external memory for DPU core2.
Reg_dpu_base_addr
The reg_dpu_base_addr register is used to indicate the address of input image and parameters for DPU
calculation in the external memory. The width of dpu_base_addr is 40 bits so it can support an address
space up to 1 TB. All registers are 32 bits wide, so two registers are required to represent a 40-bit wide
dpu_base_addr. The reg_dpu0_base_addr0_l represents the lower 32 bits of the base address0 in DPU
core0, and the reg_dpu0_base_addr0_h represents the upper eight bits of the base address0 in DPU
core0.
There are eight groups of DPU base address for each DPU core and in total 24 groups of DPU base
address for up to three DPU cores. The details of reg_dpu_base_addr are shown in Table 6.
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Table 6: Reg_dpu_base_addr
Register Address
Offset
Width Type Description
Reg_dpu0_base_addr0_l
0x224
32
R/W
The lower 32 bits of the base address0 of DPU core0.
Reg_dpu0_base_addr0_h
0x228
32
R/W
The lower 8 bits in the register represent the upper 8
bits of the base address0 of DPU core0.
Reg_dpu0_base_addr1_l
0x22C
32
R/W
The lower 32 bits of the base address1 of DPU core0.
Reg_dpu0_base_addr1_h
0x230
32
R/W
The lower 8 bits in the register represent the upper 8
bits of the base address1 of DPU core0.
Reg_dpu0_base_addr2_l
0x234
32
R/W
The lower 32 bits of the base address2 of DPU core0.
Reg_dpu0_base_addr2_h
0x238
32
R/W
The lower 8 bits in the register represent the upper 8
bits of the base address2 of DPU core0.
Reg_dpu0_base_addr3_l
0x23C
32
R/W
The lower 32 bits of the base address3 of DPU core0.
Reg_dpu0_base_addr3_h
0x240
32
R/W
The lower 8 bits in the register represent the upper 8
bits of the base address3 of DPU core0.
Reg_dpu0_base_addr4_l
0x244
32
R/W
The lower 32 bits of the base address4 of DPU core0.
Reg_dpu0_base_addr4_h
0x248
32
R/W
The lower 8 bits in the register represent the upper 8
bits of the base address4 of DPU core0.
Reg_dpu0_base_addr5_l
0x24C
32
R/W
The lower 32 bits of the base address5 of DPU core0.
Reg_dpu0_base_addr5_h
0x250
32
R/W
The lower 8 bits in the register represent the upper 8
bits of the base address5 of DPU core0.
Reg_dpu0_base_addr6_l
0x254
32
R/W
The lower 32 bits of the base address6 of DPU core0.
Reg_dpu0_base_addr6_h
0x258
32
R/W
The lower 8 bits in the register represent the upper 8
bits of the base address6 of DPU core0.
Reg_dpu0_base_addr7_l
0x25C
32
R/W
The lower 32 bits of the base address7 of DPU core0.
Reg_dpu0_base_addr7_h
0x260
32
R/W
The lower 8 bits in the register represent the upper 8
bits of the base address7 of DPU core0.
Reg_dpu1_base_addr0_l
0x324
32
R/W
The lower 32 bits of the base address0 of DPU core1.
Reg_dpu1_base_addr0_h
0x328
32
R/W
The lower 8 bits in the register represent the upper 8
bits of the base address0 of DPU core1.
Reg_dpu1_base_addr1_l
0x32C
32
R/W
The lower 32 bits of the base address1 of DPU core1.
Reg_dpu1_base_addr1_h
0x330
32
R/W
The lower 8 bits in the register represent the upper 8
bits of the base address1 of DPU core1.
Reg_dpu1_base_addr2_l
0x334
32
R/W
The lower 32 bits of the base address2 of DPU core1.
Reg_dpu1_base_addr2_h
0x338
32
R/W
The lower 8 bits in the register represent the upper 8
bits of the base address2 of DPU core1.
Reg_dpu1_base_addr3_l
0x33C
32
R/W
The lower 32 bits of the base address3 of DPU core1.
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Reg_dpu1_base_addr3_h
0x340
32
R/W
The lower 8 bits in the register represent the upper 8
bits of the base address3 of DPU core1.
Reg_dpu1_base_addr4_l
0x344
32
R/W
The lower 32 bits of the base address4 of DPU core1.
Reg_dpu1_base_addr4_h
0x348
32
R/W
The lower 8 bits in the register represent the upper 8
bits of the base address4 of DPU core1.
Reg_dpu1_base_addr5_l
0x34C
32
R/W
The lower 32 bits of the base address5 of DPU core1.
Reg_dpu1_base_addr5_h
0x350
32
R/W
The lower 8 bits in the register represent the upper 8
bits of the base address5 of DPU core1.
Reg_dpu1_base_addr6_l
0x354
32
R/W
The lower 32 bits of the base address6 of DPU core1.
Reg_dpu1_base_addr6_h
0x358
32
R/W
The lower 8 bits in the register represent the upper 8
bits of the base address6 of DPU core1.
Reg_dpu1_base_addr7_l
0x35C
32
R/W
The lower 32 bits of the base address7 of DPU core1.
Reg_dpu1_base_addr7_h
0x360
32
R/W
The lower 8 bits in the register represent the upper 8
bits of the base address7 of DPU core1.
Reg_dpu2_base_addr1_l
0x42C
32
R/W
The lower 32 bits of the base address1 of DPU core2.
Reg_dpu2_base_addr1_h
0x430
32
R/W
The lower 8 bits in the register represent the upper 8
bits of the base address1 of DPU core2.
Reg_dpu2_base_addr2_l
0x434
32
R/W
The lower 32 bits of the base address2 of DPU core2.
Reg_dpu2_base_addr2_h
0x438
32
R/W
The lower 8 bits in the register represent the upper 8
bits of the base address2 of DPU core2.
Reg_dpu2_base_addr3_l
0x43C
32
R/W
The lower 32 bits of the base address3 of DPU core2.
Reg_dpu2_base_addr3_h
0x440
32
R/W
The lower 8 bits in the register represent the upper 8
bits of the base address3 of DPU core2.
Reg_dpu2_base_addr4_l
0x444
32
R/W
The lower 32 bits of the base address4 of DPU core2.
Reg_dpu2_base_addr4_h
0x448
32
R/W
The lower 8 bits in the register represent the upper 8
bits of the base address4 of DPU core2.
Reg_dpu2_base_addr5_l
0x44C
32
R/W
The lower 32 bits of the base address5 of DPU core2.
Reg_dpu2_base_addr5_h
0x450
32
R/W
The lower 8 bits in the register represent the upper 8
bits of the base address5 of DPU core2.
Reg_dpu2_base_addr6_l
0x454
32
R/W
The lower 32 bits of the base address6 of DPU core2.
Reg_dpu2_base_addr6_h
0x458
32
R/W
The lower 8 bits in the register represent the upper 8
bits of the base address6 of DPU core2.
Reg_dpu2_base_addr7_l
0x45C
32
R/W
The lower 32 bits of the base address7 of DPU core2.
Reg_dpu2_base_addr7_h
0x460
32
R/W
The lower 8 bits in the register represent the upper 8
bits of the base address7 of DPU core2.
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Interrupts
Upon the completion of one DPU task, an interrupt from DPU occurs to signal the completion of the
task. The active-High of the Reg_dpu0_start means the start of a DPU task for DPU core0. At the end of
the DPU task, DPU sends an interrupt and one bit in the register Reg_dpu_isr is set to 1. The position of
the active bit in the Reg_dpu_isr depends on the number of DPU cores. For example, when the DPU
core1 finishes a task while the DPU core 0 is still working, the Reg_dpu_isr is set as 2, the lowest bit is 0,
and the lower bit is 1.
The data width of dpu_interrupt is determined by the number of DPU cores. When the parameter of
DPU_NUM is set to 2, it means the DPU IP is integrated with two DPU cores, and the data width of the
dpu_interrupt signal is two bits. The lower bit represents the DPU core 0 interrupt and the higher bit
represents the DPU core1 interrupt.
The interrupt connection between the DPU and PS is described in the Device Tree file, which indicates
the interrupt number of DPU connected to the PS. The reference connection is shown as Figure 9.
Figure 9: Reference Connection for DPU Interrupt
Notes:
1. If DPU is working with the DNNDK package, you should connect the dpu_interrupt at the 10th bit in
the irq signal of PS. For example, if the DPU_NUM is set as 2, the 2-bit dpu_interrupt should connect
with irq10 and irq11 of PS.
2.
irq7~irq0 corresponds to pl_ps_irq0[7:0].
3.
irq15~irq8 corresponds to pl_ps_irq1[7:0].
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Chapter 3: DPU Configuration
Introduction
The DPU IP provides some user-configurable parameters to optimize the resources or the support of
different features. You can select different configurations to use on the preferred DSP slices, LUT, block
RAM, and UltraRAM utilization based on the programmable logic resources that are allowed. There is
also an option to determine the number of DPU cores that will be used.
The deep neural network features and the associated parameters supported by DPU is shown in the
following table.
Table 7: Deep Neural Network Features and Parameters Supported by DPU
Features Description
Convolution
Kernel Sizes
W: 1-16 H: 1-16
Strides
W: 1-4 H:1-4
Padding_w
1: kernel_w-1
Padding_h
1: kernel_h-1
Input Size
Arbitrary
Input Channel
1 – 256*channel_parallel
Output Channel
1 – 256*channel_parallel
Activation
ReLU & LeakyReLU
Dilation
dilation * input_channel <= 256 * channel_parallel
&& stride_w == 1 && stride_h == 1
Deconvolution
Kernel Sizes
W: 1-16 H: 1-16
Stride_w
stride_w * output_channel <= 256 *
channel_parallel
Stride_h
Arbitrary
Padding_w
1: kernel_w-1
Padding_h
1: kernel_h-1
Input Size
Arbitrary
Input Channel
1 – 256 * channel_parallel
Output Channel
1 – 256 * channel_parallel
Activation
ReLU & LeakyReLU
Max Pooling
Kernel Sizes
W: 1-16 H: 1-16
Strides
W: 1-4 H:1-4
Padding
W: 1-4 H: 1-4
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DPU IP Product Guide www.xilinx.com 19
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Element Wise
Input channel
1 – 256*channel_parallel
Input size
arbitrary
Concat
Output channel
1 – 256*channel_parallel
Reorg Strides
stride * stride * input_channel <= 256 *
channel_parallel
FC
Input_channel
Input_channel <= 2048*channel_parallel
Output_channel
Arbitrary
Notes:
1. The parameter channel_parallel is determined by the DPU configuration . For example, the
channel_parallel of DPU-B1152 is 12, the channel_parallel of DPU-B4096 is 16.
Configuration Options
You can configure the DPU with some predefined options which includes DPU core number, DPU
convolution architecture, DSP cascade, DSP usage, and UltraRAM usage. These options enable the DPU
IP configurable in terms of DSP slice, LUT, block RAM, and UltraRAM utilization.
Figure 10 shows the DPU
configuration.
Figure 10: DPU Configuration
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Chapter 3: DPU Configuration
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PG338 (v1.2) March 26, 2019
DPU Core Number
You can use up to three DPU cores can be included in one IP. Multiple DPU cores can be used to achieve
higher performance. Consequently, it consumes more programmable logic resource.
If the requirement is to integrate more than three cores, send the request to a Xilinx ® sales
representative.
DPU Convolution Architecture
The DPU IP can be configured with different convolution architectures which is related to the
parallelism of the convolution unit. The optional architecture for DPU IP includes
B512, B800, B1024,
B1152, B1600, B2304, B3136, and B4096.
There are three dimensions of parallelism in the DPU convolution architecture - pixel parallelism, input
channel parallelism, and output channel parallelism. The input channel parallelism is always equal to the
output channel parallelism. The different convolution architecture requires different programmable
logic resource. The larger convolution architecture can achieve higher performance with more
resources. The parallelism for different convolution architecture is listed in Table 8.
Table 8: Parallelism for Different Convolution Architecture
Convolution
Architecture
Pixel
Parallelism
(PP)
Input Channel
Parallelism (ICP)
Output Channel
Parallelism
(OCP)
Peak Ops
(operations/per
clk)
B512
4
8
8
512
B800
4
10
10
800
B1024
8
8
8
1024
B1152
4
12
12
1150
B1600
8
10
10
1600
B2304
8
12
12
2304
B3136
8
14
14
3136
B4096
8
16
16
4096
Notes:
1. In each clock cycle, the convolution array finishes a multiplication and an accumulation, which
are two operations. So, the peak operations per cycle is equal to PP*ICP*OCP*2.
DSP Cascade
You can select the maximal length of DSP48E slice cascade chain. Typically, the larger cascade length
indicates less logic resources, but it might lead to worse timing. The smaller cascade length might
use more fabric resources which is not economical for small devices. Xilinx recommends selecting the
mid-value, which is 4, in the first iteration and adjust the value if the timing is not met.
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