Xilinx ML628 User manual

ML628 IBERT
Getting Started Guide
(ISE 13.1)
UG806 (v1.0) May 20, 2011

ML628 IBERT Getting Started Guide www.xilinx.com UG806 (v1.0) May 20, 2011
© Copyright 2011 Xilinx, Inc. Xilinx, the Xilinx logo, Artix, ISE, Kintex, Spartan, Virtex, Zynq, and other designated brands included herein
are trademarks of Xilinx in the United States and other countries. All other trademarks are the property of their respective owners.
DISCLAIMER
The information disclosed to you hereunder (the “Materials”) is provided solely for the selection and use of Xilinx products. To the maximum
extent permitted by applicable law: (1) Materials are made available "AS IS" and with all faults, Xilinx hereby DISCLAIMS ALL
WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and (2) Xilinx shall not be liable (whether
in contract or tort, including negligence, or under any other theory of liability) for any loss or damage of any kind or nature related to, arising
under, or in connection with, the Materials (including your use of the Materials), including for any direct, indirect, special, incidental, or
consequential loss or damage (including loss of data, profits, goodwill, or any type of loss or damage suffered as a result of any action
brought by a third party) even if such damage or loss was reasonably foreseeable or Xilinx had been advised of the possibility of the same.
Xilinx assumes no obligation to correct any errors contained in the Materials, or to advise you of any corrections or update. You may not
reproduce, modify, distribute, or publicly display the Materials without prior written consent. Certain products are subject to the terms and
conditions of the Limited Warranties which can be viewed at http://www.xilinx.com/warranty.htm; IP cores may be subject to warranty and
support terms contained in a license issued to you by Xilinx. Xilinx products are not designed or intended to be fail-safe or for use in any
application requiring fail-safe performance; you assume sole risk and liability for use of Xilinx products in Critical Applications:
http://www.xilinx.com/warranty.htm#critapps.
Revision History
The following table shows the revision history for this document.
Date Version Revision
05/20/11 1.0 Initial Xilinx release.

ML628 IBERT Getting Started Guide www.xilinx.com 3
UG806 (v1.0) May 20, 2011
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Chapter 1: ML628 IBERT Getting Started Guide
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Setting Up the ML628 Board. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Extracting the Project Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Running the GTH IBERT Demonstration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Connecting the GTH Transceivers and Reference Clocks . . . . . . . . . . . . . . . . . . . . . . . . 7
Attach the GTH Quad Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
GTH Transceiver Clock Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
GTH TX/RX Loopback Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Configuring the FPGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Setting Up the ChipScope Pro Software . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Starting the SuperClock-2 Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Viewing GTH Transceiver Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
In Case of RX Bit Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
DC Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Closing the IBERT Demonstration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
More Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Running the GTX IBERT Demonstration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Connecting the GTX Transceivers and Reference Clocks . . . . . . . . . . . . . . . . . . . . . . . 20
Attach the GTX Quad Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
GTX Transceiver Clock Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
GTX TX/RX Loopback Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Configuring the FPGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Setting Up the ChipScope Pro Software . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Starting the SuperClock-2 Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Viewing GTX Transceiver Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Closing the IBERT Demonstration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
More Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
SuperClock-2 Frequency Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
IBERT Demonstration Designs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Source Directories and Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
IBERT Design Files. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
example_ibert_v6_q1xx_top.bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
example_implement_ibert_v6_q1xx.prj . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
example_implement_ibert_v6_q1xx.xst . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
i2c_sclk2_control.ngc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
ibert_v6_q1xx.ngc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
icon_v6_1.ngc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
vio_v6_si84_so78.ngc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
implement.bat. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
example_ibert_v6_q1xx.v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
i2c_sclk2_control_bb.v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
ibert_v6_qxxx_top.ucf. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Table of Contents

4www.xilinx.com ML628 IBERT Getting Started Guide
UG806 (v1.0) May 20, 2011
vio_sclk2_control.v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Creating the GTH IBERT Core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Creating the GTX IBERT Core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Warranty. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

ML628 IBERT Getting Started Guide www.xilinx.com 5
UG806 (v1.0) May 20, 2011
Chapter 1
ML628 IBERT Getting Started Guide
Overview
This document provides a procedure for setting up the ML628 Virtex®-6 FPGA
GTX and GTH Transceiver Characterization Board to run the Integrated Bit Error Ratio
Test (IBERT) demonstration. The designs that are required to run the IBERT demonstration
are stored in a CompactFlash (CF) memory card that is provided with the ML628 board.
The demonstration shows the capabilities of the Virtex-6 XC6VHX380T FPGA GTX and
GTH transceivers.
The ML628 board is described in detail in UG771, ML628 Virtex-6 FPGA GTX and GTH
Transceiver Characterization Board User Guide.
The IBERT demonstrations operate one GTH or GTX Quad at a time. Separate procedures
are provided for GTH and GTX transceiver evaluation. The GTH procedure consists of:
1. Setting Up the ML628 Board.
2. Extracting the Project Files.
3. Connecting the GTH Transceivers and Reference Clocks.
4. Configuring the FPGA.
5. Setting Up the ChipScope Pro Software.
6. Viewing GTH Transceiver Operation.
7. Closing the IBERT Demonstration.
The GTX procedure consists of:
1. Setting Up the ML628 Board.
2. Extracting the Project Files.
3. Connecting the GTX Transceivers and Reference Clocks.
4. Configuring the FPGA.
5. Setting Up the ChipScope Pro Software.
6. Viewing GTX Transceiver Operation.
7. Closing the IBERT Demonstration.

6www.xilinx.com ML628 IBERT Getting Started Guide
UG806 (v1.0) May 20, 2011
Requirements
Requirements
The hardware and software required to run the GTX or GTH IBERT demonstrations are:
• ML628 Virtex-6 FPGA GTH and GTX Transceiver Characterization Board including:
• Two CF cards containing the IBERT demonstration designs ( IBERT #1 and
IBERT #2)
•OneSamtecBullsEyecable
• Eight SMA female-to-female (F-F) adapters
• Eight SMA (female-to-male) DC Blocks (optional)
• GTH transceiver power supply module (installed on board)
• GTX transceiver power supply module (installed on board)
• SuperClock-2 module (installed on board)
•ActiveBGAHeatsink(installed on FPGA)
• 12V DC power adapter
•JTAGcable:
• Platform Cable USB (Xilinx part number DLC9, DLC9G, or DLC9LP) or,
• Platform Cable USB II (Xilinx part number DLC10) or,
• Parallel Cable IV (Xilinx part number PC4)
• Host PC with:
• CF card reader or PCMCIA adapter card for CF cards
•USBports
• Xilinx® ChipScope™ Pro software, version 13.1 or higher.
Software is available at: http://www.xilinx.com/chipscopepro
The hardware and software required to rebuild the IBERT demonstration designs are:
• Xilinx ISE® Design Suite version 13.1 or higher
• PC with a version of the Windows operating system supported by Xilinx ISE Design
Suite
• ML628 IBERT demonstration design source files (provided online as collection
rdf0117_13-1.zip) at:
http://www.xilinx.com/products/boards/ml628/reference_designs.htm
Setting Up the ML628 Board
This section describes how to set up the ML628 Virtex-6 FPGA GTH and GTX Transceiver
Characterization Board.
Caution! The ML628 board can be damaged by electrostatic discharge (ESD). Follow standard
ESD prevention measures when handling the board.
When the ML628 board ships from the factory, it is configured for the GTH and GTX IBERT
demonstrations described in this document. If the board has been re-configured it must be
returned to the default set-up before running the IBERT demonstrations.
1. Move all jumpers to their default positions. The default jumper positions are listed in
UG771, ML628 Virtex-6 FPGA GTX and GTH Transceiver Characterization Board User
Guide.

ML628 IBERT Getting Started Guide www.xilinx.com 7
UG806 (v1.0) May 20, 2011
Extracting the Project Files
2. Install the GTX and GTH transceiver power modules:
a. Plug the GTX transceiver power module into connectors J34 and J179.
b. Plug the GTH transceiver power module into connectors J6 and J197.
3. Install the SuperClock-2 module:
a. Align the three metal standoffs on the bottom side of the module with the three
mounting holes in the CLOCK MODULE interface of the ML628 board.
b. Using three 4-40 x 0.25 inch screws, firmly screw down the module from the
bottom of the ML628 board.
c. On the SuperClock-2 module, place a jumper across pins 2–3 (2V5) of the
CONTROL VOLTAGE header, J18.
Extracting the Project Files
The ChipScope Pro Software .cpj project files for the IBERT demonstrations are located in
ml628_cpj.zip on the CF card labeled IBERT #1. They are also available online along
with .bit files for all 16 designs (as collection rdf0116_13-1.zip) at:
http://www.xilinx.com/products/boards/ml628/reference_designs.htm
ml628_cpj.zip contains two project files: ml628_gth.cpj and ml628_gtx.cpj.
These files are used to load pre-saved MGT/IBERT and SuperClock-2 module control
settings for the GTH and GTX demonstrations.
To copy the files from the CompactFlash memory card:
1. Connect the CompactFlash memory card to the host computer.
Note: The CompactFlash memory card can be plugged into a host PC’s PCMCIA interface
using a PCMCIA adapter card.
2. Locate the file ml628_cpj.zip on the Compact Flash memory card.
3. Unzip the files to a working directory on the host computer.
Running the GTH IBERT Demonstration
The GTH IBERT demonstration operates one GTH Quad at a time. This section describes
how to test GTH Quad 117. The remaining GTH Quads are tested following a similar series
of steps. The GTX IBERT demonstration is described in Running the GTX IBERT
Demonstration, page 20.
Connecting the GTH Transceivers and Reference Clocks
Figure 1-1 shows the locations for GTH transceiver Quads 106, 107, 108, 116, 117, and 118
on the ML628 board.
Note: Figure 1-1 is for reference only and might not reflect the current revision of the board.

8www.xilinx.com ML628 IBERT Getting Started Guide
UG806 (v1.0) May 20, 2011
Running the GTH IBERT Demonstration
With the exception of GTH Quad 116, all GTH transceiver pins and reference clock pins are
routed from the FPGA to a connector pad which interfaces with Samtec BullsEye
connectors. Figure 1-2 Ashows the connector pad. Figure 1-2 Bshows the connector
pinout.
X-Ref Target - Figure 1-1
Figure 1-1: GTH Quad Locations
UG806_c1_01_041411
QUAD_117
QUAD_118
QUAD_116
QUAD_108
QUAD_107
QUAD_106
X-Ref Target - Figure 1-2
Figure 1-2: A – GTH Connector Pad. B – GTH Connector Pinout
UG806_c1_02_041411
GTH Connector Pinout
BGTH
P
P
P
P
P
P
P
P
P
P
N
N
N
N
N
N
N
N
N
N
TX0
RX0
CLK0
NC
TX1
RX2
TX3
RX3
TX2
RX1
GTH Connector Pad
A

ML628 IBERT Getting Started Guide www.xilinx.com 9
UG806 (v1.0) May 20, 2011
Running the GTH IBERT Demonstration
Transmitter pairs TX0 and TX1 on Quad 116 are not connected to the BullsEye connector
pads. Refer to UG771, ML628 Virtex-6 FPGA GTX and GTH Transceiver Characterization
Board User Guide for details on accessing these signals.
The SuperClock-2 module provides LVDS clock outputs for the GTH and GTX transceiver
reference clocks in the IBERT demonstrations. Figure 1-3 shows the locations of the
differential clock SMA connectors on the clock module which can be connected to the
reference clock cables. The four SMA pairs labeled CLKOUT provide LVDS clock outputs
from the Si5368 clock multiplier/jitter attenuator device on the clock module. The SMA
pair labeled Si570_CLK provides LVPECL clock output from the Si570 programmable
oscillator on the clock module. For the GTH IBERT demonstration, the output clock
frequencies are preset to 174.690 MHz. For more information regarding the SuperClock-2
module, refer to UG770, HW-CLK-101-SCLK2 SuperClock-2 Module User Guide.
Note: The image in Figure 1-3 is for reference only and might not reflect the current revision of the
board.
Attach the GTH Quad Connector
Attach the Samtec BullsEye connector to the connector pad for GTH Quad 117 (Figure 1-4),
aligning the two indexing pins on the bottom of the connector with the guide holes on the
board. Hold the connector flush with the board and fasten it by tightening the two captive
screws.
X-Ref Target - Figure 1-3
Figure 1-3: SuperClock-2 Module Output Clock SMA Locations
UG725_c1_03_102010
CLKOUT3_N
CLKOUT1_N
SI570_CLK_N
SI570_CLK_P CLKOUT1_P
CLKOUT2_NCLKOUT4_N
CLKOUT2_P CLKOUT3_P CLKOUT4_P
X-Ref Target - Figure 1-4
Figure 1-4: BullsEye Connector Attached to Quad 117
UG806_c1_04_022411

10 www.xilinx.com ML628 IBERT Getting Started Guide
UG806 (v1.0) May 20, 2011
Running the GTH IBERT Demonstration
GTH Transceiver Clock Connections
Refer to Figure 1-2, page 8 to identify the P and N coax cables that are connected to the
reference clock (CLK0). Connect these cables to the SuperClock-2 Module as follows:
• CLK0_P coax cable → SMA connector J5 (CLKOUT1_P on the SuperClock-2 Module)
• CLK0_N coax cable → SMA connector J6 (CLKOUT1_N on the SuperClock-2 Module)
Note: Any one of the five differential outputs from the SuperClock-2 Module can be used to source
the GTH reference clock. CLKOUT1_P and CLKOUT1_N are used here as an example.
GTH TX/RX Loopback Connections
Refer to Figure 1-2, page 8 to identify the P and N coax cables that are connected to the four
receivers (RX0, RX1, RX2 and RX3) and the four transmitters (TX0, TX1, TX2 and TX3). Use
eight SMA female-to-female (F-F) adapters (Figure 1-5) to connect the transmit and receive
cables as shown in Figure 1-6 and as detailed below:
•TX0_P→ SMA F-F Adapter → RX0_P
•TX0_N→ SMA F-F Adapter → RX0_N
•TX1_P→ SMA F-F Adapter → RX1_P
•TX1_N→ SMA F-F Adapter → RX1_N
•TX2_P→ SMA F-F Adapter → RX2_P
•TX2_N→ SMA F-F Adapter → RX2_N
•TX3_P→ SMA F-F Adapter → RX3_P
•TX3_N→ SMA F-F Adapter → RX3_N
X-Ref Target - Figure 1-5
Figure 1-5: SMA F-F Adapter
X-Ref Target - Figure 1-6
Figure 1-6: TX-To-RX Loopback Connection Example
UG806_c1_05_022411
RX Coax
TX Coax
SMA F-F Adapter
UG806_c1_06_022811

ML628 IBERT Getting Started Guide www.xilinx.com 11
UG806 (v1.0) May 20, 2011
Running the GTH IBERT Demonstration
Figure 1-7 shows the ML628 board with the cable connections required for the Quad 117
GTH IBERT demonstration.
Configuring the FPGA
This section describes how to configure the FPGA using the CF cards included with the
board. The FPGA can also be configured through ChipScope Pro or iMPACT software
using the .bit files which are available online (as collection rdf0116_13-1.zip) at:
http://www.xilinx.com/products/boards/ml628/reference_designs.htm
To configure from the CF card:
1. Insert the CF card labeled IBERT #1 into the CF card reader slot located on the
bottom-side (upper-right corner) of the board.
2. Plug the 12V output from the power adapter into connector J122.
3. Connect the programming cable to the host computer. Any of these cables can be used:
•PlatformCableUSB-II(DLC10)
• Platform Cable USB (DLC9, DLC9G or DLC9LP)
X-Ref Target - Figure 1-7
Figure 1-7: Cable Connections for Quad 117 GTH IBERT Demonstration
UG806_c1_07_051111
CLKOUT1_P
CLKOUT1_N
QUAD_117
TX/RX Loopback Connections

12 www.xilinx.com ML628 IBERT Getting Started Guide
UG806 (v1.0) May 20, 2011
Running the GTH IBERT Demonstration
• Parallel Cable IV (PC4)
Connect the ribbon cable between the programming cable and the ML628 board at
JTAG connector J1.
4. Select the GTH IBERT demonstration with the System Ace™ controller CFG
ADDRESS switch, SW3. The setting on this 3-bit DIP switch (Figure 1-8) selects the file
used to configure the FPGA. A switch is in the ON position if it switched towards the
ON text printed on the DIP; otherwise, it is OFF. For the Quad 117 GTH IBERT
demonstration, set: ADR2 = ON, ADR1 = OFF, and ADR0 = OFF.
There is one IBERT demonstration design for each GTH and GTX Quad on the ML628
board, for a total of 16 designs. The designs are organized and stored on the two CF
cards (IBERT #1 and IBERT #2) as shown in Table 1-1.
5. Place the main power switch SW1 to the ON position.
X-Ref Target - Figure 1-8
Figure 1-8: Configuration Address DIP Switch (SW3)
Table 1-1: CF Card Contents and Configuration Addresses
CF Card Demonstration
Design ADR2 ADR1 ADR0
IBERT #1
GTH Quad 106 OFF OFF OFF
GTH Quad 107 OFF OFF ON
GTH Quad 108 OFF ON OFF
GTH Quad 116 OFF ON ON
GTH Quad 117 ON OFF OFF
GTH Quad 118 ON OFF ON
GTX Quad 100 ON ON OFF
GTX Quad 101 ON ON ON
IBERT #2
GTX Quad 102 OFF OFF OFF
GTX Quad 103 OFF OFF ON
GTX Quad 104 OFF ON OFF
GTX Quad 105 OFF ON ON
GTX Quad 112 ON OFF OFF
GTX Quad 113 ON OFF ON
GTX Quad 114 ON ON OFF
GTX Quad 115 ON ON ON
UG806_c1_08_022511
CFG
ADDRESS
ADR0
ADR1
ADR2
SW3ADR0 = OFF
ADR2 = ON
123
ON
ADR1 = OFF

ML628 IBERT Getting Started Guide www.xilinx.com 13
UG806 (v1.0) May 20, 2011
Running the GTH IBERT Demonstration
Setting Up the ChipScope Pro Software
1. Start the ChipScope Pro analyzer tool on the host computer and select
File → Open Project.
2. When the Project window opens, navigate to the directory where the ChipScope
software project files (.cpj) were extracted. Select ml628_gth.cpj and click Open.
The .cpj file loads pre-saved project settings for the demonstration including MGT/
IBERT and clock module control parameters. For more information regarding MGT/
IBERT settings, refer to www.xilinx.com/support/documentation/sw_manuals/
xilinx13_1/chipscope_pro_sw_cores_ug029.pdf, UG029 - ChipScope Pro Software Cores.
3. Click the Open Cable button (Figure 1-9).
4. When the dialog opens asking to set up the core with the settings from the current
project, click Yes (Figure 1-10).
Note: After completing step 4, the IBERT Console will open and display No Link on all four
lanes (Figure 1-11) and error messages will begin scrolling in the status panel at the bottom of
the GUI (Figure 1-12). This is due to a limitation in this revision of the GTH IBERT core. At this
point the IBERT core is loaded and running, but the outputs of the Si5368 on the SuperClock-2
X-Ref Target - Figure 1-9
Figure 1-9: Open Cable Button
UG806_c1_09_022511
Open Cable Button
X-Ref Target - Figure 1-10
Figure 1-10: Core Settings Dialog
ug806_c1_10_030311

14 www.xilinx.com ML628 IBERT Getting Started Guide
UG806 (v1.0) May 20, 2011
Running the GTH IBERT Demonstration
module are not enabled. Normally, a graceful re-start can be achieved by enabling the reference
clock and resetting the core. However, the issue is that the signal from the QUAD Reset button
does not reach the reset logic in the core. The workaround is to reload the core which is
described later in this procedure. This limitation will be fixed in a later release.
Note: Unlike the Si5368, the Si570 on the SuperClock-2 module is an always-on clock source.
As such, this problem will not be observed if this procedure is run with the GTH reference clock
inputs connected to Si570 outputs on the SuperClock-2 module (Si570_CLK_P and
Si570_CLK_N).
Note: This is a limitation of the GTH IBERT core only. It does not exist in the GTX IBERT core.
X-Ref Target - Figure 1-11
Figure 1-11: GTH IBERT 2.03a with No Reference Clock
ug806_c1_11_041411

ML628 IBERT Getting Started Guide www.xilinx.com 15
UG806 (v1.0) May 20, 2011
Running the GTH IBERT Demonstration
Starting the SuperClock-2 Module
The IBERT demonstration designs use an integrated ChipScope Pro software VIO core to
control the clocks on the SuperClock-2 module. The SuperClock-2 module features two
clock-source components: 1) An always-on Si570 crystal oscillator and, 2) an Si5386
jitter-attenuating clock multiplier. Outputs from either device can be used to drive the
transceiver reference clocks. To start the SuperClock-2 Module:
1. In the Project Panel, double-click VIO Console (Figure 1-13).
2. The clock sources on the SuperClock-2 module are controlled from the VIO Console.
Click on the Si5368 Start button (Figure 1-14) to enable the clock output.
Note: The ROM address values for the Si5360 and Si570 devices (i.e., Si5368 ROM Addr and
Si570 ROM Addr) are preset to 44 to produce an output frequency of 174.69 MHz. Entering a
different ROM address changes the reference clock(s) frequency. The complete list of
pre-programmed SuperClock-2 frequencies and their associated ROM addresses is provided in
Table 1-2, page 31.
X-Ref Target - Figure 1-12
Figure 1-12: GTH IBERT 2.03a with No Reference Clock
ug806_c1_12_041411
X-Ref Target - Figure 1-13
Figure 1-13: Project Panel - VIO Console (GTH)
UG806_c1_13_041411

16 www.xilinx.com ML628 IBERT Getting Started Guide
UG806 (v1.0) May 20, 2011
Running the GTH IBERT Demonstration
Note: Perform step 3 through step 8 as part of the GTH IBERT workaround described previously
in this procedure (see notes included with step 4, page 13).
3. Close the ChipScope application by selecting File → Exit. Do not save the changes
when prompted. Do not power down the board.
4. Press and release the System ACE controller reset button (SW2) on the ML628 board to
reload the GTH IBERT demonstration design.
5. Restart the ChipScope application and select File → Open Project.
6. When the Open Project window appears, select ml628_gth.cpj and click Open.
7. Click the Open Cable button (Figure 1-15).
X-Ref Target - Figure 1-14
Figure 1-14: Si5368 Address, Frequency and Start Button
UG806_c1_14_041411
Si5358start button
The ROM address value for the
Si5368clock multiplier is preset to 44
(174.690 MHz)

ML628 IBERT Getting Started Guide www.xilinx.com 17
UG806 (v1.0) May 20, 2011
Running the GTH IBERT Demonstration
8. When the dialog appears asking to set up the core with the settings from the current
project, click Yes (Figure 1-16).
Note: Restarting the SuperClock-2 module is not required. The Si5268 clock outputs will be
enabled and running at the correct frequency.
X-Ref Target - Figure 1-15
Figure 1-15: Open Cable Button
UG806_c1_15_041411
Open Cable Button
X-Ref Target - Figure 1-16
Figure 1-16: IBERT V6GTH Project Settings
ug806_c1_16_041411

18 www.xilinx.com ML628 IBERT Getting Started Guide
UG806 (v1.0) May 20, 2011
Running the GTH IBERT Demonstration
9. In the project panel, double-click IBERT Console (Figure 1-17).
10. At the top of the ChipScope Pro analyzer window, click the Reset All button
(Figure 1-18).
11. When prompted “Are you sure you want to reset all Channels and Counters?” Click
Yes.
Viewing GTH Transceiver Operation
After completing step 11 in Starting the SuperClock-2 Module, the IBERT demonstration is
configured and running. The status and test settings are displayed on the MGT/IBERT
Settings tab in the IBERT Console shown in Figure 1-19.
Note the line rate, TX differential output swing, and RX bit error count:
• The line rate for all four GTX transceivers is 11.18 Gps (see MGT Link Status in
Figure 1-19).
• The GTX transmitter differential output swing is preset to 800 mV.
• Verify that there are no bit errors. If the count is not zero, see In Case of RX Bit Errors.
X-Ref Target - Figure 1-17
Figure 1-17: Project Panel - IBERT Console (GTH)
X-Ref Target - Figure 1-18
Figure 1-18: Reset All Button
UG806_c1_17_041411
UG806_c1_18_041411

ML628 IBERT Getting Started Guide www.xilinx.com 19
UG806 (v1.0) May 20, 2011
Running the GTH IBERT Demonstration
In Case of RX Bit Errors
If after the Reset All button (Figure 1-18) has been pressed the RX Bit Error Count for one
or more Quads displays a non-zero value, click the respective BERT Reset button
(Figure 1-20) to zero the count.
If RX bit errors persist after clicking the BERT Reset buttons, additional tuning of the
transceivers might be required and/or one or more DC blocks might need to be installed in
line with the loopback cables. See DC Blocks for installation instructions.
DC Blocks
The GTH receiver analog front end (AFE) does not support DC coupling (see UG371,
Virtex-6 FPGA GTH Transceivers User Guide for details). For this reason, a DC component in
X-Ref Target - Figure 1-19
Figure 1-19: GTH IBERT Console
ug806_c1_19_050411
X-Ref Target - Figure 1-20
Figure 1-20: Resetting the RX Bit Error Count
UG806_c1_20_041411

20 www.xilinx.com ML628 IBERT Getting Started Guide
UG806 (v1.0) May 20, 2011
Running the GTX IBERT Demonstration
the signal can result in bit errors being observed by the receiver. Sixteen in-line DC blocks
are included with the ML628 board and are provided to filter the DC component in the
signal path. To use the DC block in loopback, screw one end into to the SMA F-F adapter
and then connect the RX and TX cables to each end of the union (Figure 1-21). Install a DC
block to both the P and N signals of each lane where bit errors are observed.
Closing the IBERT Demonstration
To stop the IBERT demonstration:
1. Close the ChipScope application by selecting File → Exit.
Note: Do not save changes to the project.
2. Place the main power switch SW1 in the off position.
More Information
Additional information on the ChipScope Pro software and GTH IBERT core can be found
in:
•www.xilinx.com/support/documentation/sw_manuals/xilinx13_1/
chipscope_pro_sw_cores_ug029.pdf, UG029 - ChipScope Pro Software Cores
•http://www.xilinx.com/support/documentation/ip_documentation/
chipscope_ibert_virtex6_gth.pdf, DS755 - ChipScope Integrated Bit Error Ratio Test
(IBERT) for Virtex-6 GTH.
Running the GTX IBERT Demonstration
The GTX IBERT demonstration operates one GTX Quad at a time. This section describes
how to test GTX Quad 100. The remaining GTX Quads are tested following a similar series
of steps. The GTH IBERT demonstration is described in Running the GTH IBERT
Demonstration, page 7.
Connecting the GTX Transceivers and Reference Clocks
Figure 1-22 shows the locations for GTX transceiver Quads 100, 101, 102, 103, 104, 105, 112,
113, 114, and 115 on the ML628 board.
Note: Figure 1-22 is for reference only and might not reflect the current revision of the board.
X-Ref Target - Figure 1-21
Figure 1-21: Loopback Connection with DC Block
TX Coax
RX Coax SMA F-F Adapter
UG806_c1_21_041411
DC Block