Alinco DJ-493 User manual

DJ-493
DJ-496/438
Service Manual
CONTENTS
SPECIFICATIONS
1) G EN ERAL.............................................................................2
2) TRANSM ITTER...................................................................2
3) RECEIVER............................................................................2
CIRCUIT DESCRIPTION
1) Receiver S ystem ............................................................3, 4
2) Tr nsmitter System .............................................................4
3) PLL Synthesizer C ircuit ............................................... 4, 5
4) CPU nd Peripher l Circuits ............................ . ......... 5, 6
5) M38267M8L252GP (XA0725)..................................... 6 - 8
SEMICONDUCTOR DATA
1) NMJ2070M T 1 (XA0210) ..................................................9
2) AT24C16N-10SI-2.7TER (XA0368)................................9
3) M5222FP-600C (XA0385) ............................................. 10
4) TK14521MTL (XA0515).................................................. 11
5) M64076AGP (XA0352) ................................................... 12
6) NJM2904V-TE1 (XA0573) ............................................. 12
7) NJM2902V-TE1 (XA0596) ............................................. 12
8) S-81350HG-KD-T1 (XA0724) ....................................... 13
9) S-80845ALMP-EA9-T2 (XA0620) ................................ 13
10) 2SK2975 (XE0038)........................................................... 13
11) Tr nsistor, Diode, nd LED Ontline Dr wings ........... 14
12) LCD Connection (EL0044)............................................ 14
SNCO, inc.
EXPLODED IEW
1) Front View............................................................................15
2) R e rView............................................................................16
PARTS LIST (DJ-493)
MAIN U nit .................................................................... 17-21
Mech nic l P rts..............................................................22
P cking P rts......................................................................22
PARTS LIST (DJ-496)
MAIN U nit.....................................................................23-27
Mech nic l P rts...............................................................28
P cking P rts......................................................................28
ADJUSTMENT
1) Required Test Equipment ........................................ 29, 30
2) Adjustment M ode .......................................................31-34
PC BOARD IEW
MAIN U nit.....................................................................35, 36
SCHEMATIC DIAGRAM ............................................. 37, 38
BLOCK DIAGRAM ........................................................ 39, 40
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SPECIFICATIONS
1) GENERAL
Frequency cover ge
Mode
Ch nnel steps
Memory ch nnels
Antenn connector
Frequency st bility
Microphone input imped nce
Power supply requirement
Current dr in ( t 13.8 V DC)
Us ble temper ture r nge
Dimensions
(Projections not included)
Weight
DTMF (DJ-496)
Sub udible Tone(CTCSS)
Sub udible Tone (DCS)
2) TRANSMITTER
Output power
Modul tion system
Spurious emissions
M x. frequency devi tion
3) RECEI ER
Receive system
Intermedi te frequencies
Sensitivity(12dB SINAD)
Selectivity
Audio output power
TX 430 ~ 449.995MHz RX 430 ~ 449.995MHz
TX 430 - 439.995MHz RX 430 ~ 439.995MHz
TX 450 ~ 469.995MHz RX 450 ~ 469.995MHz
TX 430 ~ 449.995MHz RX 430 ~ 449.995MHz
TX 430 ~ 439.995MHz RX 430 ~ 439.995MHz
TX 450 ~ 469.995MHz RX 450 ~ 469.995MHz
DJ-493T
E
TA2
DJ-496T
E
DJ-438TA2
F3E (FM)
5,10,12.5,15,20,25, & 30kHz
40ch nnels+1 CALL ch nnel
BNC (50Q unb l nced)
±5 ppm
2kfi nomin l
7.0 - 16.0V DC (neg tive ground)
1.4A (typic l) Tr nsmit high t 5W
200mA (typic l) Receive t 280mW
50mA (typic l) st ndby
20mA (typic l) B ttery s ve on
-10 ~ +60°C (14 ~ 140°F)
56 (W) x 124 (H) x 40 (D) mm (with EBP-48N)
2.2"(W) x 4.88"(H) x 1,57"(D) inches (with EBP-48N)
Approx. 375g (13.2oz) (with EBP-48N)
16 Buttons Keyp d
encoder/decoder inst lled (39tones)
encoder/decoder inst lled (104codes)
Approx. 4W EBP-48N inst lled
Approx. 5W 13.8V DC
Approx. 0.8W (LOW)
V ri ble re ct nce frequency modul tion
Less th n -60dB
±5 kHz
Double conversion superheterodyne
1st 45.1 MHz/2nd 455kHz
Less th n -12.0dB|x (0.25V)
-6dB :12kHz or more
-60dB : 26kHz or less
280mW (typic l with n 8Q lo d)
200mW (8i3 10% THD)
2
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CIRCUIT DESCRIPTION
1) Receiver System
The receiver system is double superheterodyne system with 45.1 MHz first IF nd 455kHz second IF.
1. Front End
The received sign l t ny frequency in the 430.00- to 449.995-MHz r nge is
p ssed through the low-p ss filter (L2, L3, L8, C2, C9, C10, C11, nd C62)
nd high-p ss filter (C56, C57, C61, L25 nd D25), nd mplified by the RF
mplifier (Q9). The sign l from Q9 is then p ssed through the tuning circuit
(L19, L20, L21 nd v ric ps D12, D13 nd D14) nd converted into 45.1MHz
by the mixer (Q10). The tuning circuit, which consists of L25, L19, L20, L21,
D15, D12, D13 nd D14 is controlled by the tr cking volt ge form the CPU so
th t it is optimized for the reception frequency. The loc l sign l from the VCO
is p ssed through the buffer (Q11), nd supplied to the source of the mixer
(Q10). The r dio uses the lower side of the superheterodyne system.
2. IF Circuit The mixer mixes the received sign l with the loc l sign l to obt in the sum of
nd difference between them. The cryst l filter (XF1) selects 45.1MHz fre
quency from the results nd elimin tes the sign ls of the unw nted frequen
cies. The first IF mplifier (Q8) then mplifies the sign l of the selected fre
quency.
3. Demodulator Circuit
After the sign l is mplified by the first IF mplifier (Q8), it is input to pin 16 of
the demodul tor IC (IC4). The second loc l sign l of 45.555MHz, which is
oscill ted by the intern l oscill tion circuit in IC4 nd cryst l (X2). Then, these
two sign ls re mixed by the intern l mixer in IC4 nd the result is converted
into the second IF sign l with frequency of 455kHz. The second IF sign l is
output from pin 3 of IC4 to the cer mic filter (FL1), where the unw nted fre
quency b nd of th t sign l is elimin ted, nd the resulting sign l is sent b ck
to the IC4 through pin 5.
The second IF sign l input vi pin 5 is demodul ted by the intern l limiter
mplifier nd qu dr ture detection circuit in IC4, nd output s n udio sign l
through pin 10.
4. Audio Circuit
The udio sign l from pin 10 of IC4 is compens ted to the udio frequency
ch r cteristics in the de-emph sis circuit (R106, R107, C128, C127) nd m
plified by the AF mplifier (Q27). The sign l is then input to pin 2 of the elec
tronic volume (IC6) for volume djustment, nd output from pin 1. The d
justed sign l is sent to the udio power mplifier (IC5) through pin 2 to drive
the spe ker.
3
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5. Squelch Circuit The sign l except for the noise component in AF sign l of 104 is cut by the
ctive filter inside 1C. The noise component is mplified nd rectified, then
converted to the DC volt ge to output from pin13 of IC4. The volt ge is led to
pin 2 of CPU nd comp red with the setting volt ge. The squelch will open if
the input volt ge is lower th n the setting volt ge.
2) Transmitter System
1. Modulator Circuit The udio sign l is converted to n electric sign l in either the intern l or
extern l microphone, nd input to the microphone mplifier (IC8). IC8 con
sists of two oper tion l mplifiers; one mplifier (pins 5, 6, nd 7) is composed
of pre-emph sis nd IDC circuits nd the other (pins 1, 2, nd 3) is composed
of spl tter filter. The m ximum frequency devi tion is obt ined by VR1 nd
input to the c thode of the v ric p of the VCO, to ch nge the electric c p city
in the oscill tion circuit. This produces the frequency modul tion.
2. Power Amplifier Circuit
The tr nsmitted sign l is oscill ted by the VCO, mplified by the pre-drive IC
(IC1) nd drive mplifier (04), nd input to the fin l mplifier (02). The sign l
is then mplified by the fin l mplifier (02) nd led to the ntenn switch (D2)
nd low-p ss filter (L5, L3,12, C24, C11, 010, nd C9), where unw nted high
h rmonic w ves re reduced s needed, nd the resulting sign l is supplied
to the ntenn .
3. APC Circuit P rt of the tr nsmission power from the low-p ss filter is detected by D7, con
verted to DC, nd then mplified by differenti l mplifier. The output volt ge
controls the bi s voit ge from the source of 02 nd 04 to m int in the tr ns
mission power const nt.
3) PLL Synthesizer Circuit
1. PLL The dividing r tio is obt ined by sending d t from the CPU (IC9) to pin 2 nd
sending clock pulses to pin 3 of the PLL IC (IC2). The oscill ted sign l from the
VCO is mplified by the buffer (05, 037) nd input to pin 6 of IC2. E ch
progr mm ble divider in IC2 divides the frequency of the input sign l by N
ccording to the frequency d t , to gener te comp rison frequency of 5 or
6.25kHz.
2. Reference Frequency Circuit
The reference frequency ppropri te for the ch nnel steps is obt ined by di
viding the 21,25MHz reference oscill tion (X1) by 4250 or 3400, ccording to
the d t from the CPU (IC9). When the resulting frequency is 5kHz, ch nnel
steps of 5, 10, 15, 20, 25, 30, nd 50kHz re used. When it is 6.25kHz, the
4 12.5kHz ch nnel step is used.
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3. Phase Comparator Circuit
The PLL (IC2) uses the reference frequency, 5 or 6.25kHz. The ph se com
p r tor in the IC2 comp res the ph se of the frequency from the VCO with
th t of the comp rison frequency, 5 or 6.25kHz, which is obt ined by the inter
n l divider in IC2.
4. PLL Loop Filter Circuit
If ph se difference is found in the ph se comp rison between the reference
frequency nd VCO output frequency, the ch rge pump output (pin 8) of IC2
gener tes pulse sign l, which is converted to DC volt ge by the PLL loop
filter nd input to the v ric p of the VCO unit for oscill tion frequency control.
5. CO Circuit A Colpitts oscill tion circuit driven by Q3 directly oscill tes the desired fre
quency. The frequency control volt ge determined in the CPU (IC9) nd PLL
circuit is input to the v ric ps (D3). This ch nge the oscill tion frequency, which
is mplified by the VCO buffer (Q5) nd output from the VCO unit.
4) CPU and Peripheral Circuits
1. LCD Display Circuit The CPU turns ON the LCD vi segment nd common termin ls with 1/4 the
duty nd 1/4 the bi s, t the fr me frequency is 112.5Hz.
2. Display Lamp Circuit When the LAMP key is pressed, “H” is output form pin 42 of CPU (IC9) to the
b ses of Q19, Q24 nd Q25.
3. Reset and Backup When the power form the DC j ck or extern l b ttery incre ses from Circuits 0
V to 2.5V or more, “H” level reset sign l is output from the reset IC (IC11) to pin
33 of the CPU (IC9), c using the CPU to reset. The reset sign l, however,
w its t 100, nd does not enter the CPU until the CPU clock (X3) h s st bi
lized.
4. S(Signal) Meter Circuit
The DC potenti l of pin 8 of iC4 is input to pin 1 of the CPU (IC9), converted
from n n log to digit l sign l, nd displ yed s the S-meter sign l on the
LCD.
5. DTMF Encoder (DJ-496)
The CPU (IC9) is equipped with n intern l DTMF encoder. The DTMF sign l
is output from pin 10, through R179 nd R180 (for level djust-ment), nd then
through the microphone mplifier (IC8), nd is sent to the v ric p of the VCO
for modul tion. At the s me time, the monitor-ing tone p sses through the AF
circuit nd is output form the spe ker.
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6. CTCSS Encoder The CPU (IC9) is equipped with n intern l tone encoder. The tone sign l
(67.0 to 250.3 Hz) is output from pin 9 of the CPU to the v ric p (D4) of the
7. DCS Encoder The CPU (IC9) is equipped with n intern l DCS code encoder. The code (023
to 754) is output from pin 9 of the CPU to the v ric p (D16) of the PLL refer
ence oscill tor. When DCS is ON, DCS MUTE circuit (Q12-ON, Q18-ON, 015-
OFF) works. The modul tion ctiv tes in X1 side only.
8. CTCSS, DCS DecoderThe voice b nd of the AF output sign l from pin 10 of IC4 is cut by sh rp ctive
filter IC7 (VCVS) nd mplified, then led to pin 4 of CPU. The input sign l is
comp red with the progr mmed tone frequency code in the CPU. The squelch
will open when they m tch.
9. Clock Shift In the unlikely event th t CPU clock noise is present on p rticul r oper ting
frequency progr mmed into the r dio, you c n shift the CPU clock frequency
to void the CPU clock-noise. The output sign l from pin 31 of the CPU turns
on Q35. Then the oscill tion frequency of X3 will be shifted bout 300 ppm.
5) M38267M8L252GP (XA0725)
CPU
Termin l Connection
(TOP VIEW)
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-- -----
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SEG7
-----
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SEG6
-- -----
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SEG5 -•
-----
[83
SEG4 —E
SEG3
-----
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SEG2
- ------
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SEG1 @7
SEGO —ÜB
VCC m
VREF -----
[90
AVSS
----
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COM3 -•
-----
[92
COM2
-- -----
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COMI -«
-----
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COMO
-- -----
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VL3
----- ►[96
VL2
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P20
• P21
- P22
- P23
- P24
• P25
• P26
• P27
VSS
- XOUT
XIN
• XCOUT
XCIN
RESET
P70/INTO
• P71
• P72
• P73
• P74
- P75
• P76
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6
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No. Pin N me Function I/O PU Logic Description
1P67/AN7 SMT I-A/D S-meter input
2P66/AN6 SQL I -A/D Noise level input for squelch
3 P65/AN5 BAT I -A/D Low b ttery detection input
4 P64/AN4 TIN I -A/D CTGSS tone input/DSG code input
5 P63/SCLK22/AN3 BP1 I-A/D B nd pl n 1
6 P62/SCLK21/AN2 BP2 I -A/D B nd pl n 2
7P61/SOUT2/AN1 DCSW o -Activ high DCS sign l mute
8 P60/SIN2/ANO F/M/KEY I -A/D Function/Moniter key input
9 P57/ADT/DA2 CTOUT 0 -D/A CTCSS tone output/DCS tone output/Tuning volt ge out
10 P56/DA1 DTOUT o -D/A DTMF output/EVR control output
11 P55/CNTR1 SCL 0-Pulse Seri l clock for EEPROM
12 P54/CNTR0 TBST I/O *Pulse/Activ low Tone burst output
13 P53/RTP1 BP4 I - - B nd pl n 4
14 P52/RTP0 MUTE I/O -Activ high Microphone mute
15 P51/PWM3 CLK 0-Pulse Seri l dock output for PLL,CTCSS
16 P50/PWM0 DATA I/O -Pulse Seri l dt output lor PLLCTCSS, PLL unlock signl input
17 P47/SROY1 TRESET I/O -Activ low/Pulse Trunking bo rd detection (when PSW is on)/Trunking bo rd reset
18 P46/SCLK1 STBP 0-Pulse Strobe for PLL IC
19 P45/TXD UTX 0-Pulse UART d t tr nsmission output
20 P44/RXD RTX I -Pulse UART d t reception output
21 P43/0/TOUT BEEP I/O -Pulse/Activ low Beep tone/B nd pl n 3(when PSW is on)
22 P42I/NT2 RE2 I*Avtiv low Rot ry encoder input
23 P41/INT1 RE1 I *Avtiv low
24 P40 SD 0-Avtiv low Sign l detection output
25 P77 PTT I -Activ high PTT input
26 P76 BP6 I*Activ high B nd pl n 6
27 P75 P5C 0 -Activ low PLL power ON/OFF output
28 P74 TCO
1 v^ -/ r\ -a . i
____
AAUllV IUW TX power ON/OFF output
29 P73 R5C o-Activ low RX power ON/OFF output
30 P72 AFP 0-Activ low AF AMP power ON/OFF output
31 P71 CLSFT o-Activ high CLOCK frequency shift
32 P70/INTO BU I -Activ low B ckup sign l detection input
33 RESET RESET I -Activ low Reset input
34 Xcin Xcin - - - -
35 Xcout Xcout - - - -
36 Xin Xin - - - M in clock input
37 Xout Xout - - - M in clock output
38 v'ss GND - - - CPU GND
39 P27 PSW I -Avtiv low Power switch input
40 P26 SDA 0-Pulse Seri l d t for EEPROM
41 P25 C5C 0 -Activ high C5V power ON/OFF output
42 P24 LAMP 0-Activ high L mp ON/OFF
43 P23 KI0 I*Avtiv low
Key m trix input
44 P22 KI1 I*Avtiv low
45 P21 K!2 !*Avtiv low
46 P20 KI3 I*Avtiv low
47 P17 K03 0-Avtiv low
Key m trix output
48 P16 K02 0-Avtiv low
49 P15/SEG39 KOI 0-Avtiv low
50 P14/SEG38 KOO 0 -Avtiv low
51 P13/SEG37 H/L 0- - Tx power H/L
52 P12/SEG36 DA2 0 - - DA converter for output power
53 P11/SEG35 DA1 0 - - DA converter for output power
54 P10/SEG34 DA0 0- - DA converter for output power
55 P07/SEG33 d Y D
L .A I T“ -UART line SW/Extern l control port 7
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No.
li e T
57 '
58 "
59 "
60
61
62 '
63
64 "
65 “
66 '
67 '
68 '
69 "
70 ‘
71
111
73 ~
74 "
75 ‘
-7/-'
( O
T T "
78 ~
79
80
81
82
83
84
85
86
87 '
88
89
90
91
92
93
~94~
95
96
97
98
99
100
Pin Name Function I/O PU Logic Description
P06/SEG32 AFC O Activ high AF tone control
P05/SEG31
P04/SEG30
P03/SEG29
P02/SEG28
P01/SEG27
P00/S EG26
P37/SEG25
P36/SEG24
P35/SEG23
P34/SEG22
P33/SEG21
P32/SEG20
P31/SEG19
P30/SEG18
SEG17
SEG16
SEG15
SEG14
SEG13
SEG11
SEG10
SEG9
SEG8
SEG7
SEG6
SEG5
SEG4
SEG3
SEG2
SEG1
SEGO
S31 O
S30 O
S29 O
S28 O
S27 O
S26 O
S25 O
S24 O
S23 O
S22 O
S21 O
S20
S19 O
S18 O
S17 O
S16 O
S15 O
S14 O
S13 O
S11 o
S10 o
S9 O
S8 O
S7 O
S6 O
S5 O
S4 O
S3 O
S2 O
S1 o
SO o
LCD segment sign l
Vcc VDD CPU power termin l
Vref Vref AD converter power supply
Avss Avss AD converter GND
COM3 COM3 O LCD COM3 output
r n M Q nniwio nLCD COM2 output
COM1 COM1 O LCD COM1 output
COMO COMO O LCD COMO output
VL3
VL2 VL3
VL2 LCD power supply
C2
C1 C1
VL1 VL1 A/D LCD power supply
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SEMICONDUCTOR DATA
1) NMJ2070M T1 (XA0210)
Low Volt ge Power Amplifier
Equiv lent Circuit
V+=6V, T =25±2‘C
Parameter Condition Symbol Min. Typ. Max. Unit
Supply volt ge V+ 1.8 -15 V
Idle current RL= lo -4 7 mA
Output volt ge Vo -2.7 -V
Input bi s current Ib-200 -nA
Output power
THD=10%, f= 1 kHz V+=6V, RL=4
Po
0.5 0.6 -W
V+-4.5V, RL-4 -0.32 -W
V+=3V, RL-4 -120 -mW
V+=2V, R U 4 -30 -mW
THD=10%, f=1kHz V+=6V, RL=4 -500 -mW
V+-4.5V, RL=4 -250 -mW
UldllM IIUI1 f-v_ r\ A\ki i a i 4 i-i i_
ru*u.^vY, n L ^ , i= i Tnu -0.25 -%
Volt ge g in f=1kHz Av 41 44 47 dB
Input imped nce f=1kHz ZlN 100 - - k
Equiv lent input noise
volt ge Rs=10k A curve Vn1 -2.5 -MV
B=22Hz to 22kHz Vn2 -3-MV
Power supply volt ge
rejection r tio f= 100Hz, Cx»100pF SVR 24 30 -dB
Power g in b nd width
(- 3dB) RL=8 , Po=250mW P.B '200 -kHz
2) AT24C16N-10SI-2.7TER (XA0368)
16K bits CMOS Seri l EEPROM
AO
1
A2
GND
Pin N me Function
A0 10 A2 Address inputs
SDA Seri l D t
SCL Seri l Clock
Test Test Input (GND or Vcc)
NC No connection
9
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3) M5222FP-600C (XA0385)
Electronic Volume
I1 I
I2
O — ---- VW—(e>
fc -0
7 ^ - °
l=WHI
10
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