Alinco DR-M03R User manual

DR-M03RI DR-03T
S e r v i c e M a n u a l
C O N T E N T S
SPECIFICATIONS
GENERAL ............................ ...................... .. ...........
TRANSMITTER .................... ................. ................
RECEIVER............. .......................................... .......
CIRCUIT D IS C R ET IO N
1) Receiver System..... ............... ............. 3,4
) Transmitter System.................... ........................ 4
3) PLL Synthesizer Circuit. ........ ....................... 4,5
4) CPU and Peripheral Circuit......... ...... ...................5,6
5) Power Supply Circuit .............. . ............. . ........ ........6
6) M38 68MCA08 GP#U0 (XA1170A) ..... ........ 7-9
SEM ICO NDUCTOR DATA
1) NJM7808FA(XA010 )................. .......... . ............ 10
) . TC4S66F (XA0115)........................... . ............. .......10
3) TC4W53FU (XA0348) .............. ................ ....... 10
4) TA31136FN (XA0404)................. ........... .. ....... ...... 11
5) LA44 5A (XA0410)..... ................. ..... . ........... 11
6) BR 4L3 FJ (XA0604Z).................................... ....... 1
7) S-80845ALMP (XA06 0) ............. ......................... 1
8) N JM78M05DL1A (XA0947) ..... . ........... ........... ....... 1
9) MB15A01PFV1 (XA1010) .......................................13
10) LM 904PWR (XA1103).............. ..................... .......14
11) LM 90 PWR (XA1106)............. ...................... .......14
1 ) TA78DS10F (XA1 49)..................................... ...... 14
13) Transistor, Diode and LED Outline Drawing... 15
14) RD16HHF1 (XE0056) ...... ......... ......... ......... 16
15) LCD Connection (TTR36 6UPFDHN):......... 17
EXPLO DED VIE W
1) Top.and Front View ........................ ..... ......... ....... 18
) Bottom View........ ..... ......... ....... 19
3) LCD Assembly ............................. ........... ....... 0
PARTS LIST
CPU Unit ................................ . .................. ...... 1
MAIN Unit ......................................... ..... 1- 4
PA Unit... .......... ....... . .............................. ....... 4
Mechanical Parts..................................... ....... 4
Packing Parts ....................... . ..................... .... 5
ACCESSORIES... ............. . .................... ....... 5
ACCESSORIES (SCREW SET) ...... ...... ....... 5
ADJUSTMENT
1) Adjustment Spot..................................... ....... 6 *
) VCO and RX Adjustment Specification.. 7
3) TX Adjustment Specification .......... ............. 7
4) RX Test Specification ............... ............. ...... 8
5) TX Test Specification .................................... 8
PC BOARD VIEW
1) CPU Unit Side A(UP0584) ..... ............. ...... 9
) CPU Unit Side B (UP0584)..... .................... 9
3) MAIN / PA Unit Side A (UP0584) .......... ....... 30
4) MAIN / PA Unit Side B (UP0584)......... 30
SCHEMATIC DIAGRAM
1) CPU Unit........................... . ................. . .........31
) MAIN Unit ................... ............. . .............. ...... 3
BLOCK DIAGRAM
1) DR-M03R / DR-03T................................... 33
ALINCO, Inc

SPECIFICATIONS
■ General DR-M03R DR-03T
Frequency coverage 8.000 ~ 9.700MHz ( RX, TX )
Operating mode FM 16K0F3E
Frequency resolution 5 , 8.33 , 10 , 1 .5 , 15 , 0 , 5 , 30 , 50 kHz
Number of memory
Channels 100
Antenna impedance 50ohm unbalanced
Power requirement 13.8V DC +/-15% (11.7 - 15.8 V )
Ground method Negative ground
Current drain Receive
Transmit 0.6 A ( m ax.) 0.4 A ( Squelched )
Approx. 3.0 A max.
Operating temperature -10 °C - 60°C
Frequency stability +/- 7ppm
Dimensions 14 ( w ) x 40 ( h ) x 174 ( d ) mm
( 14 x 40 x 188 mm for projection included )
Weight Approx. 1.0 Kg
■ Transmitter
Output power Hi
Mid
Low
10 W
5 W
1 - 4 W
Modulation system Variable reactance frequency modulation
Maximum Frequency
deviation +/- 5kHz +/- .5kHz
Spurious emission -50 dB
Adjacent channel power -60 dB
Noise and hum ratio -4 0 dB -3 4 dB
Microphone impedance kohm
■ Receiver
Sensitivity - 1 dBu for 1 dB SINAD
Receiver circuit Double conversion super-heterodyne
Intermediate frequency 1st 10.7 MHz nd 450kHz
Squelch sensitivity -1 6 dBu
Adjacent channel selectivity -65 dB
Inter-modulation rejection
ratio 60 dB
Spurious and image rejection
ratio 70 dB
Audio output power .0 W ( 8ohm , 10% T H D )
! NOTE : All specifications are subject to change without notice or obligation.
2

C IR C U IT D E S C R IP T IO N
1) Receiver System
The receiver system is a double super-heterodyne system with a 10.7MHz first IF and a 450kHz
second IF.
1. Front End The received signal at any frequency in the 8.000MHz to 9.695MHz
range is passed through the low-pass filter (L115, L114, L113, C 04,
C 03, C 0 , C 16 and C 15) and tuning circuit (L105 and D105), and
amplified by the RF amplifier (Q107). The signal from Q107 is then
passed through the tuning circuit {L104, L103, L10 , and variable
capacitor D104, D103, D10 ) and converted into 10.7MHz by the mixer
(Q106). The tuning circuit, which consists of L105, variable capacitor
D105, L104, L103, L10 , variable capacitor D104, D103 and D10 , is
controlled by the tracking voltage from the VCO. The local signal from the
VCO is passed through the buffer (Q145), and supplied to the source of
the mixer (Q106). The radio uses the upper side of the super-heterodyne
system. .
. IF Circuit The mixer mixes the received signal with the local signal to obtain the sum
of and difference between them. The crystal filter (XF101A, XF101B)
selects 10.7 MHz frequency from the results and eliminates the signal of
the unwanted frequencies. The first IF amplifier (Q105) then amplifies the
signal of the selected frequency.
3. Demodulation Circuit After the signal is amplified by the first IF amplifier (Q105), it is input to
pin16 of the demodulator IC (IC108). The second local signal of 11.15MHz
(shared with PLL IC reference oscillation), which is oscillated the external
oscillator X601, is input through pin 1 of IC108. Then, these two signals
are mixed by the internal mixer in IC108 and the result is converted into
the second IF signal with a frequency of 450kHz. The second IF signal is
output from pin 3 of IC108 to the ceramic filter (FL101), where the
unwanted frequency band of that signal is eliminated, and the resulting
signal is sent back to the IC108 through pin 5. The second IF signal input
via pin 5 is demodulated by the internal limiter amplifier and quadrature
detection circuit in IC 108, and output as an audio signal through pin 9.
4. Audio Circuit The audio signal from pin 9 of IC 108 is amplified by the audio amplifier
(IC1 0:A), and switched by the signal switch IC (IC111) and then input it to
the de-emphasis circuit.
And is compensated to the audio frequency characteristics in the
de-emphasis circuit (R 03, R 07, R 13, R 09, C191, C 18, C 17) and
amplified by the AF amplifier (IC1 0:B). The signal is then input to volume
(VR1). The adjusted signal is sent to the audio power amplifier (IC117)
through the pin 1 to drive the speaker.
3

5. Squelch Circuit t
The detected output which is outputted from pin 9 of IC108 is inputted to
pin 8 of 1C108 after it was been amplified IC1 0:A and it is outputted from
pin 7 after the noise component was been eliminated from the composed
band pass filter in the built in amplifier of the iC, then the signal is rectified
by the internal diode in IC108 to convert into DC component. The adjusted
voltage level at VR101 is delivered to the comparator of the CPU.
The voltage is led to pin of CPU and compared with the setting voltage.
The squelch will open if the input voltage is lower than the setting voltage.
During open squelch, pin 30 (SQC) of the CPU becomes “L" level, AF
control signal is begin controlled and sounds is outputted from speaker.
) Transmitter System
1. Modulator Circuit The audio signal is converted to an electrical signal by the microphone,
and input it to the microphone amplifier (Q6). Amplified signal which
passes through mic-mute control IC109 is adjusted to an appropriate
mic-volume by means of mic-gain adjust VR106.
1C114:D and C consists of two operational amplifiers; one amplifier (pin
1 ,13 and 14) is composed of pre-emphasis and I DC circuit and the other
(pin 8, 9 and 10) is composed of a splatter filter. The maximum frequency
deviation is obtained by VR107. And input to the signal switch (IC113)
(9600 bps packet signal, input switch) and input to the anode of the
variable capacitor of the VCO, to change the electric capacity in the
oscillation circuit. This produces the frequency modulation.
. Power Amplifier Circuit The transmitted signal is oscillated by the VCO, amplified by the younger
amplifier (Q115 and Q103), and input to the final power amplifier (Q701).
The signal is then amplified by the final power amplifier (Q701) and led to
the antenna switch (D110) and low-pass filter (L113, L114, L115, C 15,
C 16, C 0 , C 03 and C 04), where unwanted high harmonic waves are
reduced as needed, and the resulting signal is supplied to the antenna.
y 3. APC Circuit Part of the transmission power from the low-pass filter is detected by
D111, converted to DC. The detection voltage is passed through the APC
circuit (IC114:B), then it controls the APC voltage supplied to final power
amplifier Q701 to fix the transmission power.
3) PLL Synthesizer Circuit
The dividing ratio is obtained by sending data from CPU (1C1) to pin 10
and sending clock pulses to pin 9 of the PLL IC (IC116). The oscillated
signal from the VCO is amplified by the buffer (Q134 and Q135) and input
to pin 8 of IC116. Each programmable divider in 1C116 divides the
frequency of the input signal by N according to the frequency data, to
generate a comparison frequency of 5 or 6. 5 kHz.
The reference frequency appropriate for the channel steps is obtained by
dividing the 11.15 MHz reference oscillation (X601) by 4 50 or 3400,
according to the data from the CPU (IC1). When the resulting frequency is
5 kHz, channel step of 5, 8.33, 10, 15, 0, 5, 30 and 50 kHz are used.
When it is 6. 5 kHz, the 1 .5 kHz channel step is used.
1. PLL
. Reference Frequency
Circuit
4

3. Phase Comparator Circuit The PLL (IC116) uses the reference frequency, 5 or 6. 5 kHz. The phase
comparator in the 10116 compares the phase of the frequency from the
VCO with that of the comparison frequency, 5 or 6. 5 kHz, which is
obtained by the internal divider in IC116.
4. PLL Loop Filter Circuit If a phase difference is found in the phase comparison between the
reference frequency and the VCO output frequency, the charge pump
output (pin 5) of IC116 generates a pulse signal, which is converted DC
voltage by the PLL loop filter and input to the input to the variable
capacitor of the VCO unit for oscillation frequency control.
5. VCO Circuit AColpitts oscillation circuit driven by Q131 directly oscillates the desired
frequency. The frequency control voltage determine in the CPU (IC1) and
PLL circuit is input to the variable capacitor (D1 3). This change the
‘ oscillation frequency, which is amplified by the VCO buffer (Q134, Q145)
and output from the VCO area.
4) CPU and Peripheral Circuits
1. LCD Display Circuit
. Reset and Backup
The CPU turns ON the LCD via segment and common terminals with 1/4
the duty and 1/3 the bias, at the frame frequency is 64 Hz.
When the power from the DC cable increases from Circuits 0 V to .5 V or
more, “H” level reset signal is output from the reset IC (IC4) to pin 33 of
the CPU (1C1), causing the CPU to reset. The reset signal , however,
waits at 100, and dose not enter the CPU until the CPU clock (X1) has
stabilized.
3. S (Signal) Meter Circuit The DC potential of IF IC is input to pin 1 of the CPU (IC1), converted from
an analog to a digital signal, and displayed as the S-meter signal on the
LCD.
4. DTMF Encoder
5. Tone Encoder
The, CPU (IC1) is equipped with an internal DTMF encoder. The DTMF
signal is* output from pin 10, through R35, R34 and VR109 (for level
adjustment), and then through the microphone amplifier (1C114:D), and is
sent to the variable capacitor of the VCO for modulation. At the same time,
the monitoring tone passes through the AF circuit and is output from the
speaker.
The CPU (IC1 ) is equipped with an internal tone encoder. The tone signal
(67.0 to 50.3 Hz) is output from pin 9 of CPU to the variable capacitor
(D1 3) of the VCO for modulation.
6. DCS Encoder The CPU (1C1 ) is equipped with an internal DCS code encoder. The code
(0 3 to 754) is output from pin 9 of CPU to the variable capacitor (D601) of
the PLL reference oscillator. When DCS is ON, DCS MUTE circuit
(Q1 6-ON, Q133-ON, Q 13 -OFF) works. The modulation activates in
c X601 side only.
5

7. CTCSS, DCS Decoder -
The voice band of the AF output signal from pin 1 of IC1 0:A is cut by
sharp active filter IC104:A, B and C (VCVS) and amplified, then led to pin
4 of CPU. The input signal is compared with the programmed tone
frequency code in the CPU. The squelch will open when they match.
During DCS, Q108 is ON, C419 is working and cut off frequency is
lowered.
5) Power Supply Circuit
When power supply is ON, there is a “L” signal being inputted to pin 39 (PSW) of CPU which enables the CPU to
work. Then, “H” signal is outputted from pin 41 (C5C) of CPU and drives ON the power supply switch control Q8
and Q7 which turns the 5VS ON. 5VS turns ON the PLL 1C (IC116), main power supply switch Q1 7 and Q1 ,
AF POWER IC117 and the 8V of AVR (IC115). During reception, pin 9 (R5) of CPU outputs “H" level, Q1 4 is ON,
and the reception circuits supplied by 8 V. While during transmission, pin 8 (T5) of CPU outputs "L” level which is
reverse by Q11 so that the output in Q1 8 will be “H” level, Q1 3 is ON, and the transmission circuit is supplied by
8 V. Or, in the case when the condition of PLL is UNLOCK, “HJ level is outputted from pin 7 of PLL IC (IC116),
UNLOCK switch Q1 9 is ON, transmission switch Q1 8 is OFF which makes the transmission to stop.
6

6) M38 68MCL08 GP#U0 (XA1170A)
CPU
Terminal Connection
(TOP VIEW)
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No. Terminal Signal I/O Description
1 P67/AN7 SMT I S-meter input
P66/AN6 SQL I Noise level input for squelch
3 P65/AN5 BP5 I Band plan 5
4 P64/AN4 TIN I CTCSS tone input / DCS code input
5 P63/SCLK /AN3 r~ b p i IBand plan 1
6 P6 /SCLK 1/AN BP IBand plan
7P61/SOUT /AN1 DCSW 0 DCS signal mute
8 P60/SIN /AN0 RE I Rotary encoder input
9 P57/ADT/DA TOUT 0CTCSS tone output / DCS tone output
10 P56/DA1 DOUT oDTMF output
11 P55/CNTR1 SCL oSerial clock for EEPROM
1 P54/CNTR0 TBST oTone burst output
13 P53/RTP1 BP4 I/O Band plan 4
14 P5 /RTP0 MUTE I/O Microphone mute / Security alarm SW
15 P51/PWM1 CLK oSerial clock output for PLL
. 16 P50/PWMO DATA I/O Serial data output for PLL / PLL unlock signal input
17 P47/SRDY1 TSTB I/O Trunking board detection / Strobe signal to trunking board
18 P46/SCLK1 STB 0 Strobe for PLL IC
19 P45/TXD UTX oUART data transmission output
0 P44/RXD RTX I UART data reception output
1 P43M/TOUT BEEP I/O Beep tone / Band plan 3
P4 /INT SEC ISecurity voltage input
3 P41/INT1 RE1 I Rotary encoder input
4 P40
5 P77 PTT I PTT input
6 P76 SSTB O Security mode
7 P75 W/N oWide Narrow SW
8 P74 T5 0 TX power ON / OFF output
9 P73 R5 0 RX power ON / OFF output
30 P7 SQC 0 SQL ON/OFF
31 P71
3 P70/INT0 BU IBackup signal detection input
33 RESET RESET f Reset input
34 XCIN Xcin .. --
35 XCOUT Xcout -
36 XIN Xin - 7 Main clock input
37 XOUT Xout -Main clock output
38 VSS GND -CPU GND
39 P 7 PSW I Power switch input
40 P 6 SDA O Serial data for EEPROM
41 P 5 CSC oC5V power ON / OFF output
4 P 4 MID oTx middle power
43 P 3 LOW oTx low power
44 P EXP 0Trunking / Packet data SW
45 P 1 SW6 IKey sw 6 (SQL)
46 P 0 SW5 I Key sw 5 (CALL)
47 P17 SW4 I Key sw 4 (TSQ)
48 P16 SW3 IKey sw 3 (MHz)
49 P15/SEG39 SW I Key sw (V/M)
50 P14/SEG38 SW1 IKey sw 1 (FUNC)
8

No. Terminal Signal I/O Description
51 P13/SEG37 DOWN I Mic down input
5 P1 /SEG36
53 P11/SEG35
54 P10/SEG34 UP I Mic up input
55 P07/SEG33 S33 0
56 P06/SEG 3 S3 o
57 P05/SEG31 S31 0
58 P04/SEG30 S30 0
59 P03/SEG 9 S 9 0
60 P0 /SEG 8 S 8 o
61 P01/SEG 7 S 7 0
6 P00/SEG 6 S 6 0
63 P37/SEG 5 S 5 o
64 P36/SEG 4 S 4 o
65 P35/SEG 3 S 3 0
66 P34/SEG S 0
67 P33/SEG 1 S 1 0
68 P3 /SEG 0 S 0 o
69 P31/SEG19 S19 0
70 P30/SEG18 S18 0
71 SEG17 S17 oLCD segment signal
7 SEG16 S16 o
73 SEG15 S15 0
74 SEG14 S14 0
75 SEG13 S13 o
76 SEG1 S1 o
77 SEG11 S11 o
78 SEG10 S10 0
79 SEG9 S9 0
80 SEG8 S8 o
81 SEG7 S7 o
8 •SEG6 S6 0
83 SEG5 S5 o
84 SEG4 S4 o
85 SEG3 S3 o A
86 SEG S 0
87 SEG1 S1 o
88 SEGO SO o
89 VCC VDD -CPU power terminal
90 VREF Vref -AD converter power supply
91 AVSS Avss -AD converter GND
9 COM3 COM3 oLCD COM3 output
93 C OM COM 0 LCD C O M output
94 COM1 COM1 oLCD COM1 output
95 COMO COMO oLCD COMO output
96 VL3 VL3 -LCD power supply
97 VL VL -LCD power supply
98 C I- -
99 C1 C1 --
100 VL1 VL1 I LCD power supply
9

S E M I C O N D U C T O R D A T A
1) NJM7808FA (XA010 )
8V (1A) Voltage Regulator
1. INPUT
. COMMON
3. OUTPUT
1 3
) TC4S66F (XA0115)
Bilateral Switch
5 4
s ____ a
C9
d d d
1 2 3
1. IN/OUT
. OUT/IN
3. VSS
4. CONT
5. VDD
5
BL f l
M
d a d
1 2 3
CONT Function (IN-OUT)
L Disconnect (Hi Z)
H Connect ( 90ohm typ.)
3) TC4W53FU (XA0348)
Multiplexer / De-multiplexer
8 7 6 5
n nil a.
m i
12 3 4
1. COMMON
. INH
3. VEE
4. VSS
5. A
6. ch 1
7. ch 0
8. VDD
Control input ON channel
INH A
LLch 0
LH ch 1
H*NONE
Don’t care
10

Narrow Band FM IF IC
16 15 14 13 1 11 10 9
flflflflyn
4) TA31136FN (XA0404)
0
n u m i
1 3 4 5 6 7 8
1. OSCIN
. OSC OUT
3. MIX OUT
4 . Vcc
5. IF IN
6. DEC
7. FIL OUT
8. FILIN
9.AF OUT
10. QUAD
11. IF OUT
1 . RSSI
13. N-DET
14. N-REC
15. GND
16. MIX IN
5) LA44 5A (XA0410)
5W Audio Power Amplifier
Ö .
LA44 5
* * *
1. Input
. Small signal GND
3. Large signal GND
4. Output
5. Vcc
Test Circuit
1 3 4 5
11

6) BR 4L3 FJ (XA0604Z)
3 K-Bit EEPROM
8 7 6 5
R -ELELFL
F ¥ ¥ ¥
1 3 4
1. AO
. A1
3.A
4. Vss
5. SDA
6. SCL
7. WP
8. Vcc
Name Function
A0...A
Vss
SDA
SCL
WP
Vcc
User Configurable Chip Select
Ground
Serial Address / Data / I/O
Serial Clock
Write Protect Input
+ .5 ~ 6.0V Power Supply
7) S-80845ALMP (XA06 0)
4.5V Voltage Detector
4
P
B 6 6 *
n b t i '
1 3
1. GND
. Vin
3. Vout
4. NC
5. NC
8) NJM78M05DL1A (XA0947)
5V (500mA) Voltage Regulator
1. input
. GND
3. Output
izr ^
2
——
1 3
r i
7 8 M 0 5 A
o
12

PLL Synthesizer
16 15 14 13 12 11 10 9
9) MB15A01PFV1 (XA1010)
15A01
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u rn
1. OSCIN 9. Clock
. OSC OUT 10. Data
3. Vp 11. LE
4. Vcc 1 . FC
5. Do 13. N. C.
6. GND 14. fout
7. LD 15. 4>P
8. fin 16. 0R
1 2 3 4 5 6 7 8
( Vcc = .7 to 3.5V, Ta = -40°C to +85°C )
Parameter Symbo
ICondition Min. Typ. Max. Unit
Power supply voltage Vcc -.7 3.0 3.5 V
Power supply current Icc 500MHz
Vcc=Vp=3.75V 6.5 mA
LPF supply voltage Vp -Vcc -6.0 V
Local oscillator input level Vfin --10 +6 dBm
Local oscillator input
frequency fin *10 1100 MHz
Xin input level Vxin 0.5 -Vp-p
Xin input frequency Fxin --1 3 MHz
13

10) LM 904PWR (XA1103)
Dual Operational Amplifiers
8 7 6 5
1. Output A
. Inverting Input A
3. Non-inverting Input A
4. GND
5. Non-inverting Input B
6. Inverting Input B
7. Output B
8. Vcc
12 3 4
11) LM 90 PWR (XA1106)
Quad Operational Amplifiers
1413121110 9 81. Output A
. Inverting Input A
3. Non-inverting Input A
4. Vcc
5. Non-inverting Input B
6. Inverting Input B
7. Output B
8. Output C
9. Inverting input C
10. Non-inverting Input C
11. GND
1 . Non-inverting Input D
13. Inverting Input D
14. Output D
1 ) TA78DS10F (XA1 49)
10V (30mA) Voltage Regulator
( I
Tnrrr
1 2 3
1. OUTPUT
. COMMON
3. INPUT
14

13) Transistor, Diode and LED Outline Drawing
Top View
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XH
TT~[T
E E
Rb=1Qkohm
Rbe=47kohm Rb=10kohra
Rbe=47kohm

Nch MOS FET
14) RD16HHF1 (XE0056)
O U T L IN E D R A W IN G
9.5m
PIN
© GATE
( ) SOURCE
® DRAIN
<D FIN (SOURCE)
ABSOLUTE MAXIMUM RATING ( Tc = 5°C, unless otherwise noted )
Symbol Parameter Conditions Ratings Unit
VDSS Drain to source voltage
> 0
ii
CO
5
50 V
VGSS Gate to source voltage Vds = OV +/-. 0 V
Pch Channel dissipation Tc = 5 °C 56.8 W
Pin Input Power Zg = Zl = 50 Q 0.8 W
ID Drain to source Current -5 A
Tch Channel temperature -150 °C
Tstg Storage temperature -' -40 to+150 °C
Rth j-c Thermal resistance Junction to case . °c/w .
ELECTRICAL CHARACTERISTICS (Tc = 5 °C, unless otherwise noted )
Symbol Parameter Conditions Limits Unit
Min Typ Max
loss Zero gate voltage drain current VDs=17V,VGs=0V -10 ß A
Igss Gate to source leak current VGS = 10V,VDS = 0V - - 1/i A
Vth Gate threshold voltage Vos = 1 V, Ids = 1mA 1.7 -7.7 V
Pout Output Power f= 30MHz, Vqd = 1 .5V
Pin = 0.4W, ldq=0.5A 16 19 -W
n D Drain Efficiency 55 65 - %
Load VSWR Tolerance VDD = 15. V, P0 = 16W (Pin Control)
f = 30MHz, Jdq = 0.5A, Zg = 50 ß
Load VSWR = 0:1 (ALL Phase)
No degradation
16

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15) LCD Connection (TTR36 6UPFDHN)

) Top and Front View
AA0050
NK0073
18

3) Bottom View
' AA0050