AMD 3200 - Athlon 64 2.0 GHz Processor User manual

Revision Guide for
AMD Family 15h
Models 00h-0Fh
Processors
Publication # 48063 Revision: 3.18
Issue Date: October 2012
Advanced Micro Devices

©2010-2012 Advanced Micro Devices, Inc.All rights reserved.
The contents of this document are provided in connection with Advanced Micro Devices, Inc. ("AMD") products.
AMD makes no representations or warranties with respect to the accuracy or completeness of the contents of this
publication and reserves the right to discontinue or make changes to products, specifications, product descriptions or
documentation at any time without notice. The information contained herein may be of apreliminary or advance
nature. No license, whether express, implied, arising by estoppel, or otherwise, to any intellectual property rights is
granted by this publication. Except as set forth in AMD's Standard Terms and Conditions of Sale, AMD assumes no
liability whatsoever, and disclaims any express or implied warranty, relating to its products including, but not
limited to, the implied warranty of merchantability, fitness for aparticular purpose, or infringement of any
intellectual property right.
AMD's products are not designed, intended, authorized or warranted for use as components in systems intended for
surgical implant into the body, or in other applications intended to support or sustain life, or in any other application
in which the failure of AMD's product could create asituation where personal injury, death, or severe property or
environmental damage may occur. AMD reserves the right to discontinue or make changes to its products at any
time without notice.
Trademarks
AMD, the AMD Arrow logo, AMD FX, AMD Opteron, and combinations thereof, are trademarks of Advanced
Micro Devices, Inc.
HyperTransport is alicensed trademark of the HyperTransport Technology Consortium.
Other product names used in this publication are for identification purposes only and may be trademarks of their
respective companies.
Disclaimer
While every precaution has been taken in the preparation of this document, Advanced Micro Devices, Inc. assumes
no liability with respect to the operation or use of AMD hardware, software or other products and documentation
described herein, for any act or omission of AMD concerning such products or this documentation, for any
interruption of service, loss or interruption of business, loss of anticipatory profits, or for punitive, incidental or
consequential damages in connection with the furnishing, performance, or use of the AMD hardware, software, or
other products and documentation provided herein. Ensure that you have the latest documentation.

List of Figures
Figure 1. Format of CPUID Fn0000_0001_EAX......................................................................................................................9
48063 Rev. 3.18 October 2012 Revision Guide for AMD Family 15hModels 00h-0Fh Processors
List of Figures
3

List of Tables
Table 1. Arithmetic and Logic Operators..................................................................................................................................8
Table 2. CPUID Values for AMD Family 15hModels 00h-0Fh G34r1 Processor Revisions..................................................9
Table 3. CPUID Values for AMD Family 15hModels 00h-0Fh C32r1 Processor Revisions..................................................9
Table 4. CPUID Values for AMD Family 15hModels 00h-0Fh AM3r2 Processor Revisions..............................................10
Table 5. Supported Mixed Revision Configurations...............................................................................................................11
Table 6. Cross Reference of Product Revision to OSVW ID..................................................................................................13
Table 7. Cross-Reference of Processor Revision to Errata......................................................................................................14
Table 8. Cross-Reference of Errata to Package Type..............................................................................................................18
Table 9. Cross-Reference of Errata to Processor Segments.................................................................................................... 21
Revision Guide for AMD Family 15hModels 00h-0Fh Processors
48063 Rev. 3.18 October 2012
4
List of Tables

Revision History
Date Revision Description
October 2012 3.18 Added AMD Opteron™ 3300 Series, 4300 Series, 6300 Series Processors and OR-C0 silicon revision to
Overview and Tables 2-8. Added Mixed Processor Revision Support. Added errata #685, #699, #704, #707,
#708, #727, #734, #739, and #759. Updated erratum #668.
August 2012 3.16 Added errata #737, #740, #742, #744. and #745; Updated erratum #709.
May 2012 3.12 Added AMD Opteron™ 3200 Series Processor to Overview, Table 4, and Table 9; Updated MSRC001_0141
OS Visible Work-around MSR1 (OSVW_Status)section for errata #724; Added errata #691,#709, #714, #717-
#720, #724-#726; Removed erratum #534 as this is redundant with, and replaced by, errata #717 and #718;
Changed Fix Planned to "Yes" for errata #520 , #535-#538 , #586, #592 , #593, #600, #619, #623, #624, #636,
#658, #659, #660, #668, #671-#675, and #689.
November 2011 3.04 Added errata #600, #693-#695, and #709. Updated errata #534 and #671. Added package types G34, C32 to
Table 8. Added AMD Opteron™ 4200 Series Processor and AMD Opteron™ 6200 Series Processor to
Overview and Table 9. Added Table 2 and Table 3.
October 2011 3.00 Initial public release.
48063 Rev. 3.18 October 2012 Revision Guide for AMD Family 15hModels 00h-0Fh Processors
Revision History
5

Overview
The purpose of the Revision Guide for AMD Family 15hModels 00h-0Fh Processors is to communicate updated
product information to designers of computer systems and software developers. This revision guide includes
information on the following products:
•AMD FX™-Series Processor
•AMD Opteron™3200 Series Processor
•AMD Opteron™3300 Series Processor
•AMD Opteron™4200 Series Processor
•AMD Opteron™4300 Series Processor
•AMD Opteron™6200 Series Processor
•AMD Opteron™6300 Series Processor
This guide consists of these major sections:
•Processor Identification shows how to determine the processor revision and workaround requirements, and to
construct, program, and display the processor name string.
•Product Errata provides adetailed description of product errata, including potential effects on system
operation and suggested workarounds. An erratum is defined as adeviation from the product's specification,
and as such may cause the behavior of the processor to deviate from the published specifications.
•Documentation Support provides alisting of available technical support resources.
Revision Guide Policy
Occasionally, AMD identifies product errata that cause the processor to deviate from published specifications.
Descriptions of identified product errata are designed to assist system and software designers in using the
processors described in this revision guide. This revision guide may be updated periodically.
Revision Guide for AMD Family 15hModels 00h-0Fh Processors
48063 Rev. 3.18 October 2012
6
Overview

Conventions
Numbering
•Binary numbers. Binary numbers are indicated by appending a"b" at the end, e.g., 0110b.
•Decimal numbers. Unless specified otherwise, all numbers are decimal. This rule does not apply to the
register mnemonics.
•Hexadecimal numbers. Hexadecimal numbers are indicated by appending an "h" to the end, e.g., 45F8h.
•Underscores in numbers. Underscores are used to break up numbers to make them more readable. They do
not imply any operation. e.g., 0110_1100b.
•Undefined digit. An undefined digit, in any radix, is notated as alower case "x".
Register References and Mnemonics
In order to define errata workarounds it is sometimes necessary to reference processor registers. References to
registers in this document use amnemonic notation consistent with that defined in the
BIOS and Kernel
Developer's Guide (BKDG) for AMD Family 15hModels 00h-0Fh Processors , order# 42301. Each mnemonic is
aconcatenation of the register-space indicator and the offset of the register. The mnemonics for the various
register spaces are as follows:
•IOXXX: x86-defined input and output address space registers; XXX specifies the byte address of the I/O
register in hex (this may be 2 or 3 digits). This space includes the I/O-Space Configuration Address Register
(IOCF8) and the I/O-Space Configuration Data Port (IOCFC) to access configuration registers.
•DZFYxXXX: PCI-defined configuration space at bus 0; Zspecifies the PCI device address in hex; XXX
specifies the byte address of the configuration register (this may be 2 or 3 digits) in hex; Yspecifies the
function number. For example, D18F3x40 specifies the register at bus 0, device 18h, function 3, address 40h.
Some registers in D18F2xXXX have a_dct[1:0] mnemonic suffix, which indicates there is one instance per
DRAM controller (DCT). The DCT instance is selected by DCT Configuration Select[DctCfgSel]
(D18F1x10C[0]).
•DZFYxXXX_xZZZZZ: Port access through the PCI-defined configuration space at bus 0; Zspecifies the PCI
device address in hex; XXX specifies the byte address of the data port configuration register (this may be 2 or
3 digits) in hex; Yspecifies the function number; ZZZZZ specifies the port address (this may be 2 to 7 digits)
in hex. For example, D18F2x9C_x1Cspecifies the port 1Ch register accessed using the data port register at
bus 0, device 18h, function 2, address 9Ch. Refer to the
BIOS and Kernel Developer's Guide (BKDG) for
AMD Family 15hModels 00h-0Fh Processors
, order# 42301 for access properties. Some registers in
D18F2xXXX_xZZZZZ have a_dct[1:0] mnemonic suffix, which indicates there is one instance per DRAM
controller (DCT). The DCT instance is selected by DCT Configuration Select[DctCfgSel] (D18F1x10C[0]).
•APICXXX: APIC memory-mapped registers; XXX is the byte address offset from the base address in hex
(this may be 2 or 3 digits). The base address for this space is specified by the APIC Base Address Register
(APIC_BAR) at MSR0000_001B.
•CPUID FnXXXX_XXXX_RRR_xYYY: processor capability information returned by the CPUID instruction
where the CPUID function is XXXX_XXXX (in hex) and the ECX input is YYY (if specified). When a
register is specified by RRR, the reference is to the data returned in that register. For example, CPUID
Fn8000_0001_EAX refers to the data in the EAX register after executing CPUID instruction function
8000_0001h.
•MSRXXXX_XXXX: model specific registers; XXXX_XXXX is the MSR number in hex. This space is
accessed through x86-defined RDMSR and WRMSR instructions.
•PMCxXXX[Y]: performance monitor events; XXX is the hexadecimal event counter number programmed
into MSRC001_020[A,8,6,4,2,0][EventSelect] (PERF_CTL[5:0] bits 7:0). Y, when specified, signifies the
unit mask programmed into MSRC001_020[A,8,6,4,2,0][UnitMask] (PERF_CTL[5:0] bits 15:8).
48063 Rev. 3.18 October 2012
Revision Guide for AMD Family 15hModels 00h-0Fh Processors
Conventions
7

•NBPMCxXXX[Y]: northbridge performance monitor events; XXX is the hexadecimal event counter number
programmed into MSRC001_024[6,4,2,0][EventSelect] (NB_PERF_CTL[3:0] bits 7:0). Y, when specified,
signifies the unit mask programmed into MSRC001_024[6,4,2,0][UnitMask] (NB_PERF_CTL[3:0] bits
15:8).
Many register references use the notation "[]"to identify arange of registers. For example, D18F2x[1,0][4C:40]
is ashorthand notation for D18F2x40, D18F2x44, D18F2x48, D18F2x4C, D18F2x140, D18F2x144,
D18F2x148, and D18F2x14C.
Arithmetic and Logical Operators
In this document, formulas follow some Verilog conventions as shown in Table 1.
Table 1. Arithmetic and Logic Operators
Operator Definition
{} Curly brackets are used to indicate agroup of bits that are concatenated together. Each set of bits is separated by acomma.
E.g., {Addr[3:2], Xlate[3:0]} represents a6-bit value; the two MSBs are Addr[3:2] and the four LSBs are Xlate[3:0].
|Bitwise OR operator. E.g. (01b| 10b== 11b).
|| Logical OR operator. E.g. (01b|| 10b== 1b); logical treats multibit operand as 1 if >=1 and produces a1-bit result.
&Bitwise AND operator. E.g. (01b& 10b== 00b).
&& Logical AND operator. E.g. (01b&& 10b== 1b); logical treats multibit operand as 1 if >=1 and produces a1-bit result.
^Bitwise exclusive-OR operator; sometimes used as "raised to the power of" as well, as indicated by the context in which it is
used. E.g. (01b^10b== 11b). E.g. (2^2 == 4).
~Bitwise NOT operator (also known as one's complement). E.g. (~10b== 01b).
!Logical NOT operator. E.g. (!10b== 0b); logical treats multibit operand as 1 if >=1 and produces a1-bit result.
== Logical "is equal to" operator.
!= Logical "is not equal to" operator.
<= Less than or equal operator.
>= Greater than or equal operator.
*Arithmetic multiplication operator.
/Arithmetic division operator.
<< Shift left first operand by the number of bits specified by the 2nd operand. E.g. (01b<< 01b== 10b).
>> Shift right first operand by the number of bits specified by the 2nd operand. E.g. (10b>> 01b== 01b).
Revision Guide for AMD Family 15hModels 00h-0Fh Processors 48063 Rev. 3.18 October 2012
8
Conventions

Processor Identification
This section shows how to determine the processor revision, program and display the processor name string, and
construct the processor name string.
Revision Determination
Aprocessor revision is identified using aunique value that is returned in the EAX register after executing the
CPUID instruction function 0000_0001h(CPUID Fn0000_0001_EAX). Figure 1 shows the format of the value
from CPUID Fn0000_0001_EAX. In some cases, two or more processor revisions may exist within astepping of
aprocessor family and are identified by aunique value in D18F4x164 Fixed Errata Register (see D18F4x164
Fixed Errata Register).
Figure 1. Format of CPUID Fn0000_0001_EAX
The following tables show the identification numbers from CPUID Fn0000_0001_EAX and D18F4x164 (if
necessary) for each revision of the processor to each processor segment. "X" signifies that the revision has been
used in the processor segment. "N/A" signifies that the revision has not been used in the processor segment.
Table 2. CPUID Values for AMD Family 15hModels 00h-0Fh G34r1
Processor Revisions
CPUID Fn0000_0001_EAX, D18F4x164[1:0]
(Mnemonic)
AMD Opteron™6200 Series Processor
AMD Opteron™6300 Series Processor
00600F12h, 1b(OR-B2) X
00600F20h, 11b(OR-C0) X
48063 Rev. 3.18 October 2012 Revision Guide for AMD Family 15hModels 00h-0Fh Processors
Processor Identification
9

Table 3. CPUID Values for AMD Family 15hModels 00h-0Fh C32r1
Processor Revisions
CPUID Fn0000_0001_EAX, D18F4x164[1:0]
(Mnemonic)
AMD Opteron™4200 Series Processor AMD Opteron™4300 Series Processor
00600F12h, 1b(OR-B2) X
00600F20h, 11b(OR-C0) X
Table 4. CPUID Values for AMD Family 15hModels 00h-0Fh AM3r2 Processor
Revisions
CPUID Fn0000_0001_EAX, D18F4x164[1:0]
AMD FX™Series Processor
AMD Opteron™3200 Series Processor AMD Opteron™3300 Series Processor
00600F12h, 1b(OR-B2) X X
00600F20h, 11b(OR-C0) X
D18F4x164 Fixed Errata Register
Communicating the status of an erratum within astepping of aprocessor family is necessary in certain
circumstances. D18F4x164 is used to communicate the status of such an erratum fix so that BIOS or system
software can determine the necessity of applying the workaround. Under these circumstances, the erratum
workaround references the specified bit to enable software to test for the presence of the erratum. The erratum
may be specific to some steppings of the processor, and the specified bit may or may not be set on other
unaffected revisions within the same family. Therefore, software should use the CPUID Fn00000_0001_EAX
extended model, model, and stepping as the first criteria to identify the applicability of an erratum. Once defined,
the definition of the status bit will persist within the family of processors.
Bits Description
31:0 If CPUID Fn0000_0001_EAX is 00600F12h (OR-B2), then D18F4x164 is 0000001h. If CPUID Fn0000_0001_EAX is 00600F20h
(OR-C0), then D18F4x164 is 0000003h.
Revision Guide for AMD Family 15hModels 00h-0Fh Processors 48063 Rev. 3.18 October 2012
10
Processor Identification

Mixed Processor Revision Support
AMD Family 15hprocessors with different revisions may be mixed in amultiprocessor system. Mixed revision
support includes the AMD Opteron™processor configurations as shown in Table 5. Processors of different
package types can not be mixed in amultiprocessor system, for example aG34r1 processor can not be mixed
with aC32r1 processor.
Table 5. Supported Mixed Revision
Configurations
CPUID
Fn0000_0001_EAX
(Mnemonic)
00600F12h(OR-B2)
06000F20h(OR-C0)
00600F12h(OR-B2) YES NO
00600F20h(OR-C0) NO YES
Errata workarounds must be applied according to revision as described in the Product Errata section unless
otherwise noted in the workraound of an erratum.
Programming and Displaying the Processor Name String
This section, intended for BIOS programmers, describes how to program and display the 48-character processor
name string that is returned by CPUID Fn8000_000[4:2]. The hardware or cold reset value of the processor
name string is 48 ASCII NUL characters, so the BIOS must program the processor name string before any
general purpose application or operating system software uses the extended functions that read the name string.
It is common practice for the BIOS to display the processor name string and model number whenever it displays
processor information during boot up.
Note :Motherboards that do not program the proper processor name string and model number will not pass AMD
validation and will not be posted on the AMD Recommended Motherboard Web site.
The name string must be ASCII NUL terminated and the 48-character maximum includes that NUL character.
The processor name string is programmed by MSR writes to the six MSR addresses covered by the range
MSRC001_00[35:30]h. Refer to the BIOS and Kernel Developer's Guide (BKDG) for AMD Family 15h
Models 00h-0Fh Processors
, order# 42301 , for the format of how the 48-character processor name string maps
to the 48 bytes contained in the six 64-bit registers of MSRC001_00[35:30].
The processor name string is read by CPUID reads to arange of CPUID functions covered by CPUID
Fn8000_000[4:2]. Refer to CPUID Fn8000_000[4:2] in the BIOS and Kernel Developer's Guide (BKDG) for
AMD Family 15hModels 00h-0Fh Processors , order# 42301 , for the 48-character processor name string
mapping to the 48 bytes contained in the twelve 32-bit registers of CPUID Fn8000_000[4:2].
Constructing the Processor Name String
This section describes how to construct the processor name string. BIOS forms the name string as follows:
1. If D18F5x198_x0 is 00000000h, then use aname string of "AMD Unprogrammed Engineering Sample" and
skip the remaining steps.
2. Read {D18F5x198_x1, D18F5x198_x0} and write this value to MSRC001_0030.
3. Read {D18F5x198_x3, D18F5x198_x2} and write this value to MSRC001_0031.
48063 Rev. 3.18 October 2012
Revision Guide for AMD Family 15hModels 00h-0Fh Processors
Processor Identification
11

4. Read {D18F5x198_x5, D18F5x198_x4} and write this value to MSRC001_0032.
5. Read {D18F5x198_x7, D18F5x198_x6} and write this value to MSRC001_0033.
6. Read {D18F5x198_x9, D18F5x198_x8} and write this value to MSRC001_0034.
7. Read {D18F5x198_xB, D18F5x198_xA} and write this value to MSRC001_0035.
Revision Guide for AMD Family 15hModels 00h-0Fh Processors 48063 Rev. 3.18 October 2012
12
Processor Identification

Operating System Visible Workarounds
This section describes how to identify operating system visible workarounds.
MSRC001_0140 OS Visible Work-around MSR0 (OSVW_ID_Length)
This register, as defined in AMD64 Architecture Programmer's Manual Volume 2: System Programming , order#
24593, is used to specify the number of valid status bits within the OS Visible Work-around status registers.
The reset default value of this register is 0000_0000_0000_0000h.
BIOS shall program the OSVW_ID_Length to 0005hprior to hand-off to the OS.
Bits Description
63:16 Reserved.
15:0 OSVW_ID_Length: OS visible work-around ID length. Read-write.
MSRC001_0141 OS Visible Work-around MSR1 (OSVW_Status)
This register, as defined in AMD64 Architecture Programmer's Manual Volume 2: System Programming , order#
24593, provides the status of the known OS visible errata. Known errata are assigned an OSVW_ID
corresponding to the bit position within the valid status field.
Operating system software should use MSRC001_0140 to determine the valid length of the bit status field. For
all valid status bits: 1=Hardware contains the erratum, and an OS software work-around is required or may be
applied instead of aBIOS workaround. 0=Hardware has corrected the erratum, so an OS software work-around
is not necessary.
The reset default value of this register is 0000_0000_0000_0000h.
Bits Description
63:5 OsvwStatusBits:Reserved. OS visible work-around status bits. Read-write.
4OsvwId4: 1 = Hardware contains erratum #724, an OS workaround may be applied if available; 0 = Hardware has corrected erratum
#724.
3OsvwId3: Reserved, must be zero..
2OsvwId2: Reserved, must be zero..
1OsvwId1: Reserved, must be zero..
0OsvwId0: Reserved, must be zero..
BIOS shall program the state of the valid status bits as shown in Table 6 prior to hand-off to the OS.
Table 6. Cross Reference of Product Revision
to OSVW ID
CPUID
Fn0000_0001_EAX
(Mnemonic)
MSRC001_0141 Bits
00600F12h(OR-B2) 0000_0000_0000_0010h
00600F20h(OR-C0) 0000_0000_0000_0010h
48063 Rev. 3.18 October 2012 Revision Guide for AMD Family 15hModels 00h-0Fh Processors
Operating System Visible Workarounds
13

Product Errata
This section documents product errata for the processors. Aunique tracking number for each erratum has been
assigned within this document for user convenience in tracking the errata within specific revision levels. This
table cross-references the revisions of the part to each erratum. "No fix planned" indicates that no fix is planned
for current or future revisions of the processor.
Note: There may be missing errata numbers. Errata that do not affect this product family do not appear. In
addition, errata that have been resolved from early revisions of the processor have been deleted, and errata that
have been reconsidered may have been deleted or renumbered.
Table 7. Cross-Reference of Processor Revision to Errata
No.Errata Description
CPUID Fn0000_0001_EAX, D18F4x164[1:0]
00600F12h01b(OR-B2)
00600F20h11b(OR-C0)
361 Breakpoint Due to an Instruction That Has an Interrupt
Shadow May Be Lost No fix planned
503 APIC Task-Priority Register May Be Incorrect No fix planned
504 Corrected L3 Errors May Lead to System Hang No fix planned
505 Scrub Rate Control Register Address Depends on
DctCfgSel No fix planned
520 Some Lightweight Profiling Counters Stop Counting When
Instruction-Based Sampling is Enabled X
535 Lightweight Profiling May Not Indicate Fused Branch X
536 Performance Counter for Instruction Cache Misses Does
Not Increment for Sequential Prefetches X
537 Performance Counter for Ineffective Software Prefetches
Does Not Count for L2 Hits X
538 Performance Counter Does Not Count for Some Retired
Micro-Ops X
540 GART Table Walk Probes May Cause System Hang No fix planned
550 Latency Performance Counters Are Not Accurate No fix planned
585 Incorrect Memory Controller Operation Due to a
WrDatGrossDly Setting of 3.5 MEMCLKs No fix planned
586 AFar Control Transfer Changing Processor Operating
Mode May Generate aFalse Machine Check X
592 VPEXTRQ and VPINSRQ May Not Signal Invalid-Opcode
Exception X
593 Last-Branch Record Enabled May Cause Machine Check
and Incorrect LastBranchToIp X
600 HyperTransport™Link Retry Due to Partial CRC Error
May Cause System Hang X
602 HyperTransport™Link Frequency Changes May Cause a
System Hang No fix planned
Revision Guide for AMD Family 15hModels 00h-0Fh Processors 48063 Rev. 3.18 October 2012
14
Product Errata

Table 7. Cross-Reference of Processor Revision to Errata (continued)
No.Errata Description
CPUID Fn0000_0001_EAX, D18F4x164[1:0]
00600F12h01b(OR-B2)
00600F20h11b(OR-C0)
608 P-state Limit Changes May Not Generate Interrupts No fix planned
619 Non-Posted Reads May Block Write Dependent on Probe
Responses X
623 Small Code Segment Limits May Cause Incorrect Limit
Faults X
624 SB-RMI Processor State Accesses May Persistently
Timeout if Interrupted by aWarm Reset X
625 SB-RMI Writes May Not Be Observed by Processor No fix planned
636 Instruction Addresses Near Canonical Address Limit May
Cause #GP Exception X
637 Processor Does Not Report the Correct DRAM Address for
MCA Errors Within the CC6 Save Area No fix planned
657 MC1_STATUS Enable Bit Not Set When Logging
Corrected Errors No fix planned
658 CPUID Incorrectly Reports Large Page Support in L2
Instruction TLB X
659 VMCB Interrupt Shadow Status May Be Incorrect X
660 APERF May Increase Unpredictably X
661 P-State Limit and Stop Clock Assertion May Cause System
Hang No fix planned
663 Local Interrupts LINT0/LINT1 May Occur While APIC is
Software Disabled No fix planned
667 Processor May Generate Incorrect P-state Limit Interrupts No fix planned
668 Load Operation May Receive Incorrect Data After
Floating-point Exception X
671 Debug Breakpoint on Misaligned Store May Cause System
Hang X
672 SVM Guest Performance Counters May Be Inaccurate Due
to SMI X
673 Misaligned Page Crossing String Operations May Cause
System Hang X
674 Processor May Cache Prefetched Data from Remapped
Memory Region X
675 Instructions Performing Read-Modify-Write May Alter
Architectural State Before #PF X
685 Some Processor Cores May Have Inaccurate Instruction
Cache Fetch Performance Counter X
689 AM3r2 Six Core Processor May Limit P-State When Core
C6 State Is Disabled X
690 Northbridge FIFO Read/Write Pointer Overlap May Cause
Hang or Protocol Error Machine Check No fix planned
48063 Rev. 3.18 October 2012 Revision Guide for AMD Family 15hModels 00h-0Fh Processors
Product Errata
15

Table 7. Cross-Reference of Processor Revision to Errata (continued)
No.Errata Description
CPUID Fn0000_0001_EAX, D18F4x164[1:0]
00600F12h01b(OR-B2)
00600F20h11b(OR-C0)
691 Processors Using 1 MB L3 Subcaches May Execute a
Write-Back Invalidate Operation Incorrectly No fix planned
693 Performance Counter May Incorrectly Count MXCSR
Loads No fix planned
694 IBS Sampling of Instruction Fetches May Be Uneven No fix planned
695 Processor May Interpret FCW Incorrectly after FNSAVE/
FSAVE Limit Fault No fix planned
699 Processor May Generate Illegal Access in VMLOAD or
VMSAVE Instruction X
704 Processor May Report Incorrect Instruction Pointer X
707 Performance Counter for Locked Operations May Count
Cycles from Non-Locked Operations X
708 Initial Value of Time Stamp Counter May Include an Offset
Error X
709 Processor May Be Limited to Minimum P-state After aP-
state Limit Change No fix planned
714 Processor May Check DRAM Address Maps While Using
L2 Cache as General Storage during Boot No fix planned
717 Instruction-Based Sampling May Be Inaccurate X
718 Instruction-Based Sampling May Be Inaccurate No fix planned
719 Instruction-Based Sampling Fetch Counter Always Starts at
Maximum Value No fix planned
720 Processor May Not Respect Interrupt Shadow No fix planned
724 Unintercepted Halt Instruction May Cause Protocol
Machine Check or Unpredictable System Behavior No fix planned
725 Incorrect APIC Remote Read Behavior No fix planned
726 Processor May Report Incorrect MCA Address for Loads
that Cross Address Boundaries No fix planned
727 Processor Core May Hang During CC6 Resume X
734 Processor May Incorrectly Store VMCB Data X
737 Processor Does Not Check 128-bit Canonical Address
Boundary Case on Logical Address No fix planned
739 Processor May Read Branch Status Register With
Inconsistent Parity Bit X
740 Lightweight Profiling May Cause System Hang with
Concurrent Stop Clock No fix planned
742 DRAM Scrub Request During Register Write May Cause
Unpredictable Behavior No fix planned
744 Processor CC6 May Not Restore Trap Registers No fix planned
Revision Guide for AMD Family 15hModels 00h-0Fh Processors 48063 Rev. 3.18 October 2012
16
Product Errata

Table 7. Cross-Reference of Processor Revision to Errata (continued)
No.Errata Description
CPUID Fn0000_0001_EAX, D18F4x164[1:0]
00600F12h01b(OR-B2)
00600F20h11b(OR-C0)
745 Processor May Incorrectly Report Cache Sharing Property
in CPUID Topology X
759 One Core May Observe aTime Stamp Counter Skew X
48063 Rev. 3.18 October 2012 Revision Guide for AMD Family 15hModels 00h-0Fh Processors
Product Errata
17

Cross-Reference of Errata to Package Type
This table cross-references the errata to each package type. "X" signifies that the erratum applies to the package
type. An empty cell signifies that the erratum does not apply. An erratum may not apply to apackage type due to
aspecific characteristic of the erratum, or it may be due to the affected silicon revision(s) not being used in this
package.
Table 8. Cross-Reference
of Errata to Package Type
Errata
Package
AM3r2
C32r1
G34r1
361 X X X
503 X X X
504 X X X
505 X X X
520 X X X
535 X X X
536 X X X
537 X X X
538 X X X
540 X X X
550 X X X
585 X X X
586 X X X
592 X X X
593 X X X
600 X X
602 X X X
608 X X X
619 X X X
623 X X X
624 X X X
625 X X X
636 X X X
637 X X X
657 X X X
658 X X X
659 X X X
660 X X X
661 X X X
663 X X X
Revision Guide for AMD Family 15hModels 00h-0Fh Processors 48063 Rev. 3.18 October 2012
18
Cross-Reference of Errata to Package Type

Table 8. Cross-Reference
of Errata to Package Type
(continued)
Errata
Package
AM3r2
C32r1
G34r1
667 X X X
668 X X X
671 X X X
672 X X X
673 X X X
674 X X X
675 X X X
685 X X X
689 X
690 X X X
691 X
693 X X X
694 X X X
695 X X X
699 X X X
704 X X X
707 X X X
708 X X X
709 X X X
714 X X X
717 X X X
718 X X X
719 X X X
720 X X X
724 X X X
725 X X X
726 X X X
727 X X X
734 X X X
737 X X X
739 X X X
740 X X X
742 X X X
744 X X
745 X
48063 Rev. 3.18 October 2012 Revision Guide for AMD Family 15hModels 00h-0Fh Processors
Cross-Reference of Errata to Package Type
19

Table 8. Cross-Reference
of Errata to Package Type
(continued)
Errata
Package
AM3r2
C32r1
G34r1
759 X X X
Revision Guide for AMD Family 15hModels 00h-0Fh Processors 48063 Rev. 3.18 October 2012
20
Cross-Reference of Errata to Package Type